arch/arm/mach-ixp4xx/common.c

   1 /*
   2  * arch/arm/mach-ixp4xx/common.c
   3  *
   4  * Generic code shared across all IXP4XX platforms
   5  *
   6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
   7  *
   8  * Copyright 2002 (c) Intel Corporation
   9  * Copyright 2003-2004 (c) MontaVista, Software, Inc.
  10  *
  11  * This file is licensed under  the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/mm.h>
  18 #include <linux/init.h>
  19 #include <linux/serial.h>
  20 #include <linux/sched.h>
  21 #include <linux/tty.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/serial_core.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/bitops.h>
  26 #include <linux/time.h>
  27 #include <linux/timex.h>
  28 #include <linux/clocksource.h>
  29 #include <linux/clockchips.h>
  30 #include <linux/io.h>
  31 #include <linux/export.h>
  32
  33 #include <mach/udc.h>
  34 #include <mach/hardware.h>
  35 #include <asm/uaccess.h>
  36 #include <asm/pgtable.h>
  37 #include <asm/page.h>
  38 #include <asm/irq.h>
  39 #include <asm/sched_clock.h>
  40
  41 #include <asm/mach/map.h>
  42 #include <asm/mach/irq.h>
  43 #include <asm/mach/time.h>
  44
  45 static void __init ixp4xx_clocksource_init(void);
  46 static void __init ixp4xx_clockevent_init(void);
  47 static struct clock_event_device clockevent_ixp4xx;
  48
  49 /*************************************************************************
  50  * IXP4xx chipset I/O mapping
  51  *************************************************************************/
  52 static struct map_desc ixp4xx_io_desc[] __initdata = {
  53         {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
  54                 .virtual        = IXP4XX_PERIPHERAL_BASE_VIRT,
  55                 .pfn            = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
  56                 .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
  57                 .type           = MT_DEVICE
  58         }, {    /* Expansion Bus Config Registers */
  59                 .virtual        = IXP4XX_EXP_CFG_BASE_VIRT,
  60                 .pfn            = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
  61                 .length         = IXP4XX_EXP_CFG_REGION_SIZE,
  62                 .type           = MT_DEVICE
  63         }, {    /* PCI Registers */
  64                 .virtual        = IXP4XX_PCI_CFG_BASE_VIRT,
  65                 .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
  66                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
  67                 .type           = MT_DEVICE
  68         },
  69 #ifdef CONFIG_DEBUG_LL
  70         {       /* Debug UART mapping */
  71                 .virtual        = IXP4XX_DEBUG_UART_BASE_VIRT,
  72                 .pfn            = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
  73                 .length         = IXP4XX_DEBUG_UART_REGION_SIZE,
  74                 .type           = MT_DEVICE
  75         }
  76 #endif
  77 };
  78
  79 void __init ixp4xx_map_io(void)
  80 {
  81         iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
  82 }
  83
  84
  85 /*************************************************************************
  86  * IXP4xx chipset IRQ handling
  87  *
  88  * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
  89  *       (be it PCI or something else) configures that GPIO line
  90  *       as an IRQ.
  91  **************************************************************************/
  92 enum ixp4xx_irq_type {
  93         IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
  94 };
  95
  96 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
  97 static unsigned long long ixp4xx_irq_edge = 0;
  98
  99 /*
 100  * IRQ -> GPIO mapping table
 101  */
 102 static signed char irq2gpio[32] = {
 103         -1, -1, -1, -1, -1, -1,  0,  1,
 104         -1, -1, -1, -1, -1, -1, -1, -1,
 105         -1, -1, -1,  2,  3,  4,  5,  6,
 106          7,  8,  9, 10, 11, 12, -1, -1,
 107 };
 108
 109 int gpio_to_irq(int gpio)
 110 {
 111         int irq;
 112
 113         for (irq = 0; irq < 32; irq++) {
 114                 if (irq2gpio[irq] == gpio)
 115                         return irq;
 116         }
 117         return -EINVAL;
 118 }
 119 EXPORT_SYMBOL(gpio_to_irq);
 120
 121 int irq_to_gpio(unsigned int irq)
 122 {
 123         int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;
 124
 125         if (gpio == -1)
 126                 return -EINVAL;
 127
 128         return gpio;
 129 }
 130 EXPORT_SYMBOL(irq_to_gpio);
 131
 132 static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
 133 {
 134         int line = irq2gpio[d->irq];
 135         u32 int_style;
 136         enum ixp4xx_irq_type irq_type;
 137         volatile u32 *int_reg;
 138
 139         /*
 140          * Only for GPIO IRQs
 141          */
 142         if (line < 0)
 143                 return -EINVAL;
 144
 145         switch (type){
 146         case IRQ_TYPE_EDGE_BOTH:
 147                 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
 148                 irq_type = IXP4XX_IRQ_EDGE;
 149                 break;
 150         case IRQ_TYPE_EDGE_RISING:
 151                 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
 152                 irq_type = IXP4XX_IRQ_EDGE;
 153                 break;
 154         case IRQ_TYPE_EDGE_FALLING:
 155                 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
 156                 irq_type = IXP4XX_IRQ_EDGE;
 157                 break;
 158         case IRQ_TYPE_LEVEL_HIGH:
 159                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
 160                 irq_type = IXP4XX_IRQ_LEVEL;
 161                 break;
 162         case IRQ_TYPE_LEVEL_LOW:
 163                 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
 164                 irq_type = IXP4XX_IRQ_LEVEL;
 165                 break;
 166         default:
 167                 return -EINVAL;
 168         }
 169
 170         if (irq_type == IXP4XX_IRQ_EDGE)
 171                 ixp4xx_irq_edge |= (1 << d->irq);
 172         else
 173                 ixp4xx_irq_edge &= ~(1 << d->irq);
 174
 175         if (line >= 8) {        /* pins 8-15 */
 176                 line -= 8;
 177                 int_reg = IXP4XX_GPIO_GPIT2R;
 178         } else {                /* pins 0-7 */
 179                 int_reg = IXP4XX_GPIO_GPIT1R;
 180         }
 181
 182         /* Clear the style for the appropriate pin */
 183         *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
 184                         (line * IXP4XX_GPIO_STYLE_SIZE));
 185
 186         *IXP4XX_GPIO_GPISR = (1 << line);
 187
 188         /* Set the new style */
 189         *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
 190
 191         /* Configure the line as an input */
 192         gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN);
 193
 194         return 0;
 195 }
 196
 197 static void ixp4xx_irq_mask(struct irq_data *d)
 198 {
 199         if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
 200                 *IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
 201         else
 202                 *IXP4XX_ICMR &= ~(1 << d->irq);
 203 }
 204
 205 static void ixp4xx_irq_ack(struct irq_data *d)
 206 {
 207         int line = (d->irq < 32) ? irq2gpio[d->irq] : -1;
 208
 209         if (line >= 0)
 210                 *IXP4XX_GPIO_GPISR = (1 << line);
 211 }
 212
 213 /*
 214  * Level triggered interrupts on GPIO lines can only be cleared when the
 215  * interrupt condition disappears.
 216  */
 217 static void ixp4xx_irq_unmask(struct irq_data *d)
 218 {
 219         if (!(ixp4xx_irq_edge & (1 << d->irq)))
 220                 ixp4xx_irq_ack(d);
 221
 222         if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
 223                 *IXP4XX_ICMR2 |= (1 << (d->irq - 32));
 224         else
 225                 *IXP4XX_ICMR |= (1 << d->irq);
 226 }
 227
 228 static struct irq_chip ixp4xx_irq_chip = {
 229         .name           = "IXP4xx",
 230         .irq_ack        = ixp4xx_irq_ack,
 231         .irq_mask       = ixp4xx_irq_mask,
 232         .irq_unmask     = ixp4xx_irq_unmask,
 233         .irq_set_type   = ixp4xx_set_irq_type,
 234 };
 235
 236 void __init ixp4xx_init_irq(void)
 237 {
 238         int i = 0;
 239
 240         /* Route all sources to IRQ instead of FIQ */
 241         *IXP4XX_ICLR = 0x0;
 242
 243         /* Disable all interrupt */
 244         *IXP4XX_ICMR = 0x0;
 245
 246         if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
 247                 /* Route upper 32 sources to IRQ instead of FIQ */
 248                 *IXP4XX_ICLR2 = 0x00;
 249
 250                 /* Disable upper 32 interrupts */
 251                 *IXP4XX_ICMR2 = 0x00;
 252         }
 253
 254         /* Default to all level triggered */
 255         for(i = 0; i < NR_IRQS; i++) {
 256                 irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
 257                                          handle_level_irq);
 258                 set_irq_flags(i, IRQF_VALID);
 259         }
 260 }
 261
 262
 263 /*************************************************************************
 264  * IXP4xx timer tick
 265  * We use OS timer1 on the CPU for the timer tick and the timestamp
 266  * counter as a source of real clock ticks to account for missed jiffies.
 267  *************************************************************************/
 268
 269 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
 270 {
 271         struct clock_event_device *evt = dev_id;
 272
 273         /* Clear Pending Interrupt by writing '1' to it */
 274         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 275
 276         evt->event_handler(evt);
 277
 278         return IRQ_HANDLED;
 279 }
 280
 281 static struct irqaction ixp4xx_timer_irq = {
 282         .name           = "timer1",
 283         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 284         .handler        = ixp4xx_timer_interrupt,
 285         .dev_id         = &clockevent_ixp4xx,
 286 };
 287
 288 void __init ixp4xx_timer_init(void)
 289 {
 290         /* Reset/disable counter */
 291         *IXP4XX_OSRT1 = 0;
 292
 293         /* Clear Pending Interrupt by writing '1' to it */
 294         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
 295
 296         /* Reset time-stamp counter */
 297         *IXP4XX_OSTS = 0;
 298
 299         /* Connect the interrupt handler and enable the interrupt */
 300         setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
 301
 302         ixp4xx_clocksource_init();
 303         ixp4xx_clockevent_init();
 304 }
 305
 306 struct sys_timer ixp4xx_timer = {
 307         .init           = ixp4xx_timer_init,
 308 };
 309
 310 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
 311
 312 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
 313 {
 314         memcpy(&ixp4xx_udc_info, info, sizeof *info);
 315 }
 316
 317 static struct resource ixp4xx_udc_resources[] = {
 318         [0] = {
 319                 .start  = 0xc800b000,
 320                 .end    = 0xc800bfff,
 321                 .flags  = IORESOURCE_MEM,
 322         },
 323         [1] = {
 324                 .start  = IRQ_IXP4XX_USB,
 325                 .end    = IRQ_IXP4XX_USB,
 326                 .flags  = IORESOURCE_IRQ,
 327         },
 328 };
 329
 330 /*
 331  * USB device controller. The IXP4xx uses the same controller as PXA25X,
 332  * so we just use the same device.
 333  */
 334 static struct platform_device ixp4xx_udc_device = {
 335         .name           = "pxa25x-udc",
 336         .id             = -1,
 337         .num_resources  = 2,
 338         .resource       = ixp4xx_udc_resources,
 339         .dev            = {
 340                 .platform_data = &ixp4xx_udc_info,
 341         },
 342 };
 343
 344 static struct platform_device *ixp4xx_devices[] __initdata = {
 345         &ixp4xx_udc_device,
 346 };
 347
 348 static struct resource ixp46x_i2c_resources[] = {
 349         [0] = {
 350                 .start  = 0xc8011000,
 351                 .end    = 0xc801101c,
 352                 .flags  = IORESOURCE_MEM,
 353         },
 354         [1] = {
 355                 .start  = IRQ_IXP4XX_I2C,
 356                 .end    = IRQ_IXP4XX_I2C,
 357                 .flags  = IORESOURCE_IRQ
 358         }
 359 };
 360
 361 /*
 362  * I2C controller. The IXP46x uses the same block as the IOP3xx, so
 363  * we just use the same device name.
 364  */
 365 static struct platform_device ixp46x_i2c_controller = {
 366         .name           = "IOP3xx-I2C",
 367         .id             = 0,
 368         .num_resources  = 2,
 369         .resource       = ixp46x_i2c_resources
 370 };
 371
 372 static struct platform_device *ixp46x_devices[] __initdata = {
 373         &ixp46x_i2c_controller
 374 };
 375
 376 unsigned long ixp4xx_exp_bus_size;
 377 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
 378
 379 void __init ixp4xx_sys_init(void)
 380 {
 381         ixp4xx_exp_bus_size = SZ_16M;
 382
 383         platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
 384
 385         if (cpu_is_ixp46x()) {
 386                 int region;
 387
 388                 platform_add_devices(ixp46x_devices,
 389                                 ARRAY_SIZE(ixp46x_devices));
 390
 391                 for (region = 0; region < 7; region++) {
 392                         if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
 393                                 ixp4xx_exp_bus_size = SZ_32M;
 394                                 break;
 395                         }
 396                 }
 397         }
 398
 399         printk("IXP4xx: Using %luMiB expansion bus window size\n",
 400                         ixp4xx_exp_bus_size >> 20);
 401 }
 402
 403 /*
 404  * sched_clock()
 405  */
 406 static DEFINE_CLOCK_DATA(cd);
 407
 408 unsigned long long notrace sched_clock(void)
 409 {
 410         u32 cyc = *IXP4XX_OSTS;
 411         return cyc_to_sched_clock(&cd, cyc, (u32)~0);
 412 }
 413
 414 static void notrace ixp4xx_update_sched_clock(void)
 415 {
 416         u32 cyc = *IXP4XX_OSTS;
 417         update_sched_clock(&cd, cyc, (u32)~0);
 418 }
 419
 420 /*
 421  * clocksource
 422  */
 423
 424 static cycle_t ixp4xx_clocksource_read(struct clocksource *c)
 425 {
 426         return *IXP4XX_OSTS;
 427 }
 428
 429 unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
 430 EXPORT_SYMBOL(ixp4xx_timer_freq);
 431 static void __init ixp4xx_clocksource_init(void)
 432 {
 433         init_sched_clock(&cd, ixp4xx_update_sched_clock, 32, ixp4xx_timer_freq);
 434
 435         clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
 436                         ixp4xx_clocksource_read);
 437 }
 438
 439 /*
 440  * clockevents
 441  */
 442 static int ixp4xx_set_next_event(unsigned long evt,
 443                                  struct clock_event_device *unused)
 444 {
 445         unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
 446
 447         *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
 448
 449         return 0;
 450 }
 451
 452 static void ixp4xx_set_mode(enum clock_event_mode mode,
 453                             struct clock_event_device *evt)
 454 {
 455         unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
 456         unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
 457
 458         switch (mode) {
 459         case CLOCK_EVT_MODE_PERIODIC:
 460                 osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK;
 461                 opts = IXP4XX_OST_ENABLE;
 462                 break;
 463         case CLOCK_EVT_MODE_ONESHOT:
 464                 /* period set by 'set next_event' */
 465                 osrt = 0;
 466                 opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
 467                 break;
 468         case CLOCK_EVT_MODE_SHUTDOWN:
 469                 opts &= ~IXP4XX_OST_ENABLE;
 470                 break;
 471         case CLOCK_EVT_MODE_RESUME:
 472                 opts |= IXP4XX_OST_ENABLE;
 473                 break;
 474         case CLOCK_EVT_MODE_UNUSED:
 475         default:
 476                 osrt = opts = 0;
 477                 break;
 478         }
 479
 480         *IXP4XX_OSRT1 = osrt | opts;
 481 }
 482
 483 static struct clock_event_device clockevent_ixp4xx = {
 484         .name           = "ixp4xx timer1",
 485         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 486         .rating         = 200,
 487         .shift          = 24,
 488         .set_mode       = ixp4xx_set_mode,
 489         .set_next_event = ixp4xx_set_next_event,
 490 };
 491
 492 static void __init ixp4xx_clockevent_init(void)
 493 {
 494         clockevent_ixp4xx.mult = div_sc(IXP4XX_TIMER_FREQ, NSEC_PER_SEC,
 495                                         clockevent_ixp4xx.shift);
 496         clockevent_ixp4xx.max_delta_ns =
 497                 clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx);
 498         clockevent_ixp4xx.min_delta_ns =
 499                 clockevent_delta2ns(0xf, &clockevent_ixp4xx);
 500         clockevent_ixp4xx.cpumask = cpumask_of(0);
 501
 502         clockevents_register_device(&clockevent_ixp4xx);
 503 }