[ALSA] HDA driver - do not set mute flag for dB scale (follow HDA specification)
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / include / asm-ppc / mmu_context.h
blob2bc8589cc45130b9f223f0fb172dbb1b5a12894c
1 #ifdef __KERNEL__
2 #ifndef __PPC_MMU_CONTEXT_H
3 #define __PPC_MMU_CONTEXT_H
5 #include <asm/atomic.h>
6 #include <asm/bitops.h>
7 #include <asm/mmu.h>
8 #include <asm/cputable.h>
11 * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs
12 * (virtual segment identifiers) for each context. Although the
13 * hardware supports 24-bit VSIDs, and thus >1 million contexts,
14 * we only use 32,768 of them. That is ample, since there can be
15 * at most around 30,000 tasks in the system anyway, and it means
16 * that we can use a bitmap to indicate which contexts are in use.
17 * Using a bitmap means that we entirely avoid all of the problems
18 * that we used to have when the context number overflowed,
19 * particularly on SMP systems.
20 * -- paulus.
24 * This function defines the mapping from contexts to VSIDs (virtual
25 * segment IDs). We use a skew on both the context and the high 4 bits
26 * of the 32-bit virtual address (the "effective segment ID") in order
27 * to spread out the entries in the MMU hash table. Note, if this
28 * function is changed then arch/ppc/mm/hashtable.S will have to be
29 * changed to correspond.
31 #define CTX_TO_VSID(ctx, va) (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \
32 & 0xffffff)
35 The MPC8xx has only 16 contexts. We rotate through them on each
36 task switch. A better way would be to keep track of tasks that
37 own contexts, and implement an LRU usage. That way very active
38 tasks don't always have to pay the TLB reload overhead. The
39 kernel pages are mapped shared, so the kernel can run on behalf
40 of any task that makes a kernel entry. Shared does not mean they
41 are not protected, just that the ASID comparison is not performed.
42 -- Dan
44 The IBM4xx has 256 contexts, so we can just rotate through these
45 as a way of "switching" contexts. If the TID of the TLB is zero,
46 the PID/TID comparison is disabled, so we can use a TID of zero
47 to represent all kernel pages as shared among all contexts.
48 -- Dan
51 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
55 #ifdef CONFIG_8xx
56 #define NO_CONTEXT 16
57 #define LAST_CONTEXT 15
58 #define FIRST_CONTEXT 0
60 #elif defined(CONFIG_4xx)
61 #define NO_CONTEXT 256
62 #define LAST_CONTEXT 255
63 #define FIRST_CONTEXT 1
65 #elif defined(CONFIG_E200) || defined(CONFIG_E500)
66 #define NO_CONTEXT 256
67 #define LAST_CONTEXT 255
68 #define FIRST_CONTEXT 1
70 #else
72 /* PPC 6xx, 7xx CPUs */
73 #define NO_CONTEXT ((unsigned long) -1)
74 #define LAST_CONTEXT 32767
75 #define FIRST_CONTEXT 1
76 #endif
79 * Set the current MMU context.
80 * On 32-bit PowerPCs (other than the 8xx embedded chips), this is done by
81 * loading up the segment registers for the user part of the address space.
83 * Since the PGD is immediately available, it is much faster to simply
84 * pass this along as a second parameter, which is required for 8xx and
85 * can be used for debugging on all processors (if you happen to have
86 * an Abatron).
88 extern void set_context(unsigned long contextid, pgd_t *pgd);
91 * Bitmap of contexts in use.
92 * The size of this bitmap is LAST_CONTEXT + 1 bits.
94 extern unsigned long context_map[];
97 * This caches the next context number that we expect to be free.
98 * Its use is an optimization only, we can't rely on this context
99 * number to be free, but it usually will be.
101 extern unsigned long next_mmu_context;
104 * If we don't have sufficient contexts to give one to every task
105 * that could be in the system, we need to be able to steal contexts.
106 * These variables support that.
108 #if LAST_CONTEXT < 30000
109 #define FEW_CONTEXTS 1
110 extern atomic_t nr_free_contexts;
111 extern struct mm_struct *context_mm[LAST_CONTEXT+1];
112 extern void steal_context(void);
113 #endif
116 * Get a new mmu context for the address space described by `mm'.
118 static inline void get_mmu_context(struct mm_struct *mm)
120 unsigned long ctx;
122 if (mm->context.id != NO_CONTEXT)
123 return;
124 #ifdef FEW_CONTEXTS
125 while (atomic_dec_if_positive(&nr_free_contexts) < 0)
126 steal_context();
127 #endif
128 ctx = next_mmu_context;
129 while (test_and_set_bit(ctx, context_map)) {
130 ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
131 if (ctx > LAST_CONTEXT)
132 ctx = 0;
134 next_mmu_context = (ctx + 1) & LAST_CONTEXT;
135 mm->context.id = ctx;
136 #ifdef FEW_CONTEXTS
137 context_mm[ctx] = mm;
138 #endif
142 * Set up the context for a new address space.
144 static inline int init_new_context(struct task_struct *t, struct mm_struct *mm)
146 mm->context.id = NO_CONTEXT;
147 mm->context.vdso_base = 0;
148 return 0;
152 * We're finished using the context for an address space.
154 static inline void destroy_context(struct mm_struct *mm)
156 preempt_disable();
157 if (mm->context.id != NO_CONTEXT) {
158 clear_bit(mm->context.id, context_map);
159 mm->context.id = NO_CONTEXT;
160 #ifdef FEW_CONTEXTS
161 atomic_inc(&nr_free_contexts);
162 #endif
164 preempt_enable();
167 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
168 struct task_struct *tsk)
170 #ifdef CONFIG_ALTIVEC
171 if (cpu_has_feature(CPU_FTR_ALTIVEC))
172 asm volatile ("dssall;\n"
173 #ifndef CONFIG_POWER4
174 "sync;\n" /* G4 needs a sync here, G5 apparently not */
175 #endif
176 : : );
177 #endif /* CONFIG_ALTIVEC */
179 tsk->thread.pgdir = next->pgd;
181 /* No need to flush userspace segments if the mm doesnt change */
182 if (prev == next)
183 return;
185 /* Setup new userspace context */
186 get_mmu_context(next);
187 set_context(next->context.id, next->pgd);
190 #define deactivate_mm(tsk,mm) do { } while (0)
193 * After we have set current->mm to a new value, this activates
194 * the context for the new mm so we see the new mappings.
196 #define activate_mm(active_mm, mm) switch_mm(active_mm, mm, current)
198 extern void mmu_context_init(void);
200 #endif /* __PPC_MMU_CONTEXT_H */
201 #endif /* __KERNEL__ */