2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/pci.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
33 #include <linux/msi.h>
34 #include <linux/htirq.h>
36 #include <acpi/acpi_bus.h>
42 #include <asm/proto.h>
43 #include <asm/mach_apic.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
55 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
56 struct irq_cfg irq_cfg
[NR_IRQS
] __read_mostly
= {
57 [0] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ0_VECTOR
, },
58 [1] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ1_VECTOR
, },
59 [2] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ2_VECTOR
, },
60 [3] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ3_VECTOR
, },
61 [4] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ4_VECTOR
, },
62 [5] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ5_VECTOR
, },
63 [6] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ6_VECTOR
, },
64 [7] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ7_VECTOR
, },
65 [8] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ8_VECTOR
, },
66 [9] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ9_VECTOR
, },
67 [10] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ10_VECTOR
, },
68 [11] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ11_VECTOR
, },
69 [12] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ12_VECTOR
, },
70 [13] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ13_VECTOR
, },
71 [14] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ14_VECTOR
, },
72 [15] = { .domain
= CPU_MASK_ALL
, .vector
= IRQ15_VECTOR
, },
75 static int assign_irq_vector(int irq
, cpumask_t mask
);
77 #define __apicdebuginit __init
79 int sis_apic_bug
; /* not actually supported, dummy for compile */
81 static int no_timer_check
;
83 static int disable_timer_pin_1 __initdata
;
85 int timer_over_8254 __initdata
= 1;
87 /* Where if anywhere is the i8259 connect in external int mode */
88 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
90 static DEFINE_SPINLOCK(ioapic_lock
);
91 DEFINE_SPINLOCK(vector_lock
);
94 * # of IRQ routing registers
96 int nr_ioapic_registers
[MAX_IO_APICS
];
99 * Rough estimation of how many shared IRQs there are, can
100 * be changed anytime.
102 #define MAX_PLUS_SHARED_IRQS NR_IRQS
103 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
106 * This is performance-critical, we want to do it O(1)
108 * the indexing order of this array favors 1:1 mappings
109 * between pins and IRQs.
112 static struct irq_pin_list
{
113 short apic
, pin
, next
;
114 } irq_2_pin
[PIN_MAP_SIZE
];
118 unsigned int unused
[3];
122 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
124 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
125 + (mp_ioapics
[idx
].mpc_apicaddr
& ~PAGE_MASK
);
128 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
130 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
131 writel(reg
, &io_apic
->index
);
132 return readl(&io_apic
->data
);
135 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
137 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
138 writel(reg
, &io_apic
->index
);
139 writel(value
, &io_apic
->data
);
143 * Re-write a value: to be used for read-modify-write
144 * cycles where the read already set up the index register.
146 static inline void io_apic_modify(unsigned int apic
, unsigned int value
)
148 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
149 writel(value
, &io_apic
->data
);
153 * Synchronize the IO-APIC and the CPU by doing
154 * a dummy read from the IO-APIC
156 static inline void io_apic_sync(unsigned int apic
)
158 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
159 readl(&io_apic
->data
);
162 #define __DO_ACTION(R, ACTION, FINAL) \
166 struct irq_pin_list *entry = irq_2_pin + irq; \
168 BUG_ON(irq >= NR_IRQS); \
174 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
176 io_apic_modify(entry->apic, reg); \
180 entry = irq_2_pin + entry->next; \
185 struct { u32 w1
, w2
; };
186 struct IO_APIC_route_entry entry
;
189 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
191 union entry_union eu
;
193 spin_lock_irqsave(&ioapic_lock
, flags
);
194 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
195 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
196 spin_unlock_irqrestore(&ioapic_lock
, flags
);
201 * When we write a new IO APIC routing entry, we need to write the high
202 * word first! If the mask bit in the low word is clear, we will enable
203 * the interrupt, and we need to make sure the entry is fully populated
204 * before that happens.
207 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
209 union entry_union eu
;
211 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
212 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
215 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
218 spin_lock_irqsave(&ioapic_lock
, flags
);
219 __ioapic_write_entry(apic
, pin
, e
);
220 spin_unlock_irqrestore(&ioapic_lock
, flags
);
224 * When we mask an IO APIC routing entry, we need to write the low
225 * word first, in order to set the mask bit before we change the
228 static void ioapic_mask_entry(int apic
, int pin
)
231 union entry_union eu
= { .entry
.mask
= 1 };
233 spin_lock_irqsave(&ioapic_lock
, flags
);
234 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
235 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
236 spin_unlock_irqrestore(&ioapic_lock
, flags
);
240 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
243 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
245 BUG_ON(irq
>= NR_IRQS
);
252 io_apic_write(apic
, 0x11 + pin
*2, dest
);
253 reg
= io_apic_read(apic
, 0x10 + pin
*2);
256 io_apic_modify(apic
, reg
);
259 entry
= irq_2_pin
+ entry
->next
;
263 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
265 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
270 cpus_and(tmp
, mask
, cpu_online_map
);
274 if (assign_irq_vector(irq
, mask
))
277 cpus_and(tmp
, cfg
->domain
, mask
);
278 dest
= cpu_mask_to_apicid(tmp
);
281 * Only the high 8 bits are valid.
283 dest
= SET_APIC_LOGICAL_ID(dest
);
285 spin_lock_irqsave(&ioapic_lock
, flags
);
286 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
287 irq_desc
[irq
].affinity
= mask
;
288 spin_unlock_irqrestore(&ioapic_lock
, flags
);
293 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
294 * shared ISA-space IRQs, so we have to support them. We are super
295 * fast in the common case, and fast for shared ISA-space IRQs.
297 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
299 static int first_free_entry
= NR_IRQS
;
300 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
302 BUG_ON(irq
>= NR_IRQS
);
304 entry
= irq_2_pin
+ entry
->next
;
306 if (entry
->pin
!= -1) {
307 entry
->next
= first_free_entry
;
308 entry
= irq_2_pin
+ entry
->next
;
309 if (++first_free_entry
>= PIN_MAP_SIZE
)
310 panic("io_apic.c: ran out of irq_2_pin entries!");
317 #define DO_ACTION(name,R,ACTION, FINAL) \
319 static void name##_IO_APIC_irq (unsigned int irq) \
320 __DO_ACTION(R, ACTION, FINAL)
322 DO_ACTION( __mask
, 0, |= 0x00010000, io_apic_sync(entry
->apic
) )
324 DO_ACTION( __unmask
, 0, &= 0xfffeffff, )
327 static void mask_IO_APIC_irq (unsigned int irq
)
331 spin_lock_irqsave(&ioapic_lock
, flags
);
332 __mask_IO_APIC_irq(irq
);
333 spin_unlock_irqrestore(&ioapic_lock
, flags
);
336 static void unmask_IO_APIC_irq (unsigned int irq
)
340 spin_lock_irqsave(&ioapic_lock
, flags
);
341 __unmask_IO_APIC_irq(irq
);
342 spin_unlock_irqrestore(&ioapic_lock
, flags
);
345 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
347 struct IO_APIC_route_entry entry
;
349 /* Check delivery_mode to be sure we're not clearing an SMI pin */
350 entry
= ioapic_read_entry(apic
, pin
);
351 if (entry
.delivery_mode
== dest_SMI
)
354 * Disable it in the IO-APIC irq-routing table:
356 ioapic_mask_entry(apic
, pin
);
359 static void clear_IO_APIC (void)
363 for (apic
= 0; apic
< nr_ioapics
; apic
++)
364 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
365 clear_IO_APIC_pin(apic
, pin
);
368 int skip_ioapic_setup
;
371 /* dummy parsing: see setup.c */
373 static int __init
disable_ioapic_setup(char *str
)
375 skip_ioapic_setup
= 1;
378 early_param("noapic", disable_ioapic_setup
);
380 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
381 static int __init
disable_timer_pin_setup(char *arg
)
383 disable_timer_pin_1
= 1;
386 __setup("disable_timer_pin_1", disable_timer_pin_setup
);
388 static int __init
setup_disable_8254_timer(char *s
)
390 timer_over_8254
= -1;
393 static int __init
setup_enable_8254_timer(char *s
)
399 __setup("disable_8254_timer", setup_disable_8254_timer
);
400 __setup("enable_8254_timer", setup_enable_8254_timer
);
404 * Find the IRQ entry number of a certain pin.
406 static int find_irq_entry(int apic
, int pin
, int type
)
410 for (i
= 0; i
< mp_irq_entries
; i
++)
411 if (mp_irqs
[i
].mpc_irqtype
== type
&&
412 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
413 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
414 mp_irqs
[i
].mpc_dstirq
== pin
)
421 * Find the pin to which IRQ[irq] (ISA) is connected
423 static int __init
find_isa_irq_pin(int irq
, int type
)
427 for (i
= 0; i
< mp_irq_entries
; i
++) {
428 int lbus
= mp_irqs
[i
].mpc_srcbus
;
430 if (test_bit(lbus
, mp_bus_not_pci
) &&
431 (mp_irqs
[i
].mpc_irqtype
== type
) &&
432 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
434 return mp_irqs
[i
].mpc_dstirq
;
439 static int __init
find_isa_irq_apic(int irq
, int type
)
443 for (i
= 0; i
< mp_irq_entries
; i
++) {
444 int lbus
= mp_irqs
[i
].mpc_srcbus
;
446 if (test_bit(lbus
, mp_bus_not_pci
) &&
447 (mp_irqs
[i
].mpc_irqtype
== type
) &&
448 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
451 if (i
< mp_irq_entries
) {
453 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
454 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
463 * Find a specific PCI IRQ entry.
464 * Not an __init, possibly needed by modules
466 static int pin_2_irq(int idx
, int apic
, int pin
);
468 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
470 int apic
, i
, best_guess
= -1;
472 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
474 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
475 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
478 for (i
= 0; i
< mp_irq_entries
; i
++) {
479 int lbus
= mp_irqs
[i
].mpc_srcbus
;
481 for (apic
= 0; apic
< nr_ioapics
; apic
++)
482 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
483 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
486 if (!test_bit(lbus
, mp_bus_not_pci
) &&
487 !mp_irqs
[i
].mpc_irqtype
&&
489 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
490 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
492 if (!(apic
|| IO_APIC_IRQ(irq
)))
495 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
498 * Use the first all-but-pin matching entry as a
499 * best-guess fuzzy result for broken mptables.
505 BUG_ON(best_guess
>= NR_IRQS
);
509 /* ISA interrupts are always polarity zero edge triggered,
510 * when listed as conforming in the MP table. */
512 #define default_ISA_trigger(idx) (0)
513 #define default_ISA_polarity(idx) (0)
515 /* PCI interrupts are always polarity one level triggered,
516 * when listed as conforming in the MP table. */
518 #define default_PCI_trigger(idx) (1)
519 #define default_PCI_polarity(idx) (1)
521 static int __init
MPBIOS_polarity(int idx
)
523 int bus
= mp_irqs
[idx
].mpc_srcbus
;
527 * Determine IRQ line polarity (high active or low active):
529 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
531 case 0: /* conforms, ie. bus-type dependent polarity */
532 if (test_bit(bus
, mp_bus_not_pci
))
533 polarity
= default_ISA_polarity(idx
);
535 polarity
= default_PCI_polarity(idx
);
537 case 1: /* high active */
542 case 2: /* reserved */
544 printk(KERN_WARNING
"broken BIOS!!\n");
548 case 3: /* low active */
553 default: /* invalid */
555 printk(KERN_WARNING
"broken BIOS!!\n");
563 static int MPBIOS_trigger(int idx
)
565 int bus
= mp_irqs
[idx
].mpc_srcbus
;
569 * Determine IRQ trigger mode (edge or level sensitive):
571 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
573 case 0: /* conforms, ie. bus-type dependent */
574 if (test_bit(bus
, mp_bus_not_pci
))
575 trigger
= default_ISA_trigger(idx
);
577 trigger
= default_PCI_trigger(idx
);
584 case 2: /* reserved */
586 printk(KERN_WARNING
"broken BIOS!!\n");
595 default: /* invalid */
597 printk(KERN_WARNING
"broken BIOS!!\n");
605 static inline int irq_polarity(int idx
)
607 return MPBIOS_polarity(idx
);
610 static inline int irq_trigger(int idx
)
612 return MPBIOS_trigger(idx
);
615 static int pin_2_irq(int idx
, int apic
, int pin
)
618 int bus
= mp_irqs
[idx
].mpc_srcbus
;
621 * Debugging check, we are in big trouble if this message pops up!
623 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
624 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
626 if (test_bit(bus
, mp_bus_not_pci
)) {
627 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
630 * PCI IRQs are mapped in order
634 irq
+= nr_ioapic_registers
[i
++];
637 BUG_ON(irq
>= NR_IRQS
);
641 static int __assign_irq_vector(int irq
, cpumask_t mask
)
644 * NOTE! The local APIC isn't very good at handling
645 * multiple interrupts at the same interrupt level.
646 * As the interrupt level is determined by taking the
647 * vector number and shifting that right by 4, we
648 * want to spread these out a bit so that they don't
649 * all fall in the same interrupt level.
651 * Also, we've got to be careful not to trash gate
652 * 0x80, because int 0x80 is hm, kind of importantish. ;)
654 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
655 cpumask_t old_mask
= CPU_MASK_NONE
;
656 unsigned int old_vector
;
660 BUG_ON((unsigned)irq
>= NR_IRQS
);
663 /* Only try and allocate irqs on cpus that are present */
664 cpus_and(mask
, mask
, cpu_online_map
);
666 old_vector
= cfg
->vector
;
669 cpus_and(tmp
, cfg
->domain
, mask
);
670 if (!cpus_empty(tmp
))
672 cpus_and(old_mask
, cfg
->domain
, cpu_online_map
);
675 for_each_cpu_mask(cpu
, mask
) {
676 cpumask_t domain
, new_mask
;
677 int new_cpu
, old_cpu
;
680 domain
= vector_allocation_domain(cpu
);
681 cpus_and(new_mask
, domain
, cpu_online_map
);
683 vector
= current_vector
;
684 offset
= current_offset
;
687 if (vector
>= FIRST_SYSTEM_VECTOR
) {
688 /* If we run out of vectors on large boxen, must share them. */
689 offset
= (offset
+ 1) % 8;
690 vector
= FIRST_DEVICE_VECTOR
+ offset
;
692 if (unlikely(current_vector
== vector
))
694 if (vector
== IA32_SYSCALL_VECTOR
)
696 for_each_cpu_mask(new_cpu
, new_mask
)
697 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
700 current_vector
= vector
;
701 current_offset
= offset
;
702 for_each_cpu_mask(old_cpu
, old_mask
)
703 per_cpu(vector_irq
, old_cpu
)[old_vector
] = -1;
704 for_each_cpu_mask(new_cpu
, new_mask
)
705 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
706 cfg
->vector
= vector
;
707 cfg
->domain
= domain
;
713 static int assign_irq_vector(int irq
, cpumask_t mask
)
718 spin_lock_irqsave(&vector_lock
, flags
);
719 err
= __assign_irq_vector(irq
, mask
);
720 spin_unlock_irqrestore(&vector_lock
, flags
);
724 static void __clear_irq_vector(int irq
)
730 BUG_ON((unsigned)irq
>= NR_IRQS
);
732 BUG_ON(!cfg
->vector
);
734 vector
= cfg
->vector
;
735 cpus_and(mask
, cfg
->domain
, cpu_online_map
);
736 for_each_cpu_mask(cpu
, mask
)
737 per_cpu(vector_irq
, cpu
)[vector
] = -1;
740 cfg
->domain
= CPU_MASK_NONE
;
743 void __setup_vector_irq(int cpu
)
745 /* Initialize vector_irq on a new cpu */
746 /* This function must be called with vector_lock held */
749 /* Mark the inuse vectors */
750 for (irq
= 0; irq
< NR_IRQS
; ++irq
) {
751 if (!cpu_isset(cpu
, irq_cfg
[irq
].domain
))
753 vector
= irq_cfg
[irq
].vector
;
754 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
756 /* Mark the free vectors */
757 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
758 irq
= per_cpu(vector_irq
, cpu
)[vector
];
761 if (!cpu_isset(cpu
, irq_cfg
[irq
].domain
))
762 per_cpu(vector_irq
, cpu
)[vector
] = -1;
767 static struct irq_chip ioapic_chip
;
769 static void ioapic_register_intr(int irq
, unsigned long trigger
)
772 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
773 handle_fasteoi_irq
, "fasteoi");
775 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
776 handle_edge_irq
, "edge");
779 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
,
780 int trigger
, int polarity
)
782 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
783 struct IO_APIC_route_entry entry
;
787 if (!IO_APIC_IRQ(irq
))
791 if (assign_irq_vector(irq
, mask
))
794 cpus_and(mask
, cfg
->domain
, mask
);
796 apic_printk(APIC_VERBOSE
,KERN_DEBUG
797 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
798 "IRQ %d Mode:%i Active:%i)\n",
799 apic
, mp_ioapics
[apic
].mpc_apicid
, pin
, cfg
->vector
,
800 irq
, trigger
, polarity
);
803 * add it to the IO-APIC irq-routing table:
805 memset(&entry
,0,sizeof(entry
));
807 entry
.delivery_mode
= INT_DELIVERY_MODE
;
808 entry
.dest_mode
= INT_DEST_MODE
;
809 entry
.dest
= cpu_mask_to_apicid(mask
);
810 entry
.mask
= 0; /* enable IRQ */
811 entry
.trigger
= trigger
;
812 entry
.polarity
= polarity
;
813 entry
.vector
= cfg
->vector
;
815 /* Mask level triggered irqs.
816 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
821 ioapic_register_intr(irq
, trigger
);
823 disable_8259A_irq(irq
);
825 ioapic_write_entry(apic
, pin
, entry
);
827 spin_lock_irqsave(&ioapic_lock
, flags
);
828 irq_desc
[irq
].affinity
= TARGET_CPUS
;
829 spin_unlock_irqrestore(&ioapic_lock
, flags
);
832 static void __init
setup_IO_APIC_irqs(void)
834 int apic
, pin
, idx
, irq
, first_notcon
= 1;
836 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
838 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
839 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
841 idx
= find_irq_entry(apic
,pin
,mp_INT
);
844 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
847 apic_printk(APIC_VERBOSE
, ", %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
851 irq
= pin_2_irq(idx
, apic
, pin
);
852 add_pin_to_irq(irq
, apic
, pin
);
854 setup_IO_APIC_irq(apic
, pin
, irq
,
855 irq_trigger(idx
), irq_polarity(idx
));
860 apic_printk(APIC_VERBOSE
," not connected.\n");
864 * Set up the 8259A-master output pin as broadcast to all
867 static void __init
setup_ExtINT_IRQ0_pin(unsigned int apic
, unsigned int pin
, int vector
)
869 struct IO_APIC_route_entry entry
;
872 memset(&entry
,0,sizeof(entry
));
874 disable_8259A_irq(0);
877 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
880 * We use logical delivery to get the timer IRQ
883 entry
.dest_mode
= INT_DEST_MODE
;
884 entry
.mask
= 0; /* unmask IRQ now */
885 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
886 entry
.delivery_mode
= INT_DELIVERY_MODE
;
889 entry
.vector
= vector
;
892 * The timer IRQ doesn't have to know that behind the
893 * scene we have a 8259A-master in AEOI mode ...
895 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
898 * Add it to the IO-APIC irq-routing table:
900 spin_lock_irqsave(&ioapic_lock
, flags
);
901 io_apic_write(apic
, 0x11+2*pin
, *(((int *)&entry
)+1));
902 io_apic_write(apic
, 0x10+2*pin
, *(((int *)&entry
)+0));
903 spin_unlock_irqrestore(&ioapic_lock
, flags
);
908 void __init
UNEXPECTED_IO_APIC(void)
912 void __apicdebuginit
print_IO_APIC(void)
915 union IO_APIC_reg_00 reg_00
;
916 union IO_APIC_reg_01 reg_01
;
917 union IO_APIC_reg_02 reg_02
;
920 if (apic_verbosity
== APIC_QUIET
)
923 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
924 for (i
= 0; i
< nr_ioapics
; i
++)
925 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
926 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
929 * We are a bit conservative about what we expect. We have to
930 * know about every hardware change ASAP.
932 printk(KERN_INFO
"testing the IO APIC.......................\n");
934 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
936 spin_lock_irqsave(&ioapic_lock
, flags
);
937 reg_00
.raw
= io_apic_read(apic
, 0);
938 reg_01
.raw
= io_apic_read(apic
, 1);
939 if (reg_01
.bits
.version
>= 0x10)
940 reg_02
.raw
= io_apic_read(apic
, 2);
941 spin_unlock_irqrestore(&ioapic_lock
, flags
);
944 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
945 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
946 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
947 if (reg_00
.bits
.__reserved_1
|| reg_00
.bits
.__reserved_2
)
948 UNEXPECTED_IO_APIC();
950 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
951 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
952 if ( (reg_01
.bits
.entries
!= 0x0f) && /* older (Neptune) boards */
953 (reg_01
.bits
.entries
!= 0x17) && /* typical ISA+PCI boards */
954 (reg_01
.bits
.entries
!= 0x1b) && /* Compaq Proliant boards */
955 (reg_01
.bits
.entries
!= 0x1f) && /* dual Xeon boards */
956 (reg_01
.bits
.entries
!= 0x22) && /* bigger Xeon boards */
957 (reg_01
.bits
.entries
!= 0x2E) &&
958 (reg_01
.bits
.entries
!= 0x3F) &&
959 (reg_01
.bits
.entries
!= 0x03)
961 UNEXPECTED_IO_APIC();
963 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
964 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
965 if ( (reg_01
.bits
.version
!= 0x01) && /* 82489DX IO-APICs */
966 (reg_01
.bits
.version
!= 0x02) && /* 82801BA IO-APICs (ICH2) */
967 (reg_01
.bits
.version
!= 0x10) && /* oldest IO-APICs */
968 (reg_01
.bits
.version
!= 0x11) && /* Pentium/Pro IO-APICs */
969 (reg_01
.bits
.version
!= 0x13) && /* Xeon IO-APICs */
970 (reg_01
.bits
.version
!= 0x20) /* Intel P64H (82806 AA) */
972 UNEXPECTED_IO_APIC();
973 if (reg_01
.bits
.__reserved_1
|| reg_01
.bits
.__reserved_2
)
974 UNEXPECTED_IO_APIC();
976 if (reg_01
.bits
.version
>= 0x10) {
977 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
978 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
979 if (reg_02
.bits
.__reserved_1
|| reg_02
.bits
.__reserved_2
)
980 UNEXPECTED_IO_APIC();
983 printk(KERN_DEBUG
".... IRQ redirection table:\n");
985 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
986 " Stat Dmod Deli Vect: \n");
988 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
989 struct IO_APIC_route_entry entry
;
991 entry
= ioapic_read_entry(apic
, i
);
993 printk(KERN_DEBUG
" %02x %03X ",
998 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1003 entry
.delivery_status
,
1005 entry
.delivery_mode
,
1010 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1011 for (i
= 0; i
< NR_IRQS
; i
++) {
1012 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1015 printk(KERN_DEBUG
"IRQ%d ", i
);
1017 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1020 entry
= irq_2_pin
+ entry
->next
;
1025 printk(KERN_INFO
".................................... done.\n");
1032 static __apicdebuginit
void print_APIC_bitfield (int base
)
1037 if (apic_verbosity
== APIC_QUIET
)
1040 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1041 for (i
= 0; i
< 8; i
++) {
1042 v
= apic_read(base
+ i
*0x10);
1043 for (j
= 0; j
< 32; j
++) {
1053 void __apicdebuginit
print_local_APIC(void * dummy
)
1055 unsigned int v
, ver
, maxlvt
;
1057 if (apic_verbosity
== APIC_QUIET
)
1060 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1061 smp_processor_id(), hard_smp_processor_id());
1062 v
= apic_read(APIC_ID
);
1063 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
1064 v
= apic_read(APIC_LVR
);
1065 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1066 ver
= GET_APIC_VERSION(v
);
1067 maxlvt
= get_maxlvt();
1069 v
= apic_read(APIC_TASKPRI
);
1070 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1072 v
= apic_read(APIC_ARBPRI
);
1073 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1074 v
& APIC_ARBPRI_MASK
);
1075 v
= apic_read(APIC_PROCPRI
);
1076 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1078 v
= apic_read(APIC_EOI
);
1079 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1080 v
= apic_read(APIC_RRR
);
1081 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1082 v
= apic_read(APIC_LDR
);
1083 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1084 v
= apic_read(APIC_DFR
);
1085 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1086 v
= apic_read(APIC_SPIV
);
1087 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1089 printk(KERN_DEBUG
"... APIC ISR field:\n");
1090 print_APIC_bitfield(APIC_ISR
);
1091 printk(KERN_DEBUG
"... APIC TMR field:\n");
1092 print_APIC_bitfield(APIC_TMR
);
1093 printk(KERN_DEBUG
"... APIC IRR field:\n");
1094 print_APIC_bitfield(APIC_IRR
);
1096 v
= apic_read(APIC_ESR
);
1097 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1099 v
= apic_read(APIC_ICR
);
1100 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1101 v
= apic_read(APIC_ICR2
);
1102 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1104 v
= apic_read(APIC_LVTT
);
1105 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1107 if (maxlvt
> 3) { /* PC is LVT#4. */
1108 v
= apic_read(APIC_LVTPC
);
1109 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1111 v
= apic_read(APIC_LVT0
);
1112 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1113 v
= apic_read(APIC_LVT1
);
1114 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1116 if (maxlvt
> 2) { /* ERR is LVT#3. */
1117 v
= apic_read(APIC_LVTERR
);
1118 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1121 v
= apic_read(APIC_TMICT
);
1122 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1123 v
= apic_read(APIC_TMCCT
);
1124 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1125 v
= apic_read(APIC_TDCR
);
1126 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1130 void print_all_local_APICs (void)
1132 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1135 void __apicdebuginit
print_PIC(void)
1138 unsigned long flags
;
1140 if (apic_verbosity
== APIC_QUIET
)
1143 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1145 spin_lock_irqsave(&i8259A_lock
, flags
);
1147 v
= inb(0xa1) << 8 | inb(0x21);
1148 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1150 v
= inb(0xa0) << 8 | inb(0x20);
1151 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1155 v
= inb(0xa0) << 8 | inb(0x20);
1159 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1161 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1163 v
= inb(0x4d1) << 8 | inb(0x4d0);
1164 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1169 static void __init
enable_IO_APIC(void)
1171 union IO_APIC_reg_01 reg_01
;
1172 int i8259_apic
, i8259_pin
;
1174 unsigned long flags
;
1176 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1177 irq_2_pin
[i
].pin
= -1;
1178 irq_2_pin
[i
].next
= 0;
1182 * The number of IO-APIC IRQ registers (== #pins):
1184 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1185 spin_lock_irqsave(&ioapic_lock
, flags
);
1186 reg_01
.raw
= io_apic_read(apic
, 1);
1187 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1188 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1190 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1192 /* See if any of the pins is in ExtINT mode */
1193 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1194 struct IO_APIC_route_entry entry
;
1195 entry
= ioapic_read_entry(apic
, pin
);
1197 /* If the interrupt line is enabled and in ExtInt mode
1198 * I have found the pin where the i8259 is connected.
1200 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1201 ioapic_i8259
.apic
= apic
;
1202 ioapic_i8259
.pin
= pin
;
1208 /* Look to see what if the MP table has reported the ExtINT */
1209 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1210 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1211 /* Trust the MP table if nothing is setup in the hardware */
1212 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1213 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1214 ioapic_i8259
.pin
= i8259_pin
;
1215 ioapic_i8259
.apic
= i8259_apic
;
1217 /* Complain if the MP table and the hardware disagree */
1218 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1219 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1221 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1225 * Do not trust the IO-APIC being empty at bootup
1231 * Not an __init, needed by the reboot code
1233 void disable_IO_APIC(void)
1236 * Clear the IO-APIC before rebooting:
1241 * If the i8259 is routed through an IOAPIC
1242 * Put that IOAPIC in virtual wire mode
1243 * so legacy interrupts can be delivered.
1245 if (ioapic_i8259
.pin
!= -1) {
1246 struct IO_APIC_route_entry entry
;
1248 memset(&entry
, 0, sizeof(entry
));
1249 entry
.mask
= 0; /* Enabled */
1250 entry
.trigger
= 0; /* Edge */
1252 entry
.polarity
= 0; /* High */
1253 entry
.delivery_status
= 0;
1254 entry
.dest_mode
= 0; /* Physical */
1255 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1257 entry
.dest
= GET_APIC_ID(apic_read(APIC_ID
));
1260 * Add it to the IO-APIC irq-routing table:
1262 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1265 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1269 * There is a nasty bug in some older SMP boards, their mptable lies
1270 * about the timer IRQ. We do the following to work around the situation:
1272 * - timer IRQ defaults to IO-APIC IRQ
1273 * - if this function detects that timer IRQs are defunct, then we fall
1274 * back to ISA timer IRQs
1276 static int __init
timer_irq_works(void)
1278 unsigned long t1
= jiffies
;
1281 /* Let ten ticks pass... */
1282 mdelay((10 * 1000) / HZ
);
1285 * Expect a few ticks at least, to be sure some possible
1286 * glue logic does not lock up after one or two first
1287 * ticks in a non-ExtINT mode. Also the local APIC
1288 * might have cached one ExtINT interrupt. Finally, at
1289 * least one tick may be lost due to delays.
1293 if (jiffies
- t1
> 4)
1299 * In the SMP+IOAPIC case it might happen that there are an unspecified
1300 * number of pending IRQ events unhandled. These cases are very rare,
1301 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1302 * better to do it this way as thus we do not have to be aware of
1303 * 'pending' interrupts in the IRQ path, except at this point.
1306 * Edge triggered needs to resend any interrupt
1307 * that was delayed but this is now handled in the device
1312 * Starting up a edge-triggered IO-APIC interrupt is
1313 * nasty - we need to make sure that we get the edge.
1314 * If it is already asserted for some reason, we need
1315 * return 1 to indicate that is was pending.
1317 * This is not complete - we should be able to fake
1318 * an edge even if it isn't on the 8259A...
1321 static unsigned int startup_ioapic_irq(unsigned int irq
)
1323 int was_pending
= 0;
1324 unsigned long flags
;
1326 spin_lock_irqsave(&ioapic_lock
, flags
);
1328 disable_8259A_irq(irq
);
1329 if (i8259A_irq_pending(irq
))
1332 __unmask_IO_APIC_irq(irq
);
1333 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1338 static int ioapic_retrigger_irq(unsigned int irq
)
1340 struct irq_cfg
*cfg
= &irq_cfg
[irq
];
1342 unsigned long flags
;
1344 spin_lock_irqsave(&vector_lock
, flags
);
1346 cpu_set(first_cpu(cfg
->domain
), mask
);
1348 send_IPI_mask(mask
, cfg
->vector
);
1349 spin_unlock_irqrestore(&vector_lock
, flags
);
1355 * Level and edge triggered IO-APIC interrupts need different handling,
1356 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1357 * handled with the level-triggered descriptor, but that one has slightly
1358 * more overhead. Level-triggered interrupts cannot be handled with the
1359 * edge-triggered handler, without risking IRQ storms and other ugly
1363 static void ack_apic_edge(unsigned int irq
)
1365 move_native_irq(irq
);
1369 static void ack_apic_level(unsigned int irq
)
1371 int do_unmask_irq
= 0;
1373 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1374 /* If we are moving the irq we need to mask it */
1375 if (unlikely(irq_desc
[irq
].status
& IRQ_MOVE_PENDING
)) {
1377 mask_IO_APIC_irq(irq
);
1382 * We must acknowledge the irq before we move it or the acknowledge will
1383 * not propogate properly.
1387 /* Now we can move and renable the irq */
1388 move_masked_irq(irq
);
1389 if (unlikely(do_unmask_irq
))
1390 unmask_IO_APIC_irq(irq
);
1393 static struct irq_chip ioapic_chip __read_mostly
= {
1395 .startup
= startup_ioapic_irq
,
1396 .mask
= mask_IO_APIC_irq
,
1397 .unmask
= unmask_IO_APIC_irq
,
1398 .ack
= ack_apic_edge
,
1399 .eoi
= ack_apic_level
,
1401 .set_affinity
= set_ioapic_affinity_irq
,
1403 .retrigger
= ioapic_retrigger_irq
,
1406 static inline void init_IO_APIC_traps(void)
1411 * NOTE! The local APIC isn't very good at handling
1412 * multiple interrupts at the same interrupt level.
1413 * As the interrupt level is determined by taking the
1414 * vector number and shifting that right by 4, we
1415 * want to spread these out a bit so that they don't
1416 * all fall in the same interrupt level.
1418 * Also, we've got to be careful not to trash gate
1419 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1421 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1423 if (IO_APIC_IRQ(tmp
) && !irq_cfg
[tmp
].vector
) {
1425 * Hmm.. We don't have an entry for this,
1426 * so default to an old-fashioned 8259
1427 * interrupt if we can..
1430 make_8259A_irq(irq
);
1432 /* Strange. Oh, well.. */
1433 irq_desc
[irq
].chip
= &no_irq_chip
;
1438 static void enable_lapic_irq (unsigned int irq
)
1442 v
= apic_read(APIC_LVT0
);
1443 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
1446 static void disable_lapic_irq (unsigned int irq
)
1450 v
= apic_read(APIC_LVT0
);
1451 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
1454 static void ack_lapic_irq (unsigned int irq
)
1459 static void end_lapic_irq (unsigned int i
) { /* nothing */ }
1461 static struct hw_interrupt_type lapic_irq_type __read_mostly
= {
1462 .typename
= "local-APIC-edge",
1463 .startup
= NULL
, /* startup_irq() not used for IRQ0 */
1464 .shutdown
= NULL
, /* shutdown_irq() not used for IRQ0 */
1465 .enable
= enable_lapic_irq
,
1466 .disable
= disable_lapic_irq
,
1467 .ack
= ack_lapic_irq
,
1468 .end
= end_lapic_irq
,
1471 static void setup_nmi (void)
1474 * Dirty trick to enable the NMI watchdog ...
1475 * We put the 8259A master into AEOI mode and
1476 * unmask on all local APICs LVT0 as NMI.
1478 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1479 * is from Maciej W. Rozycki - so we do not have to EOI from
1480 * the NMI handler or the timer interrupt.
1482 printk(KERN_INFO
"activating NMI Watchdog ...");
1484 enable_NMI_through_LVT0(NULL
);
1490 * This looks a bit hackish but it's about the only one way of sending
1491 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1492 * not support the ExtINT mode, unfortunately. We need to send these
1493 * cycles as some i82489DX-based boards have glue logic that keeps the
1494 * 8259A interrupt line asserted until INTA. --macro
1496 static inline void unlock_ExtINT_logic(void)
1499 struct IO_APIC_route_entry entry0
, entry1
;
1500 unsigned char save_control
, save_freq_select
;
1501 unsigned long flags
;
1503 pin
= find_isa_irq_pin(8, mp_INT
);
1504 apic
= find_isa_irq_apic(8, mp_INT
);
1508 spin_lock_irqsave(&ioapic_lock
, flags
);
1509 *(((int *)&entry0
) + 1) = io_apic_read(apic
, 0x11 + 2 * pin
);
1510 *(((int *)&entry0
) + 0) = io_apic_read(apic
, 0x10 + 2 * pin
);
1511 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1512 clear_IO_APIC_pin(apic
, pin
);
1514 memset(&entry1
, 0, sizeof(entry1
));
1516 entry1
.dest_mode
= 0; /* physical delivery */
1517 entry1
.mask
= 0; /* unmask IRQ now */
1518 entry1
.dest
= hard_smp_processor_id();
1519 entry1
.delivery_mode
= dest_ExtINT
;
1520 entry1
.polarity
= entry0
.polarity
;
1524 spin_lock_irqsave(&ioapic_lock
, flags
);
1525 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry1
) + 1));
1526 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry1
) + 0));
1527 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1529 save_control
= CMOS_READ(RTC_CONTROL
);
1530 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
1531 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
1533 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
1538 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
1542 CMOS_WRITE(save_control
, RTC_CONTROL
);
1543 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
1544 clear_IO_APIC_pin(apic
, pin
);
1546 spin_lock_irqsave(&ioapic_lock
, flags
);
1547 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry0
) + 1));
1548 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry0
) + 0));
1549 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1553 * This code may look a bit paranoid, but it's supposed to cooperate with
1554 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1555 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1556 * fanatically on his truly buggy board.
1558 * FIXME: really need to revamp this for modern platforms only.
1560 static inline void check_timer(void)
1562 struct irq_cfg
*cfg
= irq_cfg
+ 0;
1563 int apic1
, pin1
, apic2
, pin2
;
1566 * get/set the timer IRQ vector:
1568 disable_8259A_irq(0);
1569 assign_irq_vector(0, TARGET_CPUS
);
1572 * Subtle, code in do_timer_interrupt() expects an AEOI
1573 * mode for the 8259A whenever interrupts are routed
1574 * through I/O APICs. Also IRQ0 has to be enabled in
1575 * the 8259A which implies the virtual wire has to be
1576 * disabled in the local APIC.
1578 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1580 if (timer_over_8254
> 0)
1581 enable_8259A_irq(0);
1583 pin1
= find_isa_irq_pin(0, mp_INT
);
1584 apic1
= find_isa_irq_apic(0, mp_INT
);
1585 pin2
= ioapic_i8259
.pin
;
1586 apic2
= ioapic_i8259
.apic
;
1588 apic_printk(APIC_VERBOSE
,KERN_INFO
"..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1589 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
1593 * Ok, does IRQ0 through the IOAPIC work?
1595 unmask_IO_APIC_irq(0);
1596 if (!no_timer_check
&& timer_irq_works()) {
1597 nmi_watchdog_default();
1598 if (nmi_watchdog
== NMI_IO_APIC
) {
1599 disable_8259A_irq(0);
1601 enable_8259A_irq(0);
1603 if (disable_timer_pin_1
> 0)
1604 clear_IO_APIC_pin(0, pin1
);
1607 clear_IO_APIC_pin(apic1
, pin1
);
1608 apic_printk(APIC_QUIET
,KERN_ERR
"..MP-BIOS bug: 8254 timer not "
1609 "connected to IO-APIC\n");
1612 apic_printk(APIC_VERBOSE
,KERN_INFO
"...trying to set up timer (IRQ0) "
1613 "through the 8259A ... ");
1615 apic_printk(APIC_VERBOSE
,"\n..... (found apic %d pin %d) ...",
1618 * legacy devices should be connected to IO APIC #0
1620 setup_ExtINT_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
1621 if (timer_irq_works()) {
1622 apic_printk(APIC_VERBOSE
," works.\n");
1623 nmi_watchdog_default();
1624 if (nmi_watchdog
== NMI_IO_APIC
) {
1630 * Cleanup, just in case ...
1632 clear_IO_APIC_pin(apic2
, pin2
);
1634 apic_printk(APIC_VERBOSE
," failed.\n");
1636 if (nmi_watchdog
== NMI_IO_APIC
) {
1637 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1641 apic_printk(APIC_VERBOSE
, KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
1643 disable_8259A_irq(0);
1644 irq_desc
[0].chip
= &lapic_irq_type
;
1645 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
1646 enable_8259A_irq(0);
1648 if (timer_irq_works()) {
1649 apic_printk(APIC_VERBOSE
," works.\n");
1652 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
1653 apic_printk(APIC_VERBOSE
," failed.\n");
1655 apic_printk(APIC_VERBOSE
, KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
1659 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1661 unlock_ExtINT_logic();
1663 if (timer_irq_works()) {
1664 apic_printk(APIC_VERBOSE
," works.\n");
1667 apic_printk(APIC_VERBOSE
," failed :(.\n");
1668 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1671 static int __init
notimercheck(char *s
)
1676 __setup("no_timer_check", notimercheck
);
1680 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1681 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1682 * Linux doesn't really care, as it's not actually used
1683 * for any interrupt handling anyway.
1685 #define PIC_IRQS (1<<2)
1687 void __init
setup_IO_APIC(void)
1692 io_apic_irqs
= ~0; /* all IRQs go through IOAPIC */
1694 io_apic_irqs
= ~PIC_IRQS
;
1696 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
1699 setup_IO_APIC_irqs();
1700 init_IO_APIC_traps();
1706 struct sysfs_ioapic_data
{
1707 struct sys_device dev
;
1708 struct IO_APIC_route_entry entry
[0];
1710 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
1712 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1714 struct IO_APIC_route_entry
*entry
;
1715 struct sysfs_ioapic_data
*data
;
1718 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
1719 entry
= data
->entry
;
1720 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
1721 *entry
= ioapic_read_entry(dev
->id
, i
);
1726 static int ioapic_resume(struct sys_device
*dev
)
1728 struct IO_APIC_route_entry
*entry
;
1729 struct sysfs_ioapic_data
*data
;
1730 unsigned long flags
;
1731 union IO_APIC_reg_00 reg_00
;
1734 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
1735 entry
= data
->entry
;
1737 spin_lock_irqsave(&ioapic_lock
, flags
);
1738 reg_00
.raw
= io_apic_read(dev
->id
, 0);
1739 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mpc_apicid
) {
1740 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mpc_apicid
;
1741 io_apic_write(dev
->id
, 0, reg_00
.raw
);
1743 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1744 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
1745 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
1750 static struct sysdev_class ioapic_sysdev_class
= {
1751 set_kset_name("ioapic"),
1752 .suspend
= ioapic_suspend
,
1753 .resume
= ioapic_resume
,
1756 static int __init
ioapic_init_sysfs(void)
1758 struct sys_device
* dev
;
1759 int i
, size
, error
= 0;
1761 error
= sysdev_class_register(&ioapic_sysdev_class
);
1765 for (i
= 0; i
< nr_ioapics
; i
++ ) {
1766 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
1767 * sizeof(struct IO_APIC_route_entry
);
1768 mp_ioapic_data
[i
] = kmalloc(size
, GFP_KERNEL
);
1769 if (!mp_ioapic_data
[i
]) {
1770 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
1773 memset(mp_ioapic_data
[i
], 0, size
);
1774 dev
= &mp_ioapic_data
[i
]->dev
;
1776 dev
->cls
= &ioapic_sysdev_class
;
1777 error
= sysdev_register(dev
);
1779 kfree(mp_ioapic_data
[i
]);
1780 mp_ioapic_data
[i
] = NULL
;
1781 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
1789 device_initcall(ioapic_init_sysfs
);
1792 * Dynamic irq allocate and deallocation
1794 int create_irq(void)
1796 /* Allocate an unused irq */
1799 unsigned long flags
;
1802 spin_lock_irqsave(&vector_lock
, flags
);
1803 for (new = (NR_IRQS
- 1); new >= 0; new--) {
1804 if (platform_legacy_irq(new))
1806 if (irq_cfg
[new].vector
!= 0)
1808 if (__assign_irq_vector(new, TARGET_CPUS
) == 0)
1812 spin_unlock_irqrestore(&vector_lock
, flags
);
1815 dynamic_irq_init(irq
);
1820 void destroy_irq(unsigned int irq
)
1822 unsigned long flags
;
1824 dynamic_irq_cleanup(irq
);
1826 spin_lock_irqsave(&vector_lock
, flags
);
1827 __clear_irq_vector(irq
);
1828 spin_unlock_irqrestore(&vector_lock
, flags
);
1832 * MSI mesage composition
1834 #ifdef CONFIG_PCI_MSI
1835 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
1837 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1843 err
= assign_irq_vector(irq
, tmp
);
1845 cpus_and(tmp
, cfg
->domain
, tmp
);
1846 dest
= cpu_mask_to_apicid(tmp
);
1848 msg
->address_hi
= MSI_ADDR_BASE_HI
;
1851 ((INT_DEST_MODE
== 0) ?
1852 MSI_ADDR_DEST_MODE_PHYSICAL
:
1853 MSI_ADDR_DEST_MODE_LOGICAL
) |
1854 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
1855 MSI_ADDR_REDIRECTION_CPU
:
1856 MSI_ADDR_REDIRECTION_LOWPRI
) |
1857 MSI_ADDR_DEST_ID(dest
);
1860 MSI_DATA_TRIGGER_EDGE
|
1861 MSI_DATA_LEVEL_ASSERT
|
1862 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
1863 MSI_DATA_DELIVERY_FIXED
:
1864 MSI_DATA_DELIVERY_LOWPRI
) |
1865 MSI_DATA_VECTOR(cfg
->vector
);
1871 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
1873 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1878 cpus_and(tmp
, mask
, cpu_online_map
);
1879 if (cpus_empty(tmp
))
1882 if (assign_irq_vector(irq
, mask
))
1885 cpus_and(tmp
, cfg
->domain
, mask
);
1886 dest
= cpu_mask_to_apicid(tmp
);
1888 read_msi_msg(irq
, &msg
);
1890 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
1891 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
1892 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
1893 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
1895 write_msi_msg(irq
, &msg
);
1896 irq_desc
[irq
].affinity
= mask
;
1898 #endif /* CONFIG_SMP */
1901 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1902 * which implement the MSI or MSI-X Capability Structure.
1904 static struct irq_chip msi_chip
= {
1906 .unmask
= unmask_msi_irq
,
1907 .mask
= mask_msi_irq
,
1908 .ack
= ack_apic_edge
,
1910 .set_affinity
= set_msi_irq_affinity
,
1912 .retrigger
= ioapic_retrigger_irq
,
1915 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
1923 set_irq_msi(irq
, desc
);
1924 ret
= msi_compose_msg(dev
, irq
, &msg
);
1930 write_msi_msg(irq
, &msg
);
1932 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
1937 void arch_teardown_msi_irq(unsigned int irq
)
1942 #endif /* CONFIG_PCI_MSI */
1945 * Hypertransport interrupt support
1947 #ifdef CONFIG_HT_IRQ
1951 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
1953 struct ht_irq_msg msg
;
1954 fetch_ht_irq_msg(irq
, &msg
);
1956 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
1957 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
1959 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
1960 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
1962 write_ht_irq_msg(irq
, &msg
);
1965 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
1967 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
1971 cpus_and(tmp
, mask
, cpu_online_map
);
1972 if (cpus_empty(tmp
))
1975 if (assign_irq_vector(irq
, mask
))
1978 cpus_and(tmp
, cfg
->domain
, mask
);
1979 dest
= cpu_mask_to_apicid(tmp
);
1981 target_ht_irq(irq
, dest
, cfg
->vector
);
1982 irq_desc
[irq
].affinity
= mask
;
1986 static struct irq_chip ht_irq_chip
= {
1988 .mask
= mask_ht_irq
,
1989 .unmask
= unmask_ht_irq
,
1990 .ack
= ack_apic_edge
,
1992 .set_affinity
= set_ht_irq_affinity
,
1994 .retrigger
= ioapic_retrigger_irq
,
1997 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
1999 struct irq_cfg
*cfg
= irq_cfg
+ irq
;
2004 err
= assign_irq_vector(irq
, tmp
);
2006 struct ht_irq_msg msg
;
2009 cpus_and(tmp
, cfg
->domain
, tmp
);
2010 dest
= cpu_mask_to_apicid(tmp
);
2012 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2016 HT_IRQ_LOW_DEST_ID(dest
) |
2017 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
2018 ((INT_DEST_MODE
== 0) ?
2019 HT_IRQ_LOW_DM_PHYSICAL
:
2020 HT_IRQ_LOW_DM_LOGICAL
) |
2021 HT_IRQ_LOW_RQEOI_EDGE
|
2022 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2023 HT_IRQ_LOW_MT_FIXED
:
2024 HT_IRQ_LOW_MT_ARBITRATED
) |
2025 HT_IRQ_LOW_IRQ_MASKED
;
2027 write_ht_irq_msg(irq
, &msg
);
2029 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2030 handle_edge_irq
, "edge");
2034 #endif /* CONFIG_HT_IRQ */
2036 /* --------------------------------------------------------------------------
2037 ACPI-based IOAPIC Configuration
2038 -------------------------------------------------------------------------- */
2042 #define IO_APIC_MAX_ID 0xFE
2044 int __init
io_apic_get_redir_entries (int ioapic
)
2046 union IO_APIC_reg_01 reg_01
;
2047 unsigned long flags
;
2049 spin_lock_irqsave(&ioapic_lock
, flags
);
2050 reg_01
.raw
= io_apic_read(ioapic
, 1);
2051 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2053 return reg_01
.bits
.entries
;
2057 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
2059 if (!IO_APIC_IRQ(irq
)) {
2060 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2066 * IRQs < 16 are already in the irq_2_pin[] map
2069 add_pin_to_irq(irq
, ioapic
, pin
);
2071 setup_IO_APIC_irq(ioapic
, pin
, irq
, triggering
, polarity
);
2076 #endif /* CONFIG_ACPI */
2080 * This function currently is only a helper for the i386 smp boot process where
2081 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2082 * so mask in all cases should simply be TARGET_CPUS
2085 void __init
setup_ioapic_dest(void)
2087 int pin
, ioapic
, irq
, irq_entry
;
2089 if (skip_ioapic_setup
== 1)
2092 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
2093 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
2094 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
2095 if (irq_entry
== -1)
2097 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
2099 /* setup_IO_APIC_irqs could fail to get vector for some device
2100 * when you have too many devices, because at that time only boot
2103 if (!irq_cfg
[irq
].vector
)
2104 setup_IO_APIC_irq(ioapic
, pin
, irq
,
2105 irq_trigger(irq_entry
),
2106 irq_polarity(irq_entry
));
2108 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);