2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
34 #include "intel_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
40 #include "drm_crtc_helper.h"
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
);
45 static void intel_update_watermarks(struct drm_device
*dev
);
46 static void intel_increase_pllclock(struct drm_crtc
*crtc
, bool schedule
);
47 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
);
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t
;
73 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
75 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
76 int, int, intel_clock_t
*);
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
90 #define I8XX_M2_MAX 16
92 #define I8XX_P_MAX 128
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
253 /* We have parameter ranges for different type of outputs. */
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
332 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
333 int target
, int refclk
, intel_clock_t
*best_clock
);
335 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
336 int target
, int refclk
, intel_clock_t
*best_clock
);
339 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
340 int target
, int refclk
, intel_clock_t
*best_clock
);
342 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
343 int target
, int refclk
, intel_clock_t
*best_clock
);
345 static const intel_limit_t intel_limits_i8xx_dvo
= {
346 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
347 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
348 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
349 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
350 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
351 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
352 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
353 .p1
= { .min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
354 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
355 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
356 .find_pll
= intel_find_best_PLL
,
359 static const intel_limit_t intel_limits_i8xx_lvds
= {
360 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
361 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
362 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
363 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
364 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
365 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
366 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
367 .p1
= { .min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
368 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
369 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
370 .find_pll
= intel_find_best_PLL
,
373 static const intel_limit_t intel_limits_i9xx_sdvo
= {
374 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
375 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
376 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
377 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
378 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
379 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
380 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
381 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
382 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
383 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
384 .find_pll
= intel_find_best_PLL
,
387 static const intel_limit_t intel_limits_i9xx_lvds
= {
388 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
389 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
390 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
391 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
392 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
393 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
394 .p
= { .min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
395 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
396 /* The single-channel range is 25-112Mhz, and dual-channel
397 * is 80-224Mhz. Prefer single channel as much as possible.
399 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
400 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
401 .find_pll
= intel_find_best_PLL
,
404 /* below parameter and function is for G4X Chipset Family*/
405 static const intel_limit_t intel_limits_g4x_sdvo
= {
406 .dot
= { .min
= G4X_DOT_SDVO_MIN
, .max
= G4X_DOT_SDVO_MAX
},
407 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
408 .n
= { .min
= G4X_N_SDVO_MIN
, .max
= G4X_N_SDVO_MAX
},
409 .m
= { .min
= G4X_M_SDVO_MIN
, .max
= G4X_M_SDVO_MAX
},
410 .m1
= { .min
= G4X_M1_SDVO_MIN
, .max
= G4X_M1_SDVO_MAX
},
411 .m2
= { .min
= G4X_M2_SDVO_MIN
, .max
= G4X_M2_SDVO_MAX
},
412 .p
= { .min
= G4X_P_SDVO_MIN
, .max
= G4X_P_SDVO_MAX
},
413 .p1
= { .min
= G4X_P1_SDVO_MIN
, .max
= G4X_P1_SDVO_MAX
},
414 .p2
= { .dot_limit
= G4X_P2_SDVO_LIMIT
,
415 .p2_slow
= G4X_P2_SDVO_SLOW
,
416 .p2_fast
= G4X_P2_SDVO_FAST
418 .find_pll
= intel_g4x_find_best_PLL
,
421 static const intel_limit_t intel_limits_g4x_hdmi
= {
422 .dot
= { .min
= G4X_DOT_HDMI_DAC_MIN
, .max
= G4X_DOT_HDMI_DAC_MAX
},
423 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
424 .n
= { .min
= G4X_N_HDMI_DAC_MIN
, .max
= G4X_N_HDMI_DAC_MAX
},
425 .m
= { .min
= G4X_M_HDMI_DAC_MIN
, .max
= G4X_M_HDMI_DAC_MAX
},
426 .m1
= { .min
= G4X_M1_HDMI_DAC_MIN
, .max
= G4X_M1_HDMI_DAC_MAX
},
427 .m2
= { .min
= G4X_M2_HDMI_DAC_MIN
, .max
= G4X_M2_HDMI_DAC_MAX
},
428 .p
= { .min
= G4X_P_HDMI_DAC_MIN
, .max
= G4X_P_HDMI_DAC_MAX
},
429 .p1
= { .min
= G4X_P1_HDMI_DAC_MIN
, .max
= G4X_P1_HDMI_DAC_MAX
},
430 .p2
= { .dot_limit
= G4X_P2_HDMI_DAC_LIMIT
,
431 .p2_slow
= G4X_P2_HDMI_DAC_SLOW
,
432 .p2_fast
= G4X_P2_HDMI_DAC_FAST
434 .find_pll
= intel_g4x_find_best_PLL
,
437 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
438 .dot
= { .min
= G4X_DOT_SINGLE_CHANNEL_LVDS_MIN
,
439 .max
= G4X_DOT_SINGLE_CHANNEL_LVDS_MAX
},
440 .vco
= { .min
= G4X_VCO_MIN
,
441 .max
= G4X_VCO_MAX
},
442 .n
= { .min
= G4X_N_SINGLE_CHANNEL_LVDS_MIN
,
443 .max
= G4X_N_SINGLE_CHANNEL_LVDS_MAX
},
444 .m
= { .min
= G4X_M_SINGLE_CHANNEL_LVDS_MIN
,
445 .max
= G4X_M_SINGLE_CHANNEL_LVDS_MAX
},
446 .m1
= { .min
= G4X_M1_SINGLE_CHANNEL_LVDS_MIN
,
447 .max
= G4X_M1_SINGLE_CHANNEL_LVDS_MAX
},
448 .m2
= { .min
= G4X_M2_SINGLE_CHANNEL_LVDS_MIN
,
449 .max
= G4X_M2_SINGLE_CHANNEL_LVDS_MAX
},
450 .p
= { .min
= G4X_P_SINGLE_CHANNEL_LVDS_MIN
,
451 .max
= G4X_P_SINGLE_CHANNEL_LVDS_MAX
},
452 .p1
= { .min
= G4X_P1_SINGLE_CHANNEL_LVDS_MIN
,
453 .max
= G4X_P1_SINGLE_CHANNEL_LVDS_MAX
},
454 .p2
= { .dot_limit
= G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT
,
455 .p2_slow
= G4X_P2_SINGLE_CHANNEL_LVDS_SLOW
,
456 .p2_fast
= G4X_P2_SINGLE_CHANNEL_LVDS_FAST
458 .find_pll
= intel_g4x_find_best_PLL
,
461 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
462 .dot
= { .min
= G4X_DOT_DUAL_CHANNEL_LVDS_MIN
,
463 .max
= G4X_DOT_DUAL_CHANNEL_LVDS_MAX
},
464 .vco
= { .min
= G4X_VCO_MIN
,
465 .max
= G4X_VCO_MAX
},
466 .n
= { .min
= G4X_N_DUAL_CHANNEL_LVDS_MIN
,
467 .max
= G4X_N_DUAL_CHANNEL_LVDS_MAX
},
468 .m
= { .min
= G4X_M_DUAL_CHANNEL_LVDS_MIN
,
469 .max
= G4X_M_DUAL_CHANNEL_LVDS_MAX
},
470 .m1
= { .min
= G4X_M1_DUAL_CHANNEL_LVDS_MIN
,
471 .max
= G4X_M1_DUAL_CHANNEL_LVDS_MAX
},
472 .m2
= { .min
= G4X_M2_DUAL_CHANNEL_LVDS_MIN
,
473 .max
= G4X_M2_DUAL_CHANNEL_LVDS_MAX
},
474 .p
= { .min
= G4X_P_DUAL_CHANNEL_LVDS_MIN
,
475 .max
= G4X_P_DUAL_CHANNEL_LVDS_MAX
},
476 .p1
= { .min
= G4X_P1_DUAL_CHANNEL_LVDS_MIN
,
477 .max
= G4X_P1_DUAL_CHANNEL_LVDS_MAX
},
478 .p2
= { .dot_limit
= G4X_P2_DUAL_CHANNEL_LVDS_LIMIT
,
479 .p2_slow
= G4X_P2_DUAL_CHANNEL_LVDS_SLOW
,
480 .p2_fast
= G4X_P2_DUAL_CHANNEL_LVDS_FAST
482 .find_pll
= intel_g4x_find_best_PLL
,
485 static const intel_limit_t intel_limits_g4x_display_port
= {
486 .dot
= { .min
= G4X_DOT_DISPLAY_PORT_MIN
,
487 .max
= G4X_DOT_DISPLAY_PORT_MAX
},
488 .vco
= { .min
= G4X_VCO_MIN
,
490 .n
= { .min
= G4X_N_DISPLAY_PORT_MIN
,
491 .max
= G4X_N_DISPLAY_PORT_MAX
},
492 .m
= { .min
= G4X_M_DISPLAY_PORT_MIN
,
493 .max
= G4X_M_DISPLAY_PORT_MAX
},
494 .m1
= { .min
= G4X_M1_DISPLAY_PORT_MIN
,
495 .max
= G4X_M1_DISPLAY_PORT_MAX
},
496 .m2
= { .min
= G4X_M2_DISPLAY_PORT_MIN
,
497 .max
= G4X_M2_DISPLAY_PORT_MAX
},
498 .p
= { .min
= G4X_P_DISPLAY_PORT_MIN
,
499 .max
= G4X_P_DISPLAY_PORT_MAX
},
500 .p1
= { .min
= G4X_P1_DISPLAY_PORT_MIN
,
501 .max
= G4X_P1_DISPLAY_PORT_MAX
},
502 .p2
= { .dot_limit
= G4X_P2_DISPLAY_PORT_LIMIT
,
503 .p2_slow
= G4X_P2_DISPLAY_PORT_SLOW
,
504 .p2_fast
= G4X_P2_DISPLAY_PORT_FAST
},
505 .find_pll
= intel_find_pll_g4x_dp
,
508 static const intel_limit_t intel_limits_pineview_sdvo
= {
509 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
510 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
511 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
512 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
513 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
514 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
515 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
516 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
517 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
518 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
519 .find_pll
= intel_find_best_PLL
,
522 static const intel_limit_t intel_limits_pineview_lvds
= {
523 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
524 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
525 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
526 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
527 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
528 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
529 .p
= { .min
= PINEVIEW_P_LVDS_MIN
, .max
= PINEVIEW_P_LVDS_MAX
},
530 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
531 /* Pineview only supports single-channel mode. */
532 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
533 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_SLOW
},
534 .find_pll
= intel_find_best_PLL
,
537 static const intel_limit_t intel_limits_ironlake_dac
= {
538 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
539 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
540 .n
= { .min
= IRONLAKE_DAC_N_MIN
, .max
= IRONLAKE_DAC_N_MAX
},
541 .m
= { .min
= IRONLAKE_DAC_M_MIN
, .max
= IRONLAKE_DAC_M_MAX
},
542 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
543 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
544 .p
= { .min
= IRONLAKE_DAC_P_MIN
, .max
= IRONLAKE_DAC_P_MAX
},
545 .p1
= { .min
= IRONLAKE_DAC_P1_MIN
, .max
= IRONLAKE_DAC_P1_MAX
},
546 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
547 .p2_slow
= IRONLAKE_DAC_P2_SLOW
,
548 .p2_fast
= IRONLAKE_DAC_P2_FAST
},
549 .find_pll
= intel_g4x_find_best_PLL
,
552 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
553 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
554 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
555 .n
= { .min
= IRONLAKE_LVDS_S_N_MIN
, .max
= IRONLAKE_LVDS_S_N_MAX
},
556 .m
= { .min
= IRONLAKE_LVDS_S_M_MIN
, .max
= IRONLAKE_LVDS_S_M_MAX
},
557 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
558 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
559 .p
= { .min
= IRONLAKE_LVDS_S_P_MIN
, .max
= IRONLAKE_LVDS_S_P_MAX
},
560 .p1
= { .min
= IRONLAKE_LVDS_S_P1_MIN
, .max
= IRONLAKE_LVDS_S_P1_MAX
},
561 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
562 .p2_slow
= IRONLAKE_LVDS_S_P2_SLOW
,
563 .p2_fast
= IRONLAKE_LVDS_S_P2_FAST
},
564 .find_pll
= intel_g4x_find_best_PLL
,
567 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
568 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
569 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
570 .n
= { .min
= IRONLAKE_LVDS_D_N_MIN
, .max
= IRONLAKE_LVDS_D_N_MAX
},
571 .m
= { .min
= IRONLAKE_LVDS_D_M_MIN
, .max
= IRONLAKE_LVDS_D_M_MAX
},
572 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
573 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
574 .p
= { .min
= IRONLAKE_LVDS_D_P_MIN
, .max
= IRONLAKE_LVDS_D_P_MAX
},
575 .p1
= { .min
= IRONLAKE_LVDS_D_P1_MIN
, .max
= IRONLAKE_LVDS_D_P1_MAX
},
576 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
577 .p2_slow
= IRONLAKE_LVDS_D_P2_SLOW
,
578 .p2_fast
= IRONLAKE_LVDS_D_P2_FAST
},
579 .find_pll
= intel_g4x_find_best_PLL
,
582 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
583 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
584 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
585 .n
= { .min
= IRONLAKE_LVDS_S_SSC_N_MIN
, .max
= IRONLAKE_LVDS_S_SSC_N_MAX
},
586 .m
= { .min
= IRONLAKE_LVDS_S_SSC_M_MIN
, .max
= IRONLAKE_LVDS_S_SSC_M_MAX
},
587 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
588 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
589 .p
= { .min
= IRONLAKE_LVDS_S_SSC_P_MIN
, .max
= IRONLAKE_LVDS_S_SSC_P_MAX
},
590 .p1
= { .min
= IRONLAKE_LVDS_S_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_S_SSC_P1_MAX
},
591 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
592 .p2_slow
= IRONLAKE_LVDS_S_SSC_P2_SLOW
,
593 .p2_fast
= IRONLAKE_LVDS_S_SSC_P2_FAST
},
594 .find_pll
= intel_g4x_find_best_PLL
,
597 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
598 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
599 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
600 .n
= { .min
= IRONLAKE_LVDS_D_SSC_N_MIN
, .max
= IRONLAKE_LVDS_D_SSC_N_MAX
},
601 .m
= { .min
= IRONLAKE_LVDS_D_SSC_M_MIN
, .max
= IRONLAKE_LVDS_D_SSC_M_MAX
},
602 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
603 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
604 .p
= { .min
= IRONLAKE_LVDS_D_SSC_P_MIN
, .max
= IRONLAKE_LVDS_D_SSC_P_MAX
},
605 .p1
= { .min
= IRONLAKE_LVDS_D_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_D_SSC_P1_MAX
},
606 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
607 .p2_slow
= IRONLAKE_LVDS_D_SSC_P2_SLOW
,
608 .p2_fast
= IRONLAKE_LVDS_D_SSC_P2_FAST
},
609 .find_pll
= intel_g4x_find_best_PLL
,
612 static const intel_limit_t intel_limits_ironlake_display_port
= {
613 .dot
= { .min
= IRONLAKE_DOT_MIN
,
614 .max
= IRONLAKE_DOT_MAX
},
615 .vco
= { .min
= IRONLAKE_VCO_MIN
,
616 .max
= IRONLAKE_VCO_MAX
},
617 .n
= { .min
= IRONLAKE_DP_N_MIN
,
618 .max
= IRONLAKE_DP_N_MAX
},
619 .m
= { .min
= IRONLAKE_DP_M_MIN
,
620 .max
= IRONLAKE_DP_M_MAX
},
621 .m1
= { .min
= IRONLAKE_M1_MIN
,
622 .max
= IRONLAKE_M1_MAX
},
623 .m2
= { .min
= IRONLAKE_M2_MIN
,
624 .max
= IRONLAKE_M2_MAX
},
625 .p
= { .min
= IRONLAKE_DP_P_MIN
,
626 .max
= IRONLAKE_DP_P_MAX
},
627 .p1
= { .min
= IRONLAKE_DP_P1_MIN
,
628 .max
= IRONLAKE_DP_P1_MAX
},
629 .p2
= { .dot_limit
= IRONLAKE_DP_P2_LIMIT
,
630 .p2_slow
= IRONLAKE_DP_P2_SLOW
,
631 .p2_fast
= IRONLAKE_DP_P2_FAST
},
632 .find_pll
= intel_find_pll_ironlake_dp
,
635 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
)
637 struct drm_device
*dev
= crtc
->dev
;
638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
639 const intel_limit_t
*limit
;
642 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
643 if (dev_priv
->lvds_use_ssc
&& dev_priv
->lvds_ssc_freq
== 100)
646 if ((I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) ==
647 LVDS_CLKB_POWER_UP
) {
648 /* LVDS dual channel */
650 limit
= &intel_limits_ironlake_dual_lvds_100m
;
652 limit
= &intel_limits_ironlake_dual_lvds
;
655 limit
= &intel_limits_ironlake_single_lvds_100m
;
657 limit
= &intel_limits_ironlake_single_lvds
;
659 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
661 limit
= &intel_limits_ironlake_display_port
;
663 limit
= &intel_limits_ironlake_dac
;
668 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
670 struct drm_device
*dev
= crtc
->dev
;
671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
672 const intel_limit_t
*limit
;
674 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
675 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
677 /* LVDS with dual channel */
678 limit
= &intel_limits_g4x_dual_channel_lvds
;
680 /* LVDS with dual channel */
681 limit
= &intel_limits_g4x_single_channel_lvds
;
682 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
683 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
684 limit
= &intel_limits_g4x_hdmi
;
685 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
686 limit
= &intel_limits_g4x_sdvo
;
687 } else if (intel_pipe_has_type (crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
688 limit
= &intel_limits_g4x_display_port
;
689 } else /* The option is for other outputs */
690 limit
= &intel_limits_i9xx_sdvo
;
695 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
)
697 struct drm_device
*dev
= crtc
->dev
;
698 const intel_limit_t
*limit
;
700 if (HAS_PCH_SPLIT(dev
))
701 limit
= intel_ironlake_limit(crtc
);
702 else if (IS_G4X(dev
)) {
703 limit
= intel_g4x_limit(crtc
);
704 } else if (IS_I9XX(dev
) && !IS_PINEVIEW(dev
)) {
705 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
706 limit
= &intel_limits_i9xx_lvds
;
708 limit
= &intel_limits_i9xx_sdvo
;
709 } else if (IS_PINEVIEW(dev
)) {
710 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
711 limit
= &intel_limits_pineview_lvds
;
713 limit
= &intel_limits_pineview_sdvo
;
715 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
716 limit
= &intel_limits_i8xx_lvds
;
718 limit
= &intel_limits_i8xx_dvo
;
723 /* m1 is reserved as 0 in Pineview, n is a ring counter */
724 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
726 clock
->m
= clock
->m2
+ 2;
727 clock
->p
= clock
->p1
* clock
->p2
;
728 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
729 clock
->dot
= clock
->vco
/ clock
->p
;
732 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
734 if (IS_PINEVIEW(dev
)) {
735 pineview_clock(refclk
, clock
);
738 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
739 clock
->p
= clock
->p1
* clock
->p2
;
740 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
741 clock
->dot
= clock
->vco
/ clock
->p
;
745 * Returns whether any output on the specified pipe is of the specified type
747 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
)
749 struct drm_device
*dev
= crtc
->dev
;
750 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
751 struct drm_encoder
*l_entry
;
753 list_for_each_entry(l_entry
, &mode_config
->encoder_list
, head
) {
754 if (l_entry
&& l_entry
->crtc
== crtc
) {
755 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(l_entry
);
756 if (intel_encoder
->type
== type
)
763 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
765 * Returns whether the given set of divisors are valid for a given refclk with
766 * the given connectors.
769 static bool intel_PLL_is_valid(struct drm_crtc
*crtc
, intel_clock_t
*clock
)
771 const intel_limit_t
*limit
= intel_limit (crtc
);
772 struct drm_device
*dev
= crtc
->dev
;
774 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
775 INTELPllInvalid ("p1 out of range\n");
776 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
777 INTELPllInvalid ("p out of range\n");
778 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
779 INTELPllInvalid ("m2 out of range\n");
780 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
781 INTELPllInvalid ("m1 out of range\n");
782 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
783 INTELPllInvalid ("m1 <= m2\n");
784 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
785 INTELPllInvalid ("m out of range\n");
786 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
787 INTELPllInvalid ("n out of range\n");
788 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
789 INTELPllInvalid ("vco out of range\n");
790 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
791 * connector, etc., rather than just a single range.
793 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
794 INTELPllInvalid ("dot out of range\n");
800 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
801 int target
, int refclk
, intel_clock_t
*best_clock
)
804 struct drm_device
*dev
= crtc
->dev
;
805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
809 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
810 (I915_READ(LVDS
)) != 0) {
812 * For LVDS, if the panel is on, just rely on its current
813 * settings for dual-channel. We haven't figured out how to
814 * reliably set up different single/dual channel state, if we
817 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
819 clock
.p2
= limit
->p2
.p2_fast
;
821 clock
.p2
= limit
->p2
.p2_slow
;
823 if (target
< limit
->p2
.dot_limit
)
824 clock
.p2
= limit
->p2
.p2_slow
;
826 clock
.p2
= limit
->p2
.p2_fast
;
829 memset (best_clock
, 0, sizeof (*best_clock
));
831 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
833 for (clock
.m2
= limit
->m2
.min
;
834 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
835 /* m1 is always 0 in Pineview */
836 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
838 for (clock
.n
= limit
->n
.min
;
839 clock
.n
<= limit
->n
.max
; clock
.n
++) {
840 for (clock
.p1
= limit
->p1
.min
;
841 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
844 intel_clock(dev
, refclk
, &clock
);
846 if (!intel_PLL_is_valid(crtc
, &clock
))
849 this_err
= abs(clock
.dot
- target
);
850 if (this_err
< err
) {
859 return (err
!= target
);
863 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
864 int target
, int refclk
, intel_clock_t
*best_clock
)
866 struct drm_device
*dev
= crtc
->dev
;
867 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
871 /* approximately equals target * 0.00585 */
872 int err_most
= (target
>> 8) + (target
>> 9);
875 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
878 if (HAS_PCH_SPLIT(dev
))
882 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
884 clock
.p2
= limit
->p2
.p2_fast
;
886 clock
.p2
= limit
->p2
.p2_slow
;
888 if (target
< limit
->p2
.dot_limit
)
889 clock
.p2
= limit
->p2
.p2_slow
;
891 clock
.p2
= limit
->p2
.p2_fast
;
894 memset(best_clock
, 0, sizeof(*best_clock
));
895 max_n
= limit
->n
.max
;
896 /* based on hardware requirement, prefer smaller n to precision */
897 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
898 /* based on hardware requirement, prefere larger m1,m2 */
899 for (clock
.m1
= limit
->m1
.max
;
900 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
901 for (clock
.m2
= limit
->m2
.max
;
902 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
903 for (clock
.p1
= limit
->p1
.max
;
904 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
907 intel_clock(dev
, refclk
, &clock
);
908 if (!intel_PLL_is_valid(crtc
, &clock
))
910 this_err
= abs(clock
.dot
- target
) ;
911 if (this_err
< err_most
) {
925 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
926 int target
, int refclk
, intel_clock_t
*best_clock
)
928 struct drm_device
*dev
= crtc
->dev
;
931 /* return directly when it is eDP */
935 if (target
< 200000) {
948 intel_clock(dev
, refclk
, &clock
);
949 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
953 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
955 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
956 int target
, int refclk
, intel_clock_t
*best_clock
)
959 if (target
< 200000) {
972 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
973 clock
.p
= (clock
.p1
* clock
.p2
);
974 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
976 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
981 * intel_wait_for_vblank - wait for vblank on a given pipe
983 * @pipe: pipe to wait for
985 * Wait for vblank to occur on a given pipe. Needed for various bits of
988 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
991 int pipestat_reg
= (pipe
== 0 ? PIPEASTAT
: PIPEBSTAT
);
993 /* Clear existing vblank status. Note this will clear any other
994 * sticky status fields as well.
996 * This races with i915_driver_irq_handler() with the result
997 * that either function could miss a vblank event. Here it is not
998 * fatal, as we will either wait upon the next vblank interrupt or
999 * timeout. Generally speaking intel_wait_for_vblank() is only
1000 * called during modeset at which time the GPU should be idle and
1001 * should *not* be performing page flips and thus not waiting on
1003 * Currently, the result of us stealing a vblank from the irq
1004 * handler is that a single frame will be skipped during swapbuffers.
1006 I915_WRITE(pipestat_reg
,
1007 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
1009 /* Wait for vblank interrupt bit to set */
1010 if (wait_for((I915_READ(pipestat_reg
) &
1011 PIPE_VBLANK_INTERRUPT_STATUS
),
1013 DRM_DEBUG_KMS("vblank wait timed out\n");
1017 * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1019 * @pipe: pipe to wait for
1021 * After disabling a pipe, we can't wait for vblank in the usual way,
1022 * spinning on the vblank interrupt status bit, since we won't actually
1023 * see an interrupt when the pipe is disabled.
1025 * So this function waits for the display line value to settle (it
1026 * usually ends up stopping at the start of the next frame).
1028 void intel_wait_for_vblank_off(struct drm_device
*dev
, int pipe
)
1030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1031 int pipedsl_reg
= (pipe
== 0 ? PIPEADSL
: PIPEBDSL
);
1032 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
1035 /* Wait for the display line to settle */
1037 last_line
= I915_READ(pipedsl_reg
) & DSL_LINEMASK
;
1039 } while (((I915_READ(pipedsl_reg
) & DSL_LINEMASK
) != last_line
) &&
1040 time_after(timeout
, jiffies
));
1042 if (time_after(jiffies
, timeout
))
1043 DRM_DEBUG_KMS("vblank wait timed out\n");
1046 /* Parameters have changed, update FBC info */
1047 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1049 struct drm_device
*dev
= crtc
->dev
;
1050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1051 struct drm_framebuffer
*fb
= crtc
->fb
;
1052 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1053 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
1054 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1056 u32 fbc_ctl
, fbc_ctl2
;
1058 dev_priv
->cfb_pitch
= dev_priv
->cfb_size
/ FBC_LL_SIZE
;
1060 if (fb
->pitch
< dev_priv
->cfb_pitch
)
1061 dev_priv
->cfb_pitch
= fb
->pitch
;
1063 /* FBC_CTL wants 64B units */
1064 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1065 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1066 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1067 plane
= dev_priv
->cfb_plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
1069 /* Clear old tags */
1070 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
1071 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
1074 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| plane
;
1075 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1076 fbc_ctl2
|= FBC_CTL_CPU_FENCE
;
1077 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
1078 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
1081 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
1083 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
1084 fbc_ctl
|= (dev_priv
->cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
1085 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
1086 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1087 fbc_ctl
|= dev_priv
->cfb_fence
;
1088 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1090 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1091 dev_priv
->cfb_pitch
, crtc
->y
, dev_priv
->cfb_plane
);
1094 void i8xx_disable_fbc(struct drm_device
*dev
)
1096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1099 if (!I915_HAS_FBC(dev
))
1102 if (!(I915_READ(FBC_CONTROL
) & FBC_CTL_EN
))
1103 return; /* Already off, just return */
1105 /* Disable compression */
1106 fbc_ctl
= I915_READ(FBC_CONTROL
);
1107 fbc_ctl
&= ~FBC_CTL_EN
;
1108 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1110 /* Wait for compressing bit to clear */
1111 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10, 0)) {
1112 DRM_DEBUG_KMS("FBC idle timed out\n");
1116 DRM_DEBUG_KMS("disabled FBC\n");
1119 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
1121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1123 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
1126 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1128 struct drm_device
*dev
= crtc
->dev
;
1129 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1130 struct drm_framebuffer
*fb
= crtc
->fb
;
1131 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1132 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
1133 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1134 int plane
= (intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
:
1136 unsigned long stall_watermark
= 200;
1139 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1140 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1141 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1143 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
1144 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1145 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
;
1146 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1148 I915_WRITE(DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1151 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1152 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1153 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1154 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1155 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
1158 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
1160 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1163 void g4x_disable_fbc(struct drm_device
*dev
)
1165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1168 /* Disable compression */
1169 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1170 dpfc_ctl
&= ~DPFC_CTL_EN
;
1171 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1173 DRM_DEBUG_KMS("disabled FBC\n");
1176 static bool g4x_fbc_enabled(struct drm_device
*dev
)
1178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1180 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
1183 static void ironlake_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1185 struct drm_device
*dev
= crtc
->dev
;
1186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1187 struct drm_framebuffer
*fb
= crtc
->fb
;
1188 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1189 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
1190 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1191 int plane
= (intel_crtc
->plane
== 0) ? DPFC_CTL_PLANEA
:
1193 unsigned long stall_watermark
= 200;
1196 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1197 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1198 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1200 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1201 dpfc_ctl
&= DPFC_RESERVED
;
1202 dpfc_ctl
|= (plane
| DPFC_CTL_LIMIT_1X
);
1203 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1204 dpfc_ctl
|= (DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
);
1205 I915_WRITE(ILK_DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1207 I915_WRITE(ILK_DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1210 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
1211 I915_WRITE(ILK_DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1212 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1213 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1214 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
1215 I915_WRITE(ILK_FBC_RT_BASE
, obj_priv
->gtt_offset
| ILK_FBC_RT_VALID
);
1217 I915_WRITE(ILK_DPFC_CONTROL
, I915_READ(ILK_DPFC_CONTROL
) |
1220 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1223 void ironlake_disable_fbc(struct drm_device
*dev
)
1225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1228 /* Disable compression */
1229 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1230 dpfc_ctl
&= ~DPFC_CTL_EN
;
1231 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
1233 DRM_DEBUG_KMS("disabled FBC\n");
1236 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
1238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1240 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
1243 bool intel_fbc_enabled(struct drm_device
*dev
)
1245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1247 if (!dev_priv
->display
.fbc_enabled
)
1250 return dev_priv
->display
.fbc_enabled(dev
);
1253 void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1255 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1257 if (!dev_priv
->display
.enable_fbc
)
1260 dev_priv
->display
.enable_fbc(crtc
, interval
);
1263 void intel_disable_fbc(struct drm_device
*dev
)
1265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1267 if (!dev_priv
->display
.disable_fbc
)
1270 dev_priv
->display
.disable_fbc(dev
);
1274 * intel_update_fbc - enable/disable FBC as needed
1275 * @crtc: CRTC to point the compressor at
1276 * @mode: mode in use
1278 * Set up the framebuffer compression hardware at mode set time. We
1279 * enable it if possible:
1280 * - plane A only (on pre-965)
1281 * - no pixel mulitply/line duplication
1282 * - no alpha buffer discard
1284 * - framebuffer <= 2048 in width, 1536 in height
1286 * We can't assume that any compression will take place (worst case),
1287 * so the compressed buffer has to be the same size as the uncompressed
1288 * one. It also must reside (along with the line length buffer) in
1291 * We need to enable/disable FBC on a global basis.
1293 static void intel_update_fbc(struct drm_crtc
*crtc
,
1294 struct drm_display_mode
*mode
)
1296 struct drm_device
*dev
= crtc
->dev
;
1297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1298 struct drm_framebuffer
*fb
= crtc
->fb
;
1299 struct intel_framebuffer
*intel_fb
;
1300 struct drm_i915_gem_object
*obj_priv
;
1301 struct drm_crtc
*tmp_crtc
;
1302 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1303 int plane
= intel_crtc
->plane
;
1304 int crtcs_enabled
= 0;
1306 DRM_DEBUG_KMS("\n");
1308 if (!i915_powersave
)
1311 if (!I915_HAS_FBC(dev
))
1317 intel_fb
= to_intel_framebuffer(fb
);
1318 obj_priv
= to_intel_bo(intel_fb
->obj
);
1321 * If FBC is already on, we just have to verify that we can
1322 * keep it that way...
1323 * Need to disable if:
1324 * - more than one pipe is active
1325 * - changing FBC params (stride, fence, mode)
1326 * - new fb is too large to fit in compressed buffer
1327 * - going to an unsupported config (interlace, pixel multiply, etc.)
1329 list_for_each_entry(tmp_crtc
, &dev
->mode_config
.crtc_list
, head
) {
1330 if (tmp_crtc
->enabled
)
1333 DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled
);
1334 if (crtcs_enabled
> 1) {
1335 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1336 dev_priv
->no_fbc_reason
= FBC_MULTIPLE_PIPES
;
1339 if (intel_fb
->obj
->size
> dev_priv
->cfb_size
) {
1340 DRM_DEBUG_KMS("framebuffer too large, disabling "
1342 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
1345 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
1346 (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
1347 DRM_DEBUG_KMS("mode incompatible with compression, "
1349 dev_priv
->no_fbc_reason
= FBC_UNSUPPORTED_MODE
;
1352 if ((mode
->hdisplay
> 2048) ||
1353 (mode
->vdisplay
> 1536)) {
1354 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1355 dev_priv
->no_fbc_reason
= FBC_MODE_TOO_LARGE
;
1358 if ((IS_I915GM(dev
) || IS_I945GM(dev
)) && plane
!= 0) {
1359 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1360 dev_priv
->no_fbc_reason
= FBC_BAD_PLANE
;
1363 if (obj_priv
->tiling_mode
!= I915_TILING_X
) {
1364 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1365 dev_priv
->no_fbc_reason
= FBC_NOT_TILED
;
1369 /* If the kernel debugger is active, always disable compression */
1370 if (in_dbg_master())
1373 if (intel_fbc_enabled(dev
)) {
1374 /* We can re-enable it in this case, but need to update pitch */
1375 if ((fb
->pitch
> dev_priv
->cfb_pitch
) ||
1376 (obj_priv
->fence_reg
!= dev_priv
->cfb_fence
) ||
1377 (plane
!= dev_priv
->cfb_plane
))
1378 intel_disable_fbc(dev
);
1381 /* Now try to turn it back on if possible */
1382 if (!intel_fbc_enabled(dev
))
1383 intel_enable_fbc(crtc
, 500);
1388 /* Multiple disables should be harmless */
1389 if (intel_fbc_enabled(dev
)) {
1390 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1391 intel_disable_fbc(dev
);
1396 intel_pin_and_fence_fb_obj(struct drm_device
*dev
, struct drm_gem_object
*obj
)
1398 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1402 switch (obj_priv
->tiling_mode
) {
1403 case I915_TILING_NONE
:
1404 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1405 alignment
= 128 * 1024;
1406 else if (IS_I965G(dev
))
1407 alignment
= 4 * 1024;
1409 alignment
= 64 * 1024;
1412 /* pin() will align the object as required by fence */
1416 /* FIXME: Is this true? */
1417 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1423 ret
= i915_gem_object_pin(obj
, alignment
);
1427 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1428 * fence, whereas 965+ only requires a fence if using
1429 * framebuffer compression. For simplicity, we always install
1430 * a fence as the cost is not that onerous.
1432 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
&&
1433 obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1434 ret
= i915_gem_object_get_fence_reg(obj
);
1436 i915_gem_object_unpin(obj
);
1444 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1446 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1449 struct drm_device
*dev
= crtc
->dev
;
1450 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1451 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1452 struct intel_framebuffer
*intel_fb
;
1453 struct drm_i915_gem_object
*obj_priv
;
1454 struct drm_gem_object
*obj
;
1455 int plane
= intel_crtc
->plane
;
1456 unsigned long Start
, Offset
;
1457 int dspbase
= (plane
== 0 ? DSPAADDR
: DSPBADDR
);
1458 int dspsurf
= (plane
== 0 ? DSPASURF
: DSPBSURF
);
1459 int dspstride
= (plane
== 0) ? DSPASTRIDE
: DSPBSTRIDE
;
1460 int dsptileoff
= (plane
== 0 ? DSPATILEOFF
: DSPBTILEOFF
);
1461 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1469 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1473 intel_fb
= to_intel_framebuffer(fb
);
1474 obj
= intel_fb
->obj
;
1475 obj_priv
= to_intel_bo(obj
);
1477 dspcntr
= I915_READ(dspcntr_reg
);
1478 /* Mask out pixel format bits in case we change it */
1479 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1480 switch (fb
->bits_per_pixel
) {
1482 dspcntr
|= DISPPLANE_8BPP
;
1485 if (fb
->depth
== 15)
1486 dspcntr
|= DISPPLANE_15_16BPP
;
1488 dspcntr
|= DISPPLANE_16BPP
;
1492 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
1495 DRM_ERROR("Unknown color depth\n");
1498 if (IS_I965G(dev
)) {
1499 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1500 dspcntr
|= DISPPLANE_TILED
;
1502 dspcntr
&= ~DISPPLANE_TILED
;
1505 if (HAS_PCH_SPLIT(dev
))
1507 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1509 I915_WRITE(dspcntr_reg
, dspcntr
);
1511 Start
= obj_priv
->gtt_offset
;
1512 Offset
= y
* fb
->pitch
+ x
* (fb
->bits_per_pixel
/ 8);
1514 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1515 Start
, Offset
, x
, y
, fb
->pitch
);
1516 I915_WRITE(dspstride
, fb
->pitch
);
1517 if (IS_I965G(dev
)) {
1518 I915_WRITE(dspsurf
, Start
);
1519 I915_WRITE(dsptileoff
, (y
<< 16) | x
);
1520 I915_WRITE(dspbase
, Offset
);
1522 I915_WRITE(dspbase
, Start
+ Offset
);
1524 POSTING_READ(dspbase
);
1526 if (IS_I965G(dev
) || plane
== 0)
1527 intel_update_fbc(crtc
, &crtc
->mode
);
1529 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1530 intel_increase_pllclock(crtc
, true);
1536 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
1537 struct drm_framebuffer
*old_fb
)
1539 struct drm_device
*dev
= crtc
->dev
;
1540 struct drm_i915_master_private
*master_priv
;
1541 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1542 struct intel_framebuffer
*intel_fb
;
1543 struct drm_i915_gem_object
*obj_priv
;
1544 struct drm_gem_object
*obj
;
1545 int pipe
= intel_crtc
->pipe
;
1546 int plane
= intel_crtc
->plane
;
1551 DRM_DEBUG_KMS("No FB bound\n");
1560 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1564 intel_fb
= to_intel_framebuffer(crtc
->fb
);
1565 obj
= intel_fb
->obj
;
1566 obj_priv
= to_intel_bo(obj
);
1568 mutex_lock(&dev
->struct_mutex
);
1569 ret
= intel_pin_and_fence_fb_obj(dev
, obj
);
1571 mutex_unlock(&dev
->struct_mutex
);
1575 ret
= i915_gem_object_set_to_display_plane(obj
);
1577 i915_gem_object_unpin(obj
);
1578 mutex_unlock(&dev
->struct_mutex
);
1582 ret
= intel_pipe_set_base_atomic(crtc
, crtc
->fb
, x
, y
);
1584 i915_gem_object_unpin(obj
);
1585 mutex_unlock(&dev
->struct_mutex
);
1590 intel_fb
= to_intel_framebuffer(old_fb
);
1591 obj_priv
= to_intel_bo(intel_fb
->obj
);
1592 i915_gem_object_unpin(intel_fb
->obj
);
1595 mutex_unlock(&dev
->struct_mutex
);
1597 if (!dev
->primary
->master
)
1600 master_priv
= dev
->primary
->master
->driver_priv
;
1601 if (!master_priv
->sarea_priv
)
1605 master_priv
->sarea_priv
->pipeB_x
= x
;
1606 master_priv
->sarea_priv
->pipeB_y
= y
;
1608 master_priv
->sarea_priv
->pipeA_x
= x
;
1609 master_priv
->sarea_priv
->pipeA_y
= y
;
1615 static void ironlake_set_pll_edp (struct drm_crtc
*crtc
, int clock
)
1617 struct drm_device
*dev
= crtc
->dev
;
1618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1621 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
1622 dpa_ctl
= I915_READ(DP_A
);
1623 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1625 if (clock
< 200000) {
1627 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1628 /* workaround for 160Mhz:
1629 1) program 0x4600c bits 15:0 = 0x8124
1630 2) program 0x46010 bit 0 = 1
1631 3) program 0x46034 bit 24 = 1
1632 4) program 0x64000 bit 14 = 1
1634 temp
= I915_READ(0x4600c);
1636 I915_WRITE(0x4600c, temp
| 0x8124);
1638 temp
= I915_READ(0x46010);
1639 I915_WRITE(0x46010, temp
| 1);
1641 temp
= I915_READ(0x46034);
1642 I915_WRITE(0x46034, temp
| (1 << 24));
1644 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1646 I915_WRITE(DP_A
, dpa_ctl
);
1651 /* The FDI link training functions for ILK/Ibexpeak. */
1652 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
1654 struct drm_device
*dev
= crtc
->dev
;
1655 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1656 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1657 int pipe
= intel_crtc
->pipe
;
1658 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1659 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1660 int fdi_rx_iir_reg
= (pipe
== 0) ? FDI_RXA_IIR
: FDI_RXB_IIR
;
1661 int fdi_rx_imr_reg
= (pipe
== 0) ? FDI_RXA_IMR
: FDI_RXB_IMR
;
1662 u32 temp
, tries
= 0;
1664 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1666 temp
= I915_READ(fdi_rx_imr_reg
);
1667 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1668 temp
&= ~FDI_RX_BIT_LOCK
;
1669 I915_WRITE(fdi_rx_imr_reg
, temp
);
1670 I915_READ(fdi_rx_imr_reg
);
1673 /* enable CPU FDI TX and PCH FDI RX */
1674 temp
= I915_READ(fdi_tx_reg
);
1675 temp
|= FDI_TX_ENABLE
;
1677 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1678 temp
&= ~FDI_LINK_TRAIN_NONE
;
1679 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1680 I915_WRITE(fdi_tx_reg
, temp
);
1681 I915_READ(fdi_tx_reg
);
1683 temp
= I915_READ(fdi_rx_reg
);
1684 temp
&= ~FDI_LINK_TRAIN_NONE
;
1685 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1686 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENABLE
);
1687 I915_READ(fdi_rx_reg
);
1690 for (tries
= 0; tries
< 5; tries
++) {
1691 temp
= I915_READ(fdi_rx_iir_reg
);
1692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1694 if ((temp
& FDI_RX_BIT_LOCK
)) {
1695 DRM_DEBUG_KMS("FDI train 1 done.\n");
1696 I915_WRITE(fdi_rx_iir_reg
,
1697 temp
| FDI_RX_BIT_LOCK
);
1702 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1705 temp
= I915_READ(fdi_tx_reg
);
1706 temp
&= ~FDI_LINK_TRAIN_NONE
;
1707 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1708 I915_WRITE(fdi_tx_reg
, temp
);
1710 temp
= I915_READ(fdi_rx_reg
);
1711 temp
&= ~FDI_LINK_TRAIN_NONE
;
1712 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1713 I915_WRITE(fdi_rx_reg
, temp
);
1718 for (tries
= 0; tries
< 5; tries
++) {
1719 temp
= I915_READ(fdi_rx_iir_reg
);
1720 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1722 if (temp
& FDI_RX_SYMBOL_LOCK
) {
1723 I915_WRITE(fdi_rx_iir_reg
,
1724 temp
| FDI_RX_SYMBOL_LOCK
);
1725 DRM_DEBUG_KMS("FDI train 2 done.\n");
1730 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1732 DRM_DEBUG_KMS("FDI train done\n");
1735 static int snb_b_fdi_train_param
[] = {
1736 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
1737 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
1738 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
1739 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
1742 /* The FDI link training functions for SNB/Cougarpoint. */
1743 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
1745 struct drm_device
*dev
= crtc
->dev
;
1746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1747 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1748 int pipe
= intel_crtc
->pipe
;
1749 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1750 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1751 int fdi_rx_iir_reg
= (pipe
== 0) ? FDI_RXA_IIR
: FDI_RXB_IIR
;
1752 int fdi_rx_imr_reg
= (pipe
== 0) ? FDI_RXA_IMR
: FDI_RXB_IMR
;
1755 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1757 temp
= I915_READ(fdi_rx_imr_reg
);
1758 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1759 temp
&= ~FDI_RX_BIT_LOCK
;
1760 I915_WRITE(fdi_rx_imr_reg
, temp
);
1761 I915_READ(fdi_rx_imr_reg
);
1764 /* enable CPU FDI TX and PCH FDI RX */
1765 temp
= I915_READ(fdi_tx_reg
);
1766 temp
|= FDI_TX_ENABLE
;
1768 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1769 temp
&= ~FDI_LINK_TRAIN_NONE
;
1770 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1771 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1773 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
1774 I915_WRITE(fdi_tx_reg
, temp
);
1775 I915_READ(fdi_tx_reg
);
1777 temp
= I915_READ(fdi_rx_reg
);
1778 if (HAS_PCH_CPT(dev
)) {
1779 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1780 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
1782 temp
&= ~FDI_LINK_TRAIN_NONE
;
1783 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1785 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENABLE
);
1786 I915_READ(fdi_rx_reg
);
1789 for (i
= 0; i
< 4; i
++ ) {
1790 temp
= I915_READ(fdi_tx_reg
);
1791 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1792 temp
|= snb_b_fdi_train_param
[i
];
1793 I915_WRITE(fdi_tx_reg
, temp
);
1796 temp
= I915_READ(fdi_rx_iir_reg
);
1797 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1799 if (temp
& FDI_RX_BIT_LOCK
) {
1800 I915_WRITE(fdi_rx_iir_reg
,
1801 temp
| FDI_RX_BIT_LOCK
);
1802 DRM_DEBUG_KMS("FDI train 1 done.\n");
1807 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1810 temp
= I915_READ(fdi_tx_reg
);
1811 temp
&= ~FDI_LINK_TRAIN_NONE
;
1812 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1814 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1816 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
1818 I915_WRITE(fdi_tx_reg
, temp
);
1820 temp
= I915_READ(fdi_rx_reg
);
1821 if (HAS_PCH_CPT(dev
)) {
1822 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1823 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
1825 temp
&= ~FDI_LINK_TRAIN_NONE
;
1826 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1828 I915_WRITE(fdi_rx_reg
, temp
);
1831 for (i
= 0; i
< 4; i
++ ) {
1832 temp
= I915_READ(fdi_tx_reg
);
1833 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1834 temp
|= snb_b_fdi_train_param
[i
];
1835 I915_WRITE(fdi_tx_reg
, temp
);
1838 temp
= I915_READ(fdi_rx_iir_reg
);
1839 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1841 if (temp
& FDI_RX_SYMBOL_LOCK
) {
1842 I915_WRITE(fdi_rx_iir_reg
,
1843 temp
| FDI_RX_SYMBOL_LOCK
);
1844 DRM_DEBUG_KMS("FDI train 2 done.\n");
1849 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1851 DRM_DEBUG_KMS("FDI train done.\n");
1854 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
1856 struct drm_device
*dev
= crtc
->dev
;
1857 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1858 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1859 int pipe
= intel_crtc
->pipe
;
1860 int plane
= intel_crtc
->plane
;
1861 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
1862 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
1863 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1864 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
1865 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1866 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1867 int transconf_reg
= (pipe
== 0) ? TRANSACONF
: TRANSBCONF
;
1868 int cpu_htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
1869 int cpu_hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
1870 int cpu_hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
1871 int cpu_vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
1872 int cpu_vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
1873 int cpu_vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
1874 int trans_htot_reg
= (pipe
== 0) ? TRANS_HTOTAL_A
: TRANS_HTOTAL_B
;
1875 int trans_hblank_reg
= (pipe
== 0) ? TRANS_HBLANK_A
: TRANS_HBLANK_B
;
1876 int trans_hsync_reg
= (pipe
== 0) ? TRANS_HSYNC_A
: TRANS_HSYNC_B
;
1877 int trans_vtot_reg
= (pipe
== 0) ? TRANS_VTOTAL_A
: TRANS_VTOTAL_B
;
1878 int trans_vblank_reg
= (pipe
== 0) ? TRANS_VBLANK_A
: TRANS_VBLANK_B
;
1879 int trans_vsync_reg
= (pipe
== 0) ? TRANS_VSYNC_A
: TRANS_VSYNC_B
;
1880 int trans_dpll_sel
= (pipe
== 0) ? 0 : 1;
1884 temp
= I915_READ(pipeconf_reg
);
1885 pipe_bpc
= temp
& PIPE_BPC_MASK
;
1887 /* XXX: When our outputs are all unaware of DPMS modes other than off
1888 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1891 case DRM_MODE_DPMS_ON
:
1892 case DRM_MODE_DPMS_STANDBY
:
1893 case DRM_MODE_DPMS_SUSPEND
:
1894 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe
, plane
);
1896 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1897 temp
= I915_READ(PCH_LVDS
);
1898 if ((temp
& LVDS_PORT_EN
) == 0) {
1899 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
1900 POSTING_READ(PCH_LVDS
);
1906 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1907 temp
= I915_READ(fdi_rx_reg
);
1909 * make the BPC in FDI Rx be consistent with that in
1912 temp
&= ~(0x7 << 16);
1913 temp
|= (pipe_bpc
<< 11);
1915 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1916 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
);
1917 I915_READ(fdi_rx_reg
);
1920 /* Switch from Rawclk to PCDclk */
1921 temp
= I915_READ(fdi_rx_reg
);
1922 I915_WRITE(fdi_rx_reg
, temp
| FDI_SEL_PCDCLK
);
1923 I915_READ(fdi_rx_reg
);
1926 /* Enable CPU FDI TX PLL, always on for Ironlake */
1927 temp
= I915_READ(fdi_tx_reg
);
1928 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
1929 I915_WRITE(fdi_tx_reg
, temp
| FDI_TX_PLL_ENABLE
);
1930 I915_READ(fdi_tx_reg
);
1935 /* Enable panel fitting for LVDS */
1936 if (dev_priv
->pch_pf_size
&&
1937 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)
1938 || HAS_eDP
|| intel_pch_has_edp(crtc
))) {
1939 /* Force use of hard-coded filter coefficients
1940 * as some pre-programmed values are broken,
1943 I915_WRITE(pipe
? PFB_CTL_1
: PFA_CTL_1
,
1944 PF_ENABLE
| PF_FILTER_MED_3x3
);
1945 I915_WRITE(pipe
? PFB_WIN_POS
: PFA_WIN_POS
,
1946 dev_priv
->pch_pf_pos
);
1947 I915_WRITE(pipe
? PFB_WIN_SZ
: PFA_WIN_SZ
,
1948 dev_priv
->pch_pf_size
);
1951 /* Enable CPU pipe */
1952 temp
= I915_READ(pipeconf_reg
);
1953 if ((temp
& PIPEACONF_ENABLE
) == 0) {
1954 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
1955 I915_READ(pipeconf_reg
);
1959 /* configure and enable CPU plane */
1960 temp
= I915_READ(dspcntr_reg
);
1961 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
1962 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
1963 /* Flush the plane changes */
1964 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1968 /* For PCH output, training FDI link */
1970 gen6_fdi_link_train(crtc
);
1972 ironlake_fdi_link_train(crtc
);
1974 /* enable PCH DPLL */
1975 temp
= I915_READ(pch_dpll_reg
);
1976 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
1977 I915_WRITE(pch_dpll_reg
, temp
| DPLL_VCO_ENABLE
);
1978 I915_READ(pch_dpll_reg
);
1982 if (HAS_PCH_CPT(dev
)) {
1983 /* Be sure PCH DPLL SEL is set */
1984 temp
= I915_READ(PCH_DPLL_SEL
);
1985 if (trans_dpll_sel
== 0 &&
1986 (temp
& TRANSA_DPLL_ENABLE
) == 0)
1987 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
1988 else if (trans_dpll_sel
== 1 &&
1989 (temp
& TRANSB_DPLL_ENABLE
) == 0)
1990 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
1991 I915_WRITE(PCH_DPLL_SEL
, temp
);
1992 I915_READ(PCH_DPLL_SEL
);
1995 /* set transcoder timing */
1996 I915_WRITE(trans_htot_reg
, I915_READ(cpu_htot_reg
));
1997 I915_WRITE(trans_hblank_reg
, I915_READ(cpu_hblank_reg
));
1998 I915_WRITE(trans_hsync_reg
, I915_READ(cpu_hsync_reg
));
2000 I915_WRITE(trans_vtot_reg
, I915_READ(cpu_vtot_reg
));
2001 I915_WRITE(trans_vblank_reg
, I915_READ(cpu_vblank_reg
));
2002 I915_WRITE(trans_vsync_reg
, I915_READ(cpu_vsync_reg
));
2004 /* enable normal train */
2005 temp
= I915_READ(fdi_tx_reg
);
2006 temp
&= ~FDI_LINK_TRAIN_NONE
;
2007 I915_WRITE(fdi_tx_reg
, temp
| FDI_LINK_TRAIN_NONE
|
2008 FDI_TX_ENHANCE_FRAME_ENABLE
);
2009 I915_READ(fdi_tx_reg
);
2011 temp
= I915_READ(fdi_rx_reg
);
2012 if (HAS_PCH_CPT(dev
)) {
2013 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2014 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2016 temp
&= ~FDI_LINK_TRAIN_NONE
;
2017 temp
|= FDI_LINK_TRAIN_NONE
;
2019 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2020 I915_READ(fdi_rx_reg
);
2022 /* wait one idle pattern time */
2025 /* For PCH DP, enable TRANS_DP_CTL */
2026 if (HAS_PCH_CPT(dev
) &&
2027 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
2028 int trans_dp_ctl
= (pipe
== 0) ? TRANS_DP_CTL_A
: TRANS_DP_CTL_B
;
2031 reg
= I915_READ(trans_dp_ctl
);
2032 reg
&= ~(TRANS_DP_PORT_SEL_MASK
|
2033 TRANS_DP_SYNC_MASK
);
2034 reg
|= (TRANS_DP_OUTPUT_ENABLE
|
2035 TRANS_DP_ENH_FRAMING
);
2037 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
2038 reg
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
2039 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
2040 reg
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
2042 switch (intel_trans_dp_port_sel(crtc
)) {
2044 reg
|= TRANS_DP_PORT_SEL_B
;
2047 reg
|= TRANS_DP_PORT_SEL_C
;
2050 reg
|= TRANS_DP_PORT_SEL_D
;
2053 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2054 reg
|= TRANS_DP_PORT_SEL_B
;
2058 I915_WRITE(trans_dp_ctl
, reg
);
2059 POSTING_READ(trans_dp_ctl
);
2062 /* enable PCH transcoder */
2063 temp
= I915_READ(transconf_reg
);
2065 * make the BPC in transcoder be consistent with
2066 * that in pipeconf reg.
2068 temp
&= ~PIPE_BPC_MASK
;
2070 I915_WRITE(transconf_reg
, temp
| TRANS_ENABLE
);
2071 I915_READ(transconf_reg
);
2073 if (wait_for(I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
, 100, 1))
2074 DRM_ERROR("failed to enable transcoder\n");
2077 intel_crtc_load_lut(crtc
);
2079 intel_update_fbc(crtc
, &crtc
->mode
);
2082 case DRM_MODE_DPMS_OFF
:
2083 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe
, plane
);
2085 drm_vblank_off(dev
, pipe
);
2086 /* Disable display plane */
2087 temp
= I915_READ(dspcntr_reg
);
2088 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
2089 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
2090 /* Flush the plane changes */
2091 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
2092 I915_READ(dspbase_reg
);
2095 if (dev_priv
->cfb_plane
== plane
&&
2096 dev_priv
->display
.disable_fbc
)
2097 dev_priv
->display
.disable_fbc(dev
);
2099 /* disable cpu pipe, disable after all planes disabled */
2100 temp
= I915_READ(pipeconf_reg
);
2101 if ((temp
& PIPEACONF_ENABLE
) != 0) {
2102 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
2104 /* wait for cpu pipe off, pipe state */
2105 if (wait_for((I915_READ(pipeconf_reg
) & I965_PIPECONF_ACTIVE
) == 0, 50, 1))
2106 DRM_ERROR("failed to turn off cpu pipe\n");
2108 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
2113 I915_WRITE(pipe
? PFB_CTL_1
: PFA_CTL_1
, 0);
2114 I915_WRITE(pipe
? PFB_WIN_SZ
: PFA_WIN_SZ
, 0);
2116 /* disable CPU FDI tx and PCH FDI rx */
2117 temp
= I915_READ(fdi_tx_reg
);
2118 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_ENABLE
);
2119 I915_READ(fdi_tx_reg
);
2121 temp
= I915_READ(fdi_rx_reg
);
2122 /* BPC in FDI rx is consistent with that in pipeconf */
2123 temp
&= ~(0x07 << 16);
2124 temp
|= (pipe_bpc
<< 11);
2125 I915_WRITE(fdi_rx_reg
, temp
& ~FDI_RX_ENABLE
);
2126 I915_READ(fdi_rx_reg
);
2130 /* still set train pattern 1 */
2131 temp
= I915_READ(fdi_tx_reg
);
2132 temp
&= ~FDI_LINK_TRAIN_NONE
;
2133 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2134 I915_WRITE(fdi_tx_reg
, temp
);
2135 POSTING_READ(fdi_tx_reg
);
2137 temp
= I915_READ(fdi_rx_reg
);
2138 if (HAS_PCH_CPT(dev
)) {
2139 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2140 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2142 temp
&= ~FDI_LINK_TRAIN_NONE
;
2143 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2145 I915_WRITE(fdi_rx_reg
, temp
);
2146 POSTING_READ(fdi_rx_reg
);
2150 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
2151 temp
= I915_READ(PCH_LVDS
);
2152 I915_WRITE(PCH_LVDS
, temp
& ~LVDS_PORT_EN
);
2153 I915_READ(PCH_LVDS
);
2157 /* disable PCH transcoder */
2158 temp
= I915_READ(transconf_reg
);
2159 if ((temp
& TRANS_ENABLE
) != 0) {
2160 I915_WRITE(transconf_reg
, temp
& ~TRANS_ENABLE
);
2162 /* wait for PCH transcoder off, transcoder state */
2163 if (wait_for((I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
) == 0, 50, 1))
2164 DRM_ERROR("failed to disable transcoder\n");
2167 temp
= I915_READ(transconf_reg
);
2168 /* BPC in transcoder is consistent with that in pipeconf */
2169 temp
&= ~PIPE_BPC_MASK
;
2171 I915_WRITE(transconf_reg
, temp
);
2172 I915_READ(transconf_reg
);
2175 if (HAS_PCH_CPT(dev
)) {
2176 /* disable TRANS_DP_CTL */
2177 int trans_dp_ctl
= (pipe
== 0) ? TRANS_DP_CTL_A
: TRANS_DP_CTL_B
;
2180 reg
= I915_READ(trans_dp_ctl
);
2181 reg
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
2182 I915_WRITE(trans_dp_ctl
, reg
);
2183 POSTING_READ(trans_dp_ctl
);
2185 /* disable DPLL_SEL */
2186 temp
= I915_READ(PCH_DPLL_SEL
);
2187 if (trans_dpll_sel
== 0)
2188 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
2190 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
2191 I915_WRITE(PCH_DPLL_SEL
, temp
);
2192 I915_READ(PCH_DPLL_SEL
);
2196 /* disable PCH DPLL */
2197 temp
= I915_READ(pch_dpll_reg
);
2198 I915_WRITE(pch_dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
2199 I915_READ(pch_dpll_reg
);
2201 /* Switch from PCDclk to Rawclk */
2202 temp
= I915_READ(fdi_rx_reg
);
2203 temp
&= ~FDI_SEL_PCDCLK
;
2204 I915_WRITE(fdi_rx_reg
, temp
);
2205 I915_READ(fdi_rx_reg
);
2207 /* Disable CPU FDI TX PLL */
2208 temp
= I915_READ(fdi_tx_reg
);
2209 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2210 I915_READ(fdi_tx_reg
);
2213 temp
= I915_READ(fdi_rx_reg
);
2214 temp
&= ~FDI_RX_PLL_ENABLE
;
2215 I915_WRITE(fdi_rx_reg
, temp
);
2216 I915_READ(fdi_rx_reg
);
2218 /* Wait for the clocks to turn off. */
2224 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
2226 struct intel_overlay
*overlay
;
2229 if (!enable
&& intel_crtc
->overlay
) {
2230 overlay
= intel_crtc
->overlay
;
2231 mutex_lock(&overlay
->dev
->struct_mutex
);
2233 ret
= intel_overlay_switch_off(overlay
);
2237 ret
= intel_overlay_recover_from_interrupt(overlay
, 0);
2239 /* overlay doesn't react anymore. Usually
2240 * results in a black screen and an unkillable
2243 overlay
->hw_wedged
= HW_WEDGED
;
2247 mutex_unlock(&overlay
->dev
->struct_mutex
);
2249 /* Let userspace switch the overlay on again. In most cases userspace
2250 * has to recompute where to put it anyway. */
2255 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2257 struct drm_device
*dev
= crtc
->dev
;
2258 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2259 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2260 int pipe
= intel_crtc
->pipe
;
2261 int plane
= intel_crtc
->plane
;
2262 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
2263 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
2264 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
2265 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
2268 /* XXX: When our outputs are all unaware of DPMS modes other than off
2269 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2272 case DRM_MODE_DPMS_ON
:
2273 case DRM_MODE_DPMS_STANDBY
:
2274 case DRM_MODE_DPMS_SUSPEND
:
2275 /* Enable the DPLL */
2276 temp
= I915_READ(dpll_reg
);
2277 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
2278 I915_WRITE(dpll_reg
, temp
);
2279 I915_READ(dpll_reg
);
2280 /* Wait for the clocks to stabilize. */
2282 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
2283 I915_READ(dpll_reg
);
2284 /* Wait for the clocks to stabilize. */
2286 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
2287 I915_READ(dpll_reg
);
2288 /* Wait for the clocks to stabilize. */
2292 /* Enable the pipe */
2293 temp
= I915_READ(pipeconf_reg
);
2294 if ((temp
& PIPEACONF_ENABLE
) == 0)
2295 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
2297 /* Enable the plane */
2298 temp
= I915_READ(dspcntr_reg
);
2299 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
2300 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
2301 /* Flush the plane changes */
2302 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
2305 intel_crtc_load_lut(crtc
);
2307 if ((IS_I965G(dev
) || plane
== 0))
2308 intel_update_fbc(crtc
, &crtc
->mode
);
2310 /* Give the overlay scaler a chance to enable if it's on this pipe */
2311 intel_crtc_dpms_overlay(intel_crtc
, true);
2313 case DRM_MODE_DPMS_OFF
:
2314 /* Give the overlay scaler a chance to disable if it's on this pipe */
2315 intel_crtc_dpms_overlay(intel_crtc
, false);
2316 drm_vblank_off(dev
, pipe
);
2318 if (dev_priv
->cfb_plane
== plane
&&
2319 dev_priv
->display
.disable_fbc
)
2320 dev_priv
->display
.disable_fbc(dev
);
2322 /* Disable display plane */
2323 temp
= I915_READ(dspcntr_reg
);
2324 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
2325 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
2326 /* Flush the plane changes */
2327 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
2328 I915_READ(dspbase_reg
);
2331 /* Wait for vblank for the disable to take effect */
2332 intel_wait_for_vblank_off(dev
, pipe
);
2334 /* Don't disable pipe A or pipe A PLLs if needed */
2335 if (pipeconf_reg
== PIPEACONF
&&
2336 (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
2339 /* Next, disable display pipes */
2340 temp
= I915_READ(pipeconf_reg
);
2341 if ((temp
& PIPEACONF_ENABLE
) != 0) {
2342 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
2343 I915_READ(pipeconf_reg
);
2346 /* Wait for vblank for the disable to take effect. */
2347 intel_wait_for_vblank_off(dev
, pipe
);
2349 temp
= I915_READ(dpll_reg
);
2350 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
2351 I915_WRITE(dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
2352 I915_READ(dpll_reg
);
2355 /* Wait for the clocks to turn off. */
2362 * Sets the power management mode of the pipe and plane.
2364 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2366 struct drm_device
*dev
= crtc
->dev
;
2367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2368 struct drm_i915_master_private
*master_priv
;
2369 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2370 int pipe
= intel_crtc
->pipe
;
2373 if (intel_crtc
->dpms_mode
== mode
)
2376 intel_crtc
->dpms_mode
= mode
;
2377 intel_crtc
->cursor_on
= mode
== DRM_MODE_DPMS_ON
;
2379 /* When switching on the display, ensure that SR is disabled
2380 * with multiple pipes prior to enabling to new pipe.
2382 * When switching off the display, make sure the cursor is
2383 * properly hidden prior to disabling the pipe.
2385 if (mode
== DRM_MODE_DPMS_ON
)
2386 intel_update_watermarks(dev
);
2388 intel_crtc_update_cursor(crtc
);
2390 dev_priv
->display
.dpms(crtc
, mode
);
2392 if (mode
== DRM_MODE_DPMS_ON
)
2393 intel_crtc_update_cursor(crtc
);
2395 intel_update_watermarks(dev
);
2397 if (!dev
->primary
->master
)
2400 master_priv
= dev
->primary
->master
->driver_priv
;
2401 if (!master_priv
->sarea_priv
)
2404 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
2408 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2409 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2412 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2413 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2416 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
2421 static void intel_crtc_prepare (struct drm_crtc
*crtc
)
2423 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
2424 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
2427 static void intel_crtc_commit (struct drm_crtc
*crtc
)
2429 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
2430 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
2433 void intel_encoder_prepare (struct drm_encoder
*encoder
)
2435 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2436 /* lvds has its own version of prepare see intel_lvds_prepare */
2437 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
2440 void intel_encoder_commit (struct drm_encoder
*encoder
)
2442 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2443 /* lvds has its own version of commit see intel_lvds_commit */
2444 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
2447 void intel_encoder_destroy(struct drm_encoder
*encoder
)
2449 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
2451 if (intel_encoder
->ddc_bus
)
2452 intel_i2c_destroy(intel_encoder
->ddc_bus
);
2454 if (intel_encoder
->i2c_bus
)
2455 intel_i2c_destroy(intel_encoder
->i2c_bus
);
2457 drm_encoder_cleanup(encoder
);
2458 kfree(intel_encoder
);
2461 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
2462 struct drm_display_mode
*mode
,
2463 struct drm_display_mode
*adjusted_mode
)
2465 struct drm_device
*dev
= crtc
->dev
;
2466 if (HAS_PCH_SPLIT(dev
)) {
2467 /* FDI link clock is fixed at 2.7G */
2468 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
2474 static int i945_get_display_clock_speed(struct drm_device
*dev
)
2479 static int i915_get_display_clock_speed(struct drm_device
*dev
)
2484 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
2489 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
2493 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
2495 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
2498 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
2499 case GC_DISPLAY_CLOCK_333_MHZ
:
2502 case GC_DISPLAY_CLOCK_190_200_MHZ
:
2508 static int i865_get_display_clock_speed(struct drm_device
*dev
)
2513 static int i855_get_display_clock_speed(struct drm_device
*dev
)
2516 /* Assume that the hardware is in the high speed state. This
2517 * should be the default.
2519 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
2520 case GC_CLOCK_133_200
:
2521 case GC_CLOCK_100_200
:
2523 case GC_CLOCK_166_250
:
2525 case GC_CLOCK_100_133
:
2529 /* Shouldn't happen */
2533 static int i830_get_display_clock_speed(struct drm_device
*dev
)
2539 * Return the pipe currently connected to the panel fitter,
2540 * or -1 if the panel fitter is not present or not in use
2542 int intel_panel_fitter_pipe (struct drm_device
*dev
)
2544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2547 /* i830 doesn't have a panel fitter */
2551 pfit_control
= I915_READ(PFIT_CONTROL
);
2553 /* See if the panel fitter is in use */
2554 if ((pfit_control
& PFIT_ENABLE
) == 0)
2557 /* 965 can place panel fitter on either pipe */
2559 return (pfit_control
>> 29) & 0x3;
2561 /* older chips can only use pipe 1 */
2574 fdi_reduce_ratio(u32
*num
, u32
*den
)
2576 while (*num
> 0xffffff || *den
> 0xffffff) {
2582 #define DATA_N 0x800000
2583 #define LINK_N 0x80000
2586 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
2587 int link_clock
, struct fdi_m_n
*m_n
)
2591 m_n
->tu
= 64; /* default size */
2593 temp
= (u64
) DATA_N
* pixel_clock
;
2594 temp
= div_u64(temp
, link_clock
);
2595 m_n
->gmch_m
= div_u64(temp
* bits_per_pixel
, nlanes
);
2596 m_n
->gmch_m
>>= 3; /* convert to bytes_per_pixel */
2597 m_n
->gmch_n
= DATA_N
;
2598 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
2600 temp
= (u64
) LINK_N
* pixel_clock
;
2601 m_n
->link_m
= div_u64(temp
, link_clock
);
2602 m_n
->link_n
= LINK_N
;
2603 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
2607 struct intel_watermark_params
{
2608 unsigned long fifo_size
;
2609 unsigned long max_wm
;
2610 unsigned long default_wm
;
2611 unsigned long guard_size
;
2612 unsigned long cacheline_size
;
2615 /* Pineview has different values for various configs */
2616 static struct intel_watermark_params pineview_display_wm
= {
2617 PINEVIEW_DISPLAY_FIFO
,
2621 PINEVIEW_FIFO_LINE_SIZE
2623 static struct intel_watermark_params pineview_display_hplloff_wm
= {
2624 PINEVIEW_DISPLAY_FIFO
,
2626 PINEVIEW_DFT_HPLLOFF_WM
,
2628 PINEVIEW_FIFO_LINE_SIZE
2630 static struct intel_watermark_params pineview_cursor_wm
= {
2631 PINEVIEW_CURSOR_FIFO
,
2632 PINEVIEW_CURSOR_MAX_WM
,
2633 PINEVIEW_CURSOR_DFT_WM
,
2634 PINEVIEW_CURSOR_GUARD_WM
,
2635 PINEVIEW_FIFO_LINE_SIZE
,
2637 static struct intel_watermark_params pineview_cursor_hplloff_wm
= {
2638 PINEVIEW_CURSOR_FIFO
,
2639 PINEVIEW_CURSOR_MAX_WM
,
2640 PINEVIEW_CURSOR_DFT_WM
,
2641 PINEVIEW_CURSOR_GUARD_WM
,
2642 PINEVIEW_FIFO_LINE_SIZE
2644 static struct intel_watermark_params g4x_wm_info
= {
2651 static struct intel_watermark_params g4x_cursor_wm_info
= {
2658 static struct intel_watermark_params i965_cursor_wm_info
= {
2663 I915_FIFO_LINE_SIZE
,
2665 static struct intel_watermark_params i945_wm_info
= {
2672 static struct intel_watermark_params i915_wm_info
= {
2679 static struct intel_watermark_params i855_wm_info
= {
2686 static struct intel_watermark_params i830_wm_info
= {
2694 static struct intel_watermark_params ironlake_display_wm_info
= {
2702 static struct intel_watermark_params ironlake_cursor_wm_info
= {
2710 static struct intel_watermark_params ironlake_display_srwm_info
= {
2711 ILK_DISPLAY_SR_FIFO
,
2712 ILK_DISPLAY_MAX_SRWM
,
2713 ILK_DISPLAY_DFT_SRWM
,
2718 static struct intel_watermark_params ironlake_cursor_srwm_info
= {
2720 ILK_CURSOR_MAX_SRWM
,
2721 ILK_CURSOR_DFT_SRWM
,
2727 * intel_calculate_wm - calculate watermark level
2728 * @clock_in_khz: pixel clock
2729 * @wm: chip FIFO params
2730 * @pixel_size: display pixel size
2731 * @latency_ns: memory latency for the platform
2733 * Calculate the watermark level (the level at which the display plane will
2734 * start fetching from memory again). Each chip has a different display
2735 * FIFO size and allocation, so the caller needs to figure that out and pass
2736 * in the correct intel_watermark_params structure.
2738 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2739 * on the pixel size. When it reaches the watermark level, it'll start
2740 * fetching FIFO line sized based chunks from memory until the FIFO fills
2741 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2742 * will occur, and a display engine hang could result.
2744 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
2745 struct intel_watermark_params
*wm
,
2747 unsigned long latency_ns
)
2749 long entries_required
, wm_size
;
2752 * Note: we need to make sure we don't overflow for various clock &
2754 * clocks go from a few thousand to several hundred thousand.
2755 * latency is usually a few thousand
2757 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
2759 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
2761 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required
);
2763 wm_size
= wm
->fifo_size
- (entries_required
+ wm
->guard_size
);
2765 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size
);
2767 /* Don't promote wm_size to unsigned... */
2768 if (wm_size
> (long)wm
->max_wm
)
2769 wm_size
= wm
->max_wm
;
2771 wm_size
= wm
->default_wm
;
2772 DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
2773 " entries required = %ld, available = %lu.\n",
2774 entries_required
+ wm
->guard_size
,
2781 struct cxsr_latency
{
2784 unsigned long fsb_freq
;
2785 unsigned long mem_freq
;
2786 unsigned long display_sr
;
2787 unsigned long display_hpll_disable
;
2788 unsigned long cursor_sr
;
2789 unsigned long cursor_hpll_disable
;
2792 static const struct cxsr_latency cxsr_latency_table
[] = {
2793 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2794 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2795 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2796 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2797 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2799 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2800 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2801 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2802 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2803 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2805 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2806 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2807 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2808 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2809 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2811 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2812 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2813 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2814 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2815 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2817 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2818 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2819 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2820 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2821 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2823 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2824 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2825 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2826 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2827 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2830 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
2835 const struct cxsr_latency
*latency
;
2838 if (fsb
== 0 || mem
== 0)
2841 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
2842 latency
= &cxsr_latency_table
[i
];
2843 if (is_desktop
== latency
->is_desktop
&&
2844 is_ddr3
== latency
->is_ddr3
&&
2845 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
2849 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2854 static void pineview_disable_cxsr(struct drm_device
*dev
)
2856 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2858 /* deactivate cxsr */
2859 I915_WRITE(DSPFW3
, I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
);
2863 * Latency for FIFO fetches is dependent on several factors:
2864 * - memory configuration (speed, channels)
2866 * - current MCH state
2867 * It can be fairly high in some situations, so here we assume a fairly
2868 * pessimal value. It's a tradeoff between extra memory fetches (if we
2869 * set this value too high, the FIFO will fetch frequently to stay full)
2870 * and power consumption (set it too low to save power and we might see
2871 * FIFO underruns and display "flicker").
2873 * A value of 5us seems to be a good balance; safe for very low end
2874 * platforms but not overly aggressive on lower latency configs.
2876 static const int latency_ns
= 5000;
2878 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
2880 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2881 uint32_t dsparb
= I915_READ(DSPARB
);
2884 size
= dsparb
& 0x7f;
2886 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
2888 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2889 plane
? "B" : "A", size
);
2894 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
2896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2897 uint32_t dsparb
= I915_READ(DSPARB
);
2900 size
= dsparb
& 0x1ff;
2902 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
2903 size
>>= 1; /* Convert to cachelines */
2905 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2906 plane
? "B" : "A", size
);
2911 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
2913 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2914 uint32_t dsparb
= I915_READ(DSPARB
);
2917 size
= dsparb
& 0x7f;
2918 size
>>= 2; /* Convert to cachelines */
2920 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2927 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
2929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2930 uint32_t dsparb
= I915_READ(DSPARB
);
2933 size
= dsparb
& 0x7f;
2934 size
>>= 1; /* Convert to cachelines */
2936 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2937 plane
? "B" : "A", size
);
2942 static void pineview_update_wm(struct drm_device
*dev
, int planea_clock
,
2943 int planeb_clock
, int sr_hdisplay
, int unused
,
2946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2947 const struct cxsr_latency
*latency
;
2952 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
2953 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
2955 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2956 pineview_disable_cxsr(dev
);
2960 if (!planea_clock
|| !planeb_clock
) {
2961 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2964 wm
= intel_calculate_wm(sr_clock
, &pineview_display_wm
,
2965 pixel_size
, latency
->display_sr
);
2966 reg
= I915_READ(DSPFW1
);
2967 reg
&= ~DSPFW_SR_MASK
;
2968 reg
|= wm
<< DSPFW_SR_SHIFT
;
2969 I915_WRITE(DSPFW1
, reg
);
2970 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
2973 wm
= intel_calculate_wm(sr_clock
, &pineview_cursor_wm
,
2974 pixel_size
, latency
->cursor_sr
);
2975 reg
= I915_READ(DSPFW3
);
2976 reg
&= ~DSPFW_CURSOR_SR_MASK
;
2977 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
2978 I915_WRITE(DSPFW3
, reg
);
2980 /* Display HPLL off SR */
2981 wm
= intel_calculate_wm(sr_clock
, &pineview_display_hplloff_wm
,
2982 pixel_size
, latency
->display_hpll_disable
);
2983 reg
= I915_READ(DSPFW3
);
2984 reg
&= ~DSPFW_HPLL_SR_MASK
;
2985 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
2986 I915_WRITE(DSPFW3
, reg
);
2988 /* cursor HPLL off SR */
2989 wm
= intel_calculate_wm(sr_clock
, &pineview_cursor_hplloff_wm
,
2990 pixel_size
, latency
->cursor_hpll_disable
);
2991 reg
= I915_READ(DSPFW3
);
2992 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
2993 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
2994 I915_WRITE(DSPFW3
, reg
);
2995 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
2999 I915_READ(DSPFW3
) | PINEVIEW_SELF_REFRESH_EN
);
3000 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3002 pineview_disable_cxsr(dev
);
3003 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3007 static void g4x_update_wm(struct drm_device
*dev
, int planea_clock
,
3008 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3012 int total_size
, cacheline_size
;
3013 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
, cursor_sr
;
3014 struct intel_watermark_params planea_params
, planeb_params
;
3015 unsigned long line_time_us
;
3016 int sr_clock
, sr_entries
= 0, entries_required
;
3018 /* Create copies of the base settings for each pipe */
3019 planea_params
= planeb_params
= g4x_wm_info
;
3021 /* Grab a couple of global values before we overwrite them */
3022 total_size
= planea_params
.fifo_size
;
3023 cacheline_size
= planea_params
.cacheline_size
;
3026 * Note: we need to make sure we don't overflow for various clock &
3028 * clocks go from a few thousand to several hundred thousand.
3029 * latency is usually a few thousand
3031 entries_required
= ((planea_clock
/ 1000) * pixel_size
* latency_ns
) /
3033 entries_required
= DIV_ROUND_UP(entries_required
, G4X_FIFO_LINE_SIZE
);
3034 planea_wm
= entries_required
+ planea_params
.guard_size
;
3036 entries_required
= ((planeb_clock
/ 1000) * pixel_size
* latency_ns
) /
3038 entries_required
= DIV_ROUND_UP(entries_required
, G4X_FIFO_LINE_SIZE
);
3039 planeb_wm
= entries_required
+ planeb_params
.guard_size
;
3041 cursora_wm
= cursorb_wm
= 16;
3044 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
3046 /* Calc sr entries for one plane configs */
3047 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
3048 /* self-refresh has much higher latency */
3049 static const int sr_latency_ns
= 12000;
3051 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3052 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3054 /* Use ns/us then divide to preserve precision */
3055 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3056 pixel_size
* sr_hdisplay
;
3057 sr_entries
= DIV_ROUND_UP(sr_entries
, cacheline_size
);
3059 entries_required
= (((sr_latency_ns
/ line_time_us
) +
3060 1000) / 1000) * pixel_size
* 64;
3061 entries_required
= DIV_ROUND_UP(entries_required
,
3062 g4x_cursor_wm_info
.cacheline_size
);
3063 cursor_sr
= entries_required
+ g4x_cursor_wm_info
.guard_size
;
3065 if (cursor_sr
> g4x_cursor_wm_info
.max_wm
)
3066 cursor_sr
= g4x_cursor_wm_info
.max_wm
;
3067 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3068 "cursor %d\n", sr_entries
, cursor_sr
);
3070 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
3072 /* Turn off self refresh if both pipes are enabled */
3073 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3077 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3078 planea_wm
, planeb_wm
, sr_entries
);
3083 I915_WRITE(DSPFW1
, (sr_entries
<< DSPFW_SR_SHIFT
) |
3084 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
3085 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) | planea_wm
);
3086 I915_WRITE(DSPFW2
, (I915_READ(DSPFW2
) & DSPFW_CURSORA_MASK
) |
3087 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
3088 /* HPLL off in SR has some issues on G4x... disable it */
3089 I915_WRITE(DSPFW3
, (I915_READ(DSPFW3
) & ~DSPFW_HPLL_SR_EN
) |
3090 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
3093 static void i965_update_wm(struct drm_device
*dev
, int planea_clock
,
3094 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3098 unsigned long line_time_us
;
3099 int sr_clock
, sr_entries
, srwm
= 1;
3102 /* Calc sr entries for one plane configs */
3103 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
3104 /* self-refresh has much higher latency */
3105 static const int sr_latency_ns
= 12000;
3107 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3108 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3110 /* Use ns/us then divide to preserve precision */
3111 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3112 pixel_size
* sr_hdisplay
;
3113 sr_entries
= DIV_ROUND_UP(sr_entries
, I915_FIFO_LINE_SIZE
);
3114 DRM_DEBUG("self-refresh entries: %d\n", sr_entries
);
3115 srwm
= I965_FIFO_SIZE
- sr_entries
;
3120 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3122 sr_entries
= DIV_ROUND_UP(sr_entries
,
3123 i965_cursor_wm_info
.cacheline_size
);
3124 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
3125 (sr_entries
+ i965_cursor_wm_info
.guard_size
);
3127 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
3128 cursor_sr
= i965_cursor_wm_info
.max_wm
;
3130 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3131 "cursor %d\n", srwm
, cursor_sr
);
3134 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
3136 /* Turn off self refresh if both pipes are enabled */
3138 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3142 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3145 /* 965 has limitations... */
3146 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) | (8 << 16) | (8 << 8) |
3148 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
3149 /* update cursor SR watermark */
3150 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
3153 static void i9xx_update_wm(struct drm_device
*dev
, int planea_clock
,
3154 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3160 int total_size
, cacheline_size
, cwm
, srwm
= 1;
3161 int planea_wm
, planeb_wm
;
3162 struct intel_watermark_params planea_params
, planeb_params
;
3163 unsigned long line_time_us
;
3164 int sr_clock
, sr_entries
= 0;
3166 /* Create copies of the base settings for each pipe */
3167 if (IS_I965GM(dev
) || IS_I945GM(dev
))
3168 planea_params
= planeb_params
= i945_wm_info
;
3169 else if (IS_I9XX(dev
))
3170 planea_params
= planeb_params
= i915_wm_info
;
3172 planea_params
= planeb_params
= i855_wm_info
;
3174 /* Grab a couple of global values before we overwrite them */
3175 total_size
= planea_params
.fifo_size
;
3176 cacheline_size
= planea_params
.cacheline_size
;
3178 /* Update per-plane FIFO sizes */
3179 planea_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
3180 planeb_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
3182 planea_wm
= intel_calculate_wm(planea_clock
, &planea_params
,
3183 pixel_size
, latency_ns
);
3184 planeb_wm
= intel_calculate_wm(planeb_clock
, &planeb_params
,
3185 pixel_size
, latency_ns
);
3186 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
3189 * Overlay gets an aggressive default since video jitter is bad.
3193 /* Calc sr entries for one plane configs */
3194 if (HAS_FW_BLC(dev
) && sr_hdisplay
&&
3195 (!planea_clock
|| !planeb_clock
)) {
3196 /* self-refresh has much higher latency */
3197 static const int sr_latency_ns
= 6000;
3199 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3200 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3202 /* Use ns/us then divide to preserve precision */
3203 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3204 pixel_size
* sr_hdisplay
;
3205 sr_entries
= DIV_ROUND_UP(sr_entries
, cacheline_size
);
3206 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries
);
3207 srwm
= total_size
- sr_entries
;
3211 if (IS_I945G(dev
) || IS_I945GM(dev
))
3212 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
3213 else if (IS_I915GM(dev
)) {
3214 /* 915M has a smaller SRWM field */
3215 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
3216 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
3219 /* Turn off self refresh if both pipes are enabled */
3220 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
3221 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3223 } else if (IS_I915GM(dev
)) {
3224 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
3228 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3229 planea_wm
, planeb_wm
, cwm
, srwm
);
3231 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
3232 fwater_hi
= (cwm
& 0x1f);
3234 /* Set request length to 8 cachelines per fetch */
3235 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
3236 fwater_hi
= fwater_hi
| (1 << 8);
3238 I915_WRITE(FW_BLC
, fwater_lo
);
3239 I915_WRITE(FW_BLC2
, fwater_hi
);
3242 static void i830_update_wm(struct drm_device
*dev
, int planea_clock
, int unused
,
3243 int unused2
, int unused3
, int pixel_size
)
3245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3246 uint32_t fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
3249 i830_wm_info
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
3251 planea_wm
= intel_calculate_wm(planea_clock
, &i830_wm_info
,
3252 pixel_size
, latency_ns
);
3253 fwater_lo
|= (3<<8) | planea_wm
;
3255 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
3257 I915_WRITE(FW_BLC
, fwater_lo
);
3260 #define ILK_LP0_PLANE_LATENCY 700
3261 #define ILK_LP0_CURSOR_LATENCY 1300
3263 static void ironlake_update_wm(struct drm_device
*dev
, int planea_clock
,
3264 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3268 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
3269 int sr_wm
, cursor_wm
;
3270 unsigned long line_time_us
;
3271 int sr_clock
, entries_required
;
3274 int planea_htotal
= 0, planeb_htotal
= 0;
3275 struct drm_crtc
*crtc
;
3277 /* Need htotal for all active display plane */
3278 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3279 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3280 if (intel_crtc
->dpms_mode
== DRM_MODE_DPMS_ON
) {
3281 if (intel_crtc
->plane
== 0)
3282 planea_htotal
= crtc
->mode
.htotal
;
3284 planeb_htotal
= crtc
->mode
.htotal
;
3288 /* Calculate and update the watermark for plane A */
3290 entries_required
= ((planea_clock
/ 1000) * pixel_size
*
3291 ILK_LP0_PLANE_LATENCY
) / 1000;
3292 entries_required
= DIV_ROUND_UP(entries_required
,
3293 ironlake_display_wm_info
.cacheline_size
);
3294 planea_wm
= entries_required
+
3295 ironlake_display_wm_info
.guard_size
;
3297 if (planea_wm
> (int)ironlake_display_wm_info
.max_wm
)
3298 planea_wm
= ironlake_display_wm_info
.max_wm
;
3300 /* Use the large buffer method to calculate cursor watermark */
3301 line_time_us
= (planea_htotal
* 1000) / planea_clock
;
3303 /* Use ns/us then divide to preserve precision */
3304 line_count
= (ILK_LP0_CURSOR_LATENCY
/ line_time_us
+ 1000) / 1000;
3306 /* calculate the cursor watermark for cursor A */
3307 entries_required
= line_count
* 64 * pixel_size
;
3308 entries_required
= DIV_ROUND_UP(entries_required
,
3309 ironlake_cursor_wm_info
.cacheline_size
);
3310 cursora_wm
= entries_required
+ ironlake_cursor_wm_info
.guard_size
;
3311 if (cursora_wm
> ironlake_cursor_wm_info
.max_wm
)
3312 cursora_wm
= ironlake_cursor_wm_info
.max_wm
;
3314 reg_value
= I915_READ(WM0_PIPEA_ILK
);
3315 reg_value
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
3316 reg_value
|= (planea_wm
<< WM0_PIPE_PLANE_SHIFT
) |
3317 (cursora_wm
& WM0_PIPE_CURSOR_MASK
);
3318 I915_WRITE(WM0_PIPEA_ILK
, reg_value
);
3319 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3320 "cursor: %d\n", planea_wm
, cursora_wm
);
3322 /* Calculate and update the watermark for plane B */
3324 entries_required
= ((planeb_clock
/ 1000) * pixel_size
*
3325 ILK_LP0_PLANE_LATENCY
) / 1000;
3326 entries_required
= DIV_ROUND_UP(entries_required
,
3327 ironlake_display_wm_info
.cacheline_size
);
3328 planeb_wm
= entries_required
+
3329 ironlake_display_wm_info
.guard_size
;
3331 if (planeb_wm
> (int)ironlake_display_wm_info
.max_wm
)
3332 planeb_wm
= ironlake_display_wm_info
.max_wm
;
3334 /* Use the large buffer method to calculate cursor watermark */
3335 line_time_us
= (planeb_htotal
* 1000) / planeb_clock
;
3337 /* Use ns/us then divide to preserve precision */
3338 line_count
= (ILK_LP0_CURSOR_LATENCY
/ line_time_us
+ 1000) / 1000;
3340 /* calculate the cursor watermark for cursor B */
3341 entries_required
= line_count
* 64 * pixel_size
;
3342 entries_required
= DIV_ROUND_UP(entries_required
,
3343 ironlake_cursor_wm_info
.cacheline_size
);
3344 cursorb_wm
= entries_required
+ ironlake_cursor_wm_info
.guard_size
;
3345 if (cursorb_wm
> ironlake_cursor_wm_info
.max_wm
)
3346 cursorb_wm
= ironlake_cursor_wm_info
.max_wm
;
3348 reg_value
= I915_READ(WM0_PIPEB_ILK
);
3349 reg_value
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
3350 reg_value
|= (planeb_wm
<< WM0_PIPE_PLANE_SHIFT
) |
3351 (cursorb_wm
& WM0_PIPE_CURSOR_MASK
);
3352 I915_WRITE(WM0_PIPEB_ILK
, reg_value
);
3353 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3354 "cursor: %d\n", planeb_wm
, cursorb_wm
);
3358 * Calculate and update the self-refresh watermark only when one
3359 * display plane is used.
3361 if (!planea_clock
|| !planeb_clock
) {
3363 /* Read the self-refresh latency. The unit is 0.5us */
3364 int ilk_sr_latency
= I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
;
3366 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3367 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3369 /* Use ns/us then divide to preserve precision */
3370 line_count
= ((ilk_sr_latency
* 500) / line_time_us
+ 1000)
3373 /* calculate the self-refresh watermark for display plane */
3374 entries_required
= line_count
* sr_hdisplay
* pixel_size
;
3375 entries_required
= DIV_ROUND_UP(entries_required
,
3376 ironlake_display_srwm_info
.cacheline_size
);
3377 sr_wm
= entries_required
+
3378 ironlake_display_srwm_info
.guard_size
;
3380 /* calculate the self-refresh watermark for display cursor */
3381 entries_required
= line_count
* pixel_size
* 64;
3382 entries_required
= DIV_ROUND_UP(entries_required
,
3383 ironlake_cursor_srwm_info
.cacheline_size
);
3384 cursor_wm
= entries_required
+
3385 ironlake_cursor_srwm_info
.guard_size
;
3387 /* configure watermark and enable self-refresh */
3388 reg_value
= I915_READ(WM1_LP_ILK
);
3389 reg_value
&= ~(WM1_LP_LATENCY_MASK
| WM1_LP_SR_MASK
|
3390 WM1_LP_CURSOR_MASK
);
3391 reg_value
|= WM1_LP_SR_EN
|
3392 (ilk_sr_latency
<< WM1_LP_LATENCY_SHIFT
) |
3393 (sr_wm
<< WM1_LP_SR_SHIFT
) | cursor_wm
;
3395 I915_WRITE(WM1_LP_ILK
, reg_value
);
3396 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3397 "cursor %d\n", sr_wm
, cursor_wm
);
3400 /* Turn off self refresh if both pipes are enabled */
3401 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
3405 * intel_update_watermarks - update FIFO watermark values based on current modes
3407 * Calculate watermark values for the various WM regs based on current mode
3408 * and plane configuration.
3410 * There are several cases to deal with here:
3411 * - normal (i.e. non-self-refresh)
3412 * - self-refresh (SR) mode
3413 * - lines are large relative to FIFO size (buffer can hold up to 2)
3414 * - lines are small relative to FIFO size (buffer can hold more than 2
3415 * lines), so need to account for TLB latency
3417 * The normal calculation is:
3418 * watermark = dotclock * bytes per pixel * latency
3419 * where latency is platform & configuration dependent (we assume pessimal
3422 * The SR calculation is:
3423 * watermark = (trunc(latency/line time)+1) * surface width *
3426 * line time = htotal / dotclock
3427 * surface width = hdisplay for normal plane and 64 for cursor
3428 * and latency is assumed to be high, as above.
3430 * The final value programmed to the register should always be rounded up,
3431 * and include an extra 2 entries to account for clock crossings.
3433 * We don't use the sprite, so we can ignore that. And on Crestline we have
3434 * to set the non-SR watermarks to 8.
3436 static void intel_update_watermarks(struct drm_device
*dev
)
3438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3439 struct drm_crtc
*crtc
;
3440 int sr_hdisplay
= 0;
3441 unsigned long planea_clock
= 0, planeb_clock
= 0, sr_clock
= 0;
3442 int enabled
= 0, pixel_size
= 0;
3445 if (!dev_priv
->display
.update_wm
)
3448 /* Get the clock config from both planes */
3449 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3450 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3451 if (intel_crtc
->dpms_mode
== DRM_MODE_DPMS_ON
) {
3453 if (intel_crtc
->plane
== 0) {
3454 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3455 intel_crtc
->pipe
, crtc
->mode
.clock
);
3456 planea_clock
= crtc
->mode
.clock
;
3458 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3459 intel_crtc
->pipe
, crtc
->mode
.clock
);
3460 planeb_clock
= crtc
->mode
.clock
;
3462 sr_hdisplay
= crtc
->mode
.hdisplay
;
3463 sr_clock
= crtc
->mode
.clock
;
3464 sr_htotal
= crtc
->mode
.htotal
;
3466 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3468 pixel_size
= 4; /* by default */
3475 dev_priv
->display
.update_wm(dev
, planea_clock
, planeb_clock
,
3476 sr_hdisplay
, sr_htotal
, pixel_size
);
3479 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
3480 struct drm_display_mode
*mode
,
3481 struct drm_display_mode
*adjusted_mode
,
3483 struct drm_framebuffer
*old_fb
)
3485 struct drm_device
*dev
= crtc
->dev
;
3486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3487 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3488 int pipe
= intel_crtc
->pipe
;
3489 int plane
= intel_crtc
->plane
;
3490 int fp_reg
= (pipe
== 0) ? FPA0
: FPB0
;
3491 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
3492 int dpll_md_reg
= (intel_crtc
->pipe
== 0) ? DPLL_A_MD
: DPLL_B_MD
;
3493 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
3494 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
3495 int htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
3496 int hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
3497 int hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
3498 int vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
3499 int vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
3500 int vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
3501 int dspsize_reg
= (plane
== 0) ? DSPASIZE
: DSPBSIZE
;
3502 int dsppos_reg
= (plane
== 0) ? DSPAPOS
: DSPBPOS
;
3503 int pipesrc_reg
= (pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
3504 int refclk
, num_connectors
= 0;
3505 intel_clock_t clock
, reduced_clock
;
3506 u32 dpll
= 0, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
3507 bool ok
, has_reduced_clock
= false, is_sdvo
= false, is_dvo
= false;
3508 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
3509 struct intel_encoder
*has_edp_encoder
= NULL
;
3510 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3511 struct drm_encoder
*encoder
;
3512 const intel_limit_t
*limit
;
3514 struct fdi_m_n m_n
= {0};
3515 int data_m1_reg
= (pipe
== 0) ? PIPEA_DATA_M1
: PIPEB_DATA_M1
;
3516 int data_n1_reg
= (pipe
== 0) ? PIPEA_DATA_N1
: PIPEB_DATA_N1
;
3517 int link_m1_reg
= (pipe
== 0) ? PIPEA_LINK_M1
: PIPEB_LINK_M1
;
3518 int link_n1_reg
= (pipe
== 0) ? PIPEA_LINK_N1
: PIPEB_LINK_N1
;
3519 int pch_fp_reg
= (pipe
== 0) ? PCH_FPA0
: PCH_FPB0
;
3520 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
3521 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
3522 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
3523 int trans_dpll_sel
= (pipe
== 0) ? 0 : 1;
3524 int lvds_reg
= LVDS
;
3526 int sdvo_pixel_multiply
;
3529 drm_vblank_pre_modeset(dev
, pipe
);
3531 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
3532 struct intel_encoder
*intel_encoder
;
3534 if (encoder
->crtc
!= crtc
)
3537 intel_encoder
= enc_to_intel_encoder(encoder
);
3538 switch (intel_encoder
->type
) {
3539 case INTEL_OUTPUT_LVDS
:
3542 case INTEL_OUTPUT_SDVO
:
3543 case INTEL_OUTPUT_HDMI
:
3545 if (intel_encoder
->needs_tv_clock
)
3548 case INTEL_OUTPUT_DVO
:
3551 case INTEL_OUTPUT_TVOUT
:
3554 case INTEL_OUTPUT_ANALOG
:
3557 case INTEL_OUTPUT_DISPLAYPORT
:
3560 case INTEL_OUTPUT_EDP
:
3561 has_edp_encoder
= intel_encoder
;
3568 if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_connectors
< 2) {
3569 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
3570 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3572 } else if (IS_I9XX(dev
)) {
3574 if (HAS_PCH_SPLIT(dev
))
3575 refclk
= 120000; /* 120Mhz refclk */
3582 * Returns a set of divisors for the desired target clock with the given
3583 * refclk, or FALSE. The returned values represent the clock equation:
3584 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3586 limit
= intel_limit(crtc
);
3587 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, &clock
);
3589 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3590 drm_vblank_post_modeset(dev
, pipe
);
3594 /* Ensure that the cursor is valid for the new mode before changing... */
3595 intel_crtc_update_cursor(crtc
);
3597 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
3598 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
3599 dev_priv
->lvds_downclock
,
3602 if (has_reduced_clock
&& (clock
.p
!= reduced_clock
.p
)) {
3604 * If the different P is found, it means that we can't
3605 * switch the display clock by using the FP0/FP1.
3606 * In such case we will disable the LVDS downclock
3609 DRM_DEBUG_KMS("Different P is found for "
3610 "LVDS clock/downclock\n");
3611 has_reduced_clock
= 0;
3614 /* SDVO TV has fixed PLL values depend on its clock range,
3615 this mirrors vbios setting. */
3616 if (is_sdvo
&& is_tv
) {
3617 if (adjusted_mode
->clock
>= 100000
3618 && adjusted_mode
->clock
< 140500) {
3624 } else if (adjusted_mode
->clock
>= 140500
3625 && adjusted_mode
->clock
<= 200000) {
3635 if (HAS_PCH_SPLIT(dev
)) {
3636 int lane
= 0, link_bw
, bpp
;
3637 /* eDP doesn't require FDI link, so just set DP M/N
3638 according to current link config */
3639 if (has_edp_encoder
) {
3640 target_clock
= mode
->clock
;
3641 intel_edp_link_config(has_edp_encoder
,
3644 /* DP over FDI requires target mode clock
3645 instead of link clock */
3647 target_clock
= mode
->clock
;
3649 target_clock
= adjusted_mode
->clock
;
3653 /* determine panel color depth */
3654 temp
= I915_READ(pipeconf_reg
);
3655 temp
&= ~PIPE_BPC_MASK
;
3657 int lvds_reg
= I915_READ(PCH_LVDS
);
3658 /* the BPC will be 6 if it is 18-bit LVDS panel */
3659 if ((lvds_reg
& LVDS_A3_POWER_MASK
) == LVDS_A3_POWER_UP
)
3663 } else if (has_edp_encoder
|| (is_dp
&& intel_pch_has_edp(crtc
))) {
3664 switch (dev_priv
->edp_bpp
/3) {
3680 I915_WRITE(pipeconf_reg
, temp
);
3681 I915_READ(pipeconf_reg
);
3683 switch (temp
& PIPE_BPC_MASK
) {
3697 DRM_ERROR("unknown pipe bpc value\n");
3703 * Account for spread spectrum to avoid
3704 * oversubscribing the link. Max center spread
3705 * is 2.5%; use 5% for safety's sake.
3707 u32 bps
= target_clock
* bpp
* 21 / 20;
3708 lane
= bps
/ (link_bw
* 8) + 1;
3711 intel_crtc
->fdi_lanes
= lane
;
3713 ironlake_compute_m_n(bpp
, lane
, target_clock
, link_bw
, &m_n
);
3716 /* Ironlake: try to setup display ref clock before DPLL
3717 * enabling. This is only under driver's control after
3718 * PCH B stepping, previous chipset stepping should be
3719 * ignoring this setting.
3721 if (HAS_PCH_SPLIT(dev
)) {
3722 temp
= I915_READ(PCH_DREF_CONTROL
);
3723 /* Always enable nonspread source */
3724 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
3725 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
3726 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3727 POSTING_READ(PCH_DREF_CONTROL
);
3729 temp
&= ~DREF_SSC_SOURCE_MASK
;
3730 temp
|= DREF_SSC_SOURCE_ENABLE
;
3731 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3732 POSTING_READ(PCH_DREF_CONTROL
);
3736 if (has_edp_encoder
) {
3737 if (dev_priv
->lvds_use_ssc
) {
3738 temp
|= DREF_SSC1_ENABLE
;
3739 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3740 POSTING_READ(PCH_DREF_CONTROL
);
3744 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
3745 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
3746 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3747 POSTING_READ(PCH_DREF_CONTROL
);
3749 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
3750 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3751 POSTING_READ(PCH_DREF_CONTROL
);
3756 if (IS_PINEVIEW(dev
)) {
3757 fp
= (1 << clock
.n
) << 16 | clock
.m1
<< 8 | clock
.m2
;
3758 if (has_reduced_clock
)
3759 fp2
= (1 << reduced_clock
.n
) << 16 |
3760 reduced_clock
.m1
<< 8 | reduced_clock
.m2
;
3762 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
3763 if (has_reduced_clock
)
3764 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
3768 if (!HAS_PCH_SPLIT(dev
))
3769 dpll
= DPLL_VGA_MODE_DIS
;
3773 dpll
|= DPLLB_MODE_LVDS
;
3775 dpll
|= DPLLB_MODE_DAC_SERIAL
;
3777 dpll
|= DPLL_DVO_HIGH_SPEED
;
3778 sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
3779 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3780 dpll
|= (sdvo_pixel_multiply
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
3781 else if (HAS_PCH_SPLIT(dev
))
3782 dpll
|= (sdvo_pixel_multiply
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
3785 dpll
|= DPLL_DVO_HIGH_SPEED
;
3787 /* compute bitmask from p1 value */
3788 if (IS_PINEVIEW(dev
))
3789 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
3791 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3793 if (HAS_PCH_SPLIT(dev
))
3794 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3795 if (IS_G4X(dev
) && has_reduced_clock
)
3796 dpll
|= (1 << (reduced_clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3800 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
3803 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
3806 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
3809 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
3812 if (IS_I965G(dev
) && !HAS_PCH_SPLIT(dev
))
3813 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
3816 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3819 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
3821 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3823 dpll
|= PLL_P2_DIVIDE_BY_4
;
3827 if (is_sdvo
&& is_tv
)
3828 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
3830 /* XXX: just matching BIOS for now */
3831 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3833 else if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_connectors
< 2)
3834 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
3836 dpll
|= PLL_REF_INPUT_DREFCLK
;
3838 /* setup pipeconf */
3839 pipeconf
= I915_READ(pipeconf_reg
);
3841 /* Set up the display plane register */
3842 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
3844 /* Ironlake's plane is forced to pipe, bit 24 is to
3845 enable color space conversion */
3846 if (!HAS_PCH_SPLIT(dev
)) {
3848 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
3850 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
3853 if (pipe
== 0 && !IS_I965G(dev
)) {
3854 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3857 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3861 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
3862 pipeconf
|= PIPEACONF_DOUBLE_WIDE
;
3864 pipeconf
&= ~PIPEACONF_DOUBLE_WIDE
;
3867 dspcntr
|= DISPLAY_PLANE_ENABLE
;
3868 pipeconf
|= PIPEACONF_ENABLE
;
3869 dpll
|= DPLL_VCO_ENABLE
;
3872 /* Disable the panel fitter if it was on our pipe */
3873 if (!HAS_PCH_SPLIT(dev
) && intel_panel_fitter_pipe(dev
) == pipe
)
3874 I915_WRITE(PFIT_CONTROL
, 0);
3876 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
3877 drm_mode_debug_printmodeline(mode
);
3879 /* assign to Ironlake registers */
3880 if (HAS_PCH_SPLIT(dev
)) {
3881 fp_reg
= pch_fp_reg
;
3882 dpll_reg
= pch_dpll_reg
;
3885 if (!has_edp_encoder
) {
3886 I915_WRITE(fp_reg
, fp
);
3887 I915_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3888 I915_READ(dpll_reg
);
3892 /* enable transcoder DPLL */
3893 if (HAS_PCH_CPT(dev
)) {
3894 temp
= I915_READ(PCH_DPLL_SEL
);
3895 if (trans_dpll_sel
== 0)
3896 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
3898 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3899 I915_WRITE(PCH_DPLL_SEL
, temp
);
3900 I915_READ(PCH_DPLL_SEL
);
3904 if (HAS_PCH_SPLIT(dev
)) {
3905 pipeconf
&= ~PIPE_ENABLE_DITHER
;
3906 pipeconf
&= ~PIPE_DITHER_TYPE_MASK
;
3909 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3910 * This is an exception to the general rule that mode_set doesn't turn
3916 if (HAS_PCH_SPLIT(dev
))
3917 lvds_reg
= PCH_LVDS
;
3919 lvds
= I915_READ(lvds_reg
);
3920 lvds
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
3922 if (HAS_PCH_CPT(dev
))
3923 lvds
|= PORT_TRANS_B_SEL_CPT
;
3925 lvds
|= LVDS_PIPEB_SELECT
;
3927 if (HAS_PCH_CPT(dev
))
3928 lvds
&= ~PORT_TRANS_SEL_MASK
;
3930 lvds
&= ~LVDS_PIPEB_SELECT
;
3932 /* set the corresponsding LVDS_BORDER bit */
3933 lvds
|= dev_priv
->lvds_border_bits
;
3934 /* Set the B0-B3 data pairs corresponding to whether we're going to
3935 * set the DPLLs for dual-channel mode or not.
3938 lvds
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
3940 lvds
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
3942 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3943 * appropriately here, but we need to look more thoroughly into how
3944 * panels behave in the two modes.
3946 /* set the dithering flag */
3947 if (IS_I965G(dev
)) {
3948 if (dev_priv
->lvds_dither
) {
3949 if (HAS_PCH_SPLIT(dev
)) {
3950 pipeconf
|= PIPE_ENABLE_DITHER
;
3951 pipeconf
|= PIPE_DITHER_TYPE_ST01
;
3953 lvds
|= LVDS_ENABLE_DITHER
;
3955 if (!HAS_PCH_SPLIT(dev
)) {
3956 lvds
&= ~LVDS_ENABLE_DITHER
;
3960 I915_WRITE(lvds_reg
, lvds
);
3961 I915_READ(lvds_reg
);
3964 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
3965 else if (HAS_PCH_SPLIT(dev
)) {
3966 /* For non-DP output, clear any trans DP clock recovery setting.*/
3968 I915_WRITE(TRANSA_DATA_M1
, 0);
3969 I915_WRITE(TRANSA_DATA_N1
, 0);
3970 I915_WRITE(TRANSA_DP_LINK_M1
, 0);
3971 I915_WRITE(TRANSA_DP_LINK_N1
, 0);
3973 I915_WRITE(TRANSB_DATA_M1
, 0);
3974 I915_WRITE(TRANSB_DATA_N1
, 0);
3975 I915_WRITE(TRANSB_DP_LINK_M1
, 0);
3976 I915_WRITE(TRANSB_DP_LINK_N1
, 0);
3980 if (!has_edp_encoder
) {
3981 I915_WRITE(fp_reg
, fp
);
3982 I915_WRITE(dpll_reg
, dpll
);
3983 I915_READ(dpll_reg
);
3984 /* Wait for the clocks to stabilize. */
3987 if (IS_I965G(dev
) && !HAS_PCH_SPLIT(dev
)) {
3989 sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
3990 I915_WRITE(dpll_md_reg
, (0 << DPLL_MD_UDI_DIVIDER_SHIFT
) |
3991 ((sdvo_pixel_multiply
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
));
3993 I915_WRITE(dpll_md_reg
, 0);
3995 /* write it again -- the BIOS does, after all */
3996 I915_WRITE(dpll_reg
, dpll
);
3998 I915_READ(dpll_reg
);
3999 /* Wait for the clocks to stabilize. */
4003 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
4004 I915_WRITE(fp_reg
+ 4, fp2
);
4005 intel_crtc
->lowfreq_avail
= true;
4006 if (HAS_PIPE_CXSR(dev
)) {
4007 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4008 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4011 I915_WRITE(fp_reg
+ 4, fp
);
4012 intel_crtc
->lowfreq_avail
= false;
4013 if (HAS_PIPE_CXSR(dev
)) {
4014 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4015 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4019 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4020 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4021 /* the chip adds 2 halflines automatically */
4022 adjusted_mode
->crtc_vdisplay
-= 1;
4023 adjusted_mode
->crtc_vtotal
-= 1;
4024 adjusted_mode
->crtc_vblank_start
-= 1;
4025 adjusted_mode
->crtc_vblank_end
-= 1;
4026 adjusted_mode
->crtc_vsync_end
-= 1;
4027 adjusted_mode
->crtc_vsync_start
-= 1;
4029 pipeconf
&= ~PIPECONF_INTERLACE_W_FIELD_INDICATION
; /* progressive */
4031 I915_WRITE(htot_reg
, (adjusted_mode
->crtc_hdisplay
- 1) |
4032 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4033 I915_WRITE(hblank_reg
, (adjusted_mode
->crtc_hblank_start
- 1) |
4034 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4035 I915_WRITE(hsync_reg
, (adjusted_mode
->crtc_hsync_start
- 1) |
4036 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4037 I915_WRITE(vtot_reg
, (adjusted_mode
->crtc_vdisplay
- 1) |
4038 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4039 I915_WRITE(vblank_reg
, (adjusted_mode
->crtc_vblank_start
- 1) |
4040 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4041 I915_WRITE(vsync_reg
, (adjusted_mode
->crtc_vsync_start
- 1) |
4042 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4043 /* pipesrc and dspsize control the size that is scaled from, which should
4044 * always be the user's requested size.
4046 if (!HAS_PCH_SPLIT(dev
)) {
4047 I915_WRITE(dspsize_reg
, ((mode
->vdisplay
- 1) << 16) |
4048 (mode
->hdisplay
- 1));
4049 I915_WRITE(dsppos_reg
, 0);
4051 I915_WRITE(pipesrc_reg
, ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4053 if (HAS_PCH_SPLIT(dev
)) {
4054 I915_WRITE(data_m1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
4055 I915_WRITE(data_n1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_n
);
4056 I915_WRITE(link_m1_reg
, m_n
.link_m
);
4057 I915_WRITE(link_n1_reg
, m_n
.link_n
);
4059 if (has_edp_encoder
) {
4060 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
4062 /* enable FDI RX PLL too */
4063 temp
= I915_READ(fdi_rx_reg
);
4064 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
);
4065 I915_READ(fdi_rx_reg
);
4068 /* enable FDI TX PLL too */
4069 temp
= I915_READ(fdi_tx_reg
);
4070 I915_WRITE(fdi_tx_reg
, temp
| FDI_TX_PLL_ENABLE
);
4071 I915_READ(fdi_tx_reg
);
4073 /* enable FDI RX PCDCLK */
4074 temp
= I915_READ(fdi_rx_reg
);
4075 I915_WRITE(fdi_rx_reg
, temp
| FDI_SEL_PCDCLK
);
4076 I915_READ(fdi_rx_reg
);
4081 I915_WRITE(pipeconf_reg
, pipeconf
);
4082 I915_READ(pipeconf_reg
);
4084 intel_wait_for_vblank(dev
, pipe
);
4086 if (IS_IRONLAKE(dev
)) {
4087 /* enable address swizzle for tiling buffer */
4088 temp
= I915_READ(DISP_ARB_CTL
);
4089 I915_WRITE(DISP_ARB_CTL
, temp
| DISP_TILE_SURFACE_SWIZZLING
);
4092 I915_WRITE(dspcntr_reg
, dspcntr
);
4094 /* Flush the plane changes */
4095 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
4097 intel_update_watermarks(dev
);
4099 drm_vblank_post_modeset(dev
, pipe
);
4104 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4105 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4107 struct drm_device
*dev
= crtc
->dev
;
4108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4109 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4110 int palreg
= (intel_crtc
->pipe
== 0) ? PALETTE_A
: PALETTE_B
;
4113 /* The clocks have to be on to load the palette. */
4117 /* use legacy palette for Ironlake */
4118 if (HAS_PCH_SPLIT(dev
))
4119 palreg
= (intel_crtc
->pipe
== 0) ? LGC_PALETTE_A
:
4122 for (i
= 0; i
< 256; i
++) {
4123 I915_WRITE(palreg
+ 4 * i
,
4124 (intel_crtc
->lut_r
[i
] << 16) |
4125 (intel_crtc
->lut_g
[i
] << 8) |
4126 intel_crtc
->lut_b
[i
]);
4130 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
4132 struct drm_device
*dev
= crtc
->dev
;
4133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4134 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4135 bool visible
= base
!= 0;
4138 if (intel_crtc
->cursor_visible
== visible
)
4141 cntl
= I915_READ(CURACNTR
);
4143 /* On these chipsets we can only modify the base whilst
4144 * the cursor is disabled.
4146 I915_WRITE(CURABASE
, base
);
4148 cntl
&= ~(CURSOR_FORMAT_MASK
);
4149 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4150 cntl
|= CURSOR_ENABLE
|
4151 CURSOR_GAMMA_ENABLE
|
4154 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
4155 I915_WRITE(CURACNTR
, cntl
);
4157 intel_crtc
->cursor_visible
= visible
;
4160 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
4162 struct drm_device
*dev
= crtc
->dev
;
4163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4164 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4165 int pipe
= intel_crtc
->pipe
;
4166 bool visible
= base
!= 0;
4168 if (intel_crtc
->cursor_visible
!= visible
) {
4169 uint32_t cntl
= I915_READ(pipe
== 0 ? CURACNTR
: CURBCNTR
);
4171 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
4172 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
4173 cntl
|= pipe
<< 28; /* Connect to correct pipe */
4175 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
4176 cntl
|= CURSOR_MODE_DISABLE
;
4178 I915_WRITE(pipe
== 0 ? CURACNTR
: CURBCNTR
, cntl
);
4180 intel_crtc
->cursor_visible
= visible
;
4182 /* and commit changes on next vblank */
4183 I915_WRITE(pipe
== 0 ? CURABASE
: CURBBASE
, base
);
4186 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4187 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
)
4189 struct drm_device
*dev
= crtc
->dev
;
4190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4191 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4192 int pipe
= intel_crtc
->pipe
;
4193 int x
= intel_crtc
->cursor_x
;
4194 int y
= intel_crtc
->cursor_y
;
4200 if (intel_crtc
->cursor_on
&& crtc
->fb
) {
4201 base
= intel_crtc
->cursor_addr
;
4202 if (x
> (int) crtc
->fb
->width
)
4205 if (y
> (int) crtc
->fb
->height
)
4211 if (x
+ intel_crtc
->cursor_width
< 0)
4214 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
4217 pos
|= x
<< CURSOR_X_SHIFT
;
4220 if (y
+ intel_crtc
->cursor_height
< 0)
4223 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
4226 pos
|= y
<< CURSOR_Y_SHIFT
;
4228 visible
= base
!= 0;
4229 if (!visible
&& !intel_crtc
->cursor_visible
)
4232 I915_WRITE(pipe
== 0 ? CURAPOS
: CURBPOS
, pos
);
4233 if (IS_845G(dev
) || IS_I865G(dev
))
4234 i845_update_cursor(crtc
, base
);
4236 i9xx_update_cursor(crtc
, base
);
4239 intel_mark_busy(dev
, to_intel_framebuffer(crtc
->fb
)->obj
);
4242 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
4243 struct drm_file
*file_priv
,
4245 uint32_t width
, uint32_t height
)
4247 struct drm_device
*dev
= crtc
->dev
;
4248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4249 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4250 struct drm_gem_object
*bo
;
4251 struct drm_i915_gem_object
*obj_priv
;
4255 DRM_DEBUG_KMS("\n");
4257 /* if we want to turn off the cursor ignore width and height */
4259 DRM_DEBUG_KMS("cursor off\n");
4262 mutex_lock(&dev
->struct_mutex
);
4266 /* Currently we only support 64x64 cursors */
4267 if (width
!= 64 || height
!= 64) {
4268 DRM_ERROR("we currently only support 64x64 cursors\n");
4272 bo
= drm_gem_object_lookup(dev
, file_priv
, handle
);
4276 obj_priv
= to_intel_bo(bo
);
4278 if (bo
->size
< width
* height
* 4) {
4279 DRM_ERROR("buffer is to small\n");
4284 /* we only need to pin inside GTT if cursor is non-phy */
4285 mutex_lock(&dev
->struct_mutex
);
4286 if (!dev_priv
->info
->cursor_needs_physical
) {
4287 ret
= i915_gem_object_pin(bo
, PAGE_SIZE
);
4289 DRM_ERROR("failed to pin cursor bo\n");
4293 ret
= i915_gem_object_set_to_gtt_domain(bo
, 0);
4295 DRM_ERROR("failed to move cursor bo into the GTT\n");
4299 addr
= obj_priv
->gtt_offset
;
4301 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
4302 ret
= i915_gem_attach_phys_object(dev
, bo
,
4303 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
4306 DRM_ERROR("failed to attach phys object\n");
4309 addr
= obj_priv
->phys_obj
->handle
->busaddr
;
4313 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
4316 if (intel_crtc
->cursor_bo
) {
4317 if (dev_priv
->info
->cursor_needs_physical
) {
4318 if (intel_crtc
->cursor_bo
!= bo
)
4319 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
4321 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
4322 drm_gem_object_unreference(intel_crtc
->cursor_bo
);
4325 mutex_unlock(&dev
->struct_mutex
);
4327 intel_crtc
->cursor_addr
= addr
;
4328 intel_crtc
->cursor_bo
= bo
;
4329 intel_crtc
->cursor_width
= width
;
4330 intel_crtc
->cursor_height
= height
;
4332 intel_crtc_update_cursor(crtc
);
4336 i915_gem_object_unpin(bo
);
4338 mutex_unlock(&dev
->struct_mutex
);
4340 drm_gem_object_unreference_unlocked(bo
);
4344 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
4346 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4348 intel_crtc
->cursor_x
= x
;
4349 intel_crtc
->cursor_y
= y
;
4351 intel_crtc_update_cursor(crtc
);
4356 /** Sets the color ramps on behalf of RandR */
4357 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
4358 u16 blue
, int regno
)
4360 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4362 intel_crtc
->lut_r
[regno
] = red
>> 8;
4363 intel_crtc
->lut_g
[regno
] = green
>> 8;
4364 intel_crtc
->lut_b
[regno
] = blue
>> 8;
4367 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
4368 u16
*blue
, int regno
)
4370 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4372 *red
= intel_crtc
->lut_r
[regno
] << 8;
4373 *green
= intel_crtc
->lut_g
[regno
] << 8;
4374 *blue
= intel_crtc
->lut_b
[regno
] << 8;
4377 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
4378 u16
*blue
, uint32_t start
, uint32_t size
)
4380 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
4381 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4383 for (i
= start
; i
< end
; i
++) {
4384 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
4385 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
4386 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
4389 intel_crtc_load_lut(crtc
);
4393 * Get a pipe with a simple mode set on it for doing load-based monitor
4396 * It will be up to the load-detect code to adjust the pipe as appropriate for
4397 * its requirements. The pipe will be connected to no other encoders.
4399 * Currently this code will only succeed if there is a pipe with no encoders
4400 * configured for it. In the future, it could choose to temporarily disable
4401 * some outputs to free up a pipe for its use.
4403 * \return crtc, or NULL if no pipes are available.
4406 /* VESA 640x480x72Hz mode to set on the pipe */
4407 static struct drm_display_mode load_detect_mode
= {
4408 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
4409 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
4412 struct drm_crtc
*intel_get_load_detect_pipe(struct intel_encoder
*intel_encoder
,
4413 struct drm_connector
*connector
,
4414 struct drm_display_mode
*mode
,
4417 struct intel_crtc
*intel_crtc
;
4418 struct drm_crtc
*possible_crtc
;
4419 struct drm_crtc
*supported_crtc
=NULL
;
4420 struct drm_encoder
*encoder
= &intel_encoder
->enc
;
4421 struct drm_crtc
*crtc
= NULL
;
4422 struct drm_device
*dev
= encoder
->dev
;
4423 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
4424 struct drm_crtc_helper_funcs
*crtc_funcs
;
4428 * Algorithm gets a little messy:
4429 * - if the connector already has an assigned crtc, use it (but make
4430 * sure it's on first)
4431 * - try to find the first unused crtc that can drive this connector,
4432 * and use that if we find one
4433 * - if there are no unused crtcs available, try to use the first
4434 * one we found that supports the connector
4437 /* See if we already have a CRTC for this connector */
4438 if (encoder
->crtc
) {
4439 crtc
= encoder
->crtc
;
4440 /* Make sure the crtc and connector are running */
4441 intel_crtc
= to_intel_crtc(crtc
);
4442 *dpms_mode
= intel_crtc
->dpms_mode
;
4443 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
4444 crtc_funcs
= crtc
->helper_private
;
4445 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
4446 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
4451 /* Find an unused one (if possible) */
4452 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
4454 if (!(encoder
->possible_crtcs
& (1 << i
)))
4456 if (!possible_crtc
->enabled
) {
4457 crtc
= possible_crtc
;
4460 if (!supported_crtc
)
4461 supported_crtc
= possible_crtc
;
4465 * If we didn't find an unused CRTC, don't use any.
4471 encoder
->crtc
= crtc
;
4472 connector
->encoder
= encoder
;
4473 intel_encoder
->load_detect_temp
= true;
4475 intel_crtc
= to_intel_crtc(crtc
);
4476 *dpms_mode
= intel_crtc
->dpms_mode
;
4478 if (!crtc
->enabled
) {
4480 mode
= &load_detect_mode
;
4481 drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, crtc
->fb
);
4483 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
4484 crtc_funcs
= crtc
->helper_private
;
4485 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
4488 /* Add this connector to the crtc */
4489 encoder_funcs
->mode_set(encoder
, &crtc
->mode
, &crtc
->mode
);
4490 encoder_funcs
->commit(encoder
);
4492 /* let the connector get through one full cycle before testing */
4493 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
4498 void intel_release_load_detect_pipe(struct intel_encoder
*intel_encoder
,
4499 struct drm_connector
*connector
, int dpms_mode
)
4501 struct drm_encoder
*encoder
= &intel_encoder
->enc
;
4502 struct drm_device
*dev
= encoder
->dev
;
4503 struct drm_crtc
*crtc
= encoder
->crtc
;
4504 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
4505 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
4507 if (intel_encoder
->load_detect_temp
) {
4508 encoder
->crtc
= NULL
;
4509 connector
->encoder
= NULL
;
4510 intel_encoder
->load_detect_temp
= false;
4511 crtc
->enabled
= drm_helper_crtc_in_use(crtc
);
4512 drm_helper_disable_unused_functions(dev
);
4515 /* Switch crtc and encoder back off if necessary */
4516 if (crtc
->enabled
&& dpms_mode
!= DRM_MODE_DPMS_ON
) {
4517 if (encoder
->crtc
== crtc
)
4518 encoder_funcs
->dpms(encoder
, dpms_mode
);
4519 crtc_funcs
->dpms(crtc
, dpms_mode
);
4523 /* Returns the clock of the currently programmed mode of the given pipe. */
4524 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
4526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4527 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4528 int pipe
= intel_crtc
->pipe
;
4529 u32 dpll
= I915_READ((pipe
== 0) ? DPLL_A
: DPLL_B
);
4531 intel_clock_t clock
;
4533 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
4534 fp
= I915_READ((pipe
== 0) ? FPA0
: FPB0
);
4536 fp
= I915_READ((pipe
== 0) ? FPA1
: FPB1
);
4538 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
4539 if (IS_PINEVIEW(dev
)) {
4540 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
4541 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
4543 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
4544 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
4548 if (IS_PINEVIEW(dev
))
4549 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
4550 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
4552 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
4553 DPLL_FPA01_P1_POST_DIV_SHIFT
);
4555 switch (dpll
& DPLL_MODE_MASK
) {
4556 case DPLLB_MODE_DAC_SERIAL
:
4557 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
4560 case DPLLB_MODE_LVDS
:
4561 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
4565 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4566 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
4570 /* XXX: Handle the 100Mhz refclk */
4571 intel_clock(dev
, 96000, &clock
);
4573 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
4576 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
4577 DPLL_FPA01_P1_POST_DIV_SHIFT
);
4580 if ((dpll
& PLL_REF_INPUT_MASK
) ==
4581 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
4582 /* XXX: might not be 66MHz */
4583 intel_clock(dev
, 66000, &clock
);
4585 intel_clock(dev
, 48000, &clock
);
4587 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
4590 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
4591 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
4593 if (dpll
& PLL_P2_DIVIDE_BY_4
)
4598 intel_clock(dev
, 48000, &clock
);
4602 /* XXX: It would be nice to validate the clocks, but we can't reuse
4603 * i830PllIsValid() because it relies on the xf86_config connector
4604 * configuration being accurate, which it isn't necessarily.
4610 /** Returns the currently programmed mode of the given pipe. */
4611 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
4612 struct drm_crtc
*crtc
)
4614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4615 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4616 int pipe
= intel_crtc
->pipe
;
4617 struct drm_display_mode
*mode
;
4618 int htot
= I915_READ((pipe
== 0) ? HTOTAL_A
: HTOTAL_B
);
4619 int hsync
= I915_READ((pipe
== 0) ? HSYNC_A
: HSYNC_B
);
4620 int vtot
= I915_READ((pipe
== 0) ? VTOTAL_A
: VTOTAL_B
);
4621 int vsync
= I915_READ((pipe
== 0) ? VSYNC_A
: VSYNC_B
);
4623 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
4627 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
4628 mode
->hdisplay
= (htot
& 0xffff) + 1;
4629 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
4630 mode
->hsync_start
= (hsync
& 0xffff) + 1;
4631 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
4632 mode
->vdisplay
= (vtot
& 0xffff) + 1;
4633 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
4634 mode
->vsync_start
= (vsync
& 0xffff) + 1;
4635 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
4637 drm_mode_set_name(mode
);
4638 drm_mode_set_crtcinfo(mode
, 0);
4643 #define GPU_IDLE_TIMEOUT 500 /* ms */
4645 /* When this timer fires, we've been idle for awhile */
4646 static void intel_gpu_idle_timer(unsigned long arg
)
4648 struct drm_device
*dev
= (struct drm_device
*)arg
;
4649 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4651 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4653 dev_priv
->busy
= false;
4655 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
4658 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4660 static void intel_crtc_idle_timer(unsigned long arg
)
4662 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
4663 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4664 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
4666 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4668 intel_crtc
->busy
= false;
4670 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
4673 static void intel_increase_pllclock(struct drm_crtc
*crtc
, bool schedule
)
4675 struct drm_device
*dev
= crtc
->dev
;
4676 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4677 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4678 int pipe
= intel_crtc
->pipe
;
4679 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
4680 int dpll
= I915_READ(dpll_reg
);
4682 if (HAS_PCH_SPLIT(dev
))
4685 if (!dev_priv
->lvds_downclock_avail
)
4688 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
4689 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4691 /* Unlock panel regs */
4692 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) |
4695 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
4696 I915_WRITE(dpll_reg
, dpll
);
4697 dpll
= I915_READ(dpll_reg
);
4698 intel_wait_for_vblank(dev
, pipe
);
4699 dpll
= I915_READ(dpll_reg
);
4700 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
4701 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4703 /* ...and lock them again */
4704 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
4707 /* Schedule downclock */
4709 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
4710 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
4713 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
4715 struct drm_device
*dev
= crtc
->dev
;
4716 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4717 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4718 int pipe
= intel_crtc
->pipe
;
4719 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
4720 int dpll
= I915_READ(dpll_reg
);
4722 if (HAS_PCH_SPLIT(dev
))
4725 if (!dev_priv
->lvds_downclock_avail
)
4729 * Since this is called by a timer, we should never get here in
4732 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
4733 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4735 /* Unlock panel regs */
4736 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) |
4739 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
4740 I915_WRITE(dpll_reg
, dpll
);
4741 dpll
= I915_READ(dpll_reg
);
4742 intel_wait_for_vblank(dev
, pipe
);
4743 dpll
= I915_READ(dpll_reg
);
4744 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
4745 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4747 /* ...and lock them again */
4748 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
4754 * intel_idle_update - adjust clocks for idleness
4755 * @work: work struct
4757 * Either the GPU or display (or both) went idle. Check the busy status
4758 * here and adjust the CRTC and GPU clocks as necessary.
4760 static void intel_idle_update(struct work_struct
*work
)
4762 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
4764 struct drm_device
*dev
= dev_priv
->dev
;
4765 struct drm_crtc
*crtc
;
4766 struct intel_crtc
*intel_crtc
;
4769 if (!i915_powersave
)
4772 mutex_lock(&dev
->struct_mutex
);
4774 i915_update_gfx_val(dev_priv
);
4776 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4777 /* Skip inactive CRTCs */
4782 intel_crtc
= to_intel_crtc(crtc
);
4783 if (!intel_crtc
->busy
)
4784 intel_decrease_pllclock(crtc
);
4787 if ((enabled
== 1) && (IS_I945G(dev
) || IS_I945GM(dev
))) {
4788 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4789 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
4792 mutex_unlock(&dev
->struct_mutex
);
4796 * intel_mark_busy - mark the GPU and possibly the display busy
4798 * @obj: object we're operating on
4800 * Callers can use this function to indicate that the GPU is busy processing
4801 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4802 * buffer), we'll also mark the display as busy, so we know to increase its
4805 void intel_mark_busy(struct drm_device
*dev
, struct drm_gem_object
*obj
)
4807 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4808 struct drm_crtc
*crtc
= NULL
;
4809 struct intel_framebuffer
*intel_fb
;
4810 struct intel_crtc
*intel_crtc
;
4812 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4815 if (!dev_priv
->busy
) {
4816 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4819 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4820 fw_blc_self
= I915_READ(FW_BLC_SELF
);
4821 fw_blc_self
&= ~FW_BLC_SELF_EN
;
4822 I915_WRITE(FW_BLC_SELF
, fw_blc_self
| FW_BLC_SELF_EN_MASK
);
4824 dev_priv
->busy
= true;
4826 mod_timer(&dev_priv
->idle_timer
, jiffies
+
4827 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
4829 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4833 intel_crtc
= to_intel_crtc(crtc
);
4834 intel_fb
= to_intel_framebuffer(crtc
->fb
);
4835 if (intel_fb
->obj
== obj
) {
4836 if (!intel_crtc
->busy
) {
4837 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4840 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4841 fw_blc_self
= I915_READ(FW_BLC_SELF
);
4842 fw_blc_self
&= ~FW_BLC_SELF_EN
;
4843 I915_WRITE(FW_BLC_SELF
, fw_blc_self
| FW_BLC_SELF_EN_MASK
);
4845 /* Non-busy -> busy, upclock */
4846 intel_increase_pllclock(crtc
, true);
4847 intel_crtc
->busy
= true;
4849 /* Busy -> busy, put off timer */
4850 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
4851 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
4857 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
4859 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4861 drm_crtc_cleanup(crtc
);
4865 static void intel_unpin_work_fn(struct work_struct
*__work
)
4867 struct intel_unpin_work
*work
=
4868 container_of(__work
, struct intel_unpin_work
, work
);
4870 mutex_lock(&work
->dev
->struct_mutex
);
4871 i915_gem_object_unpin(work
->old_fb_obj
);
4872 drm_gem_object_unreference(work
->pending_flip_obj
);
4873 drm_gem_object_unreference(work
->old_fb_obj
);
4874 mutex_unlock(&work
->dev
->struct_mutex
);
4878 static void do_intel_finish_page_flip(struct drm_device
*dev
,
4879 struct drm_crtc
*crtc
)
4881 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4882 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4883 struct intel_unpin_work
*work
;
4884 struct drm_i915_gem_object
*obj_priv
;
4885 struct drm_pending_vblank_event
*e
;
4887 unsigned long flags
;
4889 /* Ignore early vblank irqs */
4890 if (intel_crtc
== NULL
)
4893 spin_lock_irqsave(&dev
->event_lock
, flags
);
4894 work
= intel_crtc
->unpin_work
;
4895 if (work
== NULL
|| !work
->pending
) {
4896 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4900 intel_crtc
->unpin_work
= NULL
;
4901 drm_vblank_put(dev
, intel_crtc
->pipe
);
4905 do_gettimeofday(&now
);
4906 e
->event
.sequence
= drm_vblank_count(dev
, intel_crtc
->pipe
);
4907 e
->event
.tv_sec
= now
.tv_sec
;
4908 e
->event
.tv_usec
= now
.tv_usec
;
4909 list_add_tail(&e
->base
.link
,
4910 &e
->base
.file_priv
->event_list
);
4911 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
4914 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4916 obj_priv
= to_intel_bo(work
->pending_flip_obj
);
4918 /* Initial scanout buffer will have a 0 pending flip count */
4919 if ((atomic_read(&obj_priv
->pending_flip
) == 0) ||
4920 atomic_dec_and_test(&obj_priv
->pending_flip
))
4921 DRM_WAKEUP(&dev_priv
->pending_flip_queue
);
4922 schedule_work(&work
->work
);
4924 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
4927 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
4929 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4930 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
4932 do_intel_finish_page_flip(dev
, crtc
);
4935 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
4937 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4938 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
4940 do_intel_finish_page_flip(dev
, crtc
);
4943 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
4945 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4946 struct intel_crtc
*intel_crtc
=
4947 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
4948 unsigned long flags
;
4950 spin_lock_irqsave(&dev
->event_lock
, flags
);
4951 if (intel_crtc
->unpin_work
) {
4952 if ((++intel_crtc
->unpin_work
->pending
) > 1)
4953 DRM_ERROR("Prepared flip multiple times\n");
4955 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4957 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4960 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
4961 struct drm_framebuffer
*fb
,
4962 struct drm_pending_vblank_event
*event
)
4964 struct drm_device
*dev
= crtc
->dev
;
4965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4966 struct intel_framebuffer
*intel_fb
;
4967 struct drm_i915_gem_object
*obj_priv
;
4968 struct drm_gem_object
*obj
;
4969 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4970 struct intel_unpin_work
*work
;
4971 unsigned long flags
, offset
;
4972 int pipe
= intel_crtc
->pipe
;
4976 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
4980 work
->event
= event
;
4981 work
->dev
= crtc
->dev
;
4982 intel_fb
= to_intel_framebuffer(crtc
->fb
);
4983 work
->old_fb_obj
= intel_fb
->obj
;
4984 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
4986 /* We borrow the event spin lock for protecting unpin_work */
4987 spin_lock_irqsave(&dev
->event_lock
, flags
);
4988 if (intel_crtc
->unpin_work
) {
4989 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4992 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4995 intel_crtc
->unpin_work
= work
;
4996 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4998 intel_fb
= to_intel_framebuffer(fb
);
4999 obj
= intel_fb
->obj
;
5001 mutex_lock(&dev
->struct_mutex
);
5002 ret
= intel_pin_and_fence_fb_obj(dev
, obj
);
5006 /* Reference the objects for the scheduled work. */
5007 drm_gem_object_reference(work
->old_fb_obj
);
5008 drm_gem_object_reference(obj
);
5011 ret
= i915_gem_object_flush_write_domain(obj
);
5015 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
5019 obj_priv
= to_intel_bo(obj
);
5020 atomic_inc(&obj_priv
->pending_flip
);
5021 work
->pending_flip_obj
= obj
;
5023 if (IS_GEN3(dev
) || IS_GEN2(dev
)) {
5026 if (intel_crtc
->plane
)
5027 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
5029 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
5032 OUT_RING(MI_WAIT_FOR_EVENT
| flip_mask
);
5037 work
->enable_stall_check
= true;
5039 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5040 offset
= crtc
->y
* fb
->pitch
+ crtc
->x
* fb
->bits_per_pixel
/8;
5043 switch(INTEL_INFO(dev
)->gen
) {
5045 OUT_RING(MI_DISPLAY_FLIP
|
5046 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5047 OUT_RING(fb
->pitch
);
5048 OUT_RING(obj_priv
->gtt_offset
+ offset
);
5053 OUT_RING(MI_DISPLAY_FLIP_I915
|
5054 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5055 OUT_RING(fb
->pitch
);
5056 OUT_RING(obj_priv
->gtt_offset
+ offset
);
5062 /* i965+ uses the linear or tiled offsets from the
5063 * Display Registers (which do not change across a page-flip)
5064 * so we need only reprogram the base address.
5066 OUT_RING(MI_DISPLAY_FLIP
|
5067 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5068 OUT_RING(fb
->pitch
);
5069 OUT_RING(obj_priv
->gtt_offset
| obj_priv
->tiling_mode
);
5071 /* XXX Enabling the panel-fitter across page-flip is so far
5072 * untested on non-native modes, so ignore it for now.
5073 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5076 pipesrc
= I915_READ(pipe
== 0 ? PIPEASRC
: PIPEBSRC
) & 0x0fff0fff;
5077 OUT_RING(pf
| pipesrc
);
5081 OUT_RING(MI_DISPLAY_FLIP
|
5082 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5083 OUT_RING(fb
->pitch
| obj_priv
->tiling_mode
);
5084 OUT_RING(obj_priv
->gtt_offset
);
5086 pf
= I915_READ(pipe
== 0 ? PFA_CTL_1
: PFB_CTL_1
) & PF_ENABLE
;
5087 pipesrc
= I915_READ(pipe
== 0 ? PIPEASRC
: PIPEBSRC
) & 0x0fff0fff;
5088 OUT_RING(pf
| pipesrc
);
5093 mutex_unlock(&dev
->struct_mutex
);
5095 trace_i915_flip_request(intel_crtc
->plane
, obj
);
5100 drm_gem_object_unreference(work
->old_fb_obj
);
5101 drm_gem_object_unreference(obj
);
5103 mutex_unlock(&dev
->struct_mutex
);
5105 spin_lock_irqsave(&dev
->event_lock
, flags
);
5106 intel_crtc
->unpin_work
= NULL
;
5107 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5114 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
5115 .dpms
= intel_crtc_dpms
,
5116 .mode_fixup
= intel_crtc_mode_fixup
,
5117 .mode_set
= intel_crtc_mode_set
,
5118 .mode_set_base
= intel_pipe_set_base
,
5119 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
5120 .prepare
= intel_crtc_prepare
,
5121 .commit
= intel_crtc_commit
,
5122 .load_lut
= intel_crtc_load_lut
,
5125 static const struct drm_crtc_funcs intel_crtc_funcs
= {
5126 .cursor_set
= intel_crtc_cursor_set
,
5127 .cursor_move
= intel_crtc_cursor_move
,
5128 .gamma_set
= intel_crtc_gamma_set
,
5129 .set_config
= drm_crtc_helper_set_config
,
5130 .destroy
= intel_crtc_destroy
,
5131 .page_flip
= intel_crtc_page_flip
,
5135 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
5137 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5138 struct intel_crtc
*intel_crtc
;
5141 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
5142 if (intel_crtc
== NULL
)
5145 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
5147 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
5148 intel_crtc
->pipe
= pipe
;
5149 intel_crtc
->plane
= pipe
;
5150 for (i
= 0; i
< 256; i
++) {
5151 intel_crtc
->lut_r
[i
] = i
;
5152 intel_crtc
->lut_g
[i
] = i
;
5153 intel_crtc
->lut_b
[i
] = i
;
5156 /* Swap pipes & planes for FBC on pre-965 */
5157 intel_crtc
->pipe
= pipe
;
5158 intel_crtc
->plane
= pipe
;
5159 if (IS_MOBILE(dev
) && (IS_I9XX(dev
) && !IS_I965G(dev
))) {
5160 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5161 intel_crtc
->plane
= ((pipe
== 0) ? 1 : 0);
5164 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
5165 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
5166 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
5167 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
5169 intel_crtc
->cursor_addr
= 0;
5170 intel_crtc
->dpms_mode
= -1;
5171 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
5173 intel_crtc
->busy
= false;
5175 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
5176 (unsigned long)intel_crtc
);
5179 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
5180 struct drm_file
*file_priv
)
5182 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5183 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
5184 struct drm_mode_object
*drmmode_obj
;
5185 struct intel_crtc
*crtc
;
5188 DRM_ERROR("called with no initialization\n");
5192 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
5193 DRM_MODE_OBJECT_CRTC
);
5196 DRM_ERROR("no such CRTC id\n");
5200 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
5201 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
5206 struct drm_crtc
*intel_get_crtc_from_pipe(struct drm_device
*dev
, int pipe
)
5208 struct drm_crtc
*crtc
= NULL
;
5210 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
5211 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5212 if (intel_crtc
->pipe
== pipe
)
5218 static int intel_encoder_clones(struct drm_device
*dev
, int type_mask
)
5221 struct drm_encoder
*encoder
;
5224 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
5225 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
5226 if (type_mask
& intel_encoder
->clone_mask
)
5227 index_mask
|= (1 << entry
);
5234 static void intel_setup_outputs(struct drm_device
*dev
)
5236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5237 struct drm_encoder
*encoder
;
5238 bool dpd_is_edp
= false;
5240 if (IS_MOBILE(dev
) && !IS_I830(dev
))
5241 intel_lvds_init(dev
);
5243 if (HAS_PCH_SPLIT(dev
)) {
5244 dpd_is_edp
= intel_dpd_is_edp(dev
);
5246 if (IS_MOBILE(dev
) && (I915_READ(DP_A
) & DP_DETECTED
))
5247 intel_dp_init(dev
, DP_A
);
5249 if (dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
5250 intel_dp_init(dev
, PCH_DP_D
);
5253 intel_crt_init(dev
);
5255 if (HAS_PCH_SPLIT(dev
)) {
5258 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
5259 /* PCH SDVOB multiplex with HDMIB */
5260 found
= intel_sdvo_init(dev
, PCH_SDVOB
);
5262 intel_hdmi_init(dev
, HDMIB
);
5263 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
5264 intel_dp_init(dev
, PCH_DP_B
);
5267 if (I915_READ(HDMIC
) & PORT_DETECTED
)
5268 intel_hdmi_init(dev
, HDMIC
);
5270 if (I915_READ(HDMID
) & PORT_DETECTED
)
5271 intel_hdmi_init(dev
, HDMID
);
5273 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
5274 intel_dp_init(dev
, PCH_DP_C
);
5276 if (!dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
5277 intel_dp_init(dev
, PCH_DP_D
);
5279 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
5282 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
5283 DRM_DEBUG_KMS("probing SDVOB\n");
5284 found
= intel_sdvo_init(dev
, SDVOB
);
5285 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
5286 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5287 intel_hdmi_init(dev
, SDVOB
);
5290 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
5291 DRM_DEBUG_KMS("probing DP_B\n");
5292 intel_dp_init(dev
, DP_B
);
5296 /* Before G4X SDVOC doesn't have its own detect register */
5298 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
5299 DRM_DEBUG_KMS("probing SDVOC\n");
5300 found
= intel_sdvo_init(dev
, SDVOC
);
5303 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
5305 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
5306 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5307 intel_hdmi_init(dev
, SDVOC
);
5309 if (SUPPORTS_INTEGRATED_DP(dev
)) {
5310 DRM_DEBUG_KMS("probing DP_C\n");
5311 intel_dp_init(dev
, DP_C
);
5315 if (SUPPORTS_INTEGRATED_DP(dev
) &&
5316 (I915_READ(DP_D
) & DP_DETECTED
)) {
5317 DRM_DEBUG_KMS("probing DP_D\n");
5318 intel_dp_init(dev
, DP_D
);
5320 } else if (IS_GEN2(dev
))
5321 intel_dvo_init(dev
);
5323 if (SUPPORTS_TV(dev
))
5326 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
5327 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
5329 encoder
->possible_crtcs
= intel_encoder
->crtc_mask
;
5330 encoder
->possible_clones
= intel_encoder_clones(dev
,
5331 intel_encoder
->clone_mask
);
5335 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
5337 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
5339 drm_framebuffer_cleanup(fb
);
5340 drm_gem_object_unreference_unlocked(intel_fb
->obj
);
5345 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
5346 struct drm_file
*file_priv
,
5347 unsigned int *handle
)
5349 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
5350 struct drm_gem_object
*object
= intel_fb
->obj
;
5352 return drm_gem_handle_create(file_priv
, object
, handle
);
5355 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
5356 .destroy
= intel_user_framebuffer_destroy
,
5357 .create_handle
= intel_user_framebuffer_create_handle
,
5360 int intel_framebuffer_init(struct drm_device
*dev
,
5361 struct intel_framebuffer
*intel_fb
,
5362 struct drm_mode_fb_cmd
*mode_cmd
,
5363 struct drm_gem_object
*obj
)
5367 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
5369 DRM_ERROR("framebuffer init failed %d\n", ret
);
5373 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
5374 intel_fb
->obj
= obj
;
5378 static struct drm_framebuffer
*
5379 intel_user_framebuffer_create(struct drm_device
*dev
,
5380 struct drm_file
*filp
,
5381 struct drm_mode_fb_cmd
*mode_cmd
)
5383 struct drm_gem_object
*obj
;
5384 struct intel_framebuffer
*intel_fb
;
5387 obj
= drm_gem_object_lookup(dev
, filp
, mode_cmd
->handle
);
5389 return ERR_PTR(-ENOENT
);
5391 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
5393 return ERR_PTR(-ENOMEM
);
5395 ret
= intel_framebuffer_init(dev
, intel_fb
,
5398 drm_gem_object_unreference_unlocked(obj
);
5400 return ERR_PTR(ret
);
5403 return &intel_fb
->base
;
5406 static const struct drm_mode_config_funcs intel_mode_funcs
= {
5407 .fb_create
= intel_user_framebuffer_create
,
5408 .output_poll_changed
= intel_fb_output_poll_changed
,
5411 static struct drm_gem_object
*
5412 intel_alloc_context_page(struct drm_device
*dev
)
5414 struct drm_gem_object
*ctx
;
5417 ctx
= i915_gem_alloc_object(dev
, 4096);
5419 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5423 mutex_lock(&dev
->struct_mutex
);
5424 ret
= i915_gem_object_pin(ctx
, 4096);
5426 DRM_ERROR("failed to pin power context: %d\n", ret
);
5430 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
5432 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
5435 mutex_unlock(&dev
->struct_mutex
);
5440 i915_gem_object_unpin(ctx
);
5442 drm_gem_object_unreference(ctx
);
5443 mutex_unlock(&dev
->struct_mutex
);
5447 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
5449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5452 rgvswctl
= I915_READ16(MEMSWCTL
);
5453 if (rgvswctl
& MEMCTL_CMD_STS
) {
5454 DRM_DEBUG("gpu busy, RCS change rejected\n");
5455 return false; /* still busy with another command */
5458 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
5459 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
5460 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5461 POSTING_READ16(MEMSWCTL
);
5463 rgvswctl
|= MEMCTL_CMD_STS
;
5464 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5469 void ironlake_enable_drps(struct drm_device
*dev
)
5471 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5472 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
5473 u8 fmax
, fmin
, fstart
, vstart
;
5475 /* 100ms RC evaluation intervals */
5476 I915_WRITE(RCUPEI
, 100000);
5477 I915_WRITE(RCDNEI
, 100000);
5479 /* Set max/min thresholds to 90ms and 80ms respectively */
5480 I915_WRITE(RCBMAXAVG
, 90000);
5481 I915_WRITE(RCBMINAVG
, 80000);
5483 I915_WRITE(MEMIHYST
, 1);
5485 /* Set up min, max, and cur for interrupt handling */
5486 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
5487 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
5488 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
5489 MEMMODE_FSTART_SHIFT
;
5492 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
5495 dev_priv
->fmax
= fstart
; /* IPS callback will increase this */
5496 dev_priv
->fstart
= fstart
;
5498 dev_priv
->max_delay
= fmax
;
5499 dev_priv
->min_delay
= fmin
;
5500 dev_priv
->cur_delay
= fstart
;
5502 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax
, fmin
,
5505 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
5508 * Interrupts will be enabled in ironlake_irq_postinstall
5511 I915_WRITE(VIDSTART
, vstart
);
5512 POSTING_READ(VIDSTART
);
5514 rgvmodectl
|= MEMMODE_SWMODE_EN
;
5515 I915_WRITE(MEMMODECTL
, rgvmodectl
);
5517 if (wait_for((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 1, 0))
5518 DRM_ERROR("stuck trying to change perf mode\n");
5521 ironlake_set_drps(dev
, fstart
);
5523 dev_priv
->last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
5525 dev_priv
->last_time1
= jiffies_to_msecs(jiffies
);
5526 dev_priv
->last_count2
= I915_READ(0x112f4);
5527 getrawmonotonic(&dev_priv
->last_time2
);
5530 void ironlake_disable_drps(struct drm_device
*dev
)
5532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5533 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
5535 /* Ack interrupts, disable EFC interrupt */
5536 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
5537 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
5538 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
5539 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
5540 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
5542 /* Go back to the starting frequency */
5543 ironlake_set_drps(dev
, dev_priv
->fstart
);
5545 rgvswctl
|= MEMCTL_CMD_STS
;
5546 I915_WRITE(MEMSWCTL
, rgvswctl
);
5551 static unsigned long intel_pxfreq(u32 vidfreq
)
5554 int div
= (vidfreq
& 0x3f0000) >> 16;
5555 int post
= (vidfreq
& 0x3000) >> 12;
5556 int pre
= (vidfreq
& 0x7);
5561 freq
= ((div
* 133333) / ((1<<post
) * pre
));
5566 void intel_init_emon(struct drm_device
*dev
)
5568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5573 /* Disable to program */
5577 /* Program energy weights for various events */
5578 I915_WRITE(SDEW
, 0x15040d00);
5579 I915_WRITE(CSIEW0
, 0x007f0000);
5580 I915_WRITE(CSIEW1
, 0x1e220004);
5581 I915_WRITE(CSIEW2
, 0x04000004);
5583 for (i
= 0; i
< 5; i
++)
5584 I915_WRITE(PEW
+ (i
* 4), 0);
5585 for (i
= 0; i
< 3; i
++)
5586 I915_WRITE(DEW
+ (i
* 4), 0);
5588 /* Program P-state weights to account for frequency power adjustment */
5589 for (i
= 0; i
< 16; i
++) {
5590 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
5591 unsigned long freq
= intel_pxfreq(pxvidfreq
);
5592 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
5597 val
*= (freq
/ 1000);
5599 val
/= (127*127*900);
5601 DRM_ERROR("bad pxval: %ld\n", val
);
5604 /* Render standby states get 0 weight */
5608 for (i
= 0; i
< 4; i
++) {
5609 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
5610 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
5611 I915_WRITE(PXW
+ (i
* 4), val
);
5614 /* Adjust magic regs to magic values (more experimental results) */
5615 I915_WRITE(OGW0
, 0);
5616 I915_WRITE(OGW1
, 0);
5617 I915_WRITE(EG0
, 0x00007f00);
5618 I915_WRITE(EG1
, 0x0000000e);
5619 I915_WRITE(EG2
, 0x000e0000);
5620 I915_WRITE(EG3
, 0x68000300);
5621 I915_WRITE(EG4
, 0x42000000);
5622 I915_WRITE(EG5
, 0x00140031);
5626 for (i
= 0; i
< 8; i
++)
5627 I915_WRITE(PXWL
+ (i
* 4), 0);
5629 /* Enable PMON + select events */
5630 I915_WRITE(ECR
, 0x80000019);
5632 lcfuse
= I915_READ(LCFUSE02
);
5634 dev_priv
->corr
= (lcfuse
& LCFUSE_HIV_MASK
);
5637 void intel_init_clock_gating(struct drm_device
*dev
)
5639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5642 * Disable clock gating reported to work incorrectly according to the
5643 * specs, but enable as much else as we can.
5645 if (HAS_PCH_SPLIT(dev
)) {
5646 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
5648 if (IS_IRONLAKE(dev
)) {
5649 /* Required for FBC */
5650 dspclk_gate
|= DPFDUNIT_CLOCK_GATE_DISABLE
;
5651 /* Required for CxSR */
5652 dspclk_gate
|= DPARBUNIT_CLOCK_GATE_DISABLE
;
5654 I915_WRITE(PCH_3DCGDIS0
,
5655 MARIUNIT_CLOCK_GATE_DISABLE
|
5656 SVSMUNIT_CLOCK_GATE_DISABLE
);
5659 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
5662 * According to the spec the following bits should be set in
5663 * order to enable memory self-refresh
5664 * The bit 22/21 of 0x42004
5665 * The bit 5 of 0x42020
5666 * The bit 15 of 0x45000
5668 if (IS_IRONLAKE(dev
)) {
5669 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5670 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
5671 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
5672 I915_WRITE(ILK_DSPCLK_GATE
,
5673 (I915_READ(ILK_DSPCLK_GATE
) |
5674 ILK_DPARB_CLK_GATE
));
5675 I915_WRITE(DISP_ARB_CTL
,
5676 (I915_READ(DISP_ARB_CTL
) |
5680 * Based on the document from hardware guys the following bits
5681 * should be set unconditionally in order to enable FBC.
5682 * The bit 22 of 0x42000
5683 * The bit 22 of 0x42004
5684 * The bit 7,8,9 of 0x42020.
5686 if (IS_IRONLAKE_M(dev
)) {
5687 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5688 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5690 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5691 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5693 I915_WRITE(ILK_DSPCLK_GATE
,
5694 I915_READ(ILK_DSPCLK_GATE
) |
5700 } else if (IS_G4X(dev
)) {
5701 uint32_t dspclk_gate
;
5702 I915_WRITE(RENCLK_GATE_D1
, 0);
5703 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
5704 GS_UNIT_CLOCK_GATE_DISABLE
|
5705 CL_UNIT_CLOCK_GATE_DISABLE
);
5706 I915_WRITE(RAMCLK_GATE_D
, 0);
5707 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
5708 OVRUNIT_CLOCK_GATE_DISABLE
|
5709 OVCUNIT_CLOCK_GATE_DISABLE
;
5711 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
5712 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
5713 } else if (IS_I965GM(dev
)) {
5714 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
5715 I915_WRITE(RENCLK_GATE_D2
, 0);
5716 I915_WRITE(DSPCLK_GATE_D
, 0);
5717 I915_WRITE(RAMCLK_GATE_D
, 0);
5718 I915_WRITE16(DEUC
, 0);
5719 } else if (IS_I965G(dev
)) {
5720 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
5721 I965_RCC_CLOCK_GATE_DISABLE
|
5722 I965_RCPB_CLOCK_GATE_DISABLE
|
5723 I965_ISC_CLOCK_GATE_DISABLE
|
5724 I965_FBC_CLOCK_GATE_DISABLE
);
5725 I915_WRITE(RENCLK_GATE_D2
, 0);
5726 } else if (IS_I9XX(dev
)) {
5727 u32 dstate
= I915_READ(D_STATE
);
5729 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
5730 DSTATE_DOT_CLOCK_GATING
;
5731 I915_WRITE(D_STATE
, dstate
);
5732 } else if (IS_I85X(dev
) || IS_I865G(dev
)) {
5733 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
5734 } else if (IS_I830(dev
)) {
5735 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
5739 * GPU can automatically power down the render unit if given a page
5742 if (IS_IRONLAKE_M(dev
)) {
5743 if (dev_priv
->renderctx
== NULL
)
5744 dev_priv
->renderctx
= intel_alloc_context_page(dev
);
5745 if (dev_priv
->renderctx
) {
5746 struct drm_i915_gem_object
*obj_priv
;
5747 obj_priv
= to_intel_bo(dev_priv
->renderctx
);
5750 OUT_RING(MI_SET_CONTEXT
);
5751 OUT_RING(obj_priv
->gtt_offset
|
5753 MI_SAVE_EXT_STATE_EN
|
5754 MI_RESTORE_EXT_STATE_EN
|
5755 MI_RESTORE_INHIBIT
);
5761 DRM_DEBUG_KMS("Failed to allocate render context."
5765 if (I915_HAS_RC6(dev
) && drm_core_check_feature(dev
, DRIVER_MODESET
)) {
5766 struct drm_i915_gem_object
*obj_priv
= NULL
;
5768 if (dev_priv
->pwrctx
) {
5769 obj_priv
= to_intel_bo(dev_priv
->pwrctx
);
5771 struct drm_gem_object
*pwrctx
;
5773 pwrctx
= intel_alloc_context_page(dev
);
5775 dev_priv
->pwrctx
= pwrctx
;
5776 obj_priv
= to_intel_bo(pwrctx
);
5781 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
| PWRCTX_EN
);
5782 I915_WRITE(MCHBAR_RENDER_STANDBY
,
5783 I915_READ(MCHBAR_RENDER_STANDBY
) & ~RCX_SW_EXIT
);
5788 /* Set up chip specific display functions */
5789 static void intel_init_display(struct drm_device
*dev
)
5791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5793 /* We always want a DPMS function */
5794 if (HAS_PCH_SPLIT(dev
))
5795 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
5797 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
5799 if (I915_HAS_FBC(dev
)) {
5800 if (IS_IRONLAKE_M(dev
)) {
5801 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
5802 dev_priv
->display
.enable_fbc
= ironlake_enable_fbc
;
5803 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
5804 } else if (IS_GM45(dev
)) {
5805 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
5806 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
5807 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
5808 } else if (IS_I965GM(dev
)) {
5809 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
5810 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
5811 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
5813 /* 855GM needs testing */
5816 /* Returns the core display clock speed */
5817 if (IS_I945G(dev
) || (IS_G33(dev
) && ! IS_PINEVIEW_M(dev
)))
5818 dev_priv
->display
.get_display_clock_speed
=
5819 i945_get_display_clock_speed
;
5820 else if (IS_I915G(dev
))
5821 dev_priv
->display
.get_display_clock_speed
=
5822 i915_get_display_clock_speed
;
5823 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
5824 dev_priv
->display
.get_display_clock_speed
=
5825 i9xx_misc_get_display_clock_speed
;
5826 else if (IS_I915GM(dev
))
5827 dev_priv
->display
.get_display_clock_speed
=
5828 i915gm_get_display_clock_speed
;
5829 else if (IS_I865G(dev
))
5830 dev_priv
->display
.get_display_clock_speed
=
5831 i865_get_display_clock_speed
;
5832 else if (IS_I85X(dev
))
5833 dev_priv
->display
.get_display_clock_speed
=
5834 i855_get_display_clock_speed
;
5836 dev_priv
->display
.get_display_clock_speed
=
5837 i830_get_display_clock_speed
;
5839 /* For FIFO watermark updates */
5840 if (HAS_PCH_SPLIT(dev
)) {
5841 if (IS_IRONLAKE(dev
)) {
5842 if (I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
)
5843 dev_priv
->display
.update_wm
= ironlake_update_wm
;
5845 DRM_DEBUG_KMS("Failed to get proper latency. "
5847 dev_priv
->display
.update_wm
= NULL
;
5850 dev_priv
->display
.update_wm
= NULL
;
5851 } else if (IS_PINEVIEW(dev
)) {
5852 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
5855 dev_priv
->mem_freq
)) {
5856 DRM_INFO("failed to find known CxSR latency "
5857 "(found ddr%s fsb freq %d, mem freq %d), "
5859 (dev_priv
->is_ddr3
== 1) ? "3": "2",
5860 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
5861 /* Disable CxSR and never update its watermark again */
5862 pineview_disable_cxsr(dev
);
5863 dev_priv
->display
.update_wm
= NULL
;
5865 dev_priv
->display
.update_wm
= pineview_update_wm
;
5866 } else if (IS_G4X(dev
))
5867 dev_priv
->display
.update_wm
= g4x_update_wm
;
5868 else if (IS_I965G(dev
))
5869 dev_priv
->display
.update_wm
= i965_update_wm
;
5870 else if (IS_I9XX(dev
)) {
5871 dev_priv
->display
.update_wm
= i9xx_update_wm
;
5872 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
5873 } else if (IS_I85X(dev
)) {
5874 dev_priv
->display
.update_wm
= i9xx_update_wm
;
5875 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
5877 dev_priv
->display
.update_wm
= i830_update_wm
;
5879 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
5881 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
5886 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5887 * resume, or other times. This quirk makes sure that's the case for
5890 static void quirk_pipea_force (struct drm_device
*dev
)
5892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5894 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
5895 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5898 struct intel_quirk
{
5900 int subsystem_vendor
;
5901 int subsystem_device
;
5902 void (*hook
)(struct drm_device
*dev
);
5905 struct intel_quirk intel_quirks
[] = {
5906 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5907 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force
},
5908 /* HP Mini needs pipe A force quirk (LP: #322104) */
5909 { 0x27ae,0x103c, 0x361a, quirk_pipea_force
},
5911 /* Thinkpad R31 needs pipe A force quirk */
5912 { 0x3577, 0x1014, 0x0505, quirk_pipea_force
},
5913 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5914 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
5916 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5917 { 0x3577, 0x1014, 0x0513, quirk_pipea_force
},
5918 /* ThinkPad X40 needs pipe A force quirk */
5920 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5921 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
5923 /* 855 & before need to leave pipe A & dpll A up */
5924 { 0x3582, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
5925 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
5928 static void intel_init_quirks(struct drm_device
*dev
)
5930 struct pci_dev
*d
= dev
->pdev
;
5933 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
5934 struct intel_quirk
*q
= &intel_quirks
[i
];
5936 if (d
->device
== q
->device
&&
5937 (d
->subsystem_vendor
== q
->subsystem_vendor
||
5938 q
->subsystem_vendor
== PCI_ANY_ID
) &&
5939 (d
->subsystem_device
== q
->subsystem_device
||
5940 q
->subsystem_device
== PCI_ANY_ID
))
5945 /* Disable the VGA plane that we never use */
5946 static void i915_disable_vga(struct drm_device
*dev
)
5948 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5952 if (HAS_PCH_SPLIT(dev
))
5953 vga_reg
= CPU_VGACNTRL
;
5957 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
5958 outb(1, VGA_SR_INDEX
);
5959 sr1
= inb(VGA_SR_DATA
);
5960 outb(sr1
| 1<<5, VGA_SR_DATA
);
5961 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
5964 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
5965 POSTING_READ(vga_reg
);
5968 void intel_modeset_init(struct drm_device
*dev
)
5970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5973 drm_mode_config_init(dev
);
5975 dev
->mode_config
.min_width
= 0;
5976 dev
->mode_config
.min_height
= 0;
5978 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
5980 intel_init_quirks(dev
);
5982 intel_init_display(dev
);
5984 if (IS_I965G(dev
)) {
5985 dev
->mode_config
.max_width
= 8192;
5986 dev
->mode_config
.max_height
= 8192;
5987 } else if (IS_I9XX(dev
)) {
5988 dev
->mode_config
.max_width
= 4096;
5989 dev
->mode_config
.max_height
= 4096;
5991 dev
->mode_config
.max_width
= 2048;
5992 dev
->mode_config
.max_height
= 2048;
5995 /* set memory base */
5997 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 2);
5999 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 0);
6001 if (IS_MOBILE(dev
) || IS_I9XX(dev
))
6002 dev_priv
->num_pipe
= 2;
6004 dev_priv
->num_pipe
= 1;
6005 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6006 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
6008 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
6009 intel_crtc_init(dev
, i
);
6012 intel_setup_outputs(dev
);
6014 intel_init_clock_gating(dev
);
6016 /* Just disable it once at startup */
6017 i915_disable_vga(dev
);
6019 if (IS_IRONLAKE_M(dev
)) {
6020 ironlake_enable_drps(dev
);
6021 intel_init_emon(dev
);
6024 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
6025 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
6026 (unsigned long)dev
);
6028 intel_setup_overlay(dev
);
6031 void intel_modeset_cleanup(struct drm_device
*dev
)
6033 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6034 struct drm_crtc
*crtc
;
6035 struct intel_crtc
*intel_crtc
;
6037 mutex_lock(&dev
->struct_mutex
);
6039 drm_kms_helper_poll_fini(dev
);
6040 intel_fbdev_fini(dev
);
6042 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6043 /* Skip inactive CRTCs */
6047 intel_crtc
= to_intel_crtc(crtc
);
6048 intel_increase_pllclock(crtc
, false);
6049 del_timer_sync(&intel_crtc
->idle_timer
);
6052 del_timer_sync(&dev_priv
->idle_timer
);
6054 if (dev_priv
->display
.disable_fbc
)
6055 dev_priv
->display
.disable_fbc(dev
);
6057 if (dev_priv
->renderctx
) {
6058 struct drm_i915_gem_object
*obj_priv
;
6060 obj_priv
= to_intel_bo(dev_priv
->renderctx
);
6061 I915_WRITE(CCID
, obj_priv
->gtt_offset
&~ CCID_EN
);
6063 i915_gem_object_unpin(dev_priv
->renderctx
);
6064 drm_gem_object_unreference(dev_priv
->renderctx
);
6067 if (dev_priv
->pwrctx
) {
6068 struct drm_i915_gem_object
*obj_priv
;
6070 obj_priv
= to_intel_bo(dev_priv
->pwrctx
);
6071 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
&~ PWRCTX_EN
);
6073 i915_gem_object_unpin(dev_priv
->pwrctx
);
6074 drm_gem_object_unreference(dev_priv
->pwrctx
);
6077 if (IS_IRONLAKE_M(dev
))
6078 ironlake_disable_drps(dev
);
6080 mutex_unlock(&dev
->struct_mutex
);
6082 drm_mode_config_cleanup(dev
);
6087 * Return which encoder is currently attached for connector.
6089 struct drm_encoder
*intel_attached_encoder (struct drm_connector
*connector
)
6091 struct drm_mode_object
*obj
;
6092 struct drm_encoder
*encoder
;
6095 for (i
= 0; i
< DRM_CONNECTOR_MAX_ENCODER
; i
++) {
6096 if (connector
->encoder_ids
[i
] == 0)
6099 obj
= drm_mode_object_find(connector
->dev
,
6100 connector
->encoder_ids
[i
],
6101 DRM_MODE_OBJECT_ENCODER
);
6105 encoder
= obj_to_encoder(obj
);
6112 * set vga decode state - true == enable VGA decode
6114 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
6116 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6119 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
6121 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
6123 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
6124 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);