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Blackfin: use proper wrapper functions for modifying irq status
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / rts_pstor / rtsx_card.c
blob4f971f2e930aa0f08a3f96a13ecbd511305d2c81
1 /* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * wwang (wei_wang@realsil.com.cn)
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26 #include <linux/workqueue.h>
27 #include <linux/kernel.h>
28
29 #include "rtsx.h"
30 #include "rtsx_transport.h"
31 #include "rtsx_scsi.h"
32 #include "rtsx_card.h"
33
34 #include "rtsx_sys.h"
35 #include "general.h"
36
37 #include "sd.h"
38 #include "xd.h"
39 #include "ms.h"
40
41 void do_remaining_work(struct rtsx_chip *chip)
42 {
43 struct sd_info *sd_card = &(chip->sd_card);
44 #ifdef XD_DELAY_WRITE
45 struct xd_info *xd_card = &(chip->xd_card);
46 #endif
47 struct ms_info *ms_card = &(chip->ms_card);
48
49 if (chip->card_ready & SD_CARD) {
50 if (sd_card->seq_mode) {
51 rtsx_set_stat(chip, RTSX_STAT_RUN);
52 sd_card->cleanup_counter++;
53 } else {
54 sd_card->cleanup_counter = 0;
55 }
56 }
57
58 #ifdef XD_DELAY_WRITE
59 if (chip->card_ready & XD_CARD) {
60 if (xd_card->delay_write.delay_write_flag) {
61 rtsx_set_stat(chip, RTSX_STAT_RUN);
62 xd_card->cleanup_counter++;
63 } else {
64 xd_card->cleanup_counter = 0;
65 }
66 }
67 #endif
68
69 if (chip->card_ready & MS_CARD) {
70 if (CHK_MSPRO(ms_card)) {
71 if (ms_card->seq_mode) {
72 rtsx_set_stat(chip, RTSX_STAT_RUN);
73 ms_card->cleanup_counter++;
74 } else {
75 ms_card->cleanup_counter = 0;
76 }
77 } else {
78 #ifdef MS_DELAY_WRITE
79 if (ms_card->delay_write.delay_write_flag) {
80 rtsx_set_stat(chip, RTSX_STAT_RUN);
81 ms_card->cleanup_counter++;
82 } else {
83 ms_card->cleanup_counter = 0;
84 }
85 #endif
86 }
87 }
88
89 if (sd_card->cleanup_counter > POLLING_WAIT_CNT)
90 sd_cleanup_work(chip);
91
92 if (xd_card->cleanup_counter > POLLING_WAIT_CNT)
93 xd_cleanup_work(chip);
94
95 if (ms_card->cleanup_counter > POLLING_WAIT_CNT)
96 ms_cleanup_work(chip);
97 }
98
99 void try_to_switch_sdio_ctrl(struct rtsx_chip *chip)
100 {
101 u8 reg1 = 0, reg2 = 0;
102
103 rtsx_read_register(chip, 0xFF34, &reg1);
104 rtsx_read_register(chip, 0xFF38, &reg2);
105 RTSX_DEBUGP("reg 0xFF34: 0x%x, reg 0xFF38: 0x%x\n", reg1, reg2);
106 if ((reg1 & 0xC0) && (reg2 & 0xC0)) {
107 chip->sd_int = 1;
108 rtsx_write_register(chip, SDIO_CTRL, 0xFF, SDIO_BUS_CTRL | SDIO_CD_CTRL);
109 rtsx_write_register(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_ON);
110 }
111 }
112
113 #ifdef SUPPORT_SDIO_ASPM
114 void dynamic_configure_sdio_aspm(struct rtsx_chip *chip)
115 {
116 u8 buf[12], reg;
117 int i;
118
119 for (i = 0; i < 12; i++)
120 rtsx_read_register(chip, 0xFF08 + i, &buf[i]);
121 rtsx_read_register(chip, 0xFF25, &reg);
122 if ((memcmp(buf, chip->sdio_raw_data, 12) != 0) || (reg & 0x03)) {
123 chip->sdio_counter = 0;
124 chip->sdio_idle = 0;
125 } else {
126 if (!chip->sdio_idle) {
127 chip->sdio_counter++;
128 if (chip->sdio_counter >= SDIO_IDLE_COUNT) {
129 chip->sdio_counter = 0;
130 chip->sdio_idle = 1;
131 }
132 }
133 }
134 memcpy(chip->sdio_raw_data, buf, 12);
135
136 if (chip->sdio_idle) {
137 if (!chip->sdio_aspm) {
138 RTSX_DEBUGP("SDIO enter ASPM!\n");
139 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC,
140 0x30 | (chip->aspm_level[1] << 2));
141 chip->sdio_aspm = 1;
142 }
143 } else {
144 if (chip->sdio_aspm) {
145 RTSX_DEBUGP("SDIO exit ASPM!\n");
146 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, 0x30);
147 chip->sdio_aspm = 0;
148 }
149 }
150 }
151 #endif
152
153 void do_reset_sd_card(struct rtsx_chip *chip)
154 {
155 int retval;
156
157 RTSX_DEBUGP("%s: %d, card2lun = 0x%x\n", __func__,
158 chip->sd_reset_counter, chip->card2lun[SD_CARD]);
159
160 if (chip->card2lun[SD_CARD] >= MAX_ALLOWED_LUN_CNT) {
161 clear_bit(SD_NR, &(chip->need_reset));
162 chip->sd_reset_counter = 0;
163 chip->sd_show_cnt = 0;
164 return;
165 }
166
167 chip->rw_fail_cnt[chip->card2lun[SD_CARD]] = 0;
168
169 rtsx_set_stat(chip, RTSX_STAT_RUN);
170 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0);
171
172 retval = reset_sd_card(chip);
173 if (chip->need_release & SD_CARD)
174 return;
175 if (retval == STATUS_SUCCESS) {
176 clear_bit(SD_NR, &(chip->need_reset));
177 chip->sd_reset_counter = 0;
178 chip->sd_show_cnt = 0;
179 chip->card_ready |= SD_CARD;
180 chip->card_fail &= ~SD_CARD;
181 chip->rw_card[chip->card2lun[SD_CARD]] = sd_rw;
182 } else {
183 if (chip->sd_io || (chip->sd_reset_counter >= MAX_RESET_CNT)) {
184 clear_bit(SD_NR, &(chip->need_reset));
185 chip->sd_reset_counter = 0;
186 chip->sd_show_cnt = 0;
187 } else {
188 chip->sd_reset_counter++;
189 }
190 chip->card_ready &= ~SD_CARD;
191 chip->card_fail |= SD_CARD;
192 chip->capacity[chip->card2lun[SD_CARD]] = 0;
193 chip->rw_card[chip->card2lun[SD_CARD]] = NULL;
194
195 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
196 if (!chip->ft2_fast_mode)
197 card_power_off(chip, SD_CARD);
198 if (chip->sd_io) {
199 chip->sd_int = 0;
200 try_to_switch_sdio_ctrl(chip);
201 } else {
202 disable_card_clock(chip, SD_CARD);
203 }
204 }
205 }
206
207 void do_reset_xd_card(struct rtsx_chip *chip)
208 {
209 int retval;
210
211 RTSX_DEBUGP("%s: %d, card2lun = 0x%x\n", __func__,
212 chip->xd_reset_counter, chip->card2lun[XD_CARD]);
213
214 if (chip->card2lun[XD_CARD] >= MAX_ALLOWED_LUN_CNT) {
215 clear_bit(XD_NR, &(chip->need_reset));
216 chip->xd_reset_counter = 0;
217 chip->xd_show_cnt = 0;
218 return;
219 }
220
221 chip->rw_fail_cnt[chip->card2lun[XD_CARD]] = 0;
222
223 rtsx_set_stat(chip, RTSX_STAT_RUN);
224 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0);
225
226 retval = reset_xd_card(chip);
227 if (chip->need_release & XD_CARD)
228 return;
229 if (retval == STATUS_SUCCESS) {
230 clear_bit(XD_NR, &(chip->need_reset));
231 chip->xd_reset_counter = 0;
232 chip->card_ready |= XD_CARD;
233 chip->card_fail &= ~XD_CARD;
234 chip->rw_card[chip->card2lun[XD_CARD]] = xd_rw;
235 } else {
236 if (chip->xd_reset_counter >= MAX_RESET_CNT) {
237 clear_bit(XD_NR, &(chip->need_reset));
238 chip->xd_reset_counter = 0;
239 chip->xd_show_cnt = 0;
240 } else {
241 chip->xd_reset_counter++;
242 }
243 chip->card_ready &= ~XD_CARD;
244 chip->card_fail |= XD_CARD;
245 chip->capacity[chip->card2lun[XD_CARD]] = 0;
246 chip->rw_card[chip->card2lun[XD_CARD]] = NULL;
247
248 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
249 if (!chip->ft2_fast_mode)
250 card_power_off(chip, XD_CARD);
251 disable_card_clock(chip, XD_CARD);
252 }
253 }
254
255 void do_reset_ms_card(struct rtsx_chip *chip)
256 {
257 int retval;
258
259 RTSX_DEBUGP("%s: %d, card2lun = 0x%x\n", __func__,
260 chip->ms_reset_counter, chip->card2lun[MS_CARD]);
261
262 if (chip->card2lun[MS_CARD] >= MAX_ALLOWED_LUN_CNT) {
263 clear_bit(MS_NR, &(chip->need_reset));
264 chip->ms_reset_counter = 0;
265 chip->ms_show_cnt = 0;
266 return;
267 }
268
269 chip->rw_fail_cnt[chip->card2lun[MS_CARD]] = 0;
270
271 rtsx_set_stat(chip, RTSX_STAT_RUN);
272 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0);
273
274 retval = reset_ms_card(chip);
275 if (chip->need_release & MS_CARD)
276 return;
277 if (retval == STATUS_SUCCESS) {
278 clear_bit(MS_NR, &(chip->need_reset));
279 chip->ms_reset_counter = 0;
280 chip->card_ready |= MS_CARD;
281 chip->card_fail &= ~MS_CARD;
282 chip->rw_card[chip->card2lun[MS_CARD]] = ms_rw;
283 } else {
284 if (chip->ms_reset_counter >= MAX_RESET_CNT) {
285 clear_bit(MS_NR, &(chip->need_reset));
286 chip->ms_reset_counter = 0;
287 chip->ms_show_cnt = 0;
288 } else {
289 chip->ms_reset_counter++;
290 }
291 chip->card_ready &= ~MS_CARD;
292 chip->card_fail |= MS_CARD;
293 chip->capacity[chip->card2lun[MS_CARD]] = 0;
294 chip->rw_card[chip->card2lun[MS_CARD]] = NULL;
295
296 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
297 if (!chip->ft2_fast_mode)
298 card_power_off(chip, MS_CARD);
299 disable_card_clock(chip, MS_CARD);
300 }
301 }
302
303 static void release_sdio(struct rtsx_chip *chip)
304 {
305 if (chip->sd_io) {
306 rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR,
307 SD_STOP | SD_CLR_ERR);
308
309 if (chip->chip_insert_with_sdio) {
310 chip->chip_insert_with_sdio = 0;
311
312 if (CHECK_PID(chip, 0x5288)) {
313 rtsx_write_register(chip, 0xFE5A, 0x08, 0x00);
314 } else {
315 rtsx_write_register(chip, 0xFE70, 0x80, 0x00);
316 }
317 }
318
319 rtsx_write_register(chip, SDIO_CTRL, SDIO_CD_CTRL, 0);
320 chip->sd_io = 0;
321 }
322 }
323
324 void rtsx_power_off_card(struct rtsx_chip *chip)
325 {
326 if ((chip->card_ready & SD_CARD) || chip->sd_io) {
327 sd_cleanup_work(chip);
328 sd_power_off_card3v3(chip);
329 }
330
331 if (chip->card_ready & XD_CARD) {
332 xd_cleanup_work(chip);
333 xd_power_off_card3v3(chip);
334 }
335
336 if (chip->card_ready & MS_CARD) {
337 ms_cleanup_work(chip);
338 ms_power_off_card3v3(chip);
339 }
340 }
341
342 void rtsx_release_cards(struct rtsx_chip *chip)
343 {
344 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
345
346 if ((chip->card_ready & SD_CARD) || chip->sd_io) {
347 if (chip->int_reg & SD_EXIST)
348 sd_cleanup_work(chip);
349 release_sd_card(chip);
350 }
351
352 if (chip->card_ready & XD_CARD) {
353 if (chip->int_reg & XD_EXIST)
354 xd_cleanup_work(chip);
355 release_xd_card(chip);
356 }
357
358 if (chip->card_ready & MS_CARD) {
359 if (chip->int_reg & MS_EXIST)
360 ms_cleanup_work(chip);
361 release_ms_card(chip);
362 }
363 }
364
365 void rtsx_reset_cards(struct rtsx_chip *chip)
366 {
367 if (!chip->need_reset)
368 return;
369
370 rtsx_set_stat(chip, RTSX_STAT_RUN);
371
372 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
373
374 rtsx_disable_aspm(chip);
375
376 if ((chip->need_reset & SD_CARD) && chip->chip_insert_with_sdio)
377 clear_bit(SD_NR, &(chip->need_reset));
378
379 if (chip->need_reset & XD_CARD) {
380 chip->card_exist |= XD_CARD;
381
382 if (chip->xd_show_cnt >= MAX_SHOW_CNT) {
383 do_reset_xd_card(chip);
384 } else {
385 chip->xd_show_cnt++;
386 }
387 }
388 if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN)) {
389 if (chip->card_exist & XD_CARD) {
390 clear_bit(SD_NR, &(chip->need_reset));
391 clear_bit(MS_NR, &(chip->need_reset));
392 }
393 }
394 if (chip->need_reset & SD_CARD) {
395 chip->card_exist |= SD_CARD;
396
397 if (chip->sd_show_cnt >= MAX_SHOW_CNT) {
398 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
399 do_reset_sd_card(chip);
400 } else {
401 chip->sd_show_cnt++;
402 }
403 }
404 if (chip->need_reset & MS_CARD) {
405 chip->card_exist |= MS_CARD;
406
407 if (chip->ms_show_cnt >= MAX_SHOW_CNT) {
408 do_reset_ms_card(chip);
409 } else {
410 chip->ms_show_cnt++;
411 }
412 }
413 }
414
415 void rtsx_reinit_cards(struct rtsx_chip *chip, int reset_chip)
416 {
417 rtsx_set_stat(chip, RTSX_STAT_RUN);
418
419 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
420
421 if (reset_chip)
422 rtsx_reset_chip(chip);
423
424 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
425
426 if ((chip->int_reg & SD_EXIST) && (chip->need_reinit & SD_CARD)) {
427 release_sdio(chip);
428 release_sd_card(chip);
429
430 wait_timeout(100);
431
432 chip->card_exist |= SD_CARD;
433 do_reset_sd_card(chip);
434 }
435
436 if ((chip->int_reg & XD_EXIST) && (chip->need_reinit & XD_CARD)) {
437 release_xd_card(chip);
438
439 wait_timeout(100);
440
441 chip->card_exist |= XD_CARD;
442 do_reset_xd_card(chip);
443 }
444
445 if ((chip->int_reg & MS_EXIST) && (chip->need_reinit & MS_CARD)) {
446 release_ms_card(chip);
447
448 wait_timeout(100);
449
450 chip->card_exist |= MS_CARD;
451 do_reset_ms_card(chip);
452 }
453
454 chip->need_reinit = 0;
455 }
456
457 #ifdef DISABLE_CARD_INT
458 void card_cd_debounce(struct rtsx_chip *chip, unsigned long *need_reset, unsigned long *need_release)
459 {
460 u8 release_map = 0, reset_map = 0;
461
462 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
463
464 if (chip->card_exist) {
465 if (chip->card_exist & XD_CARD) {
466 if (!(chip->int_reg & XD_EXIST))
467 release_map |= XD_CARD;
468 } else if (chip->card_exist & SD_CARD) {
469 if (!(chip->int_reg & SD_EXIST))
470 release_map |= SD_CARD;
471 } else if (chip->card_exist & MS_CARD) {
472 if (!(chip->int_reg & MS_EXIST))
473 release_map |= MS_CARD;
474 }
475 } else {
476 if (chip->int_reg & XD_EXIST) {
477 reset_map |= XD_CARD;
478 } else if (chip->int_reg & SD_EXIST) {
479 reset_map |= SD_CARD;
480 } else if (chip->int_reg & MS_EXIST) {
481 reset_map |= MS_CARD;
482 }
483 }
484
485 if (reset_map) {
486 int xd_cnt = 0, sd_cnt = 0, ms_cnt = 0;
487 int i;
488
489 for (i = 0; i < (DEBOUNCE_CNT); i++) {
490 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
491
492 if (chip->int_reg & XD_EXIST) {
493 xd_cnt++;
494 } else {
495 xd_cnt = 0;
496 }
497 if (chip->int_reg & SD_EXIST) {
498 sd_cnt++;
499 } else {
500 sd_cnt = 0;
501 }
502 if (chip->int_reg & MS_EXIST) {
503 ms_cnt++;
504 } else {
505 ms_cnt = 0;
506 }
507 wait_timeout(30);
508 }
509
510 reset_map = 0;
511 if (!(chip->card_exist & XD_CARD) && (xd_cnt > (DEBOUNCE_CNT-1)))
512 reset_map |= XD_CARD;
513 if (!(chip->card_exist & SD_CARD) && (sd_cnt > (DEBOUNCE_CNT-1)))
514 reset_map |= SD_CARD;
515 if (!(chip->card_exist & MS_CARD) && (ms_cnt > (DEBOUNCE_CNT-1)))
516 reset_map |= MS_CARD;
517 }
518
519 if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN))
520 rtsx_write_register(chip, HOST_SLEEP_STATE, 0xC0, 0x00);
521
522 if (need_reset)
523 *need_reset = reset_map;
524 if (need_release)
525 *need_release = release_map;
526 }
527 #endif
528
529 void rtsx_init_cards(struct rtsx_chip *chip)
530 {
531 if (RTSX_TST_DELINK(chip) && (rtsx_get_stat(chip) != RTSX_STAT_SS)) {
532 RTSX_DEBUGP("Reset chip in polling thread!\n");
533 rtsx_reset_chip(chip);
534 RTSX_CLR_DELINK(chip);
535 }
536
537 #ifdef DISABLE_CARD_INT
538 card_cd_debounce(chip, &(chip->need_reset), &(chip->need_release));
539 #endif
540
541 if (chip->need_release) {
542 if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN)) {
543 if (chip->int_reg & XD_EXIST) {
544 clear_bit(SD_NR, &(chip->need_release));
545 clear_bit(MS_NR, &(chip->need_release));
546 }
547 }
548
549 if (!(chip->card_exist & SD_CARD) && !chip->sd_io)
550 clear_bit(SD_NR, &(chip->need_release));
551 if (!(chip->card_exist & XD_CARD))
552 clear_bit(XD_NR, &(chip->need_release));
553 if (!(chip->card_exist & MS_CARD))
554 clear_bit(MS_NR, &(chip->need_release));
555
556 RTSX_DEBUGP("chip->need_release = 0x%x\n", (unsigned int)(chip->need_release));
557
558 #ifdef SUPPORT_OCP
559 if (chip->need_release) {
560 if (CHECK_PID(chip, 0x5209)) {
561 u8 mask = 0, val = 0;
562 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
563 if (chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER)) {
564 mask |= MS_OCP_INT_CLR | MS_OC_CLR;
565 val |= MS_OCP_INT_CLR | MS_OC_CLR;
566 }
567 }
568 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
569 mask |= SD_OCP_INT_CLR | SD_OC_CLR;
570 val |= SD_OCP_INT_CLR | SD_OC_CLR;
571 }
572 if (mask)
573 rtsx_write_register(chip, OCPCTL, mask, val);
574 } else {
575 if (chip->ocp_stat & (CARD_OC_NOW | CARD_OC_EVER))
576 rtsx_write_register(chip, OCPCLR,
577 CARD_OC_INT_CLR | CARD_OC_CLR,
578 CARD_OC_INT_CLR | CARD_OC_CLR);
579 }
580 chip->ocp_stat = 0;
581 }
582 #endif
583 if (chip->need_release) {
584 rtsx_set_stat(chip, RTSX_STAT_RUN);
585 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
586 }
587
588 if (chip->need_release & SD_CARD) {
589 clear_bit(SD_NR, &(chip->need_release));
590 chip->card_exist &= ~SD_CARD;
591 chip->card_ejected &= ~SD_CARD;
592 chip->card_fail &= ~SD_CARD;
593 CLR_BIT(chip->lun_mc, chip->card2lun[SD_CARD]);
594 chip->rw_fail_cnt[chip->card2lun[SD_CARD]] = 0;
595 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
596
597 release_sdio(chip);
598 release_sd_card(chip);
599 }
600
601 if (chip->need_release & XD_CARD) {
602 clear_bit(XD_NR, &(chip->need_release));
603 chip->card_exist &= ~XD_CARD;
604 chip->card_ejected &= ~XD_CARD;
605 chip->card_fail &= ~XD_CARD;
606 CLR_BIT(chip->lun_mc, chip->card2lun[XD_CARD]);
607 chip->rw_fail_cnt[chip->card2lun[XD_CARD]] = 0;
608
609 release_xd_card(chip);
610
611 if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN))
612 rtsx_write_register(chip, HOST_SLEEP_STATE, 0xC0, 0xC0);
613 }
614
615 if (chip->need_release & MS_CARD) {
616 clear_bit(MS_NR, &(chip->need_release));
617 chip->card_exist &= ~MS_CARD;
618 chip->card_ejected &= ~MS_CARD;
619 chip->card_fail &= ~MS_CARD;
620 CLR_BIT(chip->lun_mc, chip->card2lun[MS_CARD]);
621 chip->rw_fail_cnt[chip->card2lun[MS_CARD]] = 0;
622
623 release_ms_card(chip);
624 }
625
626 RTSX_DEBUGP("chip->card_exist = 0x%x\n", chip->card_exist);
627
628 if (!chip->card_exist)
629 turn_off_led(chip, LED_GPIO);
630 }
631
632 if (chip->need_reset) {
633 RTSX_DEBUGP("chip->need_reset = 0x%x\n", (unsigned int)(chip->need_reset));
634
635 rtsx_reset_cards(chip);
636 }
637
638 if (chip->need_reinit) {
639 RTSX_DEBUGP("chip->need_reinit = 0x%x\n", (unsigned int)(chip->need_reinit));
640
641 rtsx_reinit_cards(chip, 0);
642 }
643 }
644
645 static inline u8 double_depth(u8 depth)
646 {
647 return ((depth > 1) ? (depth - 1) : depth);
648 }
649
650 int switch_ssc_clock(struct rtsx_chip *chip, int clk)
651 {
652 struct sd_info *sd_card = &(chip->sd_card);
653 struct ms_info *ms_card = &(chip->ms_card);
654 int retval;
655 u8 N = (u8)(clk - 2), min_N, max_N;
656 u8 mcu_cnt, div, max_div, ssc_depth, ssc_depth_mask;
657 int sd_vpclk_phase_reset = 0;
658
659 if (chip->cur_clk == clk)
660 return STATUS_SUCCESS;
661
662 if (CHECK_PID(chip, 0x5209)) {
663 min_N = 80;
664 max_N = 208;
665 max_div = CLK_DIV_8;
666 } else {
667 min_N = 60;
668 max_N = 120;
669 max_div = CLK_DIV_4;
670 }
671
672 if (CHECK_PID(chip, 0x5209) && (chip->cur_card == SD_CARD)) {
673 struct sd_info *sd_card = &(chip->sd_card);
674 if (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card))
675 sd_vpclk_phase_reset = 1;
676 }
677
678 RTSX_DEBUGP("Switch SSC clock to %dMHz (cur_clk = %d)\n", clk, chip->cur_clk);
679
680 if ((clk <= 2) || (N > max_N)) {
681 TRACE_RET(chip, STATUS_FAIL);
682 }
683
684 mcu_cnt = (u8)(125/clk + 3);
685 if (CHECK_PID(chip, 0x5209)) {
686 if (mcu_cnt > 15)
687 mcu_cnt = 15;
688 } else {
689 if (mcu_cnt > 7)
690 mcu_cnt = 7;
691 }
692
693 div = CLK_DIV_1;
694 while ((N < min_N) && (div < max_div)) {
695 N = (N + 2) * 2 - 2;
696 div++;
697 }
698 RTSX_DEBUGP("N = %d, div = %d\n", N, div);
699
700 if (chip->ssc_en) {
701 if (CHECK_PID(chip, 0x5209)) {
702 if (chip->cur_card == SD_CARD) {
703 if (CHK_SD_SDR104(sd_card)) {
704 ssc_depth = chip->ssc_depth_sd_sdr104;
705 } else if (CHK_SD_SDR50(sd_card)) {
706 ssc_depth = chip->ssc_depth_sd_sdr50;
707 } else if (CHK_SD_DDR50(sd_card)) {
708 ssc_depth = double_depth(chip->ssc_depth_sd_ddr50);
709 } else if (CHK_SD_HS(sd_card)) {
710 ssc_depth = double_depth(chip->ssc_depth_sd_hs);
711 } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) {
712 ssc_depth = double_depth(chip->ssc_depth_mmc_52m);
713 } else {
714 ssc_depth = double_depth(chip->ssc_depth_low_speed);
715 }
716 } else if (chip->cur_card == MS_CARD) {
717 if (CHK_MSPRO(ms_card)) {
718 if (CHK_HG8BIT(ms_card)) {
719 ssc_depth = double_depth(chip->ssc_depth_ms_hg);
720 } else {
721 ssc_depth = double_depth(chip->ssc_depth_ms_4bit);
722 }
723 } else {
724 if (CHK_MS4BIT(ms_card)) {
725 ssc_depth = double_depth(chip->ssc_depth_ms_4bit);
726 } else {
727 ssc_depth = double_depth(chip->ssc_depth_low_speed);
728 }
729 }
730 } else {
731 ssc_depth = double_depth(chip->ssc_depth_low_speed);
732 }
733
734 if (ssc_depth) {
735 if (div == CLK_DIV_2) {
736 if (ssc_depth > 1) {
737 ssc_depth -= 1;
738 } else {
739 ssc_depth = SSC_DEPTH_4M;
740 }
741 } else if (div == CLK_DIV_4) {
742 if (ssc_depth > 2) {
743 ssc_depth -= 2;
744 } else {
745 ssc_depth = SSC_DEPTH_4M;
746 }
747 } else if (div == CLK_DIV_8) {
748 if (ssc_depth > 3) {
749 ssc_depth -= 3;
750 } else {
751 ssc_depth = SSC_DEPTH_4M;
752 }
753 }
754 }
755 } else {
756 ssc_depth = 0x01;
757 N -= 2;
758 }
759 } else {
760 ssc_depth = 0;
761 }
762
763 if (CHECK_PID(chip, 0x5209)) {
764 ssc_depth_mask = SSC_DEPTH_MASK;
765 } else {
766 ssc_depth_mask = 0x03;
767 }
768
769 RTSX_DEBUGP("ssc_depth = %d\n", ssc_depth);
770
771 rtsx_init_cmd(chip);
772 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
773 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0xFF, (div << 4) | mcu_cnt);
774 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
775 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL2, ssc_depth_mask, ssc_depth);
776 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N);
777 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
778 if (sd_vpclk_phase_reset) {
779 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
780 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, PHASE_NOT_RESET);
781 }
782
783 retval = rtsx_send_cmd(chip, 0, WAIT_TIME);
784 if (retval < 0) {
785 TRACE_RET(chip, STATUS_ERROR);
786 }
787
788 udelay(10);
789 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
790
791 chip->cur_clk = clk;
792
793 return STATUS_SUCCESS;
794 }
795
796 int switch_normal_clock(struct rtsx_chip *chip, int clk)
797 {
798 u8 sel, div, mcu_cnt;
799 int sd_vpclk_phase_reset = 0;
800
801 if (chip->cur_clk == clk)
802 return STATUS_SUCCESS;
803
804 if (CHECK_PID(chip, 0x5209) && (chip->cur_card == SD_CARD)) {
805 struct sd_info *sd_card = &(chip->sd_card);
806 if (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card))
807 sd_vpclk_phase_reset = 1;
808 }
809
810 switch (clk) {
811 case CLK_20:
812 RTSX_DEBUGP("Switch clock to 20MHz\n");
813 sel = SSC_80;
814 div = CLK_DIV_4;
815 mcu_cnt = 7;
816 break;
817
818 case CLK_30:
819 RTSX_DEBUGP("Switch clock to 30MHz\n");
820 sel = SSC_120;
821 div = CLK_DIV_4;
822 mcu_cnt = 7;
823 break;
824
825 case CLK_40:
826 RTSX_DEBUGP("Switch clock to 40MHz\n");
827 sel = SSC_80;
828 div = CLK_DIV_2;
829 mcu_cnt = 7;
830 break;
831
832 case CLK_50:
833 RTSX_DEBUGP("Switch clock to 50MHz\n");
834 sel = SSC_100;
835 div = CLK_DIV_2;
836 mcu_cnt = 6;
837 break;
838
839 case CLK_60:
840 RTSX_DEBUGP("Switch clock to 60MHz\n");
841 sel = SSC_120;
842 div = CLK_DIV_2;
843 mcu_cnt = 6;
844 break;
845
846 case CLK_80:
847 RTSX_DEBUGP("Switch clock to 80MHz\n");
848 sel = SSC_80;
849 div = CLK_DIV_1;
850 mcu_cnt = 5;
851 break;
852
853 case CLK_100:
854 RTSX_DEBUGP("Switch clock to 100MHz\n");
855 sel = SSC_100;
856 div = CLK_DIV_1;
857 mcu_cnt = 5;
858 break;
859
860 case CLK_120:
861 RTSX_DEBUGP("Switch clock to 120MHz\n");
862 sel = SSC_120;
863 div = CLK_DIV_1;
864 mcu_cnt = 5;
865 break;
866
867 case CLK_150:
868 RTSX_DEBUGP("Switch clock to 150MHz\n");
869 sel = SSC_150;
870 div = CLK_DIV_1;
871 mcu_cnt = 4;
872 break;
873
874 case CLK_200:
875 RTSX_DEBUGP("Switch clock to 200MHz\n");
876 sel = SSC_200;
877 div = CLK_DIV_1;
878 mcu_cnt = 4;
879 break;
880
881 default:
882 RTSX_DEBUGP("Try to switch to an illegal clock (%d)\n", clk);
883 TRACE_RET(chip, STATUS_FAIL);
884 }
885
886 RTSX_WRITE_REG(chip, CLK_CTL, 0xFF, CLK_LOW_FREQ);
887 if (sd_vpclk_phase_reset) {
888 RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
889 RTSX_WRITE_REG(chip, SD_VPCLK1_CTL, PHASE_NOT_RESET, 0);
890 }
891 RTSX_WRITE_REG(chip, CLK_DIV, 0xFF, (div << 4) | mcu_cnt);
892 RTSX_WRITE_REG(chip, CLK_SEL, 0xFF, sel);
893
894 if (sd_vpclk_phase_reset) {
895 udelay(200);
896 RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, PHASE_NOT_RESET);
897 RTSX_WRITE_REG(chip, SD_VPCLK1_CTL, PHASE_NOT_RESET, PHASE_NOT_RESET);
898 udelay(200);
899 }
900 RTSX_WRITE_REG(chip, CLK_CTL, 0xFF, 0);
901
902 chip->cur_clk = clk;
903
904 return STATUS_SUCCESS;
905 }
906
907 void trans_dma_enable(enum dma_data_direction dir, struct rtsx_chip *chip, u32 byte_cnt, u8 pack_size)
908 {
909 if (pack_size > DMA_1024)
910 pack_size = DMA_512;
911
912 rtsx_add_cmd(chip, WRITE_REG_CMD, IRQSTAT0, DMA_DONE_INT, DMA_DONE_INT);
913
914 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC3, 0xFF, (u8)(byte_cnt >> 24));
915 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC2, 0xFF, (u8)(byte_cnt >> 16));
916 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC1, 0xFF, (u8)(byte_cnt >> 8));
917 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC0, 0xFF, (u8)byte_cnt);
918
919 if (dir == DMA_FROM_DEVICE) {
920 rtsx_add_cmd(chip, WRITE_REG_CMD, DMACTL, 0x03 | DMA_PACK_SIZE_MASK,
921 DMA_DIR_FROM_CARD | DMA_EN | pack_size);
922 } else {
923 rtsx_add_cmd(chip, WRITE_REG_CMD, DMACTL, 0x03 | DMA_PACK_SIZE_MASK,
924 DMA_DIR_TO_CARD | DMA_EN | pack_size);
925 }
926
927 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
928 }
929
930 int enable_card_clock(struct rtsx_chip *chip, u8 card)
931 {
932 u8 clk_en = 0;
933
934 if (card & XD_CARD)
935 clk_en |= XD_CLK_EN;
936 if (card & SD_CARD)
937 clk_en |= SD_CLK_EN;
938 if (card & MS_CARD)
939 clk_en |= MS_CLK_EN;
940
941 RTSX_WRITE_REG(chip, CARD_CLK_EN, clk_en, clk_en);
942
943 return STATUS_SUCCESS;
944 }
945
946 int disable_card_clock(struct rtsx_chip *chip, u8 card)
947 {
948 u8 clk_en = 0;
949
950 if (card & XD_CARD)
951 clk_en |= XD_CLK_EN;
952 if (card & SD_CARD)
953 clk_en |= SD_CLK_EN;
954 if (card & MS_CARD)
955 clk_en |= MS_CLK_EN;
956
957 RTSX_WRITE_REG(chip, CARD_CLK_EN, clk_en, 0);
958
959 return STATUS_SUCCESS;
960 }
961
962 int card_power_on(struct rtsx_chip *chip, u8 card)
963 {
964 int retval;
965 u8 mask, val1, val2;
966
967 if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && (card == MS_CARD)) {
968 mask = MS_POWER_MASK;
969 val1 = MS_PARTIAL_POWER_ON;
970 val2 = MS_POWER_ON;
971 } else {
972 mask = SD_POWER_MASK;
973 val1 = SD_PARTIAL_POWER_ON;
974 val2 = SD_POWER_ON;
975 }
976
977 rtsx_init_cmd(chip);
978 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, mask, val1);
979 if (CHECK_PID(chip, 0x5209) && (card == SD_CARD)) {
980 rtsx_add_cmd(chip, WRITE_REG_CMD, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_SUSPEND);
981 }
982 retval = rtsx_send_cmd(chip, 0, 100);
983 if (retval != STATUS_SUCCESS) {
984 TRACE_RET(chip, STATUS_FAIL);
985 }
986
987 udelay(chip->pmos_pwr_on_interval);
988
989 rtsx_init_cmd(chip);
990 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, mask, val2);
991 if (CHECK_PID(chip, 0x5209) && (card == SD_CARD)) {
992 rtsx_add_cmd(chip, WRITE_REG_CMD, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_ON);
993 }
994 retval = rtsx_send_cmd(chip, 0, 100);
995 if (retval != STATUS_SUCCESS) {
996 TRACE_RET(chip, STATUS_FAIL);
997 }
998
999 return STATUS_SUCCESS;
1000 }
1001
1002 int card_power_off(struct rtsx_chip *chip, u8 card)
1003 {
1004 u8 mask, val;
1005
1006 if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && (card == MS_CARD)) {
1007 mask = MS_POWER_MASK;
1008 val = MS_POWER_OFF;
1009 } else {
1010 mask = SD_POWER_MASK;
1011 val = SD_POWER_OFF;
1012 }
1013 if (CHECK_PID(chip, 0x5209)) {
1014 mask |= PMOS_STRG_MASK;
1015 val |= PMOS_STRG_400mA;
1016 }
1017
1018 RTSX_WRITE_REG(chip, CARD_PWR_CTL, mask, val);
1019 if (CHECK_PID(chip, 0x5209) && (card == SD_CARD)) {
1020 RTSX_WRITE_REG(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_OFF);
1021 }
1022
1023 return STATUS_SUCCESS;
1024 }
1025
1026 int card_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 sec_addr, u16 sec_cnt)
1027 {
1028 int retval;
1029 unsigned int lun = SCSI_LUN(srb);
1030 int i;
1031
1032 if (chip->rw_card[lun] == NULL) {
1033 TRACE_RET(chip, STATUS_FAIL);
1034 }
1035
1036 for (i = 0; i < 3; i++) {
1037 chip->rw_need_retry = 0;
1038
1039 retval = chip->rw_card[lun](srb, chip, sec_addr, sec_cnt);
1040 if (retval != STATUS_SUCCESS) {
1041 if (rtsx_check_chip_exist(chip) != STATUS_SUCCESS) {
1042 rtsx_release_chip(chip);
1043 TRACE_RET(chip, STATUS_FAIL);
1044 }
1045 if (detect_card_cd(chip, chip->cur_card) != STATUS_SUCCESS) {
1046 TRACE_RET(chip, STATUS_FAIL);
1047 }
1048 if (!chip->rw_need_retry) {
1049 RTSX_DEBUGP("RW fail, but no need to retry\n");
1050 break;
1051 }
1052 } else {
1053 chip->rw_need_retry = 0;
1054 break;
1055 }
1056
1057 RTSX_DEBUGP("Retry RW, (i = %d)\n", i);
1058 }
1059
1060 return retval;
1061 }
1062
1063 int card_share_mode(struct rtsx_chip *chip, int card)
1064 {
1065 u8 mask, value;
1066
1067 if (CHECK_PID(chip, 0x5209) || CHECK_PID(chip, 0x5208)) {
1068 mask = CARD_SHARE_MASK;
1069 if (card == SD_CARD) {
1070 value = CARD_SHARE_48_SD;
1071 } else if (card == MS_CARD) {
1072 value = CARD_SHARE_48_MS;
1073 } else if (card == XD_CARD) {
1074 value = CARD_SHARE_48_XD;
1075 } else {
1076 TRACE_RET(chip, STATUS_FAIL);
1077 }
1078 } else if (CHECK_PID(chip, 0x5288)) {
1079 mask = 0x03;
1080 if (card == SD_CARD) {
1081 value = CARD_SHARE_BAROSSA_SD;
1082 } else if (card == MS_CARD) {
1083 value = CARD_SHARE_BAROSSA_MS;
1084 } else if (card == XD_CARD) {
1085 value = CARD_SHARE_BAROSSA_XD;
1086 } else {
1087 TRACE_RET(chip, STATUS_FAIL);
1088 }
1089 } else {
1090 TRACE_RET(chip, STATUS_FAIL);
1091 }
1092
1093 RTSX_WRITE_REG(chip, CARD_SHARE_MODE, mask, value);
1094
1095 return STATUS_SUCCESS;
1096 }
1097
1098
1099 int select_card(struct rtsx_chip *chip, int card)
1100 {
1101 int retval;
1102
1103 if (chip->cur_card != card) {
1104 u8 mod;
1105
1106 if (card == SD_CARD) {
1107 mod = SD_MOD_SEL;
1108 } else if (card == MS_CARD) {
1109 mod = MS_MOD_SEL;
1110 } else if (card == XD_CARD) {
1111 mod = XD_MOD_SEL;
1112 } else if (card == SPI_CARD) {
1113 mod = SPI_MOD_SEL;
1114 } else {
1115 TRACE_RET(chip, STATUS_FAIL);
1116 }
1117 RTSX_WRITE_REG(chip, CARD_SELECT, 0x07, mod);
1118 chip->cur_card = card;
1119
1120 retval = card_share_mode(chip, card);
1121 if (retval != STATUS_SUCCESS) {
1122 TRACE_RET(chip, STATUS_FAIL);
1123 }
1124 }
1125
1126 return STATUS_SUCCESS;
1127 }
1128
1129 void toggle_gpio(struct rtsx_chip *chip, u8 gpio)
1130 {
1131 u8 temp_reg;
1132
1133 rtsx_read_register(chip, CARD_GPIO, &temp_reg);
1134 temp_reg ^= (0x01 << gpio);
1135 rtsx_write_register(chip, CARD_GPIO, 0xFF, temp_reg);
1136 }
1137
1138 void turn_on_led(struct rtsx_chip *chip, u8 gpio)
1139 {
1140 if (CHECK_PID(chip, 0x5288)) {
1141 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), (u8)(1 << gpio));
1142 } else {
1143 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 0);
1144 }
1145 }
1146
1147 void turn_off_led(struct rtsx_chip *chip, u8 gpio)
1148 {
1149 if (CHECK_PID(chip, 0x5288)) {
1150 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 0);
1151 } else {
1152 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), (u8)(1 << gpio));
1153 }
1154 }
1155
1156 int detect_card_cd(struct rtsx_chip *chip, int card)
1157 {
1158 u32 card_cd, status;
1159
1160 if (card == SD_CARD) {
1161 card_cd = SD_EXIST;
1162 } else if (card == MS_CARD) {
1163 card_cd = MS_EXIST;
1164 } else if (card == XD_CARD) {
1165 card_cd = XD_EXIST;
1166 } else {
1167 RTSX_DEBUGP("Wrong card type: 0x%x\n", card);
1168 TRACE_RET(chip, STATUS_FAIL);
1169 }
1170
1171 status = rtsx_readl(chip, RTSX_BIPR);
1172 if (!(status & card_cd)) {
1173 TRACE_RET(chip, STATUS_FAIL);
1174 }
1175
1176 return STATUS_SUCCESS;
1177 }
1178
1179 int check_card_exist(struct rtsx_chip *chip, unsigned int lun)
1180 {
1181 if (chip->card_exist & chip->lun2card[lun]) {
1182 return 1;
1183 }
1184
1185 return 0;
1186 }
1187
1188 int check_card_ready(struct rtsx_chip *chip, unsigned int lun)
1189 {
1190 if (chip->card_ready & chip->lun2card[lun]) {
1191 return 1;
1192 }
1193
1194 return 0;
1195 }
1196
1197 int check_card_wp(struct rtsx_chip *chip, unsigned int lun)
1198 {
1199 if (chip->card_wp & chip->lun2card[lun]) {
1200 return 1;
1201 }
1202
1203 return 0;
1204 }
1205
1206 int check_card_fail(struct rtsx_chip *chip, unsigned int lun)
1207 {
1208 if (chip->card_fail & chip->lun2card[lun]) {
1209 return 1;
1210 }
1211
1212 return 0;
1213 }
1214
1215 int check_card_ejected(struct rtsx_chip *chip, unsigned int lun)
1216 {
1217 if (chip->card_ejected & chip->lun2card[lun]) {
1218 return 1;
1219 }
1220
1221 return 0;
1222 }
1223
1224 u8 get_lun_card(struct rtsx_chip *chip, unsigned int lun)
1225 {
1226 if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD) {
1227 return (u8)XD_CARD;
1228 } else if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD) {
1229 return (u8)SD_CARD;
1230 } else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD) {
1231 return (u8)MS_CARD;
1232 }
1233
1234 return 0;
1235 }
1236
1237 void eject_card(struct rtsx_chip *chip, unsigned int lun)
1238 {
1239 do_remaining_work(chip);
1240
1241 if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD) {
1242 release_sd_card(chip);
1243 chip->card_ejected |= SD_CARD;
1244 chip->card_ready &= ~SD_CARD;
1245 chip->capacity[lun] = 0;
1246 } else if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD) {
1247 release_xd_card(chip);
1248 chip->card_ejected |= XD_CARD;
1249 chip->card_ready &= ~XD_CARD;
1250 chip->capacity[lun] = 0;
1251 } else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD) {
1252 release_ms_card(chip);
1253 chip->card_ejected |= MS_CARD;
1254 chip->card_ready &= ~MS_CARD;
1255 chip->capacity[lun] = 0;
1256 }
1257 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree