arch/x86/kernel/cpu/cpufreq/speedstep-lib.c

   1 /*
   2  * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
   3  *
   4  *  Licensed under the terms of the GNU GPL License version 2.
   5  *
   6  *  Library for common functions for Intel SpeedStep v.1 and v.2 support
   7  *
   8  *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/init.h>
  15 #include <linux/cpufreq.h>
  16 #include <linux/slab.h>
  17
  18 #include <asm/msr.h>
  19 #include "speedstep-lib.h"
  20
  21 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
  22                 "speedstep-lib", msg)
  23
  24 #define PFX "speedstep-lib: "
  25
  26 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
  27 static int relaxed_check;
  28 #else
  29 #define relaxed_check 0
  30 #endif
  31
  32 /*********************************************************************
  33  *                   GET PROCESSOR CORE SPEED IN KHZ                 *
  34  *********************************************************************/
  35
  36 static unsigned int pentium3_get_frequency(unsigned int processor)
  37 {
  38         /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
  39         struct {
  40                 unsigned int ratio;     /* Frequency Multiplier (x10) */
  41                 u8 bitmap;              /* power on configuration bits
  42                                         [27, 25:22] (in MSR 0x2a) */
  43         } msr_decode_mult[] = {
  44                 { 30, 0x01 },
  45                 { 35, 0x05 },
  46                 { 40, 0x02 },
  47                 { 45, 0x06 },
  48                 { 50, 0x00 },
  49                 { 55, 0x04 },
  50                 { 60, 0x0b },
  51                 { 65, 0x0f },
  52                 { 70, 0x09 },
  53                 { 75, 0x0d },
  54                 { 80, 0x0a },
  55                 { 85, 0x26 },
  56                 { 90, 0x20 },
  57                 { 100, 0x2b },
  58                 { 0, 0xff }     /* error or unknown value */
  59         };
  60
  61         /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
  62         struct {
  63                 unsigned int value;     /* Front Side Bus speed in MHz */
  64                 u8 bitmap;              /* power on configuration bits [18: 19]
  65                                         (in MSR 0x2a) */
  66         } msr_decode_fsb[] = {
  67                 {  66, 0x0 },
  68                 { 100, 0x2 },
  69                 { 133, 0x1 },
  70                 {   0, 0xff}
  71         };
  72
  73         u32 msr_lo, msr_tmp;
  74         int i = 0, j = 0;
  75
  76         /* read MSR 0x2a - we only need the low 32 bits */
  77         rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
  78         dprintk("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
  79         msr_tmp = msr_lo;
  80
  81         /* decode the FSB */
  82         msr_tmp &= 0x00c0000;
  83         msr_tmp >>= 18;
  84         while (msr_tmp != msr_decode_fsb[i].bitmap) {
  85                 if (msr_decode_fsb[i].bitmap == 0xff)
  86                         return 0;
  87                 i++;
  88         }
  89
  90         /* decode the multiplier */
  91         if (processor == SPEEDSTEP_CPU_PIII_C_EARLY) {
  92                 dprintk("workaround for early PIIIs\n");
  93                 msr_lo &= 0x03c00000;
  94         } else
  95                 msr_lo &= 0x0bc00000;
  96         msr_lo >>= 22;
  97         while (msr_lo != msr_decode_mult[j].bitmap) {
  98                 if (msr_decode_mult[j].bitmap == 0xff)
  99                         return 0;
 100                 j++;
 101         }
 102
 103         dprintk("speed is %u\n",
 104                 (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));
 105
 106         return msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100;
 107 }
 108
 109
 110 static unsigned int pentiumM_get_frequency(void)
 111 {
 112         u32 msr_lo, msr_tmp;
 113
 114         rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
 115         dprintk("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
 116
 117         /* see table B-2 of 24547212.pdf */
 118         if (msr_lo & 0x00040000) {
 119                 printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n",
 120                                 msr_lo, msr_tmp);
 121                 return 0;
 122         }
 123
 124         msr_tmp = (msr_lo >> 22) & 0x1f;
 125         dprintk("bits 22-26 are 0x%x, speed is %u\n",
 126                         msr_tmp, (msr_tmp * 100 * 1000));
 127
 128         return msr_tmp * 100 * 1000;
 129 }
 130
 131 static unsigned int pentium_core_get_frequency(void)
 132 {
 133         u32 fsb = 0;
 134         u32 msr_lo, msr_tmp;
 135         int ret;
 136
 137         rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
 138         /* see table B-2 of 25366920.pdf */
 139         switch (msr_lo & 0x07) {
 140         case 5:
 141                 fsb = 100000;
 142                 break;
 143         case 1:
 144                 fsb = 133333;
 145                 break;
 146         case 3:
 147                 fsb = 166667;
 148                 break;
 149         case 2:
 150                 fsb = 200000;
 151                 break;
 152         case 0:
 153                 fsb = 266667;
 154                 break;
 155         case 4:
 156                 fsb = 333333;
 157                 break;
 158         default:
 159                 printk(KERN_ERR "PCORE - MSR_FSB_FREQ undefined value");
 160         }
 161
 162         rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
 163         dprintk("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n",
 164                         msr_lo, msr_tmp);
 165
 166         msr_tmp = (msr_lo >> 22) & 0x1f;
 167         dprintk("bits 22-26 are 0x%x, speed is %u\n",
 168                         msr_tmp, (msr_tmp * fsb));
 169
 170         ret = (msr_tmp * fsb);
 171         return ret;
 172 }
 173
 174
 175 static unsigned int pentium4_get_frequency(void)
 176 {
 177         struct cpuinfo_x86 *c = &boot_cpu_data;
 178         u32 msr_lo, msr_hi, mult;
 179         unsigned int fsb = 0;
 180         unsigned int ret;
 181
 182         rdmsr(0x2c, msr_lo, msr_hi);
 183
 184         dprintk("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
 185
 186         /* decode the FSB: see IA-32 Intel (C) Architecture Software
 187          * Developer's Manual, Volume 3: System Prgramming Guide,
 188          * revision #12 in Table B-1: MSRs in the Pentium 4 and
 189          * Intel Xeon Processors, on page B-4 and B-5.
 190          */
 191         if (c->x86_model < 2)
 192                 fsb = 100 * 1000;
 193         else {
 194                 u8 fsb_code = (msr_lo >> 16) & 0x7;
 195                 switch (fsb_code) {
 196                 case 0:
 197                         fsb = 100 * 1000;
 198                         break;
 199                 case 1:
 200                         fsb = 13333 * 10;
 201                         break;
 202                 case 2:
 203                         fsb = 200 * 1000;
 204                         break;
 205                 }
 206         }
 207
 208         if (!fsb)
 209                 printk(KERN_DEBUG PFX "couldn't detect FSB speed. "
 210                                 "Please send an e-mail to <linux@brodo.de>\n");
 211
 212         /* Multiplier. */
 213         mult = msr_lo >> 24;
 214
 215         dprintk("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n",
 216                         fsb, mult, (fsb * mult));
 217
 218         ret = (fsb * mult);
 219         return ret;
 220 }
 221
 222
 223 unsigned int speedstep_get_frequency(unsigned int processor)
 224 {
 225         switch (processor) {
 226         case SPEEDSTEP_CPU_PCORE:
 227                 return pentium_core_get_frequency();
 228         case SPEEDSTEP_CPU_PM:
 229                 return pentiumM_get_frequency();
 230         case SPEEDSTEP_CPU_P4D:
 231         case SPEEDSTEP_CPU_P4M:
 232                 return pentium4_get_frequency();
 233         case SPEEDSTEP_CPU_PIII_T:
 234         case SPEEDSTEP_CPU_PIII_C:
 235         case SPEEDSTEP_CPU_PIII_C_EARLY:
 236                 return pentium3_get_frequency(processor);
 237         default:
 238                 return 0;
 239         };
 240         return 0;
 241 }
 242 EXPORT_SYMBOL_GPL(speedstep_get_frequency);
 243
 244
 245 /*********************************************************************
 246  *                 DETECT SPEEDSTEP-CAPABLE PROCESSOR                *
 247  *********************************************************************/
 248
 249 unsigned int speedstep_detect_processor(void)
 250 {
 251         struct cpuinfo_x86 *c = &cpu_data(0);
 252         u32 ebx, msr_lo, msr_hi;
 253
 254         dprintk("x86: %x, model: %x\n", c->x86, c->x86_model);
 255
 256         if ((c->x86_vendor != X86_VENDOR_INTEL) ||
 257             ((c->x86 != 6) && (c->x86 != 0xF)))
 258                 return 0;
 259
 260         if (c->x86 == 0xF) {
 261                 /* Intel Mobile Pentium 4-M
 262                  * or Intel Mobile Pentium 4 with 533 MHz FSB */
 263                 if (c->x86_model != 2)
 264                         return 0;
 265
 266                 ebx = cpuid_ebx(0x00000001);
 267                 ebx &= 0x000000FF;
 268
 269                 dprintk("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
 270
 271                 switch (c->x86_mask) {
 272                 case 4:
 273                         /*
 274                          * B-stepping [M-P4-M]
 275                          * sample has ebx = 0x0f, production has 0x0e.
 276                          */
 277                         if ((ebx == 0x0e) || (ebx == 0x0f))
 278                                 return SPEEDSTEP_CPU_P4M;
 279                         break;
 280                 case 7:
 281                         /*
 282                          * C-stepping [M-P4-M]
 283                          * needs to have ebx=0x0e, else it's a celeron:
 284                          * cf. 25130917.pdf / page 7, footnote 5 even
 285                          * though 25072120.pdf / page 7 doesn't say
 286                          * samples are only of B-stepping...
 287                          */
 288                         if (ebx == 0x0e)
 289                                 return SPEEDSTEP_CPU_P4M;
 290                         break;
 291                 case 9:
 292                         /*
 293                          * D-stepping [M-P4-M or M-P4/533]
 294                          *
 295                          * this is totally strange: CPUID 0x0F29 is
 296                          * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
 297                          * The latter need to be sorted out as they don't
 298                          * support speedstep.
 299                          * Celerons with CPUID 0x0F29 may have either
 300                          * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
 301                          * specific.
 302                          * M-P4-Ms may have either ebx=0xe or 0xf [see above]
 303                          * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
 304                          * also, M-P4M HTs have ebx=0x8, too
 305                          * For now, they are distinguished by the model_id
 306                          * string
 307                          */
 308                         if ((ebx == 0x0e) ||
 309                                 (strstr(c->x86_model_id,
 310                                     "Mobile Intel(R) Pentium(R) 4") != NULL))
 311                                 return SPEEDSTEP_CPU_P4M;
 312                         break;
 313                 default:
 314                         break;
 315                 }
 316                 return 0;
 317         }
 318
 319         switch (c->x86_model) {
 320         case 0x0B: /* Intel PIII [Tualatin] */
 321                 /* cpuid_ebx(1) is 0x04 for desktop PIII,
 322                  * 0x06 for mobile PIII-M */
 323                 ebx = cpuid_ebx(0x00000001);
 324                 dprintk("ebx is %x\n", ebx);
 325
 326                 ebx &= 0x000000FF;
 327
 328                 if (ebx != 0x06)
 329                         return 0;
 330
 331                 /* So far all PIII-M processors support SpeedStep. See
 332                  * Intel's 24540640.pdf of June 2003
 333                  */
 334                 return SPEEDSTEP_CPU_PIII_T;
 335
 336         case 0x08: /* Intel PIII [Coppermine] */
 337
 338                 /* all mobile PIII Coppermines have FSB 100 MHz
 339                  * ==> sort out a few desktop PIIIs. */
 340                 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
 341                 dprintk("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n",
 342                                 msr_lo, msr_hi);
 343                 msr_lo &= 0x00c0000;
 344                 if (msr_lo != 0x0080000)
 345                         return 0;
 346
 347                 /*
 348                  * If the processor is a mobile version,
 349                  * platform ID has bit 50 set
 350                  * it has SpeedStep technology if either
 351                  * bit 56 or 57 is set
 352                  */
 353                 rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
 354                 dprintk("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n",
 355                                 msr_lo, msr_hi);
 356                 if ((msr_hi & (1<<18)) &&
 357                     (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
 358                         if (c->x86_mask == 0x01) {
 359                                 dprintk("early PIII version\n");
 360                                 return SPEEDSTEP_CPU_PIII_C_EARLY;
 361                         } else
 362                                 return SPEEDSTEP_CPU_PIII_C;
 363                 }
 364
 365         default:
 366                 return 0;
 367         }
 368 }
 369 EXPORT_SYMBOL_GPL(speedstep_detect_processor);
 370
 371
 372 /*********************************************************************
 373  *                     DETECT SPEEDSTEP SPEEDS                       *
 374  *********************************************************************/
 375
 376 unsigned int speedstep_get_freqs(unsigned int processor,
 377                                   unsigned int *low_speed,
 378                                   unsigned int *high_speed,
 379                                   unsigned int *transition_latency,
 380                                   void (*set_state) (unsigned int state))
 381 {
 382         unsigned int prev_speed;
 383         unsigned int ret = 0;
 384         unsigned long flags;
 385         struct timeval tv1, tv2;
 386
 387         if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
 388                 return -EINVAL;
 389
 390         dprintk("trying to determine both speeds\n");
 391
 392         /* get current speed */
 393         prev_speed = speedstep_get_frequency(processor);
 394         if (!prev_speed)
 395                 return -EIO;
 396
 397         dprintk("previous speed is %u\n", prev_speed);
 398
 399         local_irq_save(flags);
 400
 401         /* switch to low state */
 402         set_state(SPEEDSTEP_LOW);
 403         *low_speed = speedstep_get_frequency(processor);
 404         if (!*low_speed) {
 405                 ret = -EIO;
 406                 goto out;
 407         }
 408
 409         dprintk("low speed is %u\n", *low_speed);
 410
 411         /* start latency measurement */
 412         if (transition_latency)
 413                 do_gettimeofday(&tv1);
 414
 415         /* switch to high state */
 416         set_state(SPEEDSTEP_HIGH);
 417
 418         /* end latency measurement */
 419         if (transition_latency)
 420                 do_gettimeofday(&tv2);
 421
 422         *high_speed = speedstep_get_frequency(processor);
 423         if (!*high_speed) {
 424                 ret = -EIO;
 425                 goto out;
 426         }
 427
 428         dprintk("high speed is %u\n", *high_speed);
 429
 430         if (*low_speed == *high_speed) {
 431                 ret = -ENODEV;
 432                 goto out;
 433         }
 434
 435         /* switch to previous state, if necessary */
 436         if (*high_speed != prev_speed)
 437                 set_state(SPEEDSTEP_LOW);
 438
 439         if (transition_latency) {
 440                 *transition_latency = (tv2.tv_sec - tv1.tv_sec) * USEC_PER_SEC +
 441                         tv2.tv_usec - tv1.tv_usec;
 442                 dprintk("transition latency is %u uSec\n", *transition_latency);
 443
 444                 /* convert uSec to nSec and add 20% for safety reasons */
 445                 *transition_latency *= 1200;
 446
 447                 /* check if the latency measurement is too high or too low
 448                  * and set it to a safe value (500uSec) in that case
 449                  */
 450                 if (*transition_latency > 10000000 ||
 451                     *transition_latency < 50000) {
 452                         printk(KERN_WARNING PFX "frequency transition "
 453                                         "measured seems out of range (%u "
 454                                         "nSec), falling back to a safe one of"
 455                                         "%u nSec.\n",
 456                                         *transition_latency, 500000);
 457                         *transition_latency = 500000;
 458                 }
 459         }
 460
 461 out:
 462         local_irq_restore(flags);
 463         return ret;
 464 }
 465 EXPORT_SYMBOL_GPL(speedstep_get_freqs);
 466
 467 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
 468 module_param(relaxed_check, int, 0444);
 469 MODULE_PARM_DESC(relaxed_check,
 470                 "Don't do all checks for speedstep capability.");
 471 #endif
 472
 473 MODULE_AUTHOR("Dominik Brodowski <linux@brodo.de>");
 474 MODULE_DESCRIPTION("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
 475 MODULE_LICENSE("GPL");