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IB/qib: Fix a possible data corruption when receiving packets
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / infiniband / hw / qib / qib_iba7322.c
blobb7c3c7df268ba2f654228c7a1930265080ce4e6d
1 /*
2 * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 /*
34 * This file contains all of the code that is specific to the
35 * InfiniPath 7322 chip
36 */
37
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/io.h>
42 #include <linux/jiffies.h>
43 #include <rdma/ib_verbs.h>
44 #include <rdma/ib_smi.h>
45
46 #include "qib.h"
47 #include "qib_7322_regs.h"
48 #include "qib_qsfp.h"
49
50 #include "qib_mad.h"
51
52 static void qib_setup_7322_setextled(struct qib_pportdata *, u32);
53 static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t);
54 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op);
55 static irqreturn_t qib_7322intr(int irq, void *data);
56 static irqreturn_t qib_7322bufavail(int irq, void *data);
57 static irqreturn_t sdma_intr(int irq, void *data);
58 static irqreturn_t sdma_idle_intr(int irq, void *data);
59 static irqreturn_t sdma_progress_intr(int irq, void *data);
60 static irqreturn_t sdma_cleanup_intr(int irq, void *data);
61 static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32,
62 struct qib_ctxtdata *rcd);
63 static u8 qib_7322_phys_portstate(u64);
64 static u32 qib_7322_iblink_state(u64);
65 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
66 u16 linitcmd);
67 static void force_h1(struct qib_pportdata *);
68 static void adj_tx_serdes(struct qib_pportdata *);
69 static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8);
70 static void qib_7322_mini_pcs_reset(struct qib_pportdata *);
71
72 static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32);
73 static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned);
74 static void serdes_7322_los_enable(struct qib_pportdata *, int);
75 static int serdes_7322_init_old(struct qib_pportdata *);
76 static int serdes_7322_init_new(struct qib_pportdata *);
77
78 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))
79
80 /* LE2 serdes values for different cases */
81 #define LE2_DEFAULT 5
82 #define LE2_5m 4
83 #define LE2_QME 0
84
85 /* Below is special-purpose, so only really works for the IB SerDes blocks. */
86 #define IBSD(hw_pidx) (hw_pidx + 2)
87
88 /* these are variables for documentation and experimentation purposes */
89 static const unsigned rcv_int_timeout = 375;
90 static const unsigned rcv_int_count = 16;
91 static const unsigned sdma_idle_cnt = 64;
92
93 /* Time to stop altering Rx Equalization parameters, after link up. */
94 #define RXEQ_DISABLE_MSECS 2500
95
96 /*
97 * Number of VLs we are configured to use (to allow for more
98 * credits per vl, etc.)
99 */
100 ushort qib_num_cfg_vls = 2;
101 module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO);
102 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
103
104 static ushort qib_chase = 1;
105 module_param_named(chase, qib_chase, ushort, S_IRUGO);
106 MODULE_PARM_DESC(chase, "Enable state chase handling");
107
108 static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */
109 module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO);
110 MODULE_PARM_DESC(long_attenuation, \
111 "attenuation cutoff (dB) for long copper cable setup");
112
113 static ushort qib_singleport;
114 module_param_named(singleport, qib_singleport, ushort, S_IRUGO);
115 MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space");
116
117 static ushort qib_krcvq01_no_msi;
118 module_param_named(krcvq01_no_msi, qib_krcvq01_no_msi, ushort, S_IRUGO);
119 MODULE_PARM_DESC(krcvq01_no_msi, "No MSI for kctx < 2");
120
121 /*
122 * Receive header queue sizes
123 */
124 static unsigned qib_rcvhdrcnt;
125 module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO);
126 MODULE_PARM_DESC(rcvhdrcnt, "receive header count");
127
128 static unsigned qib_rcvhdrsize;
129 module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO);
130 MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words");
131
132 static unsigned qib_rcvhdrentsize;
133 module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO);
134 MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words");
135
136 #define MAX_ATTEN_LEN 64 /* plenty for any real system */
137 /* for read back, default index is ~5m copper cable */
138 static char txselect_list[MAX_ATTEN_LEN] = "10";
139 static struct kparam_string kp_txselect = {
140 .string = txselect_list,
141 .maxlen = MAX_ATTEN_LEN
142 };
143 static int setup_txselect(const char *, struct kernel_param *);
144 module_param_call(txselect, setup_txselect, param_get_string,
145 &kp_txselect, S_IWUSR | S_IRUGO);
146 MODULE_PARM_DESC(txselect, \
147 "Tx serdes indices (for no QSFP or invalid QSFP data)");
148
149 #define BOARD_QME7342 5
150 #define BOARD_QMH7342 6
151 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
152 BOARD_QMH7342)
153 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
154 BOARD_QME7342)
155
156 #define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64))
157
158 #define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64)))
159
160 #define MASK_ACROSS(lsb, msb) \
161 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb))
162
163 #define SYM_RMASK(regname, fldname) ((u64) \
164 QIB_7322_##regname##_##fldname##_RMASK)
165
166 #define SYM_MASK(regname, fldname) ((u64) \
167 QIB_7322_##regname##_##fldname##_RMASK << \
168 QIB_7322_##regname##_##fldname##_LSB)
169
170 #define SYM_FIELD(value, regname, fldname) ((u64) \
171 (((value) >> SYM_LSB(regname, fldname)) & \
172 SYM_RMASK(regname, fldname)))
173
174 /* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */
175 #define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \
176 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))
177
178 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
179 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
180 #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
181 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
182 #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
183 /* Below because most, but not all, fields of IntMask have that full suffix */
184 #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)
185
186
187 #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB)
188
189 /*
190 * the size bits give us 2^N, in KB units. 0 marks as invalid,
191 * and 7 is reserved. We currently use only 2KB and 4KB
192 */
193 #define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB
194 #define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */
195 #define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */
196 #define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
197
198 #define SendIBSLIDAssignMask \
199 QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK
200 #define SendIBSLMCMask \
201 QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK
202
203 #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
204 #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
205 #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
206 #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
207 #define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN)
208 #define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN)
209
210 #define _QIB_GPIO_SDA_NUM 1
211 #define _QIB_GPIO_SCL_NUM 0
212 #define QIB_EEPROM_WEN_NUM 14
213 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */
214
215 /* HW counter clock is at 4nsec */
216 #define QIB_7322_PSXMITWAIT_CHECK_RATE 4000
217
218 /* full speed IB port 1 only */
219 #define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR)
220 #define PORT_SPD_CAP_SHIFT 3
221
222 /* full speed featuremask, both ports */
223 #define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT))
224
225 /*
226 * This file contains almost all the chip-specific register information and
227 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip.
228 */
229
230 /* Use defines to tie machine-generated names to lower-case names */
231 #define kr_contextcnt KREG_IDX(ContextCnt)
232 #define kr_control KREG_IDX(Control)
233 #define kr_counterregbase KREG_IDX(CntrRegBase)
234 #define kr_errclear KREG_IDX(ErrClear)
235 #define kr_errmask KREG_IDX(ErrMask)
236 #define kr_errstatus KREG_IDX(ErrStatus)
237 #define kr_extctrl KREG_IDX(EXTCtrl)
238 #define kr_extstatus KREG_IDX(EXTStatus)
239 #define kr_gpio_clear KREG_IDX(GPIOClear)
240 #define kr_gpio_mask KREG_IDX(GPIOMask)
241 #define kr_gpio_out KREG_IDX(GPIOOut)
242 #define kr_gpio_status KREG_IDX(GPIOStatus)
243 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
244 #define kr_debugportval KREG_IDX(DebugPortValueReg)
245 #define kr_fmask KREG_IDX(feature_mask)
246 #define kr_act_fmask KREG_IDX(active_feature_mask)
247 #define kr_hwerrclear KREG_IDX(HwErrClear)
248 #define kr_hwerrmask KREG_IDX(HwErrMask)
249 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
250 #define kr_intclear KREG_IDX(IntClear)
251 #define kr_intmask KREG_IDX(IntMask)
252 #define kr_intredirect KREG_IDX(IntRedirect0)
253 #define kr_intstatus KREG_IDX(IntStatus)
254 #define kr_pagealign KREG_IDX(PageAlign)
255 #define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0)
256 #define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */
257 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
258 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
259 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
260 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
261 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
262 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
263 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
264 #define kr_revision KREG_IDX(Revision)
265 #define kr_scratch KREG_IDX(Scratch)
266 #define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */
267 #define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */
268 #define kr_sendctrl KREG_IDX(SendCtrl)
269 #define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */
270 #define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */
271 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
272 #define kr_sendpiobufbase KREG_IDX(SendBufBase)
273 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
274 #define kr_sendpiosize KREG_IDX(SendBufSize)
275 #define kr_sendregbase KREG_IDX(SendRegBase)
276 #define kr_sendbufavail0 KREG_IDX(SendBufAvail0)
277 #define kr_userregbase KREG_IDX(UserRegBase)
278 #define kr_intgranted KREG_IDX(Int_Granted)
279 #define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int)
280 #define kr_intblocked KREG_IDX(IntBlocked)
281 #define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG)
282
283 /*
284 * per-port kernel registers. Access only with qib_read_kreg_port()
285 * or qib_write_kreg_port()
286 */
287 #define krp_errclear KREG_IBPORT_IDX(ErrClear)
288 #define krp_errmask KREG_IBPORT_IDX(ErrMask)
289 #define krp_errstatus KREG_IBPORT_IDX(ErrStatus)
290 #define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0)
291 #define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit)
292 #define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID)
293 #define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig)
294 #define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA)
295 #define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB)
296 #define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC)
297 #define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA)
298 #define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB)
299 #define krp_txestatus KREG_IBPORT_IDX(TXEStatus)
300 #define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0)
301 #define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl)
302 #define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey)
303 #define krp_psinterval KREG_IBPORT_IDX(PSInterval)
304 #define krp_psstart KREG_IBPORT_IDX(PSStart)
305 #define krp_psstat KREG_IBPORT_IDX(PSStat)
306 #define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP)
307 #define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl)
308 #define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt)
309 #define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA)
310 #define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0)
311 #define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15)
312 #define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl)
313 #define krp_sendctrl KREG_IBPORT_IDX(SendCtrl)
314 #define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase)
315 #define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0)
316 #define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1)
317 #define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2)
318 #define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0)
319 #define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1)
320 #define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2)
321 #define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt)
322 #define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead)
323 #define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr)
324 #define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt)
325 #define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen)
326 #define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld)
327 #define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt)
328 #define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus)
329 #define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail)
330 #define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom)
331 #define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign)
332 #define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask)
333 #define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX)
334 #define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD)
335 #define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE)
336 #define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl)
337
338 /*
339 * Per-context kernel registers. Access only with qib_read_kreg_ctxt()
340 * or qib_write_kreg_ctxt()
341 */
342 #define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0)
343 #define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
344
345 /*
346 * TID Flow table, per context. Reduces
347 * number of hdrq updates to one per flow (or on errors).
348 * context 0 and 1 share same memory, but have distinct
349 * addresses. Since for now, we never use expected sends
350 * on kernel contexts, we don't worry about that (we initialize
351 * those entries for ctxt 0/1 on driver load twice, for example).
352 */
353 #define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */
354 #define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0))
355
356 /* these are the error bits in the tid flows, and are W1C */
357 #define TIDFLOW_ERRBITS ( \
358 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
359 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
360 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
361 SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))
362
363 /* Most (not all) Counters are per-IBport.
364 * Requires LBIntCnt is at offset 0 in the group
365 */
366 #define CREG_IDX(regname) \
367 ((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
368
369 #define crp_badformat CREG_IDX(RxVersionErrCnt)
370 #define crp_err_rlen CREG_IDX(RxLenErrCnt)
371 #define crp_erricrc CREG_IDX(RxICRCErrCnt)
372 #define crp_errlink CREG_IDX(RxLinkMalformCnt)
373 #define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt)
374 #define crp_errpkey CREG_IDX(RxPKeyMismatchCnt)
375 #define crp_errvcrc CREG_IDX(RxVCRCErrCnt)
376 #define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
377 #define crp_iblinkdown CREG_IDX(IBLinkDownedCnt)
378 #define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
379 #define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt)
380 #define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
381 #define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
382 #define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
383 #define crp_pktrcv CREG_IDX(RxDataPktCnt)
384 #define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
385 #define crp_pktsend CREG_IDX(TxDataPktCnt)
386 #define crp_pktsendflow CREG_IDX(TxFlowPktCnt)
387 #define crp_psrcvdatacount CREG_IDX(PSRcvDataCount)
388 #define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount)
389 #define crp_psxmitdatacount CREG_IDX(PSXmitDataCount)
390 #define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount)
391 #define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
392 #define crp_rcvebp CREG_IDX(RxEBPCnt)
393 #define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt)
394 #define crp_rcvovfl CREG_IDX(RxBufOvflCnt)
395 #define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
396 #define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt)
397 #define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
398 #define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt)
399 #define crp_rxvlerr CREG_IDX(RxVlErrCnt)
400 #define crp_sendstall CREG_IDX(TxFlowStallCnt)
401 #define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt)
402 #define crp_txhdrerr CREG_IDX(TxHeadersErrCnt)
403 #define crp_txlenerr CREG_IDX(TxLenErrCnt)
404 #define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt)
405 #define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt)
406 #define crp_txunderrun CREG_IDX(TxUnderrunCnt)
407 #define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
408 #define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
409 #define crp_wordrcv CREG_IDX(RxDwordCnt)
410 #define crp_wordsend CREG_IDX(TxDwordCnt)
411 #define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut)
412
413 /* these are the (few) counters that are not port-specific */
414 #define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \
415 QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
416 #define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt)
417 #define cr_lbint CREG_DEVIDX(LBIntCnt)
418 #define cr_lbstall CREG_DEVIDX(LBFlowStallCnt)
419 #define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt)
420 #define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt)
421 #define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt)
422 #define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt)
423
424 /* no chip register for # of IB ports supported, so define */
425 #define NUM_IB_PORTS 2
426
427 /* 1 VL15 buffer per hardware IB port, no register for this, so define */
428 #define NUM_VL15_BUFS NUM_IB_PORTS
429
430 /*
431 * context 0 and 1 are special, and there is no chip register that
432 * defines this value, so we have to define it here.
433 * These are all allocated to either 0 or 1 for single port
434 * hardware configuration, otherwise each gets half
435 */
436 #define KCTXT0_EGRCNT 2048
437
438 /* values for vl and port fields in PBC, 7322-specific */
439 #define PBC_PORT_SEL_LSB 26
440 #define PBC_PORT_SEL_RMASK 1
441 #define PBC_VL_NUM_LSB 27
442 #define PBC_VL_NUM_RMASK 7
443 #define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
444 #define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
445
446 static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
447 [IB_RATE_2_5_GBPS] = 16,
448 [IB_RATE_5_GBPS] = 8,
449 [IB_RATE_10_GBPS] = 4,
450 [IB_RATE_20_GBPS] = 2,
451 [IB_RATE_30_GBPS] = 2,
452 [IB_RATE_40_GBPS] = 1
453 };
454
455 #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
456 #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)
457
458 /* link training states, from IBC */
459 #define IB_7322_LT_STATE_DISABLED 0x00
460 #define IB_7322_LT_STATE_LINKUP 0x01
461 #define IB_7322_LT_STATE_POLLACTIVE 0x02
462 #define IB_7322_LT_STATE_POLLQUIET 0x03
463 #define IB_7322_LT_STATE_SLEEPDELAY 0x04
464 #define IB_7322_LT_STATE_SLEEPQUIET 0x05
465 #define IB_7322_LT_STATE_CFGDEBOUNCE 0x08
466 #define IB_7322_LT_STATE_CFGRCVFCFG 0x09
467 #define IB_7322_LT_STATE_CFGWAITRMT 0x0a
468 #define IB_7322_LT_STATE_CFGIDLE 0x0b
469 #define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c
470 #define IB_7322_LT_STATE_TXREVLANES 0x0d
471 #define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e
472 #define IB_7322_LT_STATE_RECOVERIDLE 0x0f
473 #define IB_7322_LT_STATE_CFGENH 0x10
474 #define IB_7322_LT_STATE_CFGTEST 0x11
475 #define IB_7322_LT_STATE_CFGWAITRMTTEST 0x12
476 #define IB_7322_LT_STATE_CFGWAITENH 0x13
477
478 /* link state machine states from IBC */
479 #define IB_7322_L_STATE_DOWN 0x0
480 #define IB_7322_L_STATE_INIT 0x1
481 #define IB_7322_L_STATE_ARM 0x2
482 #define IB_7322_L_STATE_ACTIVE 0x3
483 #define IB_7322_L_STATE_ACT_DEFER 0x4
484
485 static const u8 qib_7322_physportstate[0x20] = {
486 [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
487 [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
488 [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
489 [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
490 [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
491 [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
492 [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN,
493 [IB_7322_LT_STATE_CFGRCVFCFG] =
494 IB_PHYSPORTSTATE_CFG_TRAIN,
495 [IB_7322_LT_STATE_CFGWAITRMT] =
496 IB_PHYSPORTSTATE_CFG_TRAIN,
497 [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE,
498 [IB_7322_LT_STATE_RECOVERRETRAIN] =
499 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
500 [IB_7322_LT_STATE_RECOVERWAITRMT] =
501 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
502 [IB_7322_LT_STATE_RECOVERIDLE] =
503 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
504 [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH,
505 [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN,
506 [IB_7322_LT_STATE_CFGWAITRMTTEST] =
507 IB_PHYSPORTSTATE_CFG_TRAIN,
508 [IB_7322_LT_STATE_CFGWAITENH] =
509 IB_PHYSPORTSTATE_CFG_WAIT_ENH,
510 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
511 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
512 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
513 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
514 };
515
516 struct qib_chip_specific {
517 u64 __iomem *cregbase;
518 u64 *cntrs;
519 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
520 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
521 u64 main_int_mask; /* clear bits which have dedicated handlers */
522 u64 int_enable_mask; /* for per port interrupts in single port mode */
523 u64 errormask;
524 u64 hwerrmask;
525 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
526 u64 gpio_mask; /* shadow the gpio mask register */
527 u64 extctrl; /* shadow the gpio output enable, etc... */
528 u32 ncntrs;
529 u32 nportcntrs;
530 u32 cntrnamelen;
531 u32 portcntrnamelen;
532 u32 numctxts;
533 u32 rcvegrcnt;
534 u32 updthresh; /* current AvailUpdThld */
535 u32 updthresh_dflt; /* default AvailUpdThld */
536 u32 r1;
537 int irq;
538 u32 num_msix_entries;
539 u32 sdmabufcnt;
540 u32 lastbuf_for_pio;
541 u32 stay_in_freeze;
542 u32 recovery_ports_initted;
543 struct msix_entry *msix_entries;
544 void **msix_arg;
545 unsigned long *sendchkenable;
546 unsigned long *sendgrhchk;
547 unsigned long *sendibchk;
548 u32 rcvavail_timeout[18];
549 char emsgbuf[128]; /* for device error interrupt msg buffer */
550 };
551
552 /* Table of entries in "human readable" form Tx Emphasis. */
553 struct txdds_ent {
554 u8 amp;
555 u8 pre;
556 u8 main;
557 u8 post;
558 };
559
560 struct vendor_txdds_ent {
561 u8 oui[QSFP_VOUI_LEN];
562 u8 *partnum;
563 struct txdds_ent sdr;
564 struct txdds_ent ddr;
565 struct txdds_ent qdr;
566 };
567
568 static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *);
569
570 #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */
571 #define TXDDS_EXTRA_SZ 13 /* number of extra tx settings entries */
572 #define TXDDS_MFG_SZ 2 /* number of mfg tx settings entries */
573 #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */
574
575 #define H1_FORCE_VAL 8
576 #define H1_FORCE_QME 1 /* may be overridden via setup_txselect() */
577 #define H1_FORCE_QMH 7 /* may be overridden via setup_txselect() */
578
579 /* The static and dynamic registers are paired, and the pairs indexed by spd */
580 #define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \
581 + ((spd) * 2))
582
583 #define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */
584 #define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */
585 #define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */
586 #define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */
587 #define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */
588
589 struct qib_chippport_specific {
590 u64 __iomem *kpregbase;
591 u64 __iomem *cpregbase;
592 u64 *portcntrs;
593 struct qib_pportdata *ppd;
594 wait_queue_head_t autoneg_wait;
595 struct delayed_work autoneg_work;
596 struct delayed_work ipg_work;
597 struct timer_list chase_timer;
598 /*
599 * these 5 fields are used to establish deltas for IB symbol
600 * errors and linkrecovery errors. They can be reported on
601 * some chips during link negotiation prior to INIT, and with
602 * DDR when faking DDR negotiations with non-IBTA switches.
603 * The chip counters are adjusted at driver unload if there is
604 * a non-zero delta.
605 */
606 u64 ibdeltainprog;
607 u64 ibsymdelta;
608 u64 ibsymsnap;
609 u64 iblnkerrdelta;
610 u64 iblnkerrsnap;
611 u64 iblnkdownsnap;
612 u64 iblnkdowndelta;
613 u64 ibmalfdelta;
614 u64 ibmalfsnap;
615 u64 ibcctrl_a; /* krp_ibcctrl_a shadow */
616 u64 ibcctrl_b; /* krp_ibcctrl_b shadow */
617 u64 qdr_dfe_time;
618 u64 chase_end;
619 u32 autoneg_tries;
620 u32 recovery_init;
621 u32 qdr_dfe_on;
622 u32 qdr_reforce;
623 /*
624 * Per-bay per-channel rcv QMH H1 values and Tx values for QDR.
625 * entry zero is unused, to simplify indexing
626 */
627 u8 h1_val;
628 u8 no_eep; /* txselect table index to use if no qsfp info */
629 u8 ipg_tries;
630 u8 ibmalfusesnap;
631 struct qib_qsfp_data qsfp_data;
632 char epmsgbuf[192]; /* for port error interrupt msg buffer */
633 };
634
635 static struct {
636 const char *name;
637 irq_handler_t handler;
638 int lsb;
639 int port; /* 0 if not port-specific, else port # */
640 } irq_table[] = {
641 { QIB_DRV_NAME, qib_7322intr, -1, 0 },
642 { QIB_DRV_NAME " (buf avail)", qib_7322bufavail,
643 SYM_LSB(IntStatus, SendBufAvail), 0 },
644 { QIB_DRV_NAME " (sdma 0)", sdma_intr,
645 SYM_LSB(IntStatus, SDmaInt_0), 1 },
646 { QIB_DRV_NAME " (sdma 1)", sdma_intr,
647 SYM_LSB(IntStatus, SDmaInt_1), 2 },
648 { QIB_DRV_NAME " (sdmaI 0)", sdma_idle_intr,
649 SYM_LSB(IntStatus, SDmaIdleInt_0), 1 },
650 { QIB_DRV_NAME " (sdmaI 1)", sdma_idle_intr,
651 SYM_LSB(IntStatus, SDmaIdleInt_1), 2 },
652 { QIB_DRV_NAME " (sdmaP 0)", sdma_progress_intr,
653 SYM_LSB(IntStatus, SDmaProgressInt_0), 1 },
654 { QIB_DRV_NAME " (sdmaP 1)", sdma_progress_intr,
655 SYM_LSB(IntStatus, SDmaProgressInt_1), 2 },
656 { QIB_DRV_NAME " (sdmaC 0)", sdma_cleanup_intr,
657 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1 },
658 { QIB_DRV_NAME " (sdmaC 1)", sdma_cleanup_intr,
659 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 },
660 };
661
662 /* ibcctrl bits */
663 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
664 /* cycle through TS1/TS2 till OK */
665 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
666 /* wait for TS1, then go on */
667 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
668 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
669
670 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
671 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
672 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
673
674 #define BLOB_7322_IBCHG 0x101
675
676 static inline void qib_write_kreg(const struct qib_devdata *dd,
677 const u32 regno, u64 value);
678 static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32);
679 static void write_7322_initregs(struct qib_devdata *);
680 static void write_7322_init_portregs(struct qib_pportdata *);
681 static void setup_7322_link_recovery(struct qib_pportdata *, u32);
682 static void check_7322_rxe_status(struct qib_pportdata *);
683 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *);
684
685 /**
686 * qib_read_ureg32 - read 32-bit virtualized per-context register
687 * @dd: device
688 * @regno: register number
689 * @ctxt: context number
690 *
691 * Return the contents of a register that is virtualized to be per context.
692 * Returns -1 on errors (not distinguishable from valid contents at
693 * runtime; we may add a separate error variable at some point).
694 */
695 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
696 enum qib_ureg regno, int ctxt)
697 {
698 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
699 return 0;
700 return readl(regno + (u64 __iomem *)(
701 (dd->ureg_align * ctxt) + (dd->userbase ?
702 (char __iomem *)dd->userbase :
703 (char __iomem *)dd->kregbase + dd->uregbase)));
704 }
705
706 /**
707 * qib_read_ureg - read virtualized per-context register
708 * @dd: device
709 * @regno: register number
710 * @ctxt: context number
711 *
712 * Return the contents of a register that is virtualized to be per context.
713 * Returns -1 on errors (not distinguishable from valid contents at
714 * runtime; we may add a separate error variable at some point).
715 */
716 static inline u64 qib_read_ureg(const struct qib_devdata *dd,
717 enum qib_ureg regno, int ctxt)
718 {
719
720 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
721 return 0;
722 return readq(regno + (u64 __iomem *)(
723 (dd->ureg_align * ctxt) + (dd->userbase ?
724 (char __iomem *)dd->userbase :
725 (char __iomem *)dd->kregbase + dd->uregbase)));
726 }
727
728 /**
729 * qib_write_ureg - write virtualized per-context register
730 * @dd: device
731 * @regno: register number
732 * @value: value
733 * @ctxt: context
734 *
735 * Write the contents of a register that is virtualized to be per context.
736 */
737 static inline void qib_write_ureg(const struct qib_devdata *dd,
738 enum qib_ureg regno, u64 value, int ctxt)
739 {
740 u64 __iomem *ubase;
741 if (dd->userbase)
742 ubase = (u64 __iomem *)
743 ((char __iomem *) dd->userbase +
744 dd->ureg_align * ctxt);
745 else
746 ubase = (u64 __iomem *)
747 (dd->uregbase +
748 (char __iomem *) dd->kregbase +
749 dd->ureg_align * ctxt);
750
751 if (dd->kregbase && (dd->flags & QIB_PRESENT))
752 writeq(value, &ubase[regno]);
753 }
754
755 static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
756 const u32 regno)
757 {
758 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
759 return -1;
760 return readl((u32 __iomem *) &dd->kregbase[regno]);
761 }
762
763 static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
764 const u32 regno)
765 {
766 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
767 return -1;
768 return readq(&dd->kregbase[regno]);
769 }
770
771 static inline void qib_write_kreg(const struct qib_devdata *dd,
772 const u32 regno, u64 value)
773 {
774 if (dd->kregbase && (dd->flags & QIB_PRESENT))
775 writeq(value, &dd->kregbase[regno]);
776 }
777
778 /*
779 * not many sanity checks for the port-specific kernel register routines,
780 * since they are only used when it's known to be safe.
781 */
782 static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd,
783 const u16 regno)
784 {
785 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT))
786 return 0ULL;
787 return readq(&ppd->cpspec->kpregbase[regno]);
788 }
789
790 static inline void qib_write_kreg_port(const struct qib_pportdata *ppd,
791 const u16 regno, u64 value)
792 {
793 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase &&
794 (ppd->dd->flags & QIB_PRESENT))
795 writeq(value, &ppd->cpspec->kpregbase[regno]);
796 }
797
798 /**
799 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
800 * @dd: the qlogic_ib device
801 * @regno: the register number to write
802 * @ctxt: the context containing the register
803 * @value: the value to write
804 */
805 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
806 const u16 regno, unsigned ctxt,
807 u64 value)
808 {
809 qib_write_kreg(dd, regno + ctxt, value);
810 }
811
812 static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno)
813 {
814 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
815 return 0;
816 return readq(&dd->cspec->cregbase[regno]);
817
818
819 }
820
821 static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno)
822 {
823 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
824 return 0;
825 return readl(&dd->cspec->cregbase[regno]);
826
827
828 }
829
830 static inline void write_7322_creg_port(const struct qib_pportdata *ppd,
831 u16 regno, u64 value)
832 {
833 if (ppd->cpspec && ppd->cpspec->cpregbase &&
834 (ppd->dd->flags & QIB_PRESENT))
835 writeq(value, &ppd->cpspec->cpregbase[regno]);
836 }
837
838 static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd,
839 u16 regno)
840 {
841 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
842 !(ppd->dd->flags & QIB_PRESENT))
843 return 0;
844 return readq(&ppd->cpspec->cpregbase[regno]);
845 }
846
847 static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd,
848 u16 regno)
849 {
850 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
851 !(ppd->dd->flags & QIB_PRESENT))
852 return 0;
853 return readl(&ppd->cpspec->cpregbase[regno]);
854 }
855
856 /* bits in Control register */
857 #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
858 #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)
859
860 /* bits in general interrupt regs */
861 #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
862 #define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17)
863 #define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB)
864 #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
865 #define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17)
866 #define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB)
867 #define QIB_I_C_ERROR INT_MASK(Err)
868
869 #define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1))
870 #define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail)
871 #define QIB_I_GPIO INT_MASK(AssertGPIO)
872 #define QIB_I_P_SDMAINT(pidx) \
873 (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
874 INT_MASK_P(SDmaProgress, pidx) | \
875 INT_MASK_PM(SDmaCleanupDone, pidx))
876
877 /* Interrupt bits that are "per port" */
878 #define QIB_I_P_BITSEXTANT(pidx) \
879 (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \
880 INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
881 INT_MASK_P(SDmaProgress, pidx) | \
882 INT_MASK_PM(SDmaCleanupDone, pidx))
883
884 /* Interrupt bits that are common to a device */
885 /* currently unused: QIB_I_SPIOSENT */
886 #define QIB_I_C_BITSEXTANT \
887 (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \
888 QIB_I_SPIOSENT | \
889 QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO)
890
891 #define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \
892 QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1))
893
894 /*
895 * Error bits that are "per port".
896 */
897 #define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged)
898 #define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr)
899 #define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr)
900 #define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr)
901 #define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr)
902 #define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr)
903 #define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr)
904 #define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr)
905 #define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr)
906 #define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr)
907 #define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr)
908 #define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr)
909 #define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr)
910 #define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr)
911 #define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr)
912 #define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr)
913 #define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr)
914 #define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr)
915 #define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr)
916 #define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr)
917 #define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr)
918 #define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr)
919 #define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr)
920 #define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr)
921 #define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr)
922 #define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr)
923 #define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr)
924 #define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr)
925
926 #define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr)
927 #define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr)
928 #define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr)
929 #define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr)
930 #define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr)
931 #define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr)
932 #define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr)
933 #define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr)
934 #define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr)
935 #define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr)
936 #define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr)
937
938 /* Error bits that are common to a device */
939 #define QIB_E_RESET ERR_MASK(ResetNegated)
940 #define QIB_E_HARDWARE ERR_MASK(HardwareErr)
941 #define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr)
942
943
944 /*
945 * Per chip (rather than per-port) errors. Most either do
946 * nothing but trigger a print (because they self-recover, or
947 * always occur in tandem with other errors that handle the
948 * issue), or because they indicate errors with no recovery,
949 * but we want to know that they happened.
950 */
951 #define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr)
952 #define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd)
953 #define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr)
954 #define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr)
955 #define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr)
956 #define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr)
957 #define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr)
958 #define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr)
959
960 /* SDMA chip errors (not per port)
961 * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get
962 * the SDMAHALT error immediately, so we just print the dup error via the
963 * E_AUTO mechanism. This is true of most of the per-port fatal errors
964 * as well, but since this is port-independent, by definition, it's
965 * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per
966 * packet send errors, and so are handled in the same manner as other
967 * per-packet errors.
968 */
969 #define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err)
970 #define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr)
971 #define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr)
972
973 /*
974 * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS
975 * it is used to print "common" packet errors.
976 */
977 #define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\
978 QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\
979 QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\
980 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
981 QIB_E_P_REBP)
982
983 /* Error Bits that Packet-related (Receive, per-port) */
984 #define QIB_E_P_RPKTERRS (\
985 QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \
986 QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \
987 QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\
988 QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \
989 QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \
990 QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP)
991
992 /*
993 * Error bits that are Send-related (per port)
994 * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling).
995 * All of these potentially need to have a buffer disarmed
996 */
997 #define QIB_E_P_SPKTERRS (\
998 QIB_E_P_SUNEXP_PKTNUM |\
999 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1000 QIB_E_P_SMAXPKTLEN |\
1001 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
1002 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \
1003 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL)
1004
1005 #define QIB_E_SPKTERRS ( \
1006 QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \
1007 ERR_MASK_N(SendUnsupportedVLErr) | \
1008 QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT)
1009
1010 #define QIB_E_P_SDMAERRS ( \
1011 QIB_E_P_SDMAHALT | \
1012 QIB_E_P_SDMADESCADDRMISALIGN | \
1013 QIB_E_P_SDMAUNEXPDATA | \
1014 QIB_E_P_SDMAMISSINGDW | \
1015 QIB_E_P_SDMADWEN | \
1016 QIB_E_P_SDMARPYTAG | \
1017 QIB_E_P_SDMA1STDESC | \
1018 QIB_E_P_SDMABASE | \
1019 QIB_E_P_SDMATAILOUTOFBOUND | \
1020 QIB_E_P_SDMAOUTOFBOUND | \
1021 QIB_E_P_SDMAGENMISMATCH)
1022
1023 /*
1024 * This sets some bits more than once, but makes it more obvious which
1025 * bits are not handled under other categories, and the repeat definition
1026 * is not a problem.
1027 */
1028 #define QIB_E_P_BITSEXTANT ( \
1029 QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \
1030 QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \
1031 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \
1032 QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \
1033 )
1034
1035 /*
1036 * These are errors that can occur when the link
1037 * changes state while a packet is being sent or received. This doesn't
1038 * cover things like EBP or VCRC that can be the result of a sending
1039 * having the link change state, so we receive a "known bad" packet.
1040 * All of these are "per port", so renamed:
1041 */
1042 #define QIB_E_P_LINK_PKTERRS (\
1043 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1044 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\
1045 QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\
1046 QIB_E_P_RUNEXPCHAR)
1047
1048 /*
1049 * This sets some bits more than once, but makes it more obvious which
1050 * bits are not handled under other categories (such as QIB_E_SPKTERRS),
1051 * and the repeat definition is not a problem.
1052 */
1053 #define QIB_E_C_BITSEXTANT (\
1054 QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\
1055 QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\
1056 QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE)
1057
1058 /* Likewise Neuter E_SPKT_ERRS_IGNORE */
1059 #define E_SPKT_ERRS_IGNORE 0
1060
1061 #define QIB_EXTS_MEMBIST_DISABLED \
1062 SYM_MASK(EXTStatus, MemBISTDisabled)
1063 #define QIB_EXTS_MEMBIST_ENDTEST \
1064 SYM_MASK(EXTStatus, MemBISTEndTest)
1065
1066 #define QIB_E_SPIOARMLAUNCH \
1067 ERR_MASK(SendArmLaunchErr)
1068
1069 #define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd)
1070 #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)
1071
1072 /*
1073 * IBTA_1_2 is set when multiple speeds are enabled (normal),
1074 * and also if forced QDR (only QDR enabled). It's enabled for the
1075 * forced QDR case so that scrambling will be enabled by the TS3
1076 * exchange, when supported by both sides of the link.
1077 */
1078 #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
1079 #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
1080 #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
1081 #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
1082 #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
1083 #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
1084 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
1085 #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)
1086
1087 #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
1088 #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)
1089
1090 #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
1091 #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1092 #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1093
1094 #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1095 #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1096 #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
1097 SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
1098 #define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \
1099 SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
1100 #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)
1101
1102 #define IBA7322_REDIRECT_VEC_PER_REG 12
1103
1104 #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
1105 #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
1106 #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
1107 #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
1108 #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)
1109
1110 #define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */
1111
1112 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
1113 .msg = #fldname , .sz = sizeof(#fldname) }
1114 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
1115 fldname##Mask##_##port), .msg = #fldname , .sz = sizeof(#fldname) }
1116 static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = {
1117 HWE_AUTO_P(IBSerdesPClkNotDetect, 1),
1118 HWE_AUTO_P(IBSerdesPClkNotDetect, 0),
1119 HWE_AUTO(PCIESerdesPClkNotDetect),
1120 HWE_AUTO(PowerOnBISTFailed),
1121 HWE_AUTO(TempsenseTholdReached),
1122 HWE_AUTO(MemoryErr),
1123 HWE_AUTO(PCIeBusParityErr),
1124 HWE_AUTO(PcieCplTimeout),
1125 HWE_AUTO(PciePoisonedTLP),
1126 HWE_AUTO_P(SDmaMemReadErr, 1),
1127 HWE_AUTO_P(SDmaMemReadErr, 0),
1128 HWE_AUTO_P(IBCBusFromSPCParityErr, 1),
1129 HWE_AUTO_P(IBCBusToSPCParityErr, 1),
1130 HWE_AUTO_P(IBCBusFromSPCParityErr, 0),
1131 HWE_AUTO(statusValidNoEop),
1132 HWE_AUTO(LATriggered),
1133 { .mask = 0, .sz = 0 }
1134 };
1135
1136 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
1137 .msg = #fldname, .sz = sizeof(#fldname) }
1138 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
1139 .msg = #fldname, .sz = sizeof(#fldname) }
1140 static const struct qib_hwerror_msgs qib_7322error_msgs[] = {
1141 E_AUTO(RcvEgrFullErr),
1142 E_AUTO(RcvHdrFullErr),
1143 E_AUTO(ResetNegated),
1144 E_AUTO(HardwareErr),
1145 E_AUTO(InvalidAddrErr),
1146 E_AUTO(SDmaVL15Err),
1147 E_AUTO(SBufVL15MisUseErr),
1148 E_AUTO(InvalidEEPCmd),
1149 E_AUTO(RcvContextShareErr),
1150 E_AUTO(SendVLMismatchErr),
1151 E_AUTO(SendArmLaunchErr),
1152 E_AUTO(SendSpecialTriggerErr),
1153 E_AUTO(SDmaWrongPortErr),
1154 E_AUTO(SDmaBufMaskDuplicateErr),
1155 { .mask = 0, .sz = 0 }
1156 };
1157
1158 static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = {
1159 E_P_AUTO(IBStatusChanged),
1160 E_P_AUTO(SHeadersErr),
1161 E_P_AUTO(VL15BufMisuseErr),
1162 /*
1163 * SDmaHaltErr is not really an error, make it clearer;
1164 */
1165 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted",
1166 .sz = 11},
1167 E_P_AUTO(SDmaDescAddrMisalignErr),
1168 E_P_AUTO(SDmaUnexpDataErr),
1169 E_P_AUTO(SDmaMissingDwErr),
1170 E_P_AUTO(SDmaDwEnErr),
1171 E_P_AUTO(SDmaRpyTagErr),
1172 E_P_AUTO(SDma1stDescErr),
1173 E_P_AUTO(SDmaBaseErr),
1174 E_P_AUTO(SDmaTailOutOfBoundErr),
1175 E_P_AUTO(SDmaOutOfBoundErr),
1176 E_P_AUTO(SDmaGenMismatchErr),
1177 E_P_AUTO(SendBufMisuseErr),
1178 E_P_AUTO(SendUnsupportedVLErr),
1179 E_P_AUTO(SendUnexpectedPktNumErr),
1180 E_P_AUTO(SendDroppedDataPktErr),
1181 E_P_AUTO(SendDroppedSmpPktErr),
1182 E_P_AUTO(SendPktLenErr),
1183 E_P_AUTO(SendUnderRunErr),
1184 E_P_AUTO(SendMaxPktLenErr),
1185 E_P_AUTO(SendMinPktLenErr),
1186 E_P_AUTO(RcvIBLostLinkErr),
1187 E_P_AUTO(RcvHdrErr),
1188 E_P_AUTO(RcvHdrLenErr),
1189 E_P_AUTO(RcvBadTidErr),
1190 E_P_AUTO(RcvBadVersionErr),
1191 E_P_AUTO(RcvIBFlowErr),
1192 E_P_AUTO(RcvEBPErr),
1193 E_P_AUTO(RcvUnsupportedVLErr),
1194 E_P_AUTO(RcvUnexpectedCharErr),
1195 E_P_AUTO(RcvShortPktLenErr),
1196 E_P_AUTO(RcvLongPktLenErr),
1197 E_P_AUTO(RcvMaxPktLenErr),
1198 E_P_AUTO(RcvMinPktLenErr),
1199 E_P_AUTO(RcvICRCErr),
1200 E_P_AUTO(RcvVCRCErr),
1201 E_P_AUTO(RcvFormatErr),
1202 { .mask = 0, .sz = 0 }
1203 };
1204
1205 /*
1206 * Below generates "auto-message" for interrupts not specific to any port or
1207 * context
1208 */
1209 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
1210 .msg = #fldname, .sz = sizeof(#fldname) }
1211 /* Below generates "auto-message" for interrupts specific to a port */
1212 #define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\
1213 SYM_LSB(IntMask, fldname##Mask##_0), \
1214 SYM_LSB(IntMask, fldname##Mask##_1)), \
1215 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") }
1216 /* For some reason, the SerDesTrimDone bits are reversed */
1217 #define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\
1218 SYM_LSB(IntMask, fldname##Mask##_1), \
1219 SYM_LSB(IntMask, fldname##Mask##_0)), \
1220 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") }
1221 /*
1222 * Below generates "auto-message" for interrupts specific to a context,
1223 * with ctxt-number appended
1224 */
1225 #define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\
1226 SYM_LSB(IntMask, fldname##0IntMask), \
1227 SYM_LSB(IntMask, fldname##17IntMask)), \
1228 .msg = #fldname "_C", .sz = sizeof(#fldname "_C") }
1229
1230 static const struct qib_hwerror_msgs qib_7322_intr_msgs[] = {
1231 INTR_AUTO_P(SDmaInt),
1232 INTR_AUTO_P(SDmaProgressInt),
1233 INTR_AUTO_P(SDmaIdleInt),
1234 INTR_AUTO_P(SDmaCleanupDone),
1235 INTR_AUTO_C(RcvUrg),
1236 INTR_AUTO_P(ErrInt),
1237 INTR_AUTO(ErrInt), /* non-port-specific errs */
1238 INTR_AUTO(AssertGPIOInt),
1239 INTR_AUTO_P(SendDoneInt),
1240 INTR_AUTO(SendBufAvailInt),
1241 INTR_AUTO_C(RcvAvail),
1242 { .mask = 0, .sz = 0 }
1243 };
1244
1245 #define TXSYMPTOM_AUTO_P(fldname) \
1246 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), \
1247 .msg = #fldname, .sz = sizeof(#fldname) }
1248 static const struct qib_hwerror_msgs hdrchk_msgs[] = {
1249 TXSYMPTOM_AUTO_P(NonKeyPacket),
1250 TXSYMPTOM_AUTO_P(GRHFail),
1251 TXSYMPTOM_AUTO_P(PkeyFail),
1252 TXSYMPTOM_AUTO_P(QPFail),
1253 TXSYMPTOM_AUTO_P(SLIDFail),
1254 TXSYMPTOM_AUTO_P(RawIPV6),
1255 TXSYMPTOM_AUTO_P(PacketTooSmall),
1256 { .mask = 0, .sz = 0 }
1257 };
1258
1259 #define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
1260
1261 /*
1262 * Called when we might have an error that is specific to a particular
1263 * PIO buffer, and may need to cancel that buffer, so it can be re-used,
1264 * because we don't need to force the update of pioavail
1265 */
1266 static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd)
1267 {
1268 struct qib_devdata *dd = ppd->dd;
1269 u32 i;
1270 int any;
1271 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
1272 u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG;
1273 unsigned long sbuf[4];
1274
1275 /*
1276 * It's possible that sendbuffererror could have bits set; might
1277 * have already done this as a result of hardware error handling.
1278 */
1279 any = 0;
1280 for (i = 0; i < regcnt; ++i) {
1281 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i);
1282 if (sbuf[i]) {
1283 any = 1;
1284 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]);
1285 }
1286 }
1287
1288 if (any)
1289 qib_disarm_piobufs_set(dd, sbuf, piobcnt);
1290 }
1291
1292 /* No txe_recover yet, if ever */
1293
1294 /* No decode__errors yet */
1295 static void err_decode(char *msg, size_t len, u64 errs,
1296 const struct qib_hwerror_msgs *msp)
1297 {
1298 u64 these, lmask;
1299 int took, multi, n = 0;
1300
1301 while (errs && msp && msp->mask) {
1302 multi = (msp->mask & (msp->mask - 1));
1303 while (errs & msp->mask) {
1304 these = (errs & msp->mask);
1305 lmask = (these & (these - 1)) ^ these;
1306 if (len) {
1307 if (n++) {
1308 /* separate the strings */
1309 *msg++ = ',';
1310 len--;
1311 }
1312 BUG_ON(!msp->sz);
1313 /* msp->sz counts the nul */
1314 took = min_t(size_t, msp->sz - (size_t)1, len);
1315 memcpy(msg, msp->msg, took);
1316 len -= took;
1317 msg += took;
1318 if (len)
1319 *msg = '\0';
1320 }
1321 errs &= ~lmask;
1322 if (len && multi) {
1323 /* More than one bit this mask */
1324 int idx = -1;
1325
1326 while (lmask & msp->mask) {
1327 ++idx;
1328 lmask >>= 1;
1329 }
1330 took = scnprintf(msg, len, "_%d", idx);
1331 len -= took;
1332 msg += took;
1333 }
1334 }
1335 ++msp;
1336 }
1337 /* If some bits are left, show in hex. */
1338 if (len && errs)
1339 snprintf(msg, len, "%sMORE:%llX", n ? "," : "",
1340 (unsigned long long) errs);
1341 }
1342
1343 /* only called if r1 set */
1344 static void flush_fifo(struct qib_pportdata *ppd)
1345 {
1346 struct qib_devdata *dd = ppd->dd;
1347 u32 __iomem *piobuf;
1348 u32 bufn;
1349 u32 *hdr;
1350 u64 pbc;
1351 const unsigned hdrwords = 7;
1352 static struct qib_ib_header ibhdr = {
1353 .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH),
1354 .lrh[1] = IB_LID_PERMISSIVE,
1355 .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC),
1356 .lrh[3] = IB_LID_PERMISSIVE,
1357 .u.oth.bth[0] = cpu_to_be32(
1358 (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY),
1359 .u.oth.bth[1] = cpu_to_be32(0),
1360 .u.oth.bth[2] = cpu_to_be32(0),
1361 .u.oth.u.ud.deth[0] = cpu_to_be32(0),
1362 .u.oth.u.ud.deth[1] = cpu_to_be32(0),
1363 };
1364
1365 /*
1366 * Send a dummy VL15 packet to flush the launch FIFO.
1367 * This will not actually be sent since the TxeBypassIbc bit is set.
1368 */
1369 pbc = PBC_7322_VL15_SEND |
1370 (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) |
1371 (hdrwords + SIZE_OF_CRC);
1372 piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn);
1373 if (!piobuf)
1374 return;
1375 writeq(pbc, piobuf);
1376 hdr = (u32 *) &ibhdr;
1377 if (dd->flags & QIB_PIO_FLUSH_WC) {
1378 qib_flush_wc();
1379 qib_pio_copy(piobuf + 2, hdr, hdrwords - 1);
1380 qib_flush_wc();
1381 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1);
1382 qib_flush_wc();
1383 } else
1384 qib_pio_copy(piobuf + 2, hdr, hdrwords);
1385 qib_sendbuf_done(dd, bufn);
1386 }
1387
1388 /*
1389 * This is called with interrupts disabled and sdma_lock held.
1390 */
1391 static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
1392 {
1393 struct qib_devdata *dd = ppd->dd;
1394 u64 set_sendctrl = 0;
1395 u64 clr_sendctrl = 0;
1396
1397 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
1398 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1399 else
1400 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1401
1402 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
1403 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1404 else
1405 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1406
1407 if (op & QIB_SDMA_SENDCTRL_OP_HALT)
1408 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1409 else
1410 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1411
1412 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN)
1413 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1414 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1415 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1416 else
1417 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1418 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1419 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1420
1421 spin_lock(&dd->sendctrl_lock);
1422
1423 /* If we are draining everything, block sends first */
1424 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1425 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
1426 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1427 qib_write_kreg(dd, kr_scratch, 0);
1428 }
1429
1430 ppd->p_sendctrl |= set_sendctrl;
1431 ppd->p_sendctrl &= ~clr_sendctrl;
1432
1433 if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP)
1434 qib_write_kreg_port(ppd, krp_sendctrl,
1435 ppd->p_sendctrl |
1436 SYM_MASK(SendCtrl_0, SDmaCleanup));
1437 else
1438 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1439 qib_write_kreg(dd, kr_scratch, 0);
1440
1441 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1442 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
1443 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1444 qib_write_kreg(dd, kr_scratch, 0);
1445 }
1446
1447 spin_unlock(&dd->sendctrl_lock);
1448
1449 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1)
1450 flush_fifo(ppd);
1451 }
1452
1453 static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd)
1454 {
1455 __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned);
1456 }
1457
1458 static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd)
1459 {
1460 /*
1461 * Set SendDmaLenGen and clear and set
1462 * the MSB of the generation count to enable generation checking
1463 * and load the internal generation counter.
1464 */
1465 qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt);
1466 qib_write_kreg_port(ppd, krp_senddmalengen,
1467 ppd->sdma_descq_cnt |
1468 (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB));
1469 }
1470
1471 /*
1472 * Must be called with sdma_lock held, or before init finished.
1473 */
1474 static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail)
1475 {
1476 /* Commit writes to memory and advance the tail on the chip */
1477 wmb();
1478 ppd->sdma_descq_tail = tail;
1479 qib_write_kreg_port(ppd, krp_senddmatail, tail);
1480 }
1481
1482 /*
1483 * This is called with interrupts disabled and sdma_lock held.
1484 */
1485 static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd)
1486 {
1487 /*
1488 * Drain all FIFOs.
1489 * The hardware doesn't require this but we do it so that verbs
1490 * and user applications don't wait for link active to send stale
1491 * data.
1492 */
1493 sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH);
1494
1495 qib_sdma_7322_setlengen(ppd);
1496 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
1497 ppd->sdma_head_dma[0] = 0;
1498 qib_7322_sdma_sendctrl(ppd,
1499 ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP);
1500 }
1501
1502 #define DISABLES_SDMA ( \
1503 QIB_E_P_SDMAHALT | \
1504 QIB_E_P_SDMADESCADDRMISALIGN | \
1505 QIB_E_P_SDMAMISSINGDW | \
1506 QIB_E_P_SDMADWEN | \
1507 QIB_E_P_SDMARPYTAG | \
1508 QIB_E_P_SDMA1STDESC | \
1509 QIB_E_P_SDMABASE | \
1510 QIB_E_P_SDMATAILOUTOFBOUND | \
1511 QIB_E_P_SDMAOUTOFBOUND | \
1512 QIB_E_P_SDMAGENMISMATCH)
1513
1514 static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs)
1515 {
1516 unsigned long flags;
1517 struct qib_devdata *dd = ppd->dd;
1518
1519 errs &= QIB_E_P_SDMAERRS;
1520
1521 if (errs & QIB_E_P_SDMAUNEXPDATA)
1522 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit,
1523 ppd->port);
1524
1525 spin_lock_irqsave(&ppd->sdma_lock, flags);
1526
1527 switch (ppd->sdma_state.current_state) {
1528 case qib_sdma_state_s00_hw_down:
1529 break;
1530
1531 case qib_sdma_state_s10_hw_start_up_wait:
1532 if (errs & QIB_E_P_SDMAHALT)
1533 __qib_sdma_process_event(ppd,
1534 qib_sdma_event_e20_hw_started);
1535 break;
1536
1537 case qib_sdma_state_s20_idle:
1538 break;
1539
1540 case qib_sdma_state_s30_sw_clean_up_wait:
1541 break;
1542
1543 case qib_sdma_state_s40_hw_clean_up_wait:
1544 if (errs & QIB_E_P_SDMAHALT)
1545 __qib_sdma_process_event(ppd,
1546 qib_sdma_event_e50_hw_cleaned);
1547 break;
1548
1549 case qib_sdma_state_s50_hw_halt_wait:
1550 if (errs & QIB_E_P_SDMAHALT)
1551 __qib_sdma_process_event(ppd,
1552 qib_sdma_event_e60_hw_halted);
1553 break;
1554
1555 case qib_sdma_state_s99_running:
1556 __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted);
1557 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
1558 break;
1559 }
1560
1561 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
1562 }
1563
1564 /*
1565 * handle per-device errors (not per-port errors)
1566 */
1567 static noinline void handle_7322_errors(struct qib_devdata *dd)
1568 {
1569 char *msg;
1570 u64 iserr = 0;
1571 u64 errs;
1572 u64 mask;
1573 int log_idx;
1574
1575 qib_stats.sps_errints++;
1576 errs = qib_read_kreg64(dd, kr_errstatus);
1577 if (!errs) {
1578 qib_devinfo(dd->pcidev, "device error interrupt, "
1579 "but no error bits set!\n");
1580 goto done;
1581 }
1582
1583 /* don't report errors that are masked */
1584 errs &= dd->cspec->errormask;
1585 msg = dd->cspec->emsgbuf;
1586
1587 /* do these first, they are most important */
1588 if (errs & QIB_E_HARDWARE) {
1589 *msg = '\0';
1590 qib_7322_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1591 } else
1592 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1593 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1594 qib_inc_eeprom_err(dd, log_idx, 1);
1595
1596 if (errs & QIB_E_SPKTERRS) {
1597 qib_disarm_7322_senderrbufs(dd->pport);
1598 qib_stats.sps_txerrs++;
1599 } else if (errs & QIB_E_INVALIDADDR)
1600 qib_stats.sps_txerrs++;
1601 else if (errs & QIB_E_ARMLAUNCH) {
1602 qib_stats.sps_txerrs++;
1603 qib_disarm_7322_senderrbufs(dd->pport);
1604 }
1605 qib_write_kreg(dd, kr_errclear, errs);
1606
1607 /*
1608 * The ones we mask off are handled specially below
1609 * or above. Also mask SDMADISABLED by default as it
1610 * is too chatty.
1611 */
1612 mask = QIB_E_HARDWARE;
1613 *msg = '\0';
1614
1615 err_decode(msg, sizeof dd->cspec->emsgbuf, errs & ~mask,
1616 qib_7322error_msgs);
1617
1618 /*
1619 * Getting reset is a tragedy for all ports. Mark the device
1620 * _and_ the ports as "offline" in way meaningful to each.
1621 */
1622 if (errs & QIB_E_RESET) {
1623 int pidx;
1624
1625 qib_dev_err(dd, "Got reset, requires re-init "
1626 "(unload and reload driver)\n");
1627 dd->flags &= ~QIB_INITTED; /* needs re-init */
1628 /* mark as having had error */
1629 *dd->devstatusp |= QIB_STATUS_HWERROR;
1630 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1631 if (dd->pport[pidx].link_speed_supported)
1632 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF;
1633 }
1634
1635 if (*msg && iserr)
1636 qib_dev_err(dd, "%s error\n", msg);
1637
1638 /*
1639 * If there were hdrq or egrfull errors, wake up any processes
1640 * waiting in poll. We used to try to check which contexts had
1641 * the overflow, but given the cost of that and the chip reads
1642 * to support it, it's better to just wake everybody up if we
1643 * get an overflow; waiters can poll again if it's not them.
1644 */
1645 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1646 qib_handle_urcv(dd, ~0U);
1647 if (errs & ERR_MASK(RcvEgrFullErr))
1648 qib_stats.sps_buffull++;
1649 else
1650 qib_stats.sps_hdrfull++;
1651 }
1652
1653 done:
1654 return;
1655 }
1656
1657 static void qib_error_tasklet(unsigned long data)
1658 {
1659 struct qib_devdata *dd = (struct qib_devdata *)data;
1660
1661 handle_7322_errors(dd);
1662 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1663 }
1664
1665 static void reenable_chase(unsigned long opaque)
1666 {
1667 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
1668
1669 ppd->cpspec->chase_timer.expires = 0;
1670 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1671 QLOGIC_IB_IBCC_LINKINITCMD_POLL);
1672 }
1673
1674 static void disable_chase(struct qib_pportdata *ppd, u64 tnow, u8 ibclt)
1675 {
1676 ppd->cpspec->chase_end = 0;
1677
1678 if (!qib_chase)
1679 return;
1680
1681 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1682 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1683 ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME;
1684 add_timer(&ppd->cpspec->chase_timer);
1685 }
1686
1687 static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
1688 {
1689 u8 ibclt;
1690 u64 tnow;
1691
1692 ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState);
1693
1694 /*
1695 * Detect and handle the state chase issue, where we can
1696 * get stuck if we are unlucky on timing on both sides of
1697 * the link. If we are, we disable, set a timer, and
1698 * then re-enable.
1699 */
1700 switch (ibclt) {
1701 case IB_7322_LT_STATE_CFGRCVFCFG:
1702 case IB_7322_LT_STATE_CFGWAITRMT:
1703 case IB_7322_LT_STATE_TXREVLANES:
1704 case IB_7322_LT_STATE_CFGENH:
1705 tnow = get_jiffies_64();
1706 if (ppd->cpspec->chase_end &&
1707 time_after64(tnow, ppd->cpspec->chase_end))
1708 disable_chase(ppd, tnow, ibclt);
1709 else if (!ppd->cpspec->chase_end)
1710 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
1711 break;
1712 default:
1713 ppd->cpspec->chase_end = 0;
1714 break;
1715 }
1716
1717 if (((ibclt >= IB_7322_LT_STATE_CFGTEST &&
1718 ibclt <= IB_7322_LT_STATE_CFGWAITENH) ||
1719 ibclt == IB_7322_LT_STATE_LINKUP) &&
1720 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) {
1721 force_h1(ppd);
1722 ppd->cpspec->qdr_reforce = 1;
1723 if (!ppd->dd->cspec->r1)
1724 serdes_7322_los_enable(ppd, 0);
1725 } else if (ppd->cpspec->qdr_reforce &&
1726 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) &&
1727 (ibclt == IB_7322_LT_STATE_CFGENH ||
1728 ibclt == IB_7322_LT_STATE_CFGIDLE ||
1729 ibclt == IB_7322_LT_STATE_LINKUP))
1730 force_h1(ppd);
1731
1732 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) &&
1733 ppd->link_speed_enabled == QIB_IB_QDR &&
1734 (ibclt == IB_7322_LT_STATE_CFGTEST ||
1735 ibclt == IB_7322_LT_STATE_CFGENH ||
1736 (ibclt >= IB_7322_LT_STATE_POLLACTIVE &&
1737 ibclt <= IB_7322_LT_STATE_SLEEPQUIET)))
1738 adj_tx_serdes(ppd);
1739
1740 if (ibclt != IB_7322_LT_STATE_LINKUP) {
1741 u8 ltstate = qib_7322_phys_portstate(ibcst);
1742 u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0,
1743 LinkTrainingState);
1744 if (!ppd->dd->cspec->r1 &&
1745 pibclt == IB_7322_LT_STATE_LINKUP &&
1746 ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1747 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1748 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1749 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1750 /* If the link went down (but no into recovery,
1751 * turn LOS back on */
1752 serdes_7322_los_enable(ppd, 1);
1753 if (!ppd->cpspec->qdr_dfe_on &&
1754 ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
1755 ppd->cpspec->qdr_dfe_on = 1;
1756 ppd->cpspec->qdr_dfe_time = 0;
1757 /* On link down, reenable QDR adaptation */
1758 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
1759 ppd->dd->cspec->r1 ?
1760 QDR_STATIC_ADAPT_DOWN_R1 :
1761 QDR_STATIC_ADAPT_DOWN);
1762 printk(KERN_INFO QIB_DRV_NAME
1763 " IB%u:%u re-enabled QDR adaptation "
1764 "ibclt %x\n", ppd->dd->unit, ppd->port, ibclt);
1765 }
1766 }
1767 }
1768
1769 static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32);
1770
1771 /*
1772 * This is per-pport error handling.
1773 * will likely get it's own MSIx interrupt (one for each port,
1774 * although just a single handler).
1775 */
1776 static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
1777 {
1778 char *msg;
1779 u64 ignore_this_time = 0, iserr = 0, errs, fmask;
1780 struct qib_devdata *dd = ppd->dd;
1781
1782 /* do this as soon as possible */
1783 fmask = qib_read_kreg64(dd, kr_act_fmask);
1784 if (!fmask)
1785 check_7322_rxe_status(ppd);
1786
1787 errs = qib_read_kreg_port(ppd, krp_errstatus);
1788 if (!errs)
1789 qib_devinfo(dd->pcidev,
1790 "Port%d error interrupt, but no error bits set!\n",
1791 ppd->port);
1792 if (!fmask)
1793 errs &= ~QIB_E_P_IBSTATUSCHANGED;
1794 if (!errs)
1795 goto done;
1796
1797 msg = ppd->cpspec->epmsgbuf;
1798 *msg = '\0';
1799
1800 if (errs & ~QIB_E_P_BITSEXTANT) {
1801 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1802 errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs);
1803 if (!*msg)
1804 snprintf(msg, sizeof ppd->cpspec->epmsgbuf,
1805 "no others");
1806 qib_dev_porterr(dd, ppd->port, "error interrupt with unknown"
1807 " errors 0x%016Lx set (and %s)\n",
1808 (errs & ~QIB_E_P_BITSEXTANT), msg);
1809 *msg = '\0';
1810 }
1811
1812 if (errs & QIB_E_P_SHDR) {
1813 u64 symptom;
1814
1815 /* determine cause, then write to clear */
1816 symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom);
1817 qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0);
1818 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, symptom,
1819 hdrchk_msgs);
1820 *msg = '\0';
1821 /* senderrbuf cleared in SPKTERRS below */
1822 }
1823
1824 if (errs & QIB_E_P_SPKTERRS) {
1825 if ((errs & QIB_E_P_LINK_PKTERRS) &&
1826 !(ppd->lflags & QIBL_LINKACTIVE)) {
1827 /*
1828 * This can happen when trying to bring the link
1829 * up, but the IB link changes state at the "wrong"
1830 * time. The IB logic then complains that the packet
1831 * isn't valid. We don't want to confuse people, so
1832 * we just don't print them, except at debug
1833 */
1834 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1835 (errs & QIB_E_P_LINK_PKTERRS),
1836 qib_7322p_error_msgs);
1837 *msg = '\0';
1838 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1839 }
1840 qib_disarm_7322_senderrbufs(ppd);
1841 } else if ((errs & QIB_E_P_LINK_PKTERRS) &&
1842 !(ppd->lflags & QIBL_LINKACTIVE)) {
1843 /*
1844 * This can happen when SMA is trying to bring the link
1845 * up, but the IB link changes state at the "wrong" time.
1846 * The IB logic then complains that the packet isn't
1847 * valid. We don't want to confuse people, so we just
1848 * don't print them, except at debug
1849 */
1850 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, errs,
1851 qib_7322p_error_msgs);
1852 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1853 *msg = '\0';
1854 }
1855
1856 qib_write_kreg_port(ppd, krp_errclear, errs);
1857
1858 errs &= ~ignore_this_time;
1859 if (!errs)
1860 goto done;
1861
1862 if (errs & QIB_E_P_RPKTERRS)
1863 qib_stats.sps_rcverrs++;
1864 if (errs & QIB_E_P_SPKTERRS)
1865 qib_stats.sps_txerrs++;
1866
1867 iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS);
1868
1869 if (errs & QIB_E_P_SDMAERRS)
1870 sdma_7322_p_errors(ppd, errs);
1871
1872 if (errs & QIB_E_P_IBSTATUSCHANGED) {
1873 u64 ibcs;
1874 u8 ltstate;
1875
1876 ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a);
1877 ltstate = qib_7322_phys_portstate(ibcs);
1878
1879 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
1880 handle_serdes_issues(ppd, ibcs);
1881 if (!(ppd->cpspec->ibcctrl_a &
1882 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) {
1883 /*
1884 * We got our interrupt, so init code should be
1885 * happy and not try alternatives. Now squelch
1886 * other "chatter" from link-negotiation (pre Init)
1887 */
1888 ppd->cpspec->ibcctrl_a |=
1889 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
1890 qib_write_kreg_port(ppd, krp_ibcctrl_a,
1891 ppd->cpspec->ibcctrl_a);
1892 }
1893
1894 /* Update our picture of width and speed from chip */
1895 ppd->link_width_active =
1896 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ?
1897 IB_WIDTH_4X : IB_WIDTH_1X;
1898 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0,
1899 LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs &
1900 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ?
1901 QIB_IB_DDR : QIB_IB_SDR;
1902
1903 if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate !=
1904 IB_PHYSPORTSTATE_DISABLED)
1905 qib_set_ib_7322_lstate(ppd, 0,
1906 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1907 else
1908 /*
1909 * Since going into a recovery state causes the link
1910 * state to go down and since recovery is transitory,
1911 * it is better if we "miss" ever seeing the link
1912 * training state go into recovery (i.e., ignore this
1913 * transition for link state special handling purposes)
1914 * without updating lastibcstat.
1915 */
1916 if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1917 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1918 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1919 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1920 qib_handle_e_ibstatuschanged(ppd, ibcs);
1921 }
1922 if (*msg && iserr)
1923 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1924
1925 if (ppd->state_wanted & ppd->lflags)
1926 wake_up_interruptible(&ppd->state_wait);
1927 done:
1928 return;
1929 }
1930
1931 /* enable/disable chip from delivering interrupts */
1932 static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable)
1933 {
1934 if (enable) {
1935 if (dd->flags & QIB_BADINTR)
1936 return;
1937 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask);
1938 /* cause any pending enabled interrupts to be re-delivered */
1939 qib_write_kreg(dd, kr_intclear, 0ULL);
1940 if (dd->cspec->num_msix_entries) {
1941 /* and same for MSIx */
1942 u64 val = qib_read_kreg64(dd, kr_intgranted);
1943 if (val)
1944 qib_write_kreg(dd, kr_intgranted, val);
1945 }
1946 } else
1947 qib_write_kreg(dd, kr_intmask, 0ULL);
1948 }
1949
1950 /*
1951 * Try to cleanup as much as possible for anything that might have gone
1952 * wrong while in freeze mode, such as pio buffers being written by user
1953 * processes (causing armlaunch), send errors due to going into freeze mode,
1954 * etc., and try to avoid causing extra interrupts while doing so.
1955 * Forcibly update the in-memory pioavail register copies after cleanup
1956 * because the chip won't do it while in freeze mode (the register values
1957 * themselves are kept correct).
1958 * Make sure that we don't lose any important interrupts by using the chip
1959 * feature that says that writing 0 to a bit in *clear that is set in
1960 * *status will cause an interrupt to be generated again (if allowed by
1961 * the *mask value).
1962 * This is in chip-specific code because of all of the register accesses,
1963 * even though the details are similar on most chips.
1964 */
1965 static void qib_7322_clear_freeze(struct qib_devdata *dd)
1966 {
1967 int pidx;
1968
1969 /* disable error interrupts, to avoid confusion */
1970 qib_write_kreg(dd, kr_errmask, 0ULL);
1971
1972 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1973 if (dd->pport[pidx].link_speed_supported)
1974 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
1975 0ULL);
1976
1977 /* also disable interrupts; errormask is sometimes overwriten */
1978 qib_7322_set_intr_state(dd, 0);
1979
1980 /* clear the freeze, and be sure chip saw it */
1981 qib_write_kreg(dd, kr_control, dd->control);
1982 qib_read_kreg32(dd, kr_scratch);
1983
1984 /*
1985 * Force new interrupt if any hwerr, error or interrupt bits are
1986 * still set, and clear "safe" send packet errors related to freeze
1987 * and cancelling sends. Re-enable error interrupts before possible
1988 * force of re-interrupt on pending interrupts.
1989 */
1990 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
1991 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
1992 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1993 /* We need to purge per-port errs and reset mask, too */
1994 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1995 if (!dd->pport[pidx].link_speed_supported)
1996 continue;
1997 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull);
1998 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull);
1999 }
2000 qib_7322_set_intr_state(dd, 1);
2001 }
2002
2003 /* no error handling to speak of */
2004 /**
2005 * qib_7322_handle_hwerrors - display hardware errors.
2006 * @dd: the qlogic_ib device
2007 * @msg: the output buffer
2008 * @msgl: the size of the output buffer
2009 *
2010 * Use same msg buffer as regular errors to avoid excessive stack
2011 * use. Most hardware errors are catastrophic, but for right now,
2012 * we'll print them and continue. We reuse the same message buffer as
2013 * qib_handle_errors() to avoid excessive stack usage.
2014 */
2015 static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg,
2016 size_t msgl)
2017 {
2018 u64 hwerrs;
2019 u32 ctrl;
2020 int isfatal = 0;
2021
2022 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2023 if (!hwerrs)
2024 goto bail;
2025 if (hwerrs == ~0ULL) {
2026 qib_dev_err(dd, "Read of hardware error status failed "
2027 "(all bits set); ignoring\n");
2028 goto bail;
2029 }
2030 qib_stats.sps_hwerrs++;
2031
2032 /* Always clear the error status register, except BIST fail */
2033 qib_write_kreg(dd, kr_hwerrclear, hwerrs &
2034 ~HWE_MASK(PowerOnBISTFailed));
2035
2036 hwerrs &= dd->cspec->hwerrmask;
2037
2038 /* no EEPROM logging, yet */
2039
2040 if (hwerrs)
2041 qib_devinfo(dd->pcidev, "Hardware error: hwerr=0x%llx "
2042 "(cleared)\n", (unsigned long long) hwerrs);
2043
2044 ctrl = qib_read_kreg32(dd, kr_control);
2045 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) {
2046 /*
2047 * No recovery yet...
2048 */
2049 if ((hwerrs & ~HWE_MASK(LATriggered)) ||
2050 dd->cspec->stay_in_freeze) {
2051 /*
2052 * If any set that we aren't ignoring only make the
2053 * complaint once, in case it's stuck or recurring,
2054 * and we get here multiple times
2055 * Force link down, so switch knows, and
2056 * LEDs are turned off.
2057 */
2058 if (dd->flags & QIB_INITTED)
2059 isfatal = 1;
2060 } else
2061 qib_7322_clear_freeze(dd);
2062 }
2063
2064 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
2065 isfatal = 1;
2066 strlcpy(msg, "[Memory BIST test failed, "
2067 "InfiniPath hardware unusable]", msgl);
2068 /* ignore from now on, so disable until driver reloaded */
2069 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
2070 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2071 }
2072
2073 err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs);
2074
2075 /* Ignore esoteric PLL failures et al. */
2076
2077 qib_dev_err(dd, "%s hardware error\n", msg);
2078
2079 if (isfatal && !dd->diag_client) {
2080 qib_dev_err(dd, "Fatal Hardware Error, no longer"
2081 " usable, SN %.16s\n", dd->serial);
2082 /*
2083 * for /sys status file and user programs to print; if no
2084 * trailing brace is copied, we'll know it was truncated.
2085 */
2086 if (dd->freezemsg)
2087 snprintf(dd->freezemsg, dd->freezelen,
2088 "{%s}", msg);
2089 qib_disable_after_error(dd);
2090 }
2091 bail:;
2092 }
2093
2094 /**
2095 * qib_7322_init_hwerrors - enable hardware errors
2096 * @dd: the qlogic_ib device
2097 *
2098 * now that we have finished initializing everything that might reasonably
2099 * cause a hardware error, and cleared those errors bits as they occur,
2100 * we can enable hardware errors in the mask (potentially enabling
2101 * freeze mode), and enable hardware errors as errors (along with
2102 * everything else) in errormask
2103 */
2104 static void qib_7322_init_hwerrors(struct qib_devdata *dd)
2105 {
2106 int pidx;
2107 u64 extsval;
2108
2109 extsval = qib_read_kreg64(dd, kr_extstatus);
2110 if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED |
2111 QIB_EXTS_MEMBIST_ENDTEST)))
2112 qib_dev_err(dd, "MemBIST did not complete!\n");
2113
2114 /* never clear BIST failure, so reported on each driver load */
2115 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
2116 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2117
2118 /* clear all */
2119 qib_write_kreg(dd, kr_errclear, ~0ULL);
2120 /* enable errors that are masked, at least this first time. */
2121 qib_write_kreg(dd, kr_errmask, ~0ULL);
2122 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
2123 for (pidx = 0; pidx < dd->num_pports; ++pidx)
2124 if (dd->pport[pidx].link_speed_supported)
2125 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
2126 ~0ULL);
2127 }
2128
2129 /*
2130 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
2131 * on chips that are count-based, rather than trigger-based. There is no
2132 * reference counting, but that's also fine, given the intended use.
2133 * Only chip-specific because it's all register accesses
2134 */
2135 static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable)
2136 {
2137 if (enable) {
2138 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH);
2139 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH;
2140 } else
2141 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH;
2142 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2143 }
2144
2145 /*
2146 * Formerly took parameter <which> in pre-shifted,
2147 * pre-merged form with LinkCmd and LinkInitCmd
2148 * together, and assuming the zero was NOP.
2149 */
2150 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
2151 u16 linitcmd)
2152 {
2153 u64 mod_wd;
2154 struct qib_devdata *dd = ppd->dd;
2155 unsigned long flags;
2156
2157 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
2158 /*
2159 * If we are told to disable, note that so link-recovery
2160 * code does not attempt to bring us back up.
2161 * Also reset everything that we can, so we start
2162 * completely clean when re-enabled (before we
2163 * actually issue the disable to the IBC)
2164 */
2165 qib_7322_mini_pcs_reset(ppd);
2166 spin_lock_irqsave(&ppd->lflags_lock, flags);
2167 ppd->lflags |= QIBL_IB_LINK_DISABLED;
2168 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2169 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
2170 /*
2171 * Any other linkinitcmd will lead to LINKDOWN and then
2172 * to INIT (if all is well), so clear flag to let
2173 * link-recovery code attempt to bring us back up.
2174 */
2175 spin_lock_irqsave(&ppd->lflags_lock, flags);
2176 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
2177 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2178 /*
2179 * Clear status change interrupt reduction so the
2180 * new state is seen.
2181 */
2182 ppd->cpspec->ibcctrl_a &=
2183 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
2184 }
2185
2186 mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) |
2187 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2188
2189 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a |
2190 mod_wd);
2191 /* write to chip to prevent back-to-back writes of ibc reg */
2192 qib_write_kreg(dd, kr_scratch, 0);
2193
2194 }
2195
2196 /*
2197 * The total RCV buffer memory is 64KB, used for both ports, and is
2198 * in units of 64 bytes (same as IB flow control credit unit).
2199 * The consumedVL unit in the same registers are in 32 byte units!
2200 * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks,
2201 * and we can therefore allocate just 9 IB credits for 2 VL15 packets
2202 * in krp_rxcreditvl15, rather than 10.
2203 */
2204 #define RCV_BUF_UNITSZ 64
2205 #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports))
2206
2207 static void set_vls(struct qib_pportdata *ppd)
2208 {
2209 int i, numvls, totcred, cred_vl, vl0extra;
2210 struct qib_devdata *dd = ppd->dd;
2211 u64 val;
2212
2213 numvls = qib_num_vls(ppd->vls_operational);
2214
2215 /*
2216 * Set up per-VL credits. Below is kluge based on these assumptions:
2217 * 1) port is disabled at the time early_init is called.
2218 * 2) give VL15 17 credits, for two max-plausible packets.
2219 * 3) Give VL0-N the rest, with any rounding excess used for VL0
2220 */
2221 /* 2 VL15 packets @ 288 bytes each (including IB headers) */
2222 totcred = NUM_RCV_BUF_UNITS(dd);
2223 cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ;
2224 totcred -= cred_vl;
2225 qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl);
2226 cred_vl = totcred / numvls;
2227 vl0extra = totcred - cred_vl * numvls;
2228 qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra);
2229 for (i = 1; i < numvls; i++)
2230 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl);
2231 for (; i < 8; i++) /* no buffer space for other VLs */
2232 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
2233
2234 /* Notify IBC that credits need to be recalculated */
2235 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
2236 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2237 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2238 qib_write_kreg(dd, kr_scratch, 0ULL);
2239 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2240 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2241
2242 for (i = 0; i < numvls; i++)
2243 val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i);
2244 val = qib_read_kreg_port(ppd, krp_rxcreditvl15);
2245
2246 /* Change the number of operational VLs */
2247 ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a &
2248 ~SYM_MASK(IBCCtrlA_0, NumVLane)) |
2249 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane));
2250 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2251 qib_write_kreg(dd, kr_scratch, 0ULL);
2252 }
2253
2254 /*
2255 * The code that deals with actual SerDes is in serdes_7322_init().
2256 * Compared to the code for iba7220, it is minimal.
2257 */
2258 static int serdes_7322_init(struct qib_pportdata *ppd);
2259
2260 /**
2261 * qib_7322_bringup_serdes - bring up the serdes
2262 * @ppd: physical port on the qlogic_ib device
2263 */
2264 static int qib_7322_bringup_serdes(struct qib_pportdata *ppd)
2265 {
2266 struct qib_devdata *dd = ppd->dd;
2267 u64 val, guid, ibc;
2268 unsigned long flags;
2269 int ret = 0;
2270
2271 /*
2272 * SerDes model not in Pd, but still need to
2273 * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere
2274 * eventually.
2275 */
2276 /* Put IBC in reset, sends disabled (should be in reset already) */
2277 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2278 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2279 qib_write_kreg(dd, kr_scratch, 0ULL);
2280
2281 if (qib_compat_ddr_negotiate) {
2282 ppd->cpspec->ibdeltainprog = 1;
2283 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
2284 crp_ibsymbolerr);
2285 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
2286 crp_iblinkerrrecov);
2287 }
2288
2289 /* flowcontrolwatermark is in units of KBytes */
2290 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark);
2291 /*
2292 * Flow control is sent this often, even if no changes in
2293 * buffer space occur. Units are 128ns for this chip.
2294 * Set to 3usec.
2295 */
2296 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod);
2297 /* max error tolerance */
2298 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
2299 /* IB credit flow control. */
2300 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold);
2301 /*
2302 * set initial max size pkt IBC will send, including ICRC; it's the
2303 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
2304 */
2305 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) <<
2306 SYM_LSB(IBCCtrlA_0, MaxPktLen);
2307 ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */
2308
2309 /* initially come up waiting for TS1, without sending anything. */
2310 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
2311 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2312
2313 /*
2314 * Reset the PCS interface to the serdes (and also ibc, which is still
2315 * in reset from above). Writes new value of ibcctrl_a as last step.
2316 */
2317 qib_7322_mini_pcs_reset(ppd);
2318 qib_write_kreg(dd, kr_scratch, 0ULL);
2319
2320 if (!ppd->cpspec->ibcctrl_b) {
2321 unsigned lse = ppd->link_speed_enabled;
2322
2323 /*
2324 * Not on re-init after reset, establish shadow
2325 * and force initial config.
2326 */
2327 ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd,
2328 krp_ibcctrl_b);
2329 ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR |
2330 IBA7322_IBC_SPEED_DDR |
2331 IBA7322_IBC_SPEED_SDR |
2332 IBA7322_IBC_WIDTH_AUTONEG |
2333 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED));
2334 if (lse & (lse - 1)) /* Muliple speeds enabled */
2335 ppd->cpspec->ibcctrl_b |=
2336 (lse << IBA7322_IBC_SPEED_LSB) |
2337 IBA7322_IBC_IBTA_1_2_MASK |
2338 IBA7322_IBC_MAX_SPEED_MASK;
2339 else
2340 ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ?
2341 IBA7322_IBC_SPEED_QDR |
2342 IBA7322_IBC_IBTA_1_2_MASK :
2343 (lse == QIB_IB_DDR) ?
2344 IBA7322_IBC_SPEED_DDR :
2345 IBA7322_IBC_SPEED_SDR;
2346 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
2347 (IB_WIDTH_1X | IB_WIDTH_4X))
2348 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG;
2349 else
2350 ppd->cpspec->ibcctrl_b |=
2351 ppd->link_width_enabled == IB_WIDTH_4X ?
2352 IBA7322_IBC_WIDTH_4X_ONLY :
2353 IBA7322_IBC_WIDTH_1X_ONLY;
2354
2355 /* always enable these on driver reload, not sticky */
2356 ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK |
2357 IBA7322_IBC_HRTBT_MASK);
2358 }
2359 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
2360
2361 /* setup so we have more time at CFGTEST to change H1 */
2362 val = qib_read_kreg_port(ppd, krp_ibcctrl_c);
2363 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH);
2364 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH);
2365 qib_write_kreg_port(ppd, krp_ibcctrl_c, val);
2366
2367 serdes_7322_init(ppd);
2368
2369 guid = be64_to_cpu(ppd->guid);
2370 if (!guid) {
2371 if (dd->base_guid)
2372 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1;
2373 ppd->guid = cpu_to_be64(guid);
2374 }
2375
2376 qib_write_kreg_port(ppd, krp_hrtbt_guid, guid);
2377 /* write to chip to prevent back-to-back writes of ibc reg */
2378 qib_write_kreg(dd, kr_scratch, 0);
2379
2380 /* Enable port */
2381 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn);
2382 set_vls(ppd);
2383
2384 /* be paranoid against later code motion, etc. */
2385 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2386 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable);
2387 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
2388 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2389
2390 /* Hold the link state machine for mezz boards */
2391 if (IS_QMH(dd) || IS_QME(dd))
2392 qib_set_ib_7322_lstate(ppd, 0,
2393 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
2394
2395 /* Also enable IBSTATUSCHG interrupt. */
2396 val = qib_read_kreg_port(ppd, krp_errmask);
2397 qib_write_kreg_port(ppd, krp_errmask,
2398 val | ERR_MASK_N(IBStatusChanged));
2399
2400 /* Always zero until we start messing with SerDes for real */
2401 return ret;
2402 }
2403
2404 /**
2405 * qib_7322_quiet_serdes - set serdes to txidle
2406 * @dd: the qlogic_ib device
2407 * Called when driver is being unloaded
2408 */
2409 static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd)
2410 {
2411 u64 val;
2412 unsigned long flags;
2413
2414 qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
2415
2416 spin_lock_irqsave(&ppd->lflags_lock, flags);
2417 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
2418 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2419 wake_up(&ppd->cpspec->autoneg_wait);
2420 cancel_delayed_work_sync(&ppd->cpspec->autoneg_work);
2421 if (ppd->dd->cspec->r1)
2422 cancel_delayed_work_sync(&ppd->cpspec->ipg_work);
2423
2424 ppd->cpspec->chase_end = 0;
2425 if (ppd->cpspec->chase_timer.data) /* if initted */
2426 del_timer_sync(&ppd->cpspec->chase_timer);
2427
2428 /*
2429 * Despite the name, actually disables IBC as well. Do it when
2430 * we are as sure as possible that no more packets can be
2431 * received, following the down and the PCS reset.
2432 * The actual disabling happens in qib_7322_mini_pci_reset(),
2433 * along with the PCS being reset.
2434 */
2435 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2436 qib_7322_mini_pcs_reset(ppd);
2437
2438 /*
2439 * Update the adjusted counters so the adjustment persists
2440 * across driver reload.
2441 */
2442 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
2443 ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) {
2444 struct qib_devdata *dd = ppd->dd;
2445 u64 diagc;
2446
2447 /* enable counter writes */
2448 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
2449 qib_write_kreg(dd, kr_hwdiagctrl,
2450 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
2451
2452 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
2453 val = read_7322_creg32_port(ppd, crp_ibsymbolerr);
2454 if (ppd->cpspec->ibdeltainprog)
2455 val -= val - ppd->cpspec->ibsymsnap;
2456 val -= ppd->cpspec->ibsymdelta;
2457 write_7322_creg_port(ppd, crp_ibsymbolerr, val);
2458 }
2459 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
2460 val = read_7322_creg32_port(ppd, crp_iblinkerrrecov);
2461 if (ppd->cpspec->ibdeltainprog)
2462 val -= val - ppd->cpspec->iblnkerrsnap;
2463 val -= ppd->cpspec->iblnkerrdelta;
2464 write_7322_creg_port(ppd, crp_iblinkerrrecov, val);
2465 }
2466 if (ppd->cpspec->iblnkdowndelta) {
2467 val = read_7322_creg32_port(ppd, crp_iblinkdown);
2468 val += ppd->cpspec->iblnkdowndelta;
2469 write_7322_creg_port(ppd, crp_iblinkdown, val);
2470 }
2471 /*
2472 * No need to save ibmalfdelta since IB perfcounters
2473 * are cleared on driver reload.
2474 */
2475
2476 /* and disable counter writes */
2477 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
2478 }
2479 }
2480
2481 /**
2482 * qib_setup_7322_setextled - set the state of the two external LEDs
2483 * @ppd: physical port on the qlogic_ib device
2484 * @on: whether the link is up or not
2485 *
2486 * The exact combo of LEDs if on is true is determined by looking
2487 * at the ibcstatus.
2488 *
2489 * These LEDs indicate the physical and logical state of IB link.
2490 * For this chip (at least with recommended board pinouts), LED1
2491 * is Yellow (logical state) and LED2 is Green (physical state),
2492 *
2493 * Note: We try to match the Mellanox HCA LED behavior as best
2494 * we can. Green indicates physical link state is OK (something is
2495 * plugged in, and we can train).
2496 * Amber indicates the link is logically up (ACTIVE).
2497 * Mellanox further blinks the amber LED to indicate data packet
2498 * activity, but we have no hardware support for that, so it would
2499 * require waking up every 10-20 msecs and checking the counters
2500 * on the chip, and then turning the LED off if appropriate. That's
2501 * visible overhead, so not something we will do.
2502 */
2503 static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on)
2504 {
2505 struct qib_devdata *dd = ppd->dd;
2506 u64 extctl, ledblink = 0, val;
2507 unsigned long flags;
2508 int yel, grn;
2509
2510 /*
2511 * The diags use the LED to indicate diag info, so we leave
2512 * the external LED alone when the diags are running.
2513 */
2514 if (dd->diag_client)
2515 return;
2516
2517 /* Allow override of LED display for, e.g. Locating system in rack */
2518 if (ppd->led_override) {
2519 grn = (ppd->led_override & QIB_LED_PHYS);
2520 yel = (ppd->led_override & QIB_LED_LOG);
2521 } else if (on) {
2522 val = qib_read_kreg_port(ppd, krp_ibcstatus_a);
2523 grn = qib_7322_phys_portstate(val) ==
2524 IB_PHYSPORTSTATE_LINKUP;
2525 yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE;
2526 } else {
2527 grn = 0;
2528 yel = 0;
2529 }
2530
2531 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2532 extctl = dd->cspec->extctrl & (ppd->port == 1 ?
2533 ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK);
2534 if (grn) {
2535 extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN;
2536 /*
2537 * Counts are in chip clock (4ns) periods.
2538 * This is 1/16 sec (66.6ms) on,
2539 * 3/16 sec (187.5 ms) off, with packets rcvd.
2540 */
2541 ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) |
2542 ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT);
2543 }
2544 if (yel)
2545 extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL;
2546 dd->cspec->extctrl = extctl;
2547 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
2548 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2549
2550 if (ledblink) /* blink the LED on packet receive */
2551 qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink);
2552 }
2553
2554 /*
2555 * Disable MSIx interrupt if enabled, call generic MSIx code
2556 * to cleanup, and clear pending MSIx interrupts.
2557 * Used for fallback to INTx, after reset, and when MSIx setup fails.
2558 */
2559 static void qib_7322_nomsix(struct qib_devdata *dd)
2560 {
2561 u64 intgranted;
2562 int n;
2563
2564 dd->cspec->main_int_mask = ~0ULL;
2565 n = dd->cspec->num_msix_entries;
2566 if (n) {
2567 int i;
2568
2569 dd->cspec->num_msix_entries = 0;
2570 for (i = 0; i < n; i++)
2571 free_irq(dd->cspec->msix_entries[i].vector,
2572 dd->cspec->msix_arg[i]);
2573 qib_nomsix(dd);
2574 }
2575 /* make sure no MSIx interrupts are left pending */
2576 intgranted = qib_read_kreg64(dd, kr_intgranted);
2577 if (intgranted)
2578 qib_write_kreg(dd, kr_intgranted, intgranted);
2579 }
2580
2581 static void qib_7322_free_irq(struct qib_devdata *dd)
2582 {
2583 if (dd->cspec->irq) {
2584 free_irq(dd->cspec->irq, dd);
2585 dd->cspec->irq = 0;
2586 }
2587 qib_7322_nomsix(dd);
2588 }
2589
2590 static void qib_setup_7322_cleanup(struct qib_devdata *dd)
2591 {
2592 int i;
2593
2594 qib_7322_free_irq(dd);
2595 kfree(dd->cspec->cntrs);
2596 kfree(dd->cspec->sendchkenable);
2597 kfree(dd->cspec->sendgrhchk);
2598 kfree(dd->cspec->sendibchk);
2599 kfree(dd->cspec->msix_entries);
2600 kfree(dd->cspec->msix_arg);
2601 for (i = 0; i < dd->num_pports; i++) {
2602 unsigned long flags;
2603 u32 mask = QSFP_GPIO_MOD_PRS_N |
2604 (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT);
2605
2606 kfree(dd->pport[i].cpspec->portcntrs);
2607 if (dd->flags & QIB_HAS_QSFP) {
2608 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2609 dd->cspec->gpio_mask &= ~mask;
2610 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2611 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2612 qib_qsfp_deinit(&dd->pport[i].cpspec->qsfp_data);
2613 }
2614 if (dd->pport[i].ibport_data.smi_ah)
2615 ib_destroy_ah(&dd->pport[i].ibport_data.smi_ah->ibah);
2616 }
2617 }
2618
2619 /* handle SDMA interrupts */
2620 static void sdma_7322_intr(struct qib_devdata *dd, u64 istat)
2621 {
2622 struct qib_pportdata *ppd0 = &dd->pport[0];
2623 struct qib_pportdata *ppd1 = &dd->pport[1];
2624 u64 intr0 = istat & (INT_MASK_P(SDma, 0) |
2625 INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0));
2626 u64 intr1 = istat & (INT_MASK_P(SDma, 1) |
2627 INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1));
2628
2629 if (intr0)
2630 qib_sdma_intr(ppd0);
2631 if (intr1)
2632 qib_sdma_intr(ppd1);
2633
2634 if (istat & INT_MASK_PM(SDmaCleanupDone, 0))
2635 qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started);
2636 if (istat & INT_MASK_PM(SDmaCleanupDone, 1))
2637 qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started);
2638 }
2639
2640 /*
2641 * Set or clear the Send buffer available interrupt enable bit.
2642 */
2643 static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint)
2644 {
2645 unsigned long flags;
2646
2647 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2648 if (needint)
2649 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
2650 else
2651 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
2652 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2653 qib_write_kreg(dd, kr_scratch, 0ULL);
2654 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2655 }
2656
2657 /*
2658 * Somehow got an interrupt with reserved bits set in interrupt status.
2659 * Print a message so we know it happened, then clear them.
2660 * keep mainline interrupt handler cache-friendly
2661 */
2662 static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat)
2663 {
2664 u64 kills;
2665 char msg[128];
2666
2667 kills = istat & ~QIB_I_BITSEXTANT;
2668 qib_dev_err(dd, "Clearing reserved interrupt(s) 0x%016llx:"
2669 " %s\n", (unsigned long long) kills, msg);
2670 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills));
2671 }
2672
2673 /* keep mainline interrupt handler cache-friendly */
2674 static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd)
2675 {
2676 u32 gpiostatus;
2677 int handled = 0;
2678 int pidx;
2679
2680 /*
2681 * Boards for this chip currently don't use GPIO interrupts,
2682 * so clear by writing GPIOstatus to GPIOclear, and complain
2683 * to developer. To avoid endless repeats, clear
2684 * the bits in the mask, since there is some kind of
2685 * programming error or chip problem.
2686 */
2687 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
2688 /*
2689 * In theory, writing GPIOstatus to GPIOclear could
2690 * have a bad side-effect on some diagnostic that wanted
2691 * to poll for a status-change, but the various shadows
2692 * make that problematic at best. Diags will just suppress
2693 * all GPIO interrupts during such tests.
2694 */
2695 qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
2696 /*
2697 * Check for QSFP MOD_PRS changes
2698 * only works for single port if IB1 != pidx1
2699 */
2700 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP);
2701 ++pidx) {
2702 struct qib_pportdata *ppd;
2703 struct qib_qsfp_data *qd;
2704 u32 mask;
2705 if (!dd->pport[pidx].link_speed_supported)
2706 continue;
2707 mask = QSFP_GPIO_MOD_PRS_N;
2708 ppd = dd->pport + pidx;
2709 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
2710 if (gpiostatus & dd->cspec->gpio_mask & mask) {
2711 u64 pins;
2712 qd = &ppd->cpspec->qsfp_data;
2713 gpiostatus &= ~mask;
2714 pins = qib_read_kreg64(dd, kr_extstatus);
2715 pins >>= SYM_LSB(EXTStatus, GPIOIn);
2716 if (!(pins & mask)) {
2717 ++handled;
2718 qd->t_insert = get_jiffies_64();
2719 queue_work(ib_wq, &qd->work);
2720 }
2721 }
2722 }
2723
2724 if (gpiostatus && !handled) {
2725 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
2726 u32 gpio_irq = mask & gpiostatus;
2727
2728 /*
2729 * Clear any troublemakers, and update chip from shadow
2730 */
2731 dd->cspec->gpio_mask &= ~gpio_irq;
2732 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2733 }
2734 }
2735
2736 /*
2737 * Handle errors and unusual events first, separate function
2738 * to improve cache hits for fast path interrupt handling.
2739 */
2740 static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat)
2741 {
2742 if (istat & ~QIB_I_BITSEXTANT)
2743 unknown_7322_ibits(dd, istat);
2744 if (istat & QIB_I_GPIO)
2745 unknown_7322_gpio_intr(dd);
2746 if (istat & QIB_I_C_ERROR) {
2747 qib_write_kreg(dd, kr_errmask, 0ULL);
2748 tasklet_schedule(&dd->error_tasklet);
2749 }
2750 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0])
2751 handle_7322_p_errors(dd->rcd[0]->ppd);
2752 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1])
2753 handle_7322_p_errors(dd->rcd[1]->ppd);
2754 }
2755
2756 /*
2757 * Dynamically adjust the rcv int timeout for a context based on incoming
2758 * packet rate.
2759 */
2760 static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts)
2761 {
2762 struct qib_devdata *dd = rcd->dd;
2763 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt];
2764
2765 /*
2766 * Dynamically adjust idle timeout on chip
2767 * based on number of packets processed.
2768 */
2769 if (npkts < rcv_int_count && timeout > 2)
2770 timeout >>= 1;
2771 else if (npkts >= rcv_int_count && timeout < rcv_int_timeout)
2772 timeout = min(timeout << 1, rcv_int_timeout);
2773 else
2774 return;
2775
2776 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout;
2777 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout);
2778 }
2779
2780 /*
2781 * This is the main interrupt handler.
2782 * It will normally only be used for low frequency interrupts but may
2783 * have to handle all interrupts if INTx is enabled or fewer than normal
2784 * MSIx interrupts were allocated.
2785 * This routine should ignore the interrupt bits for any of the
2786 * dedicated MSIx handlers.
2787 */
2788 static irqreturn_t qib_7322intr(int irq, void *data)
2789 {
2790 struct qib_devdata *dd = data;
2791 irqreturn_t ret;
2792 u64 istat;
2793 u64 ctxtrbits;
2794 u64 rmask;
2795 unsigned i;
2796 u32 npkts;
2797
2798 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
2799 /*
2800 * This return value is not great, but we do not want the
2801 * interrupt core code to remove our interrupt handler
2802 * because we don't appear to be handling an interrupt
2803 * during a chip reset.
2804 */
2805 ret = IRQ_HANDLED;
2806 goto bail;
2807 }
2808
2809 istat = qib_read_kreg64(dd, kr_intstatus);
2810
2811 if (unlikely(istat == ~0ULL)) {
2812 qib_bad_intrstatus(dd);
2813 qib_dev_err(dd, "Interrupt status all f's, skipping\n");
2814 /* don't know if it was our interrupt or not */
2815 ret = IRQ_NONE;
2816 goto bail;
2817 }
2818
2819 istat &= dd->cspec->main_int_mask;
2820 if (unlikely(!istat)) {
2821 /* already handled, or shared and not us */
2822 ret = IRQ_NONE;
2823 goto bail;
2824 }
2825
2826 qib_stats.sps_ints++;
2827 if (dd->int_counter != (u32) -1)
2828 dd->int_counter++;
2829
2830 /* handle "errors" of various kinds first, device ahead of port */
2831 if (unlikely(istat & (~QIB_I_BITSEXTANT | QIB_I_GPIO |
2832 QIB_I_C_ERROR | INT_MASK_P(Err, 0) |
2833 INT_MASK_P(Err, 1))))
2834 unlikely_7322_intr(dd, istat);
2835
2836 /*
2837 * Clear the interrupt bits we found set, relatively early, so we
2838 * "know" know the chip will have seen this by the time we process
2839 * the queue, and will re-interrupt if necessary. The processor
2840 * itself won't take the interrupt again until we return.
2841 */
2842 qib_write_kreg(dd, kr_intclear, istat);
2843
2844 /*
2845 * Handle kernel receive queues before checking for pio buffers
2846 * available since receives can overflow; piobuf waiters can afford
2847 * a few extra cycles, since they were waiting anyway.
2848 */
2849 ctxtrbits = istat & (QIB_I_RCVAVAIL_MASK | QIB_I_RCVURG_MASK);
2850 if (ctxtrbits) {
2851 rmask = (1ULL << QIB_I_RCVAVAIL_LSB) |
2852 (1ULL << QIB_I_RCVURG_LSB);
2853 for (i = 0; i < dd->first_user_ctxt; i++) {
2854 if (ctxtrbits & rmask) {
2855 ctxtrbits &= ~rmask;
2856 if (dd->rcd[i]) {
2857 qib_kreceive(dd->rcd[i], NULL, &npkts);
2858 }
2859 }
2860 rmask <<= 1;
2861 }
2862 if (ctxtrbits) {
2863 ctxtrbits = (ctxtrbits >> QIB_I_RCVAVAIL_LSB) |
2864 (ctxtrbits >> QIB_I_RCVURG_LSB);
2865 qib_handle_urcv(dd, ctxtrbits);
2866 }
2867 }
2868
2869 if (istat & (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1)))
2870 sdma_7322_intr(dd, istat);
2871
2872 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
2873 qib_ib_piobufavail(dd);
2874
2875 ret = IRQ_HANDLED;
2876 bail:
2877 return ret;
2878 }
2879
2880 /*
2881 * Dedicated receive packet available interrupt handler.
2882 */
2883 static irqreturn_t qib_7322pintr(int irq, void *data)
2884 {
2885 struct qib_ctxtdata *rcd = data;
2886 struct qib_devdata *dd = rcd->dd;
2887 u32 npkts;
2888
2889 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2890 /*
2891 * This return value is not great, but we do not want the
2892 * interrupt core code to remove our interrupt handler
2893 * because we don't appear to be handling an interrupt
2894 * during a chip reset.
2895 */
2896 return IRQ_HANDLED;
2897
2898 qib_stats.sps_ints++;
2899 if (dd->int_counter != (u32) -1)
2900 dd->int_counter++;
2901
2902 /* Clear the interrupt bit we expect to be set. */
2903 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) |
2904 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt);
2905
2906 qib_kreceive(rcd, NULL, &npkts);
2907
2908 return IRQ_HANDLED;
2909 }
2910
2911 /*
2912 * Dedicated Send buffer available interrupt handler.
2913 */
2914 static irqreturn_t qib_7322bufavail(int irq, void *data)
2915 {
2916 struct qib_devdata *dd = data;
2917
2918 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2919 /*
2920 * This return value is not great, but we do not want the
2921 * interrupt core code to remove our interrupt handler
2922 * because we don't appear to be handling an interrupt
2923 * during a chip reset.
2924 */
2925 return IRQ_HANDLED;
2926
2927 qib_stats.sps_ints++;
2928 if (dd->int_counter != (u32) -1)
2929 dd->int_counter++;
2930
2931 /* Clear the interrupt bit we expect to be set. */
2932 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL);
2933
2934 /* qib_ib_piobufavail() will clear the want PIO interrupt if needed */
2935 if (dd->flags & QIB_INITTED)
2936 qib_ib_piobufavail(dd);
2937 else
2938 qib_wantpiobuf_7322_intr(dd, 0);
2939
2940 return IRQ_HANDLED;
2941 }
2942
2943 /*
2944 * Dedicated Send DMA interrupt handler.
2945 */
2946 static irqreturn_t sdma_intr(int irq, void *data)
2947 {
2948 struct qib_pportdata *ppd = data;
2949 struct qib_devdata *dd = ppd->dd;
2950
2951 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2952 /*
2953 * This return value is not great, but we do not want the
2954 * interrupt core code to remove our interrupt handler
2955 * because we don't appear to be handling an interrupt
2956 * during a chip reset.
2957 */
2958 return IRQ_HANDLED;
2959
2960 qib_stats.sps_ints++;
2961 if (dd->int_counter != (u32) -1)
2962 dd->int_counter++;
2963
2964 /* Clear the interrupt bit we expect to be set. */
2965 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2966 INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0));
2967 qib_sdma_intr(ppd);
2968
2969 return IRQ_HANDLED;
2970 }
2971
2972 /*
2973 * Dedicated Send DMA idle interrupt handler.
2974 */
2975 static irqreturn_t sdma_idle_intr(int irq, void *data)
2976 {
2977 struct qib_pportdata *ppd = data;
2978 struct qib_devdata *dd = ppd->dd;
2979
2980 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2981 /*
2982 * This return value is not great, but we do not want the
2983 * interrupt core code to remove our interrupt handler
2984 * because we don't appear to be handling an interrupt
2985 * during a chip reset.
2986 */
2987 return IRQ_HANDLED;
2988
2989 qib_stats.sps_ints++;
2990 if (dd->int_counter != (u32) -1)
2991 dd->int_counter++;
2992
2993 /* Clear the interrupt bit we expect to be set. */
2994 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2995 INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0));
2996 qib_sdma_intr(ppd);
2997
2998 return IRQ_HANDLED;
2999 }
3000
3001 /*
3002 * Dedicated Send DMA progress interrupt handler.
3003 */
3004 static irqreturn_t sdma_progress_intr(int irq, void *data)
3005 {
3006 struct qib_pportdata *ppd = data;
3007 struct qib_devdata *dd = ppd->dd;
3008
3009 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3010 /*
3011 * This return value is not great, but we do not want the
3012 * interrupt core code to remove our interrupt handler
3013 * because we don't appear to be handling an interrupt
3014 * during a chip reset.
3015 */
3016 return IRQ_HANDLED;
3017
3018 qib_stats.sps_ints++;
3019 if (dd->int_counter != (u32) -1)
3020 dd->int_counter++;
3021
3022 /* Clear the interrupt bit we expect to be set. */
3023 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3024 INT_MASK_P(SDmaProgress, 1) :
3025 INT_MASK_P(SDmaProgress, 0));
3026 qib_sdma_intr(ppd);
3027
3028 return IRQ_HANDLED;
3029 }
3030
3031 /*
3032 * Dedicated Send DMA cleanup interrupt handler.
3033 */
3034 static irqreturn_t sdma_cleanup_intr(int irq, void *data)
3035 {
3036 struct qib_pportdata *ppd = data;
3037 struct qib_devdata *dd = ppd->dd;
3038
3039 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3040 /*
3041 * This return value is not great, but we do not want the
3042 * interrupt core code to remove our interrupt handler
3043 * because we don't appear to be handling an interrupt
3044 * during a chip reset.
3045 */
3046 return IRQ_HANDLED;
3047
3048 qib_stats.sps_ints++;
3049 if (dd->int_counter != (u32) -1)
3050 dd->int_counter++;
3051
3052 /* Clear the interrupt bit we expect to be set. */
3053 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3054 INT_MASK_PM(SDmaCleanupDone, 1) :
3055 INT_MASK_PM(SDmaCleanupDone, 0));
3056 qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started);
3057
3058 return IRQ_HANDLED;
3059 }
3060
3061 /*
3062 * Set up our chip-specific interrupt handler.
3063 * The interrupt type has already been setup, so
3064 * we just need to do the registration and error checking.
3065 * If we are using MSIx interrupts, we may fall back to
3066 * INTx later, if the interrupt handler doesn't get called
3067 * within 1/2 second (see verify_interrupt()).
3068 */
3069 static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend)
3070 {
3071 int ret, i, msixnum;
3072 u64 redirect[6];
3073 u64 mask;
3074
3075 if (!dd->num_pports)
3076 return;
3077
3078 if (clearpend) {
3079 /*
3080 * if not switching interrupt types, be sure interrupts are
3081 * disabled, and then clear anything pending at this point,
3082 * because we are starting clean.
3083 */
3084 qib_7322_set_intr_state(dd, 0);
3085
3086 /* clear the reset error, init error/hwerror mask */
3087 qib_7322_init_hwerrors(dd);
3088
3089 /* clear any interrupt bits that might be set */
3090 qib_write_kreg(dd, kr_intclear, ~0ULL);
3091
3092 /* make sure no pending MSIx intr, and clear diag reg */
3093 qib_write_kreg(dd, kr_intgranted, ~0ULL);
3094 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL);
3095 }
3096
3097 if (!dd->cspec->num_msix_entries) {
3098 /* Try to get INTx interrupt */
3099 try_intx:
3100 if (!dd->pcidev->irq) {
3101 qib_dev_err(dd, "irq is 0, BIOS error? "
3102 "Interrupts won't work\n");
3103 goto bail;
3104 }
3105 ret = request_irq(dd->pcidev->irq, qib_7322intr,
3106 IRQF_SHARED, QIB_DRV_NAME, dd);
3107 if (ret) {
3108 qib_dev_err(dd, "Couldn't setup INTx "
3109 "interrupt (irq=%d): %d\n",
3110 dd->pcidev->irq, ret);
3111 goto bail;
3112 }
3113 dd->cspec->irq = dd->pcidev->irq;
3114 dd->cspec->main_int_mask = ~0ULL;
3115 goto bail;
3116 }
3117
3118 /* Try to get MSIx interrupts */
3119 memset(redirect, 0, sizeof redirect);
3120 mask = ~0ULL;
3121 msixnum = 0;
3122 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) {
3123 irq_handler_t handler;
3124 const char *name;
3125 void *arg;
3126 u64 val;
3127 int lsb, reg, sh;
3128
3129 if (i < ARRAY_SIZE(irq_table)) {
3130 if (irq_table[i].port) {
3131 /* skip if for a non-configured port */
3132 if (irq_table[i].port > dd->num_pports)
3133 continue;
3134 arg = dd->pport + irq_table[i].port - 1;
3135 } else
3136 arg = dd;
3137 lsb = irq_table[i].lsb;
3138 handler = irq_table[i].handler;
3139 name = irq_table[i].name;
3140 } else {
3141 unsigned ctxt;
3142
3143 ctxt = i - ARRAY_SIZE(irq_table);
3144 /* per krcvq context receive interrupt */
3145 arg = dd->rcd[ctxt];
3146 if (!arg)
3147 continue;
3148 if (qib_krcvq01_no_msi && ctxt < 2)
3149 continue;
3150 lsb = QIB_I_RCVAVAIL_LSB + ctxt;
3151 handler = qib_7322pintr;
3152 name = QIB_DRV_NAME " (kctx)";
3153 }
3154 ret = request_irq(dd->cspec->msix_entries[msixnum].vector,
3155 handler, 0, name, arg);
3156 if (ret) {
3157 /*
3158 * Shouldn't happen since the enable said we could
3159 * have as many as we are trying to setup here.
3160 */
3161 qib_dev_err(dd, "Couldn't setup MSIx "
3162 "interrupt (vec=%d, irq=%d): %d\n", msixnum,
3163 dd->cspec->msix_entries[msixnum].vector,
3164 ret);
3165 qib_7322_nomsix(dd);
3166 goto try_intx;
3167 }
3168 dd->cspec->msix_arg[msixnum] = arg;
3169 if (lsb >= 0) {
3170 reg = lsb / IBA7322_REDIRECT_VEC_PER_REG;
3171 sh = (lsb % IBA7322_REDIRECT_VEC_PER_REG) *
3172 SYM_LSB(IntRedirect0, vec1);
3173 mask &= ~(1ULL << lsb);
3174 redirect[reg] |= ((u64) msixnum) << sh;
3175 }
3176 val = qib_read_kreg64(dd, 2 * msixnum + 1 +
3177 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3178 msixnum++;
3179 }
3180 /* Initialize the vector mapping */
3181 for (i = 0; i < ARRAY_SIZE(redirect); i++)
3182 qib_write_kreg(dd, kr_intredirect + i, redirect[i]);
3183 dd->cspec->main_int_mask = mask;
3184 tasklet_init(&dd->error_tasklet, qib_error_tasklet,
3185 (unsigned long)dd);
3186 bail:;
3187 }
3188
3189 /**
3190 * qib_7322_boardname - fill in the board name and note features
3191 * @dd: the qlogic_ib device
3192 *
3193 * info will be based on the board revision register
3194 */
3195 static unsigned qib_7322_boardname(struct qib_devdata *dd)
3196 {
3197 /* Will need enumeration of board-types here */
3198 char *n;
3199 u32 boardid, namelen;
3200 unsigned features = DUAL_PORT_CAP;
3201
3202 boardid = SYM_FIELD(dd->revision, Revision, BoardID);
3203
3204 switch (boardid) {
3205 case 0:
3206 n = "InfiniPath_QLE7342_Emulation";
3207 break;
3208 case 1:
3209 n = "InfiniPath_QLE7340";
3210 dd->flags |= QIB_HAS_QSFP;
3211 features = PORT_SPD_CAP;
3212 break;
3213 case 2:
3214 n = "InfiniPath_QLE7342";
3215 dd->flags |= QIB_HAS_QSFP;
3216 break;
3217 case 3:
3218 n = "InfiniPath_QMI7342";
3219 break;
3220 case 4:
3221 n = "InfiniPath_Unsupported7342";
3222 qib_dev_err(dd, "Unsupported version of QMH7342\n");
3223 features = 0;
3224 break;
3225 case BOARD_QMH7342:
3226 n = "InfiniPath_QMH7342";
3227 features = 0x24;
3228 break;
3229 case BOARD_QME7342:
3230 n = "InfiniPath_QME7342";
3231 break;
3232 case 8:
3233 n = "InfiniPath_QME7362";
3234 dd->flags |= QIB_HAS_QSFP;
3235 break;
3236 case 15:
3237 n = "InfiniPath_QLE7342_TEST";
3238 dd->flags |= QIB_HAS_QSFP;
3239 break;
3240 default:
3241 n = "InfiniPath_QLE73xy_UNKNOWN";
3242 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid);
3243 break;
3244 }
3245 dd->board_atten = 1; /* index into txdds_Xdr */
3246
3247 namelen = strlen(n) + 1;
3248 dd->boardname = kmalloc(namelen, GFP_KERNEL);
3249 if (!dd->boardname)
3250 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
3251 else
3252 snprintf(dd->boardname, namelen, "%s", n);
3253
3254 snprintf(dd->boardversion, sizeof(dd->boardversion),
3255 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
3256 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
3257 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
3258 dd->majrev, dd->minrev,
3259 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
3260
3261 if (qib_singleport && (features >> PORT_SPD_CAP_SHIFT) & PORT_SPD_CAP) {
3262 qib_devinfo(dd->pcidev, "IB%u: Forced to single port mode"
3263 " by module parameter\n", dd->unit);
3264 features &= PORT_SPD_CAP;
3265 }
3266
3267 return features;
3268 }
3269
3270 /*
3271 * This routine sleeps, so it can only be called from user context, not
3272 * from interrupt context.
3273 */
3274 static int qib_do_7322_reset(struct qib_devdata *dd)
3275 {
3276 u64 val;
3277 u64 *msix_vecsave;
3278 int i, msix_entries, ret = 1;
3279 u16 cmdval;
3280 u8 int_line, clinesz;
3281 unsigned long flags;
3282
3283 /* Use dev_err so it shows up in logs, etc. */
3284 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
3285
3286 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
3287
3288 msix_entries = dd->cspec->num_msix_entries;
3289
3290 /* no interrupts till re-initted */
3291 qib_7322_set_intr_state(dd, 0);
3292
3293 if (msix_entries) {
3294 qib_7322_nomsix(dd);
3295 /* can be up to 512 bytes, too big for stack */
3296 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries *
3297 sizeof(u64), GFP_KERNEL);
3298 if (!msix_vecsave)
3299 qib_dev_err(dd, "No mem to save MSIx data\n");
3300 } else
3301 msix_vecsave = NULL;
3302
3303 /*
3304 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector
3305 * info that is set up by the BIOS, so we have to save and restore
3306 * it ourselves. There is some risk something could change it,
3307 * after we save it, but since we have disabled the MSIx, it
3308 * shouldn't be touched...
3309 */
3310 for (i = 0; i < msix_entries; i++) {
3311 u64 vecaddr, vecdata;
3312 vecaddr = qib_read_kreg64(dd, 2 * i +
3313 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3314 vecdata = qib_read_kreg64(dd, 1 + 2 * i +
3315 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3316 if (msix_vecsave) {
3317 msix_vecsave[2 * i] = vecaddr;
3318 /* save it without the masked bit set */
3319 msix_vecsave[1 + 2 * i] = vecdata & ~0x100000000ULL;
3320 }
3321 }
3322
3323 dd->pport->cpspec->ibdeltainprog = 0;
3324 dd->pport->cpspec->ibsymdelta = 0;
3325 dd->pport->cpspec->iblnkerrdelta = 0;
3326 dd->pport->cpspec->ibmalfdelta = 0;
3327 dd->int_counter = 0; /* so we check interrupts work again */
3328
3329 /*
3330 * Keep chip from being accessed until we are ready. Use
3331 * writeq() directly, to allow the write even though QIB_PRESENT
3332 * isn't set.
3333 */
3334 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR);
3335 dd->flags |= QIB_DOING_RESET;
3336 val = dd->control | QLOGIC_IB_C_RESET;
3337 writeq(val, &dd->kregbase[kr_control]);
3338
3339 for (i = 1; i <= 5; i++) {
3340 /*
3341 * Allow MBIST, etc. to complete; longer on each retry.
3342 * We sometimes get machine checks from bus timeout if no
3343 * response, so for now, make it *really* long.
3344 */
3345 msleep(1000 + (1 + i) * 3000);
3346
3347 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
3348
3349 /*
3350 * Use readq directly, so we don't need to mark it as PRESENT
3351 * until we get a successful indication that all is well.
3352 */
3353 val = readq(&dd->kregbase[kr_revision]);
3354 if (val == dd->revision)
3355 break;
3356 if (i == 5) {
3357 qib_dev_err(dd, "Failed to initialize after reset, "
3358 "unusable\n");
3359 ret = 0;
3360 goto bail;
3361 }
3362 }
3363
3364 dd->flags |= QIB_PRESENT; /* it's back */
3365
3366 if (msix_entries) {
3367 /* restore the MSIx vector address and data if saved above */
3368 for (i = 0; i < msix_entries; i++) {
3369 dd->cspec->msix_entries[i].entry = i;
3370 if (!msix_vecsave || !msix_vecsave[2 * i])
3371 continue;
3372 qib_write_kreg(dd, 2 * i +
3373 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3374 msix_vecsave[2 * i]);
3375 qib_write_kreg(dd, 1 + 2 * i +
3376 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3377 msix_vecsave[1 + 2 * i]);
3378 }
3379 }
3380
3381 /* initialize the remaining registers. */
3382 for (i = 0; i < dd->num_pports; ++i)
3383 write_7322_init_portregs(&dd->pport[i]);
3384 write_7322_initregs(dd);
3385
3386 if (qib_pcie_params(dd, dd->lbus_width,
3387 &dd->cspec->num_msix_entries,
3388 dd->cspec->msix_entries))
3389 qib_dev_err(dd, "Reset failed to setup PCIe or interrupts; "
3390 "continuing anyway\n");
3391
3392 qib_setup_7322_interrupt(dd, 1);
3393
3394 for (i = 0; i < dd->num_pports; ++i) {
3395 struct qib_pportdata *ppd = &dd->pport[i];
3396
3397 spin_lock_irqsave(&ppd->lflags_lock, flags);
3398 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
3399 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3400 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3401 }
3402
3403 bail:
3404 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */
3405 kfree(msix_vecsave);
3406 return ret;
3407 }
3408
3409 /**
3410 * qib_7322_put_tid - write a TID to the chip
3411 * @dd: the qlogic_ib device
3412 * @tidptr: pointer to the expected TID (in chip) to update
3413 * @tidtype: 0 for eager, 1 for expected
3414 * @pa: physical address of in memory buffer; tidinvalid if freeing
3415 */
3416 static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
3417 u32 type, unsigned long pa)
3418 {
3419 if (!(dd->flags & QIB_PRESENT))
3420 return;
3421 if (pa != dd->tidinvalid) {
3422 u64 chippa = pa >> IBA7322_TID_PA_SHIFT;
3423
3424 /* paranoia checks */
3425 if (pa != (chippa << IBA7322_TID_PA_SHIFT)) {
3426 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
3427 pa);
3428 return;
3429 }
3430 if (chippa >= (1UL << IBA7322_TID_SZ_SHIFT)) {
3431 qib_dev_err(dd, "Physical page address 0x%lx "
3432 "larger than supported\n", pa);
3433 return;
3434 }
3435
3436 if (type == RCVHQ_RCV_TYPE_EAGER)
3437 chippa |= dd->tidtemplate;
3438 else /* for now, always full 4KB page */
3439 chippa |= IBA7322_TID_SZ_4K;
3440 pa = chippa;
3441 }
3442 writeq(pa, tidptr);
3443 mmiowb();
3444 }
3445
3446 /**
3447 * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager
3448 * @dd: the qlogic_ib device
3449 * @ctxt: the ctxt
3450 *
3451 * clear all TID entries for a ctxt, expected and eager.
3452 * Used from qib_close().
3453 */
3454 static void qib_7322_clear_tids(struct qib_devdata *dd,
3455 struct qib_ctxtdata *rcd)
3456 {
3457 u64 __iomem *tidbase;
3458 unsigned long tidinv;
3459 u32 ctxt;
3460 int i;
3461
3462 if (!dd->kregbase || !rcd)
3463 return;
3464
3465 ctxt = rcd->ctxt;
3466
3467 tidinv = dd->tidinvalid;
3468 tidbase = (u64 __iomem *)
3469 ((char __iomem *) dd->kregbase +
3470 dd->rcvtidbase +
3471 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
3472
3473 for (i = 0; i < dd->rcvtidcnt; i++)
3474 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
3475 tidinv);
3476
3477 tidbase = (u64 __iomem *)
3478 ((char __iomem *) dd->kregbase +
3479 dd->rcvegrbase +
3480 rcd->rcvegr_tid_base * sizeof(*tidbase));
3481
3482 for (i = 0; i < rcd->rcvegrcnt; i++)
3483 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
3484 tidinv);
3485 }
3486
3487 /**
3488 * qib_7322_tidtemplate - setup constants for TID updates
3489 * @dd: the qlogic_ib device
3490 *
3491 * We setup stuff that we use a lot, to avoid calculating each time
3492 */
3493 static void qib_7322_tidtemplate(struct qib_devdata *dd)
3494 {
3495 /*
3496 * For now, we always allocate 4KB buffers (at init) so we can
3497 * receive max size packets. We may want a module parameter to
3498 * specify 2KB or 4KB and/or make it per port instead of per device
3499 * for those who want to reduce memory footprint. Note that the
3500 * rcvhdrentsize size must be large enough to hold the largest
3501 * IB header (currently 96 bytes) that we expect to handle (plus of
3502 * course the 2 dwords of RHF).
3503 */
3504 if (dd->rcvegrbufsize == 2048)
3505 dd->tidtemplate = IBA7322_TID_SZ_2K;
3506 else if (dd->rcvegrbufsize == 4096)
3507 dd->tidtemplate = IBA7322_TID_SZ_4K;
3508 dd->tidinvalid = 0;
3509 }
3510
3511 /**
3512 * qib_init_7322_get_base_info - set chip-specific flags for user code
3513 * @rcd: the qlogic_ib ctxt
3514 * @kbase: qib_base_info pointer
3515 *
3516 * We set the PCIE flag because the lower bandwidth on PCIe vs
3517 * HyperTransport can affect some user packet algorithims.
3518 */
3519
3520 static int qib_7322_get_base_info(struct qib_ctxtdata *rcd,
3521 struct qib_base_info *kinfo)
3522 {
3523 kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP |
3524 QIB_RUNTIME_PCIE | QIB_RUNTIME_NODMA_RTAIL |
3525 QIB_RUNTIME_HDRSUPP | QIB_RUNTIME_SDMA;
3526 if (rcd->dd->cspec->r1)
3527 kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK;
3528 if (rcd->dd->flags & QIB_USE_SPCL_TRIG)
3529 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER;
3530
3531 return 0;
3532 }
3533
3534 static struct qib_message_header *
3535 qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
3536 {
3537 u32 offset = qib_hdrget_offset(rhf_addr);
3538
3539 return (struct qib_message_header *)
3540 (rhf_addr - dd->rhf_offset + offset);
3541 }
3542
3543 /*
3544 * Configure number of contexts.
3545 */
3546 static void qib_7322_config_ctxts(struct qib_devdata *dd)
3547 {
3548 unsigned long flags;
3549 u32 nchipctxts;
3550
3551 nchipctxts = qib_read_kreg32(dd, kr_contextcnt);
3552 dd->cspec->numctxts = nchipctxts;
3553 if (qib_n_krcv_queues > 1 && dd->num_pports) {
3554 dd->first_user_ctxt = NUM_IB_PORTS +
3555 (qib_n_krcv_queues - 1) * dd->num_pports;
3556 if (dd->first_user_ctxt > nchipctxts)
3557 dd->first_user_ctxt = nchipctxts;
3558 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports;
3559 } else {
3560 dd->first_user_ctxt = NUM_IB_PORTS;
3561 dd->n_krcv_queues = 1;
3562 }
3563
3564 if (!qib_cfgctxts) {
3565 int nctxts = dd->first_user_ctxt + num_online_cpus();
3566
3567 if (nctxts <= 6)
3568 dd->ctxtcnt = 6;
3569 else if (nctxts <= 10)
3570 dd->ctxtcnt = 10;
3571 else if (nctxts <= nchipctxts)
3572 dd->ctxtcnt = nchipctxts;
3573 } else if (qib_cfgctxts < dd->num_pports)
3574 dd->ctxtcnt = dd->num_pports;
3575 else if (qib_cfgctxts <= nchipctxts)
3576 dd->ctxtcnt = qib_cfgctxts;
3577 if (!dd->ctxtcnt) /* none of the above, set to max */
3578 dd->ctxtcnt = nchipctxts;
3579
3580 /*
3581 * Chip can be configured for 6, 10, or 18 ctxts, and choice
3582 * affects number of eager TIDs per ctxt (1K, 2K, 4K).
3583 * Lock to be paranoid about later motion, etc.
3584 */
3585 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
3586 if (dd->ctxtcnt > 10)
3587 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg);
3588 else if (dd->ctxtcnt > 6)
3589 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg);
3590 /* else configure for default 6 receive ctxts */
3591
3592 /* The XRC opcode is 5. */
3593 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode);
3594
3595 /*
3596 * RcvCtrl *must* be written here so that the
3597 * chip understands how to change rcvegrcnt below.
3598 */
3599 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
3600 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
3601
3602 /* kr_rcvegrcnt changes based on the number of contexts enabled */
3603 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3604 if (qib_rcvhdrcnt)
3605 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt);
3606 else
3607 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt,
3608 dd->num_pports > 1 ? 1024U : 2048U);
3609 }
3610
3611 static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which)
3612 {
3613
3614 int lsb, ret = 0;
3615 u64 maskr; /* right-justified mask */
3616
3617 switch (which) {
3618
3619 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */
3620 ret = ppd->link_width_enabled;
3621 goto done;
3622
3623 case QIB_IB_CFG_LWID: /* Get currently active Link-width */
3624 ret = ppd->link_width_active;
3625 goto done;
3626
3627 case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
3628 ret = ppd->link_speed_enabled;
3629 goto done;
3630
3631 case QIB_IB_CFG_SPD: /* Get current Link spd */
3632 ret = ppd->link_speed_active;
3633 goto done;
3634
3635 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
3636 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3637 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3638 break;
3639
3640 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
3641 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3642 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3643 break;
3644
3645 case QIB_IB_CFG_LINKLATENCY:
3646 ret = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
3647 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency);
3648 goto done;
3649
3650 case QIB_IB_CFG_OP_VLS:
3651 ret = ppd->vls_operational;
3652 goto done;
3653
3654 case QIB_IB_CFG_VL_HIGH_CAP:
3655 ret = 16;
3656 goto done;
3657
3658 case QIB_IB_CFG_VL_LOW_CAP:
3659 ret = 16;
3660 goto done;
3661
3662 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
3663 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3664 OverrunThreshold);
3665 goto done;
3666
3667 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
3668 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3669 PhyerrThreshold);
3670 goto done;
3671
3672 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
3673 /* will only take effect when the link state changes */
3674 ret = (ppd->cpspec->ibcctrl_a &
3675 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ?
3676 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
3677 goto done;
3678
3679 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
3680 lsb = IBA7322_IBC_HRTBT_LSB;
3681 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
3682 break;
3683
3684 case QIB_IB_CFG_PMA_TICKS:
3685 /*
3686 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs
3687 * Since the clock is always 250MHz, the value is 3, 1 or 0.
3688 */
3689 if (ppd->link_speed_active == QIB_IB_QDR)
3690 ret = 3;
3691 else if (ppd->link_speed_active == QIB_IB_DDR)
3692 ret = 1;
3693 else
3694 ret = 0;
3695 goto done;
3696
3697 default:
3698 ret = -EINVAL;
3699 goto done;
3700 }
3701 ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr);
3702 done:
3703 return ret;
3704 }
3705
3706 /*
3707 * Below again cribbed liberally from older version. Do not lean
3708 * heavily on it.
3709 */
3710 #define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB
3711 #define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \
3712 | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16))
3713
3714 static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
3715 {
3716 struct qib_devdata *dd = ppd->dd;
3717 u64 maskr; /* right-justified mask */
3718 int lsb, ret = 0;
3719 u16 lcmd, licmd;
3720 unsigned long flags;
3721
3722 switch (which) {
3723 case QIB_IB_CFG_LIDLMC:
3724 /*
3725 * Set LID and LMC. Combined to avoid possible hazard
3726 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
3727 */
3728 lsb = IBA7322_IBC_DLIDLMC_SHIFT;
3729 maskr = IBA7322_IBC_DLIDLMC_MASK;
3730 /*
3731 * For header-checking, the SLID in the packet will
3732 * be masked with SendIBSLMCMask, and compared
3733 * with SendIBSLIDAssignMask. Make sure we do not
3734 * set any bits not covered by the mask, or we get
3735 * false-positives.
3736 */
3737 qib_write_kreg_port(ppd, krp_sendslid,
3738 val & (val >> 16) & SendIBSLIDAssignMask);
3739 qib_write_kreg_port(ppd, krp_sendslidmask,
3740 (val >> 16) & SendIBSLMCMask);
3741 break;
3742
3743 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */
3744 ppd->link_width_enabled = val;
3745 /* convert IB value to chip register value */
3746 if (val == IB_WIDTH_1X)
3747 val = 0;
3748 else if (val == IB_WIDTH_4X)
3749 val = 1;
3750 else
3751 val = 3;
3752 maskr = SYM_RMASK(IBCCtrlB_0, IB_NUM_CHANNELS);
3753 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS);
3754 break;
3755
3756 case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */
3757 /*
3758 * As with width, only write the actual register if the
3759 * link is currently down, otherwise takes effect on next
3760 * link change. Since setting is being explicitly requested
3761 * (via MAD or sysfs), clear autoneg failure status if speed
3762 * autoneg is enabled.
3763 */
3764 ppd->link_speed_enabled = val;
3765 val <<= IBA7322_IBC_SPEED_LSB;
3766 maskr = IBA7322_IBC_SPEED_MASK | IBA7322_IBC_IBTA_1_2_MASK |
3767 IBA7322_IBC_MAX_SPEED_MASK;
3768 if (val & (val - 1)) {
3769 /* Muliple speeds enabled */
3770 val |= IBA7322_IBC_IBTA_1_2_MASK |
3771 IBA7322_IBC_MAX_SPEED_MASK;
3772 spin_lock_irqsave(&ppd->lflags_lock, flags);
3773 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3774 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3775 } else if (val & IBA7322_IBC_SPEED_QDR)
3776 val |= IBA7322_IBC_IBTA_1_2_MASK;
3777 /* IBTA 1.2 mode + min/max + speed bits are contiguous */
3778 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE);
3779 break;
3780
3781 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
3782 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3783 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3784 break;
3785
3786 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
3787 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3788 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3789 break;
3790
3791 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
3792 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3793 OverrunThreshold);
3794 if (maskr != val) {
3795 ppd->cpspec->ibcctrl_a &=
3796 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold);
3797 ppd->cpspec->ibcctrl_a |= (u64) val <<
3798 SYM_LSB(IBCCtrlA_0, OverrunThreshold);
3799 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3800 ppd->cpspec->ibcctrl_a);
3801 qib_write_kreg(dd, kr_scratch, 0ULL);
3802 }
3803 goto bail;
3804
3805 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
3806 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3807 PhyerrThreshold);
3808 if (maskr != val) {
3809 ppd->cpspec->ibcctrl_a &=
3810 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold);
3811 ppd->cpspec->ibcctrl_a |= (u64) val <<
3812 SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
3813 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3814 ppd->cpspec->ibcctrl_a);
3815 qib_write_kreg(dd, kr_scratch, 0ULL);
3816 }
3817 goto bail;
3818
3819 case QIB_IB_CFG_PKEYS: /* update pkeys */
3820 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
3821 ((u64) ppd->pkeys[2] << 32) |
3822 ((u64) ppd->pkeys[3] << 48);
3823 qib_write_kreg_port(ppd, krp_partitionkey, maskr);
3824 goto bail;
3825
3826 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
3827 /* will only take effect when the link state changes */
3828 if (val == IB_LINKINITCMD_POLL)
3829 ppd->cpspec->ibcctrl_a &=
3830 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3831 else /* SLEEP */
3832 ppd->cpspec->ibcctrl_a |=
3833 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3834 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
3835 qib_write_kreg(dd, kr_scratch, 0ULL);
3836 goto bail;
3837
3838 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
3839 /*
3840 * Update our housekeeping variables, and set IBC max
3841 * size, same as init code; max IBC is max we allow in
3842 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
3843 * Set even if it's unchanged, print debug message only
3844 * on changes.
3845 */
3846 val = (ppd->ibmaxlen >> 2) + 1;
3847 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen);
3848 ppd->cpspec->ibcctrl_a |= (u64)val <<
3849 SYM_LSB(IBCCtrlA_0, MaxPktLen);
3850 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3851 ppd->cpspec->ibcctrl_a);
3852 qib_write_kreg(dd, kr_scratch, 0ULL);
3853 goto bail;
3854
3855 case QIB_IB_CFG_LSTATE: /* set the IB link state */
3856 switch (val & 0xffff0000) {
3857 case IB_LINKCMD_DOWN:
3858 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
3859 ppd->cpspec->ibmalfusesnap = 1;
3860 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
3861 crp_errlink);
3862 if (!ppd->cpspec->ibdeltainprog &&
3863 qib_compat_ddr_negotiate) {
3864 ppd->cpspec->ibdeltainprog = 1;
3865 ppd->cpspec->ibsymsnap =
3866 read_7322_creg32_port(ppd,
3867 crp_ibsymbolerr);
3868 ppd->cpspec->iblnkerrsnap =
3869 read_7322_creg32_port(ppd,
3870 crp_iblinkerrrecov);
3871 }
3872 break;
3873
3874 case IB_LINKCMD_ARMED:
3875 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
3876 if (ppd->cpspec->ibmalfusesnap) {
3877 ppd->cpspec->ibmalfusesnap = 0;
3878 ppd->cpspec->ibmalfdelta +=
3879 read_7322_creg32_port(ppd,
3880 crp_errlink) -
3881 ppd->cpspec->ibmalfsnap;
3882 }
3883 break;
3884
3885 case IB_LINKCMD_ACTIVE:
3886 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
3887 break;
3888
3889 default:
3890 ret = -EINVAL;
3891 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
3892 goto bail;
3893 }
3894 switch (val & 0xffff) {
3895 case IB_LINKINITCMD_NOP:
3896 licmd = 0;
3897 break;
3898
3899 case IB_LINKINITCMD_POLL:
3900 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
3901 break;
3902
3903 case IB_LINKINITCMD_SLEEP:
3904 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
3905 break;
3906
3907 case IB_LINKINITCMD_DISABLE:
3908 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
3909 ppd->cpspec->chase_end = 0;
3910 /*
3911 * stop state chase counter and timer, if running.
3912 * wait forpending timer, but don't clear .data (ppd)!
3913 */
3914 if (ppd->cpspec->chase_timer.expires) {
3915 del_timer_sync(&ppd->cpspec->chase_timer);
3916 ppd->cpspec->chase_timer.expires = 0;
3917 }
3918 break;
3919
3920 default:
3921 ret = -EINVAL;
3922 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
3923 val & 0xffff);
3924 goto bail;
3925 }
3926 qib_set_ib_7322_lstate(ppd, lcmd, licmd);
3927 goto bail;
3928
3929 case QIB_IB_CFG_OP_VLS:
3930 if (ppd->vls_operational != val) {
3931 ppd->vls_operational = val;
3932 set_vls(ppd);
3933 }
3934 goto bail;
3935
3936 case QIB_IB_CFG_VL_HIGH_LIMIT:
3937 qib_write_kreg_port(ppd, krp_highprio_limit, val);
3938 goto bail;
3939
3940 case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
3941 if (val > 3) {
3942 ret = -EINVAL;
3943 goto bail;
3944 }
3945 lsb = IBA7322_IBC_HRTBT_LSB;
3946 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
3947 break;
3948
3949 case QIB_IB_CFG_PORT:
3950 /* val is the port number of the switch we are connected to. */
3951 if (ppd->dd->cspec->r1) {
3952 cancel_delayed_work(&ppd->cpspec->ipg_work);
3953 ppd->cpspec->ipg_tries = 0;
3954 }
3955 goto bail;
3956
3957 default:
3958 ret = -EINVAL;
3959 goto bail;
3960 }
3961 ppd->cpspec->ibcctrl_b &= ~(maskr << lsb);
3962 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb);
3963 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
3964 qib_write_kreg(dd, kr_scratch, 0);
3965 bail:
3966 return ret;
3967 }
3968
3969 static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what)
3970 {
3971 int ret = 0;
3972 u64 val, ctrlb;
3973
3974 /* only IBC loopback, may add serdes and xgxs loopbacks later */
3975 if (!strncmp(what, "ibc", 3)) {
3976 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0,
3977 Loopback);
3978 val = 0; /* disable heart beat, so link will come up */
3979 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
3980 ppd->dd->unit, ppd->port);
3981 } else if (!strncmp(what, "off", 3)) {
3982 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0,
3983 Loopback);
3984 /* enable heart beat again */
3985 val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB;
3986 qib_devinfo(ppd->dd->pcidev, "Disabling IB%u:%u IBC loopback "
3987 "(normal)\n", ppd->dd->unit, ppd->port);
3988 } else
3989 ret = -EINVAL;
3990 if (!ret) {
3991 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3992 ppd->cpspec->ibcctrl_a);
3993 ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK
3994 << IBA7322_IBC_HRTBT_LSB);
3995 ppd->cpspec->ibcctrl_b = ctrlb | val;
3996 qib_write_kreg_port(ppd, krp_ibcctrl_b,
3997 ppd->cpspec->ibcctrl_b);
3998 qib_write_kreg(ppd->dd, kr_scratch, 0);
3999 }
4000 return ret;
4001 }
4002
4003 static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4004 struct ib_vl_weight_elem *vl)
4005 {
4006 unsigned i;
4007
4008 for (i = 0; i < 16; i++, regno++, vl++) {
4009 u32 val = qib_read_kreg_port(ppd, regno);
4010
4011 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) &
4012 SYM_RMASK(LowPriority0_0, VirtualLane);
4013 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) &
4014 SYM_RMASK(LowPriority0_0, Weight);
4015 }
4016 }
4017
4018 static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4019 struct ib_vl_weight_elem *vl)
4020 {
4021 unsigned i;
4022
4023 for (i = 0; i < 16; i++, regno++, vl++) {
4024 u64 val;
4025
4026 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) <<
4027 SYM_LSB(LowPriority0_0, VirtualLane)) |
4028 ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) <<
4029 SYM_LSB(LowPriority0_0, Weight));
4030 qib_write_kreg_port(ppd, regno, val);
4031 }
4032 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) {
4033 struct qib_devdata *dd = ppd->dd;
4034 unsigned long flags;
4035
4036 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4037 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn);
4038 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4039 qib_write_kreg(dd, kr_scratch, 0);
4040 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4041 }
4042 }
4043
4044 static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t)
4045 {
4046 switch (which) {
4047 case QIB_IB_TBL_VL_HIGH_ARB:
4048 get_vl_weights(ppd, krp_highprio_0, t);
4049 break;
4050
4051 case QIB_IB_TBL_VL_LOW_ARB:
4052 get_vl_weights(ppd, krp_lowprio_0, t);
4053 break;
4054
4055 default:
4056 return -EINVAL;
4057 }
4058 return 0;
4059 }
4060
4061 static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t)
4062 {
4063 switch (which) {
4064 case QIB_IB_TBL_VL_HIGH_ARB:
4065 set_vl_weights(ppd, krp_highprio_0, t);
4066 break;
4067
4068 case QIB_IB_TBL_VL_LOW_ARB:
4069 set_vl_weights(ppd, krp_lowprio_0, t);
4070 break;
4071
4072 default:
4073 return -EINVAL;
4074 }
4075 return 0;
4076 }
4077
4078 static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd,
4079 u32 updegr, u32 egrhd, u32 npkts)
4080 {
4081 /*
4082 * Need to write timeout register before updating rcvhdrhead to ensure
4083 * that the timer is enabled on reception of a packet.
4084 */
4085 if (hd >> IBA7322_HDRHEAD_PKTINT_SHIFT)
4086 adjust_rcv_timeout(rcd, npkts);
4087 if (updegr)
4088 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
4089 mmiowb();
4090 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4091 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4092 mmiowb();
4093 }
4094
4095 static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd)
4096 {
4097 u32 head, tail;
4098
4099 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
4100 if (rcd->rcvhdrtail_kvaddr)
4101 tail = qib_get_rcvhdrtail(rcd);
4102 else
4103 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
4104 return head == tail;
4105 }
4106
4107 #define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \
4108 QIB_RCVCTRL_CTXT_DIS | \
4109 QIB_RCVCTRL_TIDFLOW_ENB | \
4110 QIB_RCVCTRL_TIDFLOW_DIS | \
4111 QIB_RCVCTRL_TAILUPD_ENB | \
4112 QIB_RCVCTRL_TAILUPD_DIS | \
4113 QIB_RCVCTRL_INTRAVAIL_ENB | \
4114 QIB_RCVCTRL_INTRAVAIL_DIS | \
4115 QIB_RCVCTRL_BP_ENB | \
4116 QIB_RCVCTRL_BP_DIS)
4117
4118 #define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \
4119 QIB_RCVCTRL_CTXT_DIS | \
4120 QIB_RCVCTRL_PKEY_DIS | \
4121 QIB_RCVCTRL_PKEY_ENB)
4122
4123 /*
4124 * Modify the RCVCTRL register in chip-specific way. This
4125 * is a function because bit positions and (future) register
4126 * location is chip-specifc, but the needed operations are
4127 * generic. <op> is a bit-mask because we often want to
4128 * do multiple modifications.
4129 */
4130 static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op,
4131 int ctxt)
4132 {
4133 struct qib_devdata *dd = ppd->dd;
4134 struct qib_ctxtdata *rcd;
4135 u64 mask, val;
4136 unsigned long flags;
4137
4138 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
4139
4140 if (op & QIB_RCVCTRL_TIDFLOW_ENB)
4141 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable);
4142 if (op & QIB_RCVCTRL_TIDFLOW_DIS)
4143 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable);
4144 if (op & QIB_RCVCTRL_TAILUPD_ENB)
4145 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4146 if (op & QIB_RCVCTRL_TAILUPD_DIS)
4147 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd);
4148 if (op & QIB_RCVCTRL_PKEY_ENB)
4149 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4150 if (op & QIB_RCVCTRL_PKEY_DIS)
4151 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4152 if (ctxt < 0) {
4153 mask = (1ULL << dd->ctxtcnt) - 1;
4154 rcd = NULL;
4155 } else {
4156 mask = (1ULL << ctxt);
4157 rcd = dd->rcd[ctxt];
4158 }
4159 if ((op & QIB_RCVCTRL_CTXT_ENB) && rcd) {
4160 ppd->p_rcvctrl |=
4161 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4162 if (!(dd->flags & QIB_NODMA_RTAIL)) {
4163 op |= QIB_RCVCTRL_TAILUPD_ENB; /* need reg write */
4164 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4165 }
4166 /* Write these registers before the context is enabled. */
4167 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt,
4168 rcd->rcvhdrqtailaddr_phys);
4169 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt,
4170 rcd->rcvhdrq_phys);
4171 rcd->seq_cnt = 1;
4172 }
4173 if (op & QIB_RCVCTRL_CTXT_DIS)
4174 ppd->p_rcvctrl &=
4175 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4176 if (op & QIB_RCVCTRL_BP_ENB)
4177 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull);
4178 if (op & QIB_RCVCTRL_BP_DIS)
4179 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull));
4180 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
4181 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail));
4182 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
4183 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail));
4184 /*
4185 * Decide which registers to write depending on the ops enabled.
4186 * Special case is "flush" (no bits set at all)
4187 * which needs to write both.
4188 */
4189 if (op == 0 || (op & RCVCTRL_COMMON_MODS))
4190 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
4191 if (op == 0 || (op & RCVCTRL_PORT_MODS))
4192 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
4193 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) {
4194 /*
4195 * Init the context registers also; if we were
4196 * disabled, tail and head should both be zero
4197 * already from the enable, but since we don't
4198 * know, we have to do it explicitly.
4199 */
4200 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
4201 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
4202
4203 /* be sure enabling write seen; hd/tl should be 0 */
4204 (void) qib_read_kreg32(dd, kr_scratch);
4205 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
4206 dd->rcd[ctxt]->head = val;
4207 /* If kctxt, interrupt on next receive. */
4208 if (ctxt < dd->first_user_ctxt)
4209 val |= dd->rhdrhead_intr_off;
4210 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4211 } else if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) &&
4212 dd->rcd[ctxt] && dd->rhdrhead_intr_off) {
4213 /* arm rcv interrupt */
4214 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off;
4215 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4216 }
4217 if (op & QIB_RCVCTRL_CTXT_DIS) {
4218 unsigned f;
4219
4220 /* Now that the context is disabled, clear these registers. */
4221 if (ctxt >= 0) {
4222 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0);
4223 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0);
4224 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4225 qib_write_ureg(dd, ur_rcvflowtable + f,
4226 TIDFLOW_ERRBITS, ctxt);
4227 } else {
4228 unsigned i;
4229
4230 for (i = 0; i < dd->cfgctxts; i++) {
4231 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr,
4232 i, 0);
4233 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0);
4234 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4235 qib_write_ureg(dd, ur_rcvflowtable + f,
4236 TIDFLOW_ERRBITS, i);
4237 }
4238 }
4239 }
4240 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
4241 }
4242
4243 /*
4244 * Modify the SENDCTRL register in chip-specific way. This
4245 * is a function where there are multiple such registers with
4246 * slightly different layouts.
4247 * The chip doesn't allow back-to-back sendctrl writes, so write
4248 * the scratch register after writing sendctrl.
4249 *
4250 * Which register is written depends on the operation.
4251 * Most operate on the common register, while
4252 * SEND_ENB and SEND_DIS operate on the per-port ones.
4253 * SEND_ENB is included in common because it can change SPCL_TRIG
4254 */
4255 #define SENDCTRL_COMMON_MODS (\
4256 QIB_SENDCTRL_CLEAR | \
4257 QIB_SENDCTRL_AVAIL_DIS | \
4258 QIB_SENDCTRL_AVAIL_ENB | \
4259 QIB_SENDCTRL_AVAIL_BLIP | \
4260 QIB_SENDCTRL_DISARM | \
4261 QIB_SENDCTRL_DISARM_ALL | \
4262 QIB_SENDCTRL_SEND_ENB)
4263
4264 #define SENDCTRL_PORT_MODS (\
4265 QIB_SENDCTRL_CLEAR | \
4266 QIB_SENDCTRL_SEND_ENB | \
4267 QIB_SENDCTRL_SEND_DIS | \
4268 QIB_SENDCTRL_FLUSH)
4269
4270 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op)
4271 {
4272 struct qib_devdata *dd = ppd->dd;
4273 u64 tmp_dd_sendctrl;
4274 unsigned long flags;
4275
4276 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4277
4278 /* First the dd ones that are "sticky", saved in shadow */
4279 if (op & QIB_SENDCTRL_CLEAR)
4280 dd->sendctrl = 0;
4281 if (op & QIB_SENDCTRL_AVAIL_DIS)
4282 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4283 else if (op & QIB_SENDCTRL_AVAIL_ENB) {
4284 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
4285 if (dd->flags & QIB_USE_SPCL_TRIG)
4286 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn);
4287 }
4288
4289 /* Then the ppd ones that are "sticky", saved in shadow */
4290 if (op & QIB_SENDCTRL_SEND_DIS)
4291 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
4292 else if (op & QIB_SENDCTRL_SEND_ENB)
4293 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
4294
4295 if (op & QIB_SENDCTRL_DISARM_ALL) {
4296 u32 i, last;
4297
4298 tmp_dd_sendctrl = dd->sendctrl;
4299 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
4300 /*
4301 * Disarm any buffers that are not yet launched,
4302 * disabling updates until done.
4303 */
4304 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4305 for (i = 0; i < last; i++) {
4306 qib_write_kreg(dd, kr_sendctrl,
4307 tmp_dd_sendctrl |
4308 SYM_MASK(SendCtrl, Disarm) | i);
4309 qib_write_kreg(dd, kr_scratch, 0);
4310 }
4311 }
4312
4313 if (op & QIB_SENDCTRL_FLUSH) {
4314 u64 tmp_ppd_sendctrl = ppd->p_sendctrl;
4315
4316 /*
4317 * Now drain all the fifos. The Abort bit should never be
4318 * needed, so for now, at least, we don't use it.
4319 */
4320 tmp_ppd_sendctrl |=
4321 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) |
4322 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) |
4323 SYM_MASK(SendCtrl_0, TxeBypassIbc);
4324 qib_write_kreg_port(ppd, krp_sendctrl, tmp_ppd_sendctrl);
4325 qib_write_kreg(dd, kr_scratch, 0);
4326 }
4327
4328 tmp_dd_sendctrl = dd->sendctrl;
4329
4330 if (op & QIB_SENDCTRL_DISARM)
4331 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
4332 ((op & QIB_7322_SendCtrl_DisarmSendBuf_RMASK) <<
4333 SYM_LSB(SendCtrl, DisarmSendBuf));
4334 if ((op & QIB_SENDCTRL_AVAIL_BLIP) &&
4335 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
4336 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4337
4338 if (op == 0 || (op & SENDCTRL_COMMON_MODS)) {
4339 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
4340 qib_write_kreg(dd, kr_scratch, 0);
4341 }
4342
4343 if (op == 0 || (op & SENDCTRL_PORT_MODS)) {
4344 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4345 qib_write_kreg(dd, kr_scratch, 0);
4346 }
4347
4348 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
4349 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
4350 qib_write_kreg(dd, kr_scratch, 0);
4351 }
4352
4353 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4354
4355 if (op & QIB_SENDCTRL_FLUSH) {
4356 u32 v;
4357 /*
4358 * ensure writes have hit chip, then do a few
4359 * more reads, to allow DMA of pioavail registers
4360 * to occur, so in-memory copy is in sync with
4361 * the chip. Not always safe to sleep.
4362 */
4363 v = qib_read_kreg32(dd, kr_scratch);
4364 qib_write_kreg(dd, kr_scratch, v);
4365 v = qib_read_kreg32(dd, kr_scratch);
4366 qib_write_kreg(dd, kr_scratch, v);
4367 qib_read_kreg32(dd, kr_scratch);
4368 }
4369 }
4370
4371 #define _PORT_VIRT_FLAG 0x8000U /* "virtual", need adjustments */
4372 #define _PORT_64BIT_FLAG 0x10000U /* not "virtual", but 64bit */
4373 #define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */
4374
4375 /**
4376 * qib_portcntr_7322 - read a per-port chip counter
4377 * @ppd: the qlogic_ib pport
4378 * @creg: the counter to read (not a chip offset)
4379 */
4380 static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg)
4381 {
4382 struct qib_devdata *dd = ppd->dd;
4383 u64 ret = 0ULL;
4384 u16 creg;
4385 /* 0xffff for unimplemented or synthesized counters */
4386 static const u32 xlator[] = {
4387 [QIBPORTCNTR_PKTSEND] = crp_pktsend | _PORT_64BIT_FLAG,
4388 [QIBPORTCNTR_WORDSEND] = crp_wordsend | _PORT_64BIT_FLAG,
4389 [QIBPORTCNTR_PSXMITDATA] = crp_psxmitdatacount,
4390 [QIBPORTCNTR_PSXMITPKTS] = crp_psxmitpktscount,
4391 [QIBPORTCNTR_PSXMITWAIT] = crp_psxmitwaitcount,
4392 [QIBPORTCNTR_SENDSTALL] = crp_sendstall,
4393 [QIBPORTCNTR_PKTRCV] = crp_pktrcv | _PORT_64BIT_FLAG,
4394 [QIBPORTCNTR_PSRCVDATA] = crp_psrcvdatacount,
4395 [QIBPORTCNTR_PSRCVPKTS] = crp_psrcvpktscount,
4396 [QIBPORTCNTR_RCVEBP] = crp_rcvebp,
4397 [QIBPORTCNTR_RCVOVFL] = crp_rcvovfl,
4398 [QIBPORTCNTR_WORDRCV] = crp_wordrcv | _PORT_64BIT_FLAG,
4399 [QIBPORTCNTR_RXDROPPKT] = 0xffff, /* not needed for 7322 */
4400 [QIBPORTCNTR_RXLOCALPHYERR] = crp_rxotherlocalphyerr,
4401 [QIBPORTCNTR_RXVLERR] = crp_rxvlerr,
4402 [QIBPORTCNTR_ERRICRC] = crp_erricrc,
4403 [QIBPORTCNTR_ERRVCRC] = crp_errvcrc,
4404 [QIBPORTCNTR_ERRLPCRC] = crp_errlpcrc,
4405 [QIBPORTCNTR_BADFORMAT] = crp_badformat,
4406 [QIBPORTCNTR_ERR_RLEN] = crp_err_rlen,
4407 [QIBPORTCNTR_IBSYMBOLERR] = crp_ibsymbolerr,
4408 [QIBPORTCNTR_INVALIDRLEN] = crp_invalidrlen,
4409 [QIBPORTCNTR_UNSUPVL] = crp_txunsupvl,
4410 [QIBPORTCNTR_EXCESSBUFOVFL] = crp_excessbufferovfl,
4411 [QIBPORTCNTR_ERRLINK] = crp_errlink,
4412 [QIBPORTCNTR_IBLINKDOWN] = crp_iblinkdown,
4413 [QIBPORTCNTR_IBLINKERRRECOV] = crp_iblinkerrrecov,
4414 [QIBPORTCNTR_LLI] = crp_locallinkintegrityerr,
4415 [QIBPORTCNTR_VL15PKTDROP] = crp_vl15droppedpkt,
4416 [QIBPORTCNTR_ERRPKEY] = crp_errpkey,
4417 /*
4418 * the next 3 aren't really counters, but were implemented
4419 * as counters in older chips, so still get accessed as
4420 * though they were counters from this code.
4421 */
4422 [QIBPORTCNTR_PSINTERVAL] = krp_psinterval,
4423 [QIBPORTCNTR_PSSTART] = krp_psstart,
4424 [QIBPORTCNTR_PSSTAT] = krp_psstat,
4425 /* pseudo-counter, summed for all ports */
4426 [QIBPORTCNTR_KHDROVFL] = 0xffff,
4427 };
4428
4429 if (reg >= ARRAY_SIZE(xlator)) {
4430 qib_devinfo(ppd->dd->pcidev,
4431 "Unimplemented portcounter %u\n", reg);
4432 goto done;
4433 }
4434 creg = xlator[reg] & _PORT_CNTR_IDXMASK;
4435
4436 /* handle non-counters and special cases first */
4437 if (reg == QIBPORTCNTR_KHDROVFL) {
4438 int i;
4439
4440 /* sum over all kernel contexts (skip if mini_init) */
4441 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) {
4442 struct qib_ctxtdata *rcd = dd->rcd[i];
4443
4444 if (!rcd || rcd->ppd != ppd)
4445 continue;
4446 ret += read_7322_creg32(dd, cr_base_egrovfl + i);
4447 }
4448 goto done;
4449 } else if (reg == QIBPORTCNTR_RXDROPPKT) {
4450 /*
4451 * Used as part of the synthesis of port_rcv_errors
4452 * in the verbs code for IBTA counters. Not needed for 7322,
4453 * because all the errors are already counted by other cntrs.
4454 */
4455 goto done;
4456 } else if (reg == QIBPORTCNTR_PSINTERVAL ||
4457 reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) {
4458 /* were counters in older chips, now per-port kernel regs */
4459 ret = qib_read_kreg_port(ppd, creg);
4460 goto done;
4461 }
4462
4463 /*
4464 * Only fast increment counters are 64 bits; use 32 bit reads to
4465 * avoid two independent reads when on Opteron.
4466 */
4467 if (xlator[reg] & _PORT_64BIT_FLAG)
4468 ret = read_7322_creg_port(ppd, creg);
4469 else
4470 ret = read_7322_creg32_port(ppd, creg);
4471 if (creg == crp_ibsymbolerr) {
4472 if (ppd->cpspec->ibdeltainprog)
4473 ret -= ret - ppd->cpspec->ibsymsnap;
4474 ret -= ppd->cpspec->ibsymdelta;
4475 } else if (creg == crp_iblinkerrrecov) {
4476 if (ppd->cpspec->ibdeltainprog)
4477 ret -= ret - ppd->cpspec->iblnkerrsnap;
4478 ret -= ppd->cpspec->iblnkerrdelta;
4479 } else if (creg == crp_errlink)
4480 ret -= ppd->cpspec->ibmalfdelta;
4481 else if (creg == crp_iblinkdown)
4482 ret += ppd->cpspec->iblnkdowndelta;
4483 done:
4484 return ret;
4485 }
4486
4487 /*
4488 * Device counter names (not port-specific), one line per stat,
4489 * single string. Used by utilities like ipathstats to print the stats
4490 * in a way which works for different versions of drivers, without changing
4491 * the utility. Names need to be 12 chars or less (w/o newline), for proper
4492 * display by utility.
4493 * Non-error counters are first.
4494 * Start of "error" conters is indicated by a leading "E " on the first
4495 * "error" counter, and doesn't count in label length.
4496 * The EgrOvfl list needs to be last so we truncate them at the configured
4497 * context count for the device.
4498 * cntr7322indices contains the corresponding register indices.
4499 */
4500 static const char cntr7322names[] =
4501 "Interrupts\n"
4502 "HostBusStall\n"
4503 "E RxTIDFull\n"
4504 "RxTIDInvalid\n"
4505 "RxTIDFloDrop\n" /* 7322 only */
4506 "Ctxt0EgrOvfl\n"
4507 "Ctxt1EgrOvfl\n"
4508 "Ctxt2EgrOvfl\n"
4509 "Ctxt3EgrOvfl\n"
4510 "Ctxt4EgrOvfl\n"
4511 "Ctxt5EgrOvfl\n"
4512 "Ctxt6EgrOvfl\n"
4513 "Ctxt7EgrOvfl\n"
4514 "Ctxt8EgrOvfl\n"
4515 "Ctxt9EgrOvfl\n"
4516 "Ctx10EgrOvfl\n"
4517 "Ctx11EgrOvfl\n"
4518 "Ctx12EgrOvfl\n"
4519 "Ctx13EgrOvfl\n"
4520 "Ctx14EgrOvfl\n"
4521 "Ctx15EgrOvfl\n"
4522 "Ctx16EgrOvfl\n"
4523 "Ctx17EgrOvfl\n"
4524 ;
4525
4526 static const u32 cntr7322indices[] = {
4527 cr_lbint | _PORT_64BIT_FLAG,
4528 cr_lbstall | _PORT_64BIT_FLAG,
4529 cr_tidfull,
4530 cr_tidinvalid,
4531 cr_rxtidflowdrop,
4532 cr_base_egrovfl + 0,
4533 cr_base_egrovfl + 1,
4534 cr_base_egrovfl + 2,
4535 cr_base_egrovfl + 3,
4536 cr_base_egrovfl + 4,
4537 cr_base_egrovfl + 5,
4538 cr_base_egrovfl + 6,
4539 cr_base_egrovfl + 7,
4540 cr_base_egrovfl + 8,
4541 cr_base_egrovfl + 9,
4542 cr_base_egrovfl + 10,
4543 cr_base_egrovfl + 11,
4544 cr_base_egrovfl + 12,
4545 cr_base_egrovfl + 13,
4546 cr_base_egrovfl + 14,
4547 cr_base_egrovfl + 15,
4548 cr_base_egrovfl + 16,
4549 cr_base_egrovfl + 17,
4550 };
4551
4552 /*
4553 * same as cntr7322names and cntr7322indices, but for port-specific counters.
4554 * portcntr7322indices is somewhat complicated by some registers needing
4555 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
4556 */
4557 static const char portcntr7322names[] =
4558 "TxPkt\n"
4559 "TxFlowPkt\n"
4560 "TxWords\n"
4561 "RxPkt\n"
4562 "RxFlowPkt\n"
4563 "RxWords\n"
4564 "TxFlowStall\n"
4565 "TxDmaDesc\n" /* 7220 and 7322-only */
4566 "E RxDlidFltr\n" /* 7220 and 7322-only */
4567 "IBStatusChng\n"
4568 "IBLinkDown\n"
4569 "IBLnkRecov\n"
4570 "IBRxLinkErr\n"
4571 "IBSymbolErr\n"
4572 "RxLLIErr\n"
4573 "RxBadFormat\n"
4574 "RxBadLen\n"
4575 "RxBufOvrfl\n"
4576 "RxEBP\n"
4577 "RxFlowCtlErr\n"
4578 "RxICRCerr\n"
4579 "RxLPCRCerr\n"
4580 "RxVCRCerr\n"
4581 "RxInvalLen\n"
4582 "RxInvalPKey\n"
4583 "RxPktDropped\n"
4584 "TxBadLength\n"
4585 "TxDropped\n"
4586 "TxInvalLen\n"
4587 "TxUnderrun\n"
4588 "TxUnsupVL\n"
4589 "RxLclPhyErr\n" /* 7220 and 7322-only from here down */
4590 "RxVL15Drop\n"
4591 "RxVlErr\n"
4592 "XcessBufOvfl\n"
4593 "RxQPBadCtxt\n" /* 7322-only from here down */
4594 "TXBadHeader\n"
4595 ;
4596
4597 static const u32 portcntr7322indices[] = {
4598 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
4599 crp_pktsendflow,
4600 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
4601 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
4602 crp_pktrcvflowctrl,
4603 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
4604 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
4605 crp_txsdmadesc | _PORT_64BIT_FLAG,
4606 crp_rxdlidfltr,
4607 crp_ibstatuschange,
4608 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
4609 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
4610 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
4611 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
4612 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
4613 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
4614 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
4615 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
4616 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
4617 crp_rcvflowctrlviol,
4618 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
4619 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
4620 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
4621 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
4622 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
4623 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
4624 crp_txminmaxlenerr,
4625 crp_txdroppedpkt,
4626 crp_txlenerr,
4627 crp_txunderrun,
4628 crp_txunsupvl,
4629 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG,
4630 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG,
4631 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG,
4632 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG,
4633 crp_rxqpinvalidctxt,
4634 crp_txhdrerr,
4635 };
4636
4637 /* do all the setup to make the counter reads efficient later */
4638 static void init_7322_cntrnames(struct qib_devdata *dd)
4639 {
4640 int i, j = 0;
4641 char *s;
4642
4643 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts;
4644 i++) {
4645 /* we always have at least one counter before the egrovfl */
4646 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
4647 j = 1;
4648 s = strchr(s + 1, '\n');
4649 if (s && j)
4650 j++;
4651 }
4652 dd->cspec->ncntrs = i;
4653 if (!s)
4654 /* full list; size is without terminating null */
4655 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1;
4656 else
4657 dd->cspec->cntrnamelen = 1 + s - cntr7322names;
4658 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
4659 * sizeof(u64), GFP_KERNEL);
4660 if (!dd->cspec->cntrs)
4661 qib_dev_err(dd, "Failed allocation for counters\n");
4662
4663 for (i = 0, s = (char *)portcntr7322names; s; i++)
4664 s = strchr(s + 1, '\n');
4665 dd->cspec->nportcntrs = i - 1;
4666 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1;
4667 for (i = 0; i < dd->num_pports; ++i) {
4668 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs
4669 * sizeof(u64), GFP_KERNEL);
4670 if (!dd->pport[i].cpspec->portcntrs)
4671 qib_dev_err(dd, "Failed allocation for"
4672 " portcounters\n");
4673 }
4674 }
4675
4676 static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
4677 u64 **cntrp)
4678 {
4679 u32 ret;
4680
4681 if (namep) {
4682 ret = dd->cspec->cntrnamelen;
4683 if (pos >= ret)
4684 ret = 0; /* final read after getting everything */
4685 else
4686 *namep = (char *) cntr7322names;
4687 } else {
4688 u64 *cntr = dd->cspec->cntrs;
4689 int i;
4690
4691 ret = dd->cspec->ncntrs * sizeof(u64);
4692 if (!cntr || pos >= ret) {
4693 /* everything read, or couldn't get memory */
4694 ret = 0;
4695 goto done;
4696 }
4697 *cntrp = cntr;
4698 for (i = 0; i < dd->cspec->ncntrs; i++)
4699 if (cntr7322indices[i] & _PORT_64BIT_FLAG)
4700 *cntr++ = read_7322_creg(dd,
4701 cntr7322indices[i] &
4702 _PORT_CNTR_IDXMASK);
4703 else
4704 *cntr++ = read_7322_creg32(dd,
4705 cntr7322indices[i]);
4706 }
4707 done:
4708 return ret;
4709 }
4710
4711 static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
4712 char **namep, u64 **cntrp)
4713 {
4714 u32 ret;
4715
4716 if (namep) {
4717 ret = dd->cspec->portcntrnamelen;
4718 if (pos >= ret)
4719 ret = 0; /* final read after getting everything */
4720 else
4721 *namep = (char *)portcntr7322names;
4722 } else {
4723 struct qib_pportdata *ppd = &dd->pport[port];
4724 u64 *cntr = ppd->cpspec->portcntrs;
4725 int i;
4726
4727 ret = dd->cspec->nportcntrs * sizeof(u64);
4728 if (!cntr || pos >= ret) {
4729 /* everything read, or couldn't get memory */
4730 ret = 0;
4731 goto done;
4732 }
4733 *cntrp = cntr;
4734 for (i = 0; i < dd->cspec->nportcntrs; i++) {
4735 if (portcntr7322indices[i] & _PORT_VIRT_FLAG)
4736 *cntr++ = qib_portcntr_7322(ppd,
4737 portcntr7322indices[i] &
4738 _PORT_CNTR_IDXMASK);
4739 else if (portcntr7322indices[i] & _PORT_64BIT_FLAG)
4740 *cntr++ = read_7322_creg_port(ppd,
4741 portcntr7322indices[i] &
4742 _PORT_CNTR_IDXMASK);
4743 else
4744 *cntr++ = read_7322_creg32_port(ppd,
4745 portcntr7322indices[i]);
4746 }
4747 }
4748 done:
4749 return ret;
4750 }
4751
4752 /**
4753 * qib_get_7322_faststats - get word counters from chip before they overflow
4754 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
4755 *
4756 * VESTIGIAL IBA7322 has no "small fast counters", so the only
4757 * real purpose of this function is to maintain the notion of
4758 * "active time", which in turn is only logged into the eeprom,
4759 * which we don;t have, yet, for 7322-based boards.
4760 *
4761 * called from add_timer
4762 */
4763 static void qib_get_7322_faststats(unsigned long opaque)
4764 {
4765 struct qib_devdata *dd = (struct qib_devdata *) opaque;
4766 struct qib_pportdata *ppd;
4767 unsigned long flags;
4768 u64 traffic_wds;
4769 int pidx;
4770
4771 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
4772 ppd = dd->pport + pidx;
4773
4774 /*
4775 * If port isn't enabled or not operational ports, or
4776 * diags is running (can cause memory diags to fail)
4777 * skip this port this time.
4778 */
4779 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED)
4780 || dd->diag_client)
4781 continue;
4782
4783 /*
4784 * Maintain an activity timer, based on traffic
4785 * exceeding a threshold, so we need to check the word-counts
4786 * even if they are 64-bit.
4787 */
4788 traffic_wds = qib_portcntr_7322(ppd, QIBPORTCNTR_WORDRCV) +
4789 qib_portcntr_7322(ppd, QIBPORTCNTR_WORDSEND);
4790 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags);
4791 traffic_wds -= ppd->dd->traffic_wds;
4792 ppd->dd->traffic_wds += traffic_wds;
4793 if (traffic_wds >= QIB_TRAFFIC_ACTIVE_THRESHOLD)
4794 atomic_add(ACTIVITY_TIMER, &ppd->dd->active_time);
4795 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags);
4796 if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active &
4797 QIB_IB_QDR) &&
4798 (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
4799 QIBL_LINKACTIVE)) &&
4800 ppd->cpspec->qdr_dfe_time &&
4801 time_after64(get_jiffies_64(), ppd->cpspec->qdr_dfe_time)) {
4802 ppd->cpspec->qdr_dfe_on = 0;
4803
4804 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
4805 ppd->dd->cspec->r1 ?
4806 QDR_STATIC_ADAPT_INIT_R1 :
4807 QDR_STATIC_ADAPT_INIT);
4808 force_h1(ppd);
4809 }
4810 }
4811 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
4812 }
4813
4814 /*
4815 * If we were using MSIx, try to fallback to INTx.
4816 */
4817 static int qib_7322_intr_fallback(struct qib_devdata *dd)
4818 {
4819 if (!dd->cspec->num_msix_entries)
4820 return 0; /* already using INTx */
4821
4822 qib_devinfo(dd->pcidev, "MSIx interrupt not detected,"
4823 " trying INTx interrupts\n");
4824 qib_7322_nomsix(dd);
4825 qib_enable_intx(dd->pcidev);
4826 qib_setup_7322_interrupt(dd, 0);
4827 return 1;
4828 }
4829
4830 /*
4831 * Reset the XGXS (between serdes and IBC). Slightly less intrusive
4832 * than resetting the IBC or external link state, and useful in some
4833 * cases to cause some retraining. To do this right, we reset IBC
4834 * as well, then return to previous state (which may be still in reset)
4835 * NOTE: some callers of this "know" this writes the current value
4836 * of cpspec->ibcctrl_a as part of it's operation, so if that changes,
4837 * check all callers.
4838 */
4839 static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd)
4840 {
4841 u64 val;
4842 struct qib_devdata *dd = ppd->dd;
4843 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) |
4844 SYM_MASK(IBPCSConfig_0, xcv_treset) |
4845 SYM_MASK(IBPCSConfig_0, tx_rx_reset);
4846
4847 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig);
4848 qib_write_kreg(dd, kr_hwerrmask,
4849 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop));
4850 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4851 ppd->cpspec->ibcctrl_a &
4852 ~SYM_MASK(IBCCtrlA_0, IBLinkEn));
4853
4854 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits);
4855 qib_read_kreg32(dd, kr_scratch);
4856 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits);
4857 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
4858 qib_write_kreg(dd, kr_scratch, 0ULL);
4859 qib_write_kreg(dd, kr_hwerrclear,
4860 SYM_MASK(HwErrClear, statusValidNoEopClear));
4861 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
4862 }
4863
4864 /*
4865 * This code for non-IBTA-compliant IB speed negotiation is only known to
4866 * work for the SDR to DDR transition, and only between an HCA and a switch
4867 * with recent firmware. It is based on observed heuristics, rather than
4868 * actual knowledge of the non-compliant speed negotiation.
4869 * It has a number of hard-coded fields, since the hope is to rewrite this
4870 * when a spec is available on how the negoation is intended to work.
4871 */
4872 static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr,
4873 u32 dcnt, u32 *data)
4874 {
4875 int i;
4876 u64 pbc;
4877 u32 __iomem *piobuf;
4878 u32 pnum, control, len;
4879 struct qib_devdata *dd = ppd->dd;
4880
4881 i = 0;
4882 len = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
4883 control = qib_7322_setpbc_control(ppd, len, 0, 15);
4884 pbc = ((u64) control << 32) | len;
4885 while (!(piobuf = qib_7322_getsendbuf(ppd, pbc, &pnum))) {
4886 if (i++ > 15)
4887 return;
4888 udelay(2);
4889 }
4890 /* disable header check on this packet, since it can't be valid */
4891 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL);
4892 writeq(pbc, piobuf);
4893 qib_flush_wc();
4894 qib_pio_copy(piobuf + 2, hdr, 7);
4895 qib_pio_copy(piobuf + 9, data, dcnt);
4896 if (dd->flags & QIB_USE_SPCL_TRIG) {
4897 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023;
4898
4899 qib_flush_wc();
4900 __raw_writel(0xaebecede, piobuf + spcl_off);
4901 }
4902 qib_flush_wc();
4903 qib_sendbuf_done(dd, pnum);
4904 /* and re-enable hdr check */
4905 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL);
4906 }
4907
4908 /*
4909 * _start packet gets sent twice at start, _done gets sent twice at end
4910 */
4911 static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which)
4912 {
4913 struct qib_devdata *dd = ppd->dd;
4914 static u32 swapped;
4915 u32 dw, i, hcnt, dcnt, *data;
4916 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
4917 static u32 madpayload_start[0x40] = {
4918 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4919 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4920 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
4921 };
4922 static u32 madpayload_done[0x40] = {
4923 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4924 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4925 0x40000001, 0x1388, 0x15e, /* rest 0's */
4926 };
4927
4928 dcnt = ARRAY_SIZE(madpayload_start);
4929 hcnt = ARRAY_SIZE(hdr);
4930 if (!swapped) {
4931 /* for maintainability, do it at runtime */
4932 for (i = 0; i < hcnt; i++) {
4933 dw = (__force u32) cpu_to_be32(hdr[i]);
4934 hdr[i] = dw;
4935 }
4936 for (i = 0; i < dcnt; i++) {
4937 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
4938 madpayload_start[i] = dw;
4939 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
4940 madpayload_done[i] = dw;
4941 }
4942 swapped = 1;
4943 }
4944
4945 data = which ? madpayload_done : madpayload_start;
4946
4947 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
4948 qib_read_kreg64(dd, kr_scratch);
4949 udelay(2);
4950 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
4951 qib_read_kreg64(dd, kr_scratch);
4952 udelay(2);
4953 }
4954
4955 /*
4956 * Do the absolute minimum to cause an IB speed change, and make it
4957 * ready, but don't actually trigger the change. The caller will
4958 * do that when ready (if link is in Polling training state, it will
4959 * happen immediately, otherwise when link next goes down)
4960 *
4961 * This routine should only be used as part of the DDR autonegotation
4962 * code for devices that are not compliant with IB 1.2 (or code that
4963 * fixes things up for same).
4964 *
4965 * When link has gone down, and autoneg enabled, or autoneg has
4966 * failed and we give up until next time we set both speeds, and
4967 * then we want IBTA enabled as well as "use max enabled speed.
4968 */
4969 static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed)
4970 {
4971 u64 newctrlb;
4972 newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK |
4973 IBA7322_IBC_IBTA_1_2_MASK |
4974 IBA7322_IBC_MAX_SPEED_MASK);
4975
4976 if (speed & (speed - 1)) /* multiple speeds */
4977 newctrlb |= (speed << IBA7322_IBC_SPEED_LSB) |
4978 IBA7322_IBC_IBTA_1_2_MASK |
4979 IBA7322_IBC_MAX_SPEED_MASK;
4980 else
4981 newctrlb |= speed == QIB_IB_QDR ?
4982 IBA7322_IBC_SPEED_QDR | IBA7322_IBC_IBTA_1_2_MASK :
4983 ((speed == QIB_IB_DDR ?
4984 IBA7322_IBC_SPEED_DDR : IBA7322_IBC_SPEED_SDR));
4985
4986 if (newctrlb == ppd->cpspec->ibcctrl_b)
4987 return;
4988
4989 ppd->cpspec->ibcctrl_b = newctrlb;
4990 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
4991 qib_write_kreg(ppd->dd, kr_scratch, 0);
4992 }
4993
4994 /*
4995 * This routine is only used when we are not talking to another
4996 * IB 1.2-compliant device that we think can do DDR.
4997 * (This includes all existing switch chips as of Oct 2007.)
4998 * 1.2-compliant devices go directly to DDR prior to reaching INIT
4999 */
5000 static void try_7322_autoneg(struct qib_pportdata *ppd)
5001 {
5002 unsigned long flags;
5003
5004 spin_lock_irqsave(&ppd->lflags_lock, flags);
5005 ppd->lflags |= QIBL_IB_AUTONEG_INPROG;
5006 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5007 qib_autoneg_7322_send(ppd, 0);
5008 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5009 qib_7322_mini_pcs_reset(ppd);
5010 /* 2 msec is minimum length of a poll cycle */
5011 queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work,
5012 msecs_to_jiffies(2));
5013 }
5014
5015 /*
5016 * Handle the empirically determined mechanism for auto-negotiation
5017 * of DDR speed with switches.
5018 */
5019 static void autoneg_7322_work(struct work_struct *work)
5020 {
5021 struct qib_pportdata *ppd;
5022 struct qib_devdata *dd;
5023 u64 startms;
5024 u32 i;
5025 unsigned long flags;
5026
5027 ppd = container_of(work, struct qib_chippport_specific,
5028 autoneg_work.work)->ppd;
5029 dd = ppd->dd;
5030
5031 startms = jiffies_to_msecs(jiffies);
5032
5033 /*
5034 * Busy wait for this first part, it should be at most a
5035 * few hundred usec, since we scheduled ourselves for 2msec.
5036 */
5037 for (i = 0; i < 25; i++) {
5038 if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState)
5039 == IB_7322_LT_STATE_POLLQUIET) {
5040 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE);
5041 break;
5042 }
5043 udelay(100);
5044 }
5045
5046 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
5047 goto done; /* we got there early or told to stop */
5048
5049 /* we expect this to timeout */
5050 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5051 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5052 msecs_to_jiffies(90)))
5053 goto done;
5054 qib_7322_mini_pcs_reset(ppd);
5055
5056 /* we expect this to timeout */
5057 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5058 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5059 msecs_to_jiffies(1700)))
5060 goto done;
5061 qib_7322_mini_pcs_reset(ppd);
5062
5063 set_7322_ibspeed_fast(ppd, QIB_IB_SDR);
5064
5065 /*
5066 * Wait up to 250 msec for link to train and get to INIT at DDR;
5067 * this should terminate early.
5068 */
5069 wait_event_timeout(ppd->cpspec->autoneg_wait,
5070 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5071 msecs_to_jiffies(250));
5072 done:
5073 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) {
5074 spin_lock_irqsave(&ppd->lflags_lock, flags);
5075 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
5076 if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) {
5077 ppd->lflags |= QIBL_IB_AUTONEG_FAILED;
5078 ppd->cpspec->autoneg_tries = 0;
5079 }
5080 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5081 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5082 }
5083 }
5084
5085 /*
5086 * This routine is used to request IPG set in the QLogic switch.
5087 * Only called if r1.
5088 */
5089 static void try_7322_ipg(struct qib_pportdata *ppd)
5090 {
5091 struct qib_ibport *ibp = &ppd->ibport_data;
5092 struct ib_mad_send_buf *send_buf;
5093 struct ib_mad_agent *agent;
5094 struct ib_smp *smp;
5095 unsigned delay;
5096 int ret;
5097
5098 agent = ibp->send_agent;
5099 if (!agent)
5100 goto retry;
5101
5102 send_buf = ib_create_send_mad(agent, 0, 0, 0, IB_MGMT_MAD_HDR,
5103 IB_MGMT_MAD_DATA, GFP_ATOMIC);
5104 if (IS_ERR(send_buf))
5105 goto retry;
5106
5107 if (!ibp->smi_ah) {
5108 struct ib_ah_attr attr;
5109 struct ib_ah *ah;
5110
5111 memset(&attr, 0, sizeof attr);
5112 attr.dlid = be16_to_cpu(IB_LID_PERMISSIVE);
5113 attr.port_num = ppd->port;
5114 ah = ib_create_ah(ibp->qp0->ibqp.pd, &attr);
5115 if (IS_ERR(ah))
5116 ret = -EINVAL;
5117 else {
5118 send_buf->ah = ah;
5119 ibp->smi_ah = to_iah(ah);
5120 ret = 0;
5121 }
5122 } else {
5123 send_buf->ah = &ibp->smi_ah->ibah;
5124 ret = 0;
5125 }
5126
5127 smp = send_buf->mad;
5128 smp->base_version = IB_MGMT_BASE_VERSION;
5129 smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE;
5130 smp->class_version = 1;
5131 smp->method = IB_MGMT_METHOD_SEND;
5132 smp->hop_cnt = 1;
5133 smp->attr_id = QIB_VENDOR_IPG;
5134 smp->attr_mod = 0;
5135
5136 if (!ret)
5137 ret = ib_post_send_mad(send_buf, NULL);
5138 if (ret)
5139 ib_free_send_mad(send_buf);
5140 retry:
5141 delay = 2 << ppd->cpspec->ipg_tries;
5142 queue_delayed_work(ib_wq, &ppd->cpspec->ipg_work,
5143 msecs_to_jiffies(delay));
5144 }
5145
5146 /*
5147 * Timeout handler for setting IPG.
5148 * Only called if r1.
5149 */
5150 static void ipg_7322_work(struct work_struct *work)
5151 {
5152 struct qib_pportdata *ppd;
5153
5154 ppd = container_of(work, struct qib_chippport_specific,
5155 ipg_work.work)->ppd;
5156 if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE))
5157 && ++ppd->cpspec->ipg_tries <= 10)
5158 try_7322_ipg(ppd);
5159 }
5160
5161 static u32 qib_7322_iblink_state(u64 ibcs)
5162 {
5163 u32 state = (u32)SYM_FIELD(ibcs, IBCStatusA_0, LinkState);
5164
5165 switch (state) {
5166 case IB_7322_L_STATE_INIT:
5167 state = IB_PORT_INIT;
5168 break;
5169 case IB_7322_L_STATE_ARM:
5170 state = IB_PORT_ARMED;
5171 break;
5172 case IB_7322_L_STATE_ACTIVE:
5173 /* fall through */
5174 case IB_7322_L_STATE_ACT_DEFER:
5175 state = IB_PORT_ACTIVE;
5176 break;
5177 default: /* fall through */
5178 case IB_7322_L_STATE_DOWN:
5179 state = IB_PORT_DOWN;
5180 break;
5181 }
5182 return state;
5183 }
5184
5185 /* returns the IBTA port state, rather than the IBC link training state */
5186 static u8 qib_7322_phys_portstate(u64 ibcs)
5187 {
5188 u8 state = (u8)SYM_FIELD(ibcs, IBCStatusA_0, LinkTrainingState);
5189 return qib_7322_physportstate[state];
5190 }
5191
5192 static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
5193 {
5194 int ret = 0, symadj = 0;
5195 unsigned long flags;
5196 int mult;
5197
5198 spin_lock_irqsave(&ppd->lflags_lock, flags);
5199 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
5200 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5201
5202 /* Update our picture of width and speed from chip */
5203 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) {
5204 ppd->link_speed_active = QIB_IB_QDR;
5205 mult = 4;
5206 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) {
5207 ppd->link_speed_active = QIB_IB_DDR;
5208 mult = 2;
5209 } else {
5210 ppd->link_speed_active = QIB_IB_SDR;
5211 mult = 1;
5212 }
5213 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) {
5214 ppd->link_width_active = IB_WIDTH_4X;
5215 mult *= 4;
5216 } else
5217 ppd->link_width_active = IB_WIDTH_1X;
5218 ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)];
5219
5220 if (!ibup) {
5221 u64 clr;
5222
5223 /* Link went down. */
5224 /* do IPG MAD again after linkdown, even if last time failed */
5225 ppd->cpspec->ipg_tries = 0;
5226 clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
5227 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) |
5228 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk));
5229 if (clr)
5230 qib_write_kreg_port(ppd, krp_ibcstatus_b, clr);
5231 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5232 QIBL_IB_AUTONEG_INPROG)))
5233 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5234 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5235 /* unlock the Tx settings, speed may change */
5236 qib_write_kreg_port(ppd, krp_tx_deemph_override,
5237 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
5238 reset_tx_deemphasis_override));
5239 qib_cancel_sends(ppd);
5240 /* on link down, ensure sane pcs state */
5241 qib_7322_mini_pcs_reset(ppd);
5242 spin_lock_irqsave(&ppd->sdma_lock, flags);
5243 if (__qib_sdma_running(ppd))
5244 __qib_sdma_process_event(ppd,
5245 qib_sdma_event_e70_go_idle);
5246 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
5247 }
5248 clr = read_7322_creg32_port(ppd, crp_iblinkdown);
5249 if (clr == ppd->cpspec->iblnkdownsnap)
5250 ppd->cpspec->iblnkdowndelta++;
5251 } else {
5252 if (qib_compat_ddr_negotiate &&
5253 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5254 QIBL_IB_AUTONEG_INPROG)) &&
5255 ppd->link_speed_active == QIB_IB_SDR &&
5256 (ppd->link_speed_enabled & QIB_IB_DDR)
5257 && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) {
5258 /* we are SDR, and auto-negotiation enabled */
5259 ++ppd->cpspec->autoneg_tries;
5260 if (!ppd->cpspec->ibdeltainprog) {
5261 ppd->cpspec->ibdeltainprog = 1;
5262 ppd->cpspec->ibsymdelta +=
5263 read_7322_creg32_port(ppd,
5264 crp_ibsymbolerr) -
5265 ppd->cpspec->ibsymsnap;
5266 ppd->cpspec->iblnkerrdelta +=
5267 read_7322_creg32_port(ppd,
5268 crp_iblinkerrrecov) -
5269 ppd->cpspec->iblnkerrsnap;
5270 }
5271 try_7322_autoneg(ppd);
5272 ret = 1; /* no other IB status change processing */
5273 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5274 ppd->link_speed_active == QIB_IB_SDR) {
5275 qib_autoneg_7322_send(ppd, 1);
5276 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5277 qib_7322_mini_pcs_reset(ppd);
5278 udelay(2);
5279 ret = 1; /* no other IB status change processing */
5280 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5281 (ppd->link_speed_active & QIB_IB_DDR)) {
5282 spin_lock_irqsave(&ppd->lflags_lock, flags);
5283 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG |
5284 QIBL_IB_AUTONEG_FAILED);
5285 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5286 ppd->cpspec->autoneg_tries = 0;
5287 /* re-enable SDR, for next link down */
5288 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5289 wake_up(&ppd->cpspec->autoneg_wait);
5290 symadj = 1;
5291 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) {
5292 /*
5293 * Clear autoneg failure flag, and do setup
5294 * so we'll try next time link goes down and
5295 * back to INIT (possibly connected to a
5296 * different device).
5297 */
5298 spin_lock_irqsave(&ppd->lflags_lock, flags);
5299 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
5300 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5301 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK;
5302 symadj = 1;
5303 }
5304 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5305 symadj = 1;
5306 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10)
5307 try_7322_ipg(ppd);
5308 if (!ppd->cpspec->recovery_init)
5309 setup_7322_link_recovery(ppd, 0);
5310 ppd->cpspec->qdr_dfe_time = jiffies +
5311 msecs_to_jiffies(QDR_DFE_DISABLE_DELAY);
5312 }
5313 ppd->cpspec->ibmalfusesnap = 0;
5314 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
5315 crp_errlink);
5316 }
5317 if (symadj) {
5318 ppd->cpspec->iblnkdownsnap =
5319 read_7322_creg32_port(ppd, crp_iblinkdown);
5320 if (ppd->cpspec->ibdeltainprog) {
5321 ppd->cpspec->ibdeltainprog = 0;
5322 ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd,
5323 crp_ibsymbolerr) - ppd->cpspec->ibsymsnap;
5324 ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd,
5325 crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap;
5326 }
5327 } else if (!ibup && qib_compat_ddr_negotiate &&
5328 !ppd->cpspec->ibdeltainprog &&
5329 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5330 ppd->cpspec->ibdeltainprog = 1;
5331 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
5332 crp_ibsymbolerr);
5333 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
5334 crp_iblinkerrrecov);
5335 }
5336
5337 if (!ret)
5338 qib_setup_7322_setextled(ppd, ibup);
5339 return ret;
5340 }
5341
5342 /*
5343 * Does read/modify/write to appropriate registers to
5344 * set output and direction bits selected by mask.
5345 * these are in their canonical postions (e.g. lsb of
5346 * dir will end up in D48 of extctrl on existing chips).
5347 * returns contents of GP Inputs.
5348 */
5349 static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
5350 {
5351 u64 read_val, new_out;
5352 unsigned long flags;
5353
5354 if (mask) {
5355 /* some bits being written, lock access to GPIO */
5356 dir &= mask;
5357 out &= mask;
5358 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5359 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5360 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
5361 new_out = (dd->cspec->gpio_out & ~mask) | out;
5362
5363 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5364 qib_write_kreg(dd, kr_gpio_out, new_out);
5365 dd->cspec->gpio_out = new_out;
5366 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5367 }
5368 /*
5369 * It is unlikely that a read at this time would get valid
5370 * data on a pin whose direction line was set in the same
5371 * call to this function. We include the read here because
5372 * that allows us to potentially combine a change on one pin with
5373 * a read on another, and because the old code did something like
5374 * this.
5375 */
5376 read_val = qib_read_kreg64(dd, kr_extstatus);
5377 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
5378 }
5379
5380 /* Enable writes to config EEPROM, if possible. Returns previous state */
5381 static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen)
5382 {
5383 int prev_wen;
5384 u32 mask;
5385
5386 mask = 1 << QIB_EEPROM_WEN_NUM;
5387 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM;
5388 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask);
5389
5390 return prev_wen & 1;
5391 }
5392
5393 /*
5394 * Read fundamental info we need to use the chip. These are
5395 * the registers that describe chip capabilities, and are
5396 * saved in shadow registers.
5397 */
5398 static void get_7322_chip_params(struct qib_devdata *dd)
5399 {
5400 u64 val;
5401 u32 piobufs;
5402 int mtu;
5403
5404 dd->palign = qib_read_kreg32(dd, kr_pagealign);
5405
5406 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
5407
5408 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
5409 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
5410 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
5411 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
5412 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
5413
5414 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
5415 dd->piobcnt2k = val & ~0U;
5416 dd->piobcnt4k = val >> 32;
5417 val = qib_read_kreg64(dd, kr_sendpiosize);
5418 dd->piosize2k = val & ~0U;
5419 dd->piosize4k = val >> 32;
5420
5421 mtu = ib_mtu_enum_to_int(qib_ibmtu);
5422 if (mtu == -1)
5423 mtu = QIB_DEFAULT_MTU;
5424 dd->pport[0].ibmtu = (u32)mtu;
5425 dd->pport[1].ibmtu = (u32)mtu;
5426
5427 /* these may be adjusted in init_chip_wc_pat() */
5428 dd->pio2kbase = (u32 __iomem *)
5429 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase);
5430 dd->pio4kbase = (u32 __iomem *)
5431 ((char __iomem *) dd->kregbase +
5432 (dd->piobufbase >> 32));
5433 /*
5434 * 4K buffers take 2 pages; we use roundup just to be
5435 * paranoid; we calculate it once here, rather than on
5436 * ever buf allocate
5437 */
5438 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
5439
5440 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS;
5441
5442 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
5443 (sizeof(u64) * BITS_PER_BYTE / 2);
5444 }
5445
5446 /*
5447 * The chip base addresses in cspec and cpspec have to be set
5448 * after possible init_chip_wc_pat(), rather than in
5449 * get_7322_chip_params(), so split out as separate function
5450 */
5451 static void qib_7322_set_baseaddrs(struct qib_devdata *dd)
5452 {
5453 u32 cregbase;
5454 cregbase = qib_read_kreg32(dd, kr_counterregbase);
5455
5456 dd->cspec->cregbase = (u64 __iomem *)(cregbase +
5457 (char __iomem *)dd->kregbase);
5458
5459 dd->egrtidbase = (u64 __iomem *)
5460 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
5461
5462 /* port registers are defined as relative to base of chip */
5463 dd->pport[0].cpspec->kpregbase =
5464 (u64 __iomem *)((char __iomem *)dd->kregbase);
5465 dd->pport[1].cpspec->kpregbase =
5466 (u64 __iomem *)(dd->palign +
5467 (char __iomem *)dd->kregbase);
5468 dd->pport[0].cpspec->cpregbase =
5469 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0],
5470 kr_counterregbase) + (char __iomem *)dd->kregbase);
5471 dd->pport[1].cpspec->cpregbase =
5472 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1],
5473 kr_counterregbase) + (char __iomem *)dd->kregbase);
5474 }
5475
5476 /*
5477 * This is a fairly special-purpose observer, so we only support
5478 * the port-specific parts of SendCtrl
5479 */
5480
5481 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \
5482 SYM_MASK(SendCtrl_0, SDmaEnable) | \
5483 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \
5484 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \
5485 SYM_MASK(SendCtrl_0, SDmaHalt) | \
5486 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \
5487 SYM_MASK(SendCtrl_0, ForceCreditUpToDate))
5488
5489 static int sendctrl_hook(struct qib_devdata *dd,
5490 const struct diag_observer *op, u32 offs,
5491 u64 *data, u64 mask, int only_32)
5492 {
5493 unsigned long flags;
5494 unsigned idx;
5495 unsigned pidx;
5496 struct qib_pportdata *ppd = NULL;
5497 u64 local_data, all_bits;
5498
5499 /*
5500 * The fixed correspondence between Physical ports and pports is
5501 * severed. We need to hunt for the ppd that corresponds
5502 * to the offset we got. And we have to do that without admitting
5503 * we know the stride, apparently.
5504 */
5505 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5506 u64 __iomem *psptr;
5507 u32 psoffs;
5508
5509 ppd = dd->pport + pidx;
5510 if (!ppd->cpspec->kpregbase)
5511 continue;
5512
5513 psptr = ppd->cpspec->kpregbase + krp_sendctrl;
5514 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr);
5515 if (psoffs == offs)
5516 break;
5517 }
5518
5519 /* If pport is not being managed by driver, just avoid shadows. */
5520 if (pidx >= dd->num_pports)
5521 ppd = NULL;
5522
5523 /* In any case, "idx" is flat index in kreg space */
5524 idx = offs / sizeof(u64);
5525
5526 all_bits = ~0ULL;
5527 if (only_32)
5528 all_bits >>= 32;
5529
5530 spin_lock_irqsave(&dd->sendctrl_lock, flags);
5531 if (!ppd || (mask & all_bits) != all_bits) {
5532 /*
5533 * At least some mask bits are zero, so we need
5534 * to read. The judgement call is whether from
5535 * reg or shadow. First-cut: read reg, and complain
5536 * if any bits which should be shadowed are different
5537 * from their shadowed value.
5538 */
5539 if (only_32)
5540 local_data = (u64)qib_read_kreg32(dd, idx);
5541 else
5542 local_data = qib_read_kreg64(dd, idx);
5543 *data = (local_data & ~mask) | (*data & mask);
5544 }
5545 if (mask) {
5546 /*
5547 * At least some mask bits are one, so we need
5548 * to write, but only shadow some bits.
5549 */
5550 u64 sval, tval; /* Shadowed, transient */
5551
5552 /*
5553 * New shadow val is bits we don't want to touch,
5554 * ORed with bits we do, that are intended for shadow.
5555 */
5556 if (ppd) {
5557 sval = ppd->p_sendctrl & ~mask;
5558 sval |= *data & SENDCTRL_SHADOWED & mask;
5559 ppd->p_sendctrl = sval;
5560 } else
5561 sval = *data & SENDCTRL_SHADOWED & mask;
5562 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
5563 qib_write_kreg(dd, idx, tval);
5564 qib_write_kreg(dd, kr_scratch, 0Ull);
5565 }
5566 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
5567 return only_32 ? 4 : 8;
5568 }
5569
5570 static const struct diag_observer sendctrl_0_observer = {
5571 sendctrl_hook, KREG_IDX(SendCtrl_0) * sizeof(u64),
5572 KREG_IDX(SendCtrl_0) * sizeof(u64)
5573 };
5574
5575 static const struct diag_observer sendctrl_1_observer = {
5576 sendctrl_hook, KREG_IDX(SendCtrl_1) * sizeof(u64),
5577 KREG_IDX(SendCtrl_1) * sizeof(u64)
5578 };
5579
5580 static ushort sdma_fetch_prio = 8;
5581 module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO);
5582 MODULE_PARM_DESC(sdma_fetch_prio, "SDMA descriptor fetch priority");
5583
5584 /* Besides logging QSFP events, we set appropriate TxDDS values */
5585 static void init_txdds_table(struct qib_pportdata *ppd, int override);
5586
5587 static void qsfp_7322_event(struct work_struct *work)
5588 {
5589 struct qib_qsfp_data *qd;
5590 struct qib_pportdata *ppd;
5591 u64 pwrup;
5592 int ret;
5593 u32 le2;
5594
5595 qd = container_of(work, struct qib_qsfp_data, work);
5596 ppd = qd->ppd;
5597 pwrup = qd->t_insert + msecs_to_jiffies(QSFP_PWR_LAG_MSEC);
5598
5599 /*
5600 * Some QSFP's not only do not respond until the full power-up
5601 * time, but may behave badly if we try. So hold off responding
5602 * to insertion.
5603 */
5604 while (1) {
5605 u64 now = get_jiffies_64();
5606 if (time_after64(now, pwrup))
5607 break;
5608 msleep(20);
5609 }
5610 ret = qib_refresh_qsfp_cache(ppd, &qd->cache);
5611 /*
5612 * Need to change LE2 back to defaults if we couldn't
5613 * read the cable type (to handle cable swaps), so do this
5614 * even on failure to read cable information. We don't
5615 * get here for QME, so IS_QME check not needed here.
5616 */
5617 if (!ret && !ppd->dd->cspec->r1) {
5618 if (QSFP_IS_ACTIVE_FAR(qd->cache.tech))
5619 le2 = LE2_QME;
5620 else if (qd->cache.atten[1] >= qib_long_atten &&
5621 QSFP_IS_CU(qd->cache.tech))
5622 le2 = LE2_5m;
5623 else
5624 le2 = LE2_DEFAULT;
5625 } else
5626 le2 = LE2_DEFAULT;
5627 ibsd_wr_allchans(ppd, 13, (le2 << 7), BMASK(9, 7));
5628 init_txdds_table(ppd, 0);
5629 }
5630
5631 /*
5632 * There is little we can do but complain to the user if QSFP
5633 * initialization fails.
5634 */
5635 static void qib_init_7322_qsfp(struct qib_pportdata *ppd)
5636 {
5637 unsigned long flags;
5638 struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data;
5639 struct qib_devdata *dd = ppd->dd;
5640 u64 mod_prs_bit = QSFP_GPIO_MOD_PRS_N;
5641
5642 mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
5643 qd->ppd = ppd;
5644 qib_qsfp_init(qd, qsfp_7322_event);
5645 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5646 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert));
5647 dd->cspec->gpio_mask |= mod_prs_bit;
5648 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5649 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
5650 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5651 }
5652
5653 /*
5654 * called at device initialization time, and also if the txselect
5655 * module parameter is changed. This is used for cables that don't
5656 * have valid QSFP EEPROMs (not present, or attenuation is zero).
5657 * We initialize to the default, then if there is a specific
5658 * unit,port match, we use that (and set it immediately, for the
5659 * current speed, if the link is at INIT or better).
5660 * String format is "default# unit#,port#=# ... u,p=#", separators must
5661 * be a SPACE character. A newline terminates. The u,p=# tuples may
5662 * optionally have "u,p=#,#", where the final # is the H1 value
5663 * The last specific match is used (actually, all are used, but last
5664 * one is the one that winds up set); if none at all, fall back on default.
5665 */
5666 static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
5667 {
5668 char *nxt, *str;
5669 u32 pidx, unit, port, deflt, h1;
5670 unsigned long val;
5671 int any = 0, seth1;
5672 int txdds_size;
5673
5674 str = txselect_list;
5675
5676 /* default number is validated in setup_txselect() */
5677 deflt = simple_strtoul(str, &nxt, 0);
5678 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5679 dd->pport[pidx].cpspec->no_eep = deflt;
5680
5681 txdds_size = TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ;
5682 if (IS_QME(dd) || IS_QMH(dd))
5683 txdds_size += TXDDS_MFG_SZ;
5684
5685 while (*nxt && nxt[1]) {
5686 str = ++nxt;
5687 unit = simple_strtoul(str, &nxt, 0);
5688 if (nxt == str || !*nxt || *nxt != ',') {
5689 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5690 ;
5691 continue;
5692 }
5693 str = ++nxt;
5694 port = simple_strtoul(str, &nxt, 0);
5695 if (nxt == str || *nxt != '=') {
5696 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5697 ;
5698 continue;
5699 }
5700 str = ++nxt;
5701 val = simple_strtoul(str, &nxt, 0);
5702 if (nxt == str) {
5703 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5704 ;
5705 continue;
5706 }
5707 if (val >= txdds_size)
5708 continue;
5709 seth1 = 0;
5710 h1 = 0; /* gcc thinks it might be used uninitted */
5711 if (*nxt == ',' && nxt[1]) {
5712 str = ++nxt;
5713 h1 = (u32)simple_strtoul(str, &nxt, 0);
5714 if (nxt == str)
5715 while (*nxt && *nxt++ != ' ') /* skip */
5716 ;
5717 else
5718 seth1 = 1;
5719 }
5720 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports;
5721 ++pidx) {
5722 struct qib_pportdata *ppd = &dd->pport[pidx];
5723
5724 if (ppd->port != port || !ppd->link_speed_supported)
5725 continue;
5726 ppd->cpspec->no_eep = val;
5727 if (seth1)
5728 ppd->cpspec->h1_val = h1;
5729 /* now change the IBC and serdes, overriding generic */
5730 init_txdds_table(ppd, 1);
5731 /* Re-enable the physical state machine on mezz boards
5732 * now that the correct settings have been set. */
5733 if (IS_QMH(dd) || IS_QME(dd))
5734 qib_set_ib_7322_lstate(ppd, 0,
5735 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP);
5736 any++;
5737 }
5738 if (*nxt == '\n')
5739 break; /* done */
5740 }
5741 if (change && !any) {
5742 /* no specific setting, use the default.
5743 * Change the IBC and serdes, but since it's
5744 * general, don't override specific settings.
5745 */
5746 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5747 if (dd->pport[pidx].link_speed_supported)
5748 init_txdds_table(&dd->pport[pidx], 0);
5749 }
5750 }
5751
5752 /* handle the txselect parameter changing */
5753 static int setup_txselect(const char *str, struct kernel_param *kp)
5754 {
5755 struct qib_devdata *dd;
5756 unsigned long val;
5757 char *n;
5758 if (strlen(str) >= MAX_ATTEN_LEN) {
5759 printk(KERN_INFO QIB_DRV_NAME " txselect_values string "
5760 "too long\n");
5761 return -ENOSPC;
5762 }
5763 val = simple_strtoul(str, &n, 0);
5764 if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
5765 TXDDS_MFG_SZ)) {
5766 printk(KERN_INFO QIB_DRV_NAME
5767 "txselect_values must start with a number < %d\n",
5768 TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ);
5769 return -EINVAL;
5770 }
5771 strcpy(txselect_list, str);
5772
5773 list_for_each_entry(dd, &qib_dev_list, list)
5774 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322)
5775 set_no_qsfp_atten(dd, 1);
5776 return 0;
5777 }
5778
5779 /*
5780 * Write the final few registers that depend on some of the
5781 * init setup. Done late in init, just before bringing up
5782 * the serdes.
5783 */
5784 static int qib_late_7322_initreg(struct qib_devdata *dd)
5785 {
5786 int ret = 0, n;
5787 u64 val;
5788
5789 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
5790 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
5791 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
5792 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
5793 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
5794 if (val != dd->pioavailregs_phys) {
5795 qib_dev_err(dd, "Catastrophic software error, "
5796 "SendPIOAvailAddr written as %lx, "
5797 "read back as %llx\n",
5798 (unsigned long) dd->pioavailregs_phys,
5799 (unsigned long long) val);
5800 ret = -EINVAL;
5801 }
5802
5803 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
5804 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL);
5805 /* driver sends get pkey, lid, etc. checking also, to catch bugs */
5806 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL);
5807
5808 qib_register_observer(dd, &sendctrl_0_observer);
5809 qib_register_observer(dd, &sendctrl_1_observer);
5810
5811 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN;
5812 qib_write_kreg(dd, kr_control, dd->control);
5813 /*
5814 * Set SendDmaFetchPriority and init Tx params, including
5815 * QSFP handler on boards that have QSFP.
5816 * First set our default attenuation entry for cables that
5817 * don't have valid attenuation.
5818 */
5819 set_no_qsfp_atten(dd, 0);
5820 for (n = 0; n < dd->num_pports; ++n) {
5821 struct qib_pportdata *ppd = dd->pport + n;
5822
5823 qib_write_kreg_port(ppd, krp_senddmaprioritythld,
5824 sdma_fetch_prio & 0xf);
5825 /* Initialize qsfp if present on board. */
5826 if (dd->flags & QIB_HAS_QSFP)
5827 qib_init_7322_qsfp(ppd);
5828 }
5829 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN;
5830 qib_write_kreg(dd, kr_control, dd->control);
5831
5832 return ret;
5833 }
5834
5835 /* per IB port errors. */
5836 #define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \
5837 MASK_ACROSS(8, 15))
5838 #define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41))
5839 #define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \
5840 MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \
5841 MASK_ACROSS(0, 11))
5842
5843 /*
5844 * Write the initialization per-port registers that need to be done at
5845 * driver load and after reset completes (i.e., that aren't done as part
5846 * of other init procedures called from qib_init.c).
5847 * Some of these should be redundant on reset, but play safe.
5848 */
5849 static void write_7322_init_portregs(struct qib_pportdata *ppd)
5850 {
5851 u64 val;
5852 int i;
5853
5854 if (!ppd->link_speed_supported) {
5855 /* no buffer credits for this port */
5856 for (i = 1; i < 8; i++)
5857 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
5858 qib_write_kreg_port(ppd, krp_ibcctrl_b, 0);
5859 qib_write_kreg(ppd->dd, kr_scratch, 0);
5860 return;
5861 }
5862
5863 /*
5864 * Set the number of supported virtual lanes in IBC,
5865 * for flow control packet handling on unsupported VLs
5866 */
5867 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
5868 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP);
5869 val |= (u64)(ppd->vls_supported - 1) <<
5870 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP);
5871 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
5872
5873 qib_write_kreg_port(ppd, krp_rcvbthqp, QIB_KD_QP);
5874
5875 /* enable tx header checking */
5876 qib_write_kreg_port(ppd, krp_sendcheckcontrol, IBA7322_SENDCHK_PKEY |
5877 IBA7322_SENDCHK_BTHQP | IBA7322_SENDCHK_SLID |
5878 IBA7322_SENDCHK_RAW_IPV6 | IBA7322_SENDCHK_MINSZ);
5879
5880 qib_write_kreg_port(ppd, krp_ncmodectrl,
5881 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal));
5882
5883 /*
5884 * Unconditionally clear the bufmask bits. If SDMA is
5885 * enabled, we'll set them appropriately later.
5886 */
5887 qib_write_kreg_port(ppd, krp_senddmabufmask0, 0);
5888 qib_write_kreg_port(ppd, krp_senddmabufmask1, 0);
5889 qib_write_kreg_port(ppd, krp_senddmabufmask2, 0);
5890 if (ppd->dd->cspec->r1)
5891 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate);
5892 }
5893
5894 /*
5895 * Write the initialization per-device registers that need to be done at
5896 * driver load and after reset completes (i.e., that aren't done as part
5897 * of other init procedures called from qib_init.c). Also write per-port
5898 * registers that are affected by overall device config, such as QP mapping
5899 * Some of these should be redundant on reset, but play safe.
5900 */
5901 static void write_7322_initregs(struct qib_devdata *dd)
5902 {
5903 struct qib_pportdata *ppd;
5904 int i, pidx;
5905 u64 val;
5906
5907 /* Set Multicast QPs received by port 2 to map to context one. */
5908 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1);
5909
5910 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5911 unsigned n, regno;
5912 unsigned long flags;
5913
5914 if (dd->n_krcv_queues < 2 ||
5915 !dd->pport[pidx].link_speed_supported)
5916 continue;
5917
5918 ppd = &dd->pport[pidx];
5919
5920 /* be paranoid against later code motion, etc. */
5921 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
5922 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable);
5923 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
5924
5925 /* Initialize QP to context mapping */
5926 regno = krp_rcvqpmaptable;
5927 val = 0;
5928 if (dd->num_pports > 1)
5929 n = dd->first_user_ctxt / dd->num_pports;
5930 else
5931 n = dd->first_user_ctxt - 1;
5932 for (i = 0; i < 32; ) {
5933 unsigned ctxt;
5934
5935 if (dd->num_pports > 1)
5936 ctxt = (i % n) * dd->num_pports + pidx;
5937 else if (i % n)
5938 ctxt = (i % n) + 1;
5939 else
5940 ctxt = ppd->hw_pidx;
5941 val |= ctxt << (5 * (i % 6));
5942 i++;
5943 if (i % 6 == 0) {
5944 qib_write_kreg_port(ppd, regno, val);
5945 val = 0;
5946 regno++;
5947 }
5948 }
5949 qib_write_kreg_port(ppd, regno, val);
5950 }
5951
5952 /*
5953 * Setup up interrupt mitigation for kernel contexts, but
5954 * not user contexts (user contexts use interrupts when
5955 * stalled waiting for any packet, so want those interrupts
5956 * right away).
5957 */
5958 for (i = 0; i < dd->first_user_ctxt; i++) {
5959 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout;
5960 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout);
5961 }
5962
5963 /*
5964 * Initialize as (disabled) rcvflow tables. Application code
5965 * will setup each flow as it uses the flow.
5966 * Doesn't clear any of the error bits that might be set.
5967 */
5968 val = TIDFLOW_ERRBITS; /* these are W1C */
5969 for (i = 0; i < dd->cfgctxts; i++) {
5970 int flow;
5971 for (flow = 0; flow < NUM_TIDFLOWS_CTXT; flow++)
5972 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i);
5973 }
5974
5975 /*
5976 * dual cards init to dual port recovery, single port cards to
5977 * the one port. Dual port cards may later adjust to 1 port,
5978 * and then back to dual port if both ports are connected
5979 * */
5980 if (dd->num_pports)
5981 setup_7322_link_recovery(dd->pport, dd->num_pports > 1);
5982 }
5983
5984 static int qib_init_7322_variables(struct qib_devdata *dd)
5985 {
5986 struct qib_pportdata *ppd;
5987 unsigned features, pidx, sbufcnt;
5988 int ret, mtu;
5989 u32 sbufs, updthresh;
5990
5991 /* pport structs are contiguous, allocated after devdata */
5992 ppd = (struct qib_pportdata *)(dd + 1);
5993 dd->pport = ppd;
5994 ppd[0].dd = dd;
5995 ppd[1].dd = dd;
5996
5997 dd->cspec = (struct qib_chip_specific *)(ppd + 2);
5998
5999 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1);
6000 ppd[1].cpspec = &ppd[0].cpspec[1];
6001 ppd[0].cpspec->ppd = &ppd[0]; /* for autoneg_7322_work() */
6002 ppd[1].cpspec->ppd = &ppd[1]; /* for autoneg_7322_work() */
6003
6004 spin_lock_init(&dd->cspec->rcvmod_lock);
6005 spin_lock_init(&dd->cspec->gpio_lock);
6006
6007 /* we haven't yet set QIB_PRESENT, so use read directly */
6008 dd->revision = readq(&dd->kregbase[kr_revision]);
6009
6010 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
6011 qib_dev_err(dd, "Revision register read failure, "
6012 "giving up initialization\n");
6013 ret = -ENODEV;
6014 goto bail;
6015 }
6016 dd->flags |= QIB_PRESENT; /* now register routines work */
6017
6018 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor);
6019 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor);
6020 dd->cspec->r1 = dd->minrev == 1;
6021
6022 get_7322_chip_params(dd);
6023 features = qib_7322_boardname(dd);
6024
6025 /* now that piobcnt2k and 4k set, we can allocate these */
6026 sbufcnt = dd->piobcnt2k + dd->piobcnt4k +
6027 NUM_VL15_BUFS + BITS_PER_LONG - 1;
6028 sbufcnt /= BITS_PER_LONG;
6029 dd->cspec->sendchkenable = kmalloc(sbufcnt *
6030 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL);
6031 dd->cspec->sendgrhchk = kmalloc(sbufcnt *
6032 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL);
6033 dd->cspec->sendibchk = kmalloc(sbufcnt *
6034 sizeof(*dd->cspec->sendibchk), GFP_KERNEL);
6035 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk ||
6036 !dd->cspec->sendibchk) {
6037 qib_dev_err(dd, "Failed allocation for hdrchk bitmaps\n");
6038 ret = -ENOMEM;
6039 goto bail;
6040 }
6041
6042 ppd = dd->pport;
6043
6044 /*
6045 * GPIO bits for TWSI data and clock,
6046 * used for serial EEPROM.
6047 */
6048 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
6049 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
6050 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV;
6051
6052 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY |
6053 QIB_NODMA_RTAIL | QIB_HAS_VLSUPP | QIB_HAS_HDRSUPP |
6054 QIB_HAS_THRESH_UPDATE |
6055 (sdma_idle_cnt ? QIB_HAS_SDMA_TIMEOUT : 0);
6056 dd->flags |= qib_special_trigger ?
6057 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
6058
6059 /*
6060 * Setup initial values. These may change when PAT is enabled, but
6061 * we need these to do initial chip register accesses.
6062 */
6063 qib_7322_set_baseaddrs(dd);
6064
6065 mtu = ib_mtu_enum_to_int(qib_ibmtu);
6066 if (mtu == -1)
6067 mtu = QIB_DEFAULT_MTU;
6068
6069 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT;
6070 /* all hwerrors become interrupts, unless special purposed */
6071 dd->cspec->hwerrmask = ~0ULL;
6072 /* link_recovery setup causes these errors, so ignore them,
6073 * other than clearing them when they occur */
6074 dd->cspec->hwerrmask &=
6075 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) |
6076 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) |
6077 HWE_MASK(LATriggered));
6078
6079 for (pidx = 0; pidx < NUM_IB_PORTS; ++pidx) {
6080 struct qib_chippport_specific *cp = ppd->cpspec;
6081 ppd->link_speed_supported = features & PORT_SPD_CAP;
6082 features >>= PORT_SPD_CAP_SHIFT;
6083 if (!ppd->link_speed_supported) {
6084 /* single port mode (7340, or configured) */
6085 dd->skip_kctxt_mask |= 1 << pidx;
6086 if (pidx == 0) {
6087 /* Make sure port is disabled. */
6088 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6089 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6090 ppd[0] = ppd[1];
6091 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6092 IBSerdesPClkNotDetectMask_0)
6093 | SYM_MASK(HwErrMask,
6094 SDmaMemReadErrMask_0));
6095 dd->cspec->int_enable_mask &= ~(
6096 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) |
6097 SYM_MASK(IntMask, SDmaIdleIntMask_0) |
6098 SYM_MASK(IntMask, SDmaProgressIntMask_0) |
6099 SYM_MASK(IntMask, SDmaIntMask_0) |
6100 SYM_MASK(IntMask, ErrIntMask_0) |
6101 SYM_MASK(IntMask, SendDoneIntMask_0));
6102 } else {
6103 /* Make sure port is disabled. */
6104 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6105 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6106 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6107 IBSerdesPClkNotDetectMask_1)
6108 | SYM_MASK(HwErrMask,
6109 SDmaMemReadErrMask_1));
6110 dd->cspec->int_enable_mask &= ~(
6111 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) |
6112 SYM_MASK(IntMask, SDmaIdleIntMask_1) |
6113 SYM_MASK(IntMask, SDmaProgressIntMask_1) |
6114 SYM_MASK(IntMask, SDmaIntMask_1) |
6115 SYM_MASK(IntMask, ErrIntMask_1) |
6116 SYM_MASK(IntMask, SendDoneIntMask_1));
6117 }
6118 continue;
6119 }
6120
6121 dd->num_pports++;
6122 qib_init_pportdata(ppd, dd, pidx, dd->num_pports);
6123
6124 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
6125 ppd->link_width_enabled = IB_WIDTH_4X;
6126 ppd->link_speed_enabled = ppd->link_speed_supported;
6127 /*
6128 * Set the initial values to reasonable default, will be set
6129 * for real when link is up.
6130 */
6131 ppd->link_width_active = IB_WIDTH_4X;
6132 ppd->link_speed_active = QIB_IB_SDR;
6133 ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS];
6134 switch (qib_num_cfg_vls) {
6135 case 1:
6136 ppd->vls_supported = IB_VL_VL0;
6137 break;
6138 case 2:
6139 ppd->vls_supported = IB_VL_VL0_1;
6140 break;
6141 default:
6142 qib_devinfo(dd->pcidev,
6143 "Invalid num_vls %u, using 4 VLs\n",
6144 qib_num_cfg_vls);
6145 qib_num_cfg_vls = 4;
6146 /* fall through */
6147 case 4:
6148 ppd->vls_supported = IB_VL_VL0_3;
6149 break;
6150 case 8:
6151 if (mtu <= 2048)
6152 ppd->vls_supported = IB_VL_VL0_7;
6153 else {
6154 qib_devinfo(dd->pcidev,
6155 "Invalid num_vls %u for MTU %d "
6156 ", using 4 VLs\n",
6157 qib_num_cfg_vls, mtu);
6158 ppd->vls_supported = IB_VL_VL0_3;
6159 qib_num_cfg_vls = 4;
6160 }
6161 break;
6162 }
6163 ppd->vls_operational = ppd->vls_supported;
6164
6165 init_waitqueue_head(&cp->autoneg_wait);
6166 INIT_DELAYED_WORK(&cp->autoneg_work,
6167 autoneg_7322_work);
6168 if (ppd->dd->cspec->r1)
6169 INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work);
6170
6171 /*
6172 * For Mez and similar cards, no qsfp info, so do
6173 * the "cable info" setup here. Can be overridden
6174 * in adapter-specific routines.
6175 */
6176 if (!(dd->flags & QIB_HAS_QSFP)) {
6177 if (!IS_QMH(dd) && !IS_QME(dd))
6178 qib_devinfo(dd->pcidev, "IB%u:%u: "
6179 "Unknown mezzanine card type\n",
6180 dd->unit, ppd->port);
6181 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME;
6182 /*
6183 * Choose center value as default tx serdes setting
6184 * until changed through module parameter.
6185 */
6186 ppd->cpspec->no_eep = IS_QMH(dd) ?
6187 TXDDS_TABLE_SZ + 2 : TXDDS_TABLE_SZ + 4;
6188 } else
6189 cp->h1_val = H1_FORCE_VAL;
6190
6191 /* Avoid writes to chip for mini_init */
6192 if (!qib_mini_init)
6193 write_7322_init_portregs(ppd);
6194
6195 init_timer(&cp->chase_timer);
6196 cp->chase_timer.function = reenable_chase;
6197 cp->chase_timer.data = (unsigned long)ppd;
6198
6199 ppd++;
6200 }
6201
6202 dd->rcvhdrentsize = qib_rcvhdrentsize ?
6203 qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE;
6204 dd->rcvhdrsize = qib_rcvhdrsize ?
6205 qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE;
6206 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
6207
6208 /* we always allocate at least 2048 bytes for eager buffers */
6209 dd->rcvegrbufsize = max(mtu, 2048);
6210
6211 qib_7322_tidtemplate(dd);
6212
6213 /*
6214 * We can request a receive interrupt for 1 or
6215 * more packets from current offset.
6216 */
6217 dd->rhdrhead_intr_off =
6218 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT;
6219
6220 /* setup the stats timer; the add_timer is done at end of init */
6221 init_timer(&dd->stats_timer);
6222 dd->stats_timer.function = qib_get_7322_faststats;
6223 dd->stats_timer.data = (unsigned long) dd;
6224
6225 dd->ureg_align = 0x10000; /* 64KB alignment */
6226
6227 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
6228
6229 qib_7322_config_ctxts(dd);
6230 qib_set_ctxtcnt(dd);
6231
6232 if (qib_wc_pat) {
6233 resource_size_t vl15off;
6234 /*
6235 * We do not set WC on the VL15 buffers to avoid
6236 * a rare problem with unaligned writes from
6237 * interrupt-flushed store buffers, so we need
6238 * to map those separately here. We can't solve
6239 * this for the rarely used mtrr case.
6240 */
6241 ret = init_chip_wc_pat(dd, 0);
6242 if (ret)
6243 goto bail;
6244
6245 /* vl15 buffers start just after the 4k buffers */
6246 vl15off = dd->physaddr + (dd->piobufbase >> 32) +
6247 dd->piobcnt4k * dd->align4k;
6248 dd->piovl15base = ioremap_nocache(vl15off,
6249 NUM_VL15_BUFS * dd->align4k);
6250 if (!dd->piovl15base)
6251 goto bail;
6252 }
6253 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */
6254
6255 ret = 0;
6256 if (qib_mini_init)
6257 goto bail;
6258 if (!dd->num_pports) {
6259 qib_dev_err(dd, "No ports enabled, giving up initialization\n");
6260 goto bail; /* no error, so can still figure out why err */
6261 }
6262
6263 write_7322_initregs(dd);
6264 ret = qib_create_ctxts(dd);
6265 init_7322_cntrnames(dd);
6266
6267 updthresh = 8U; /* update threshold */
6268
6269 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA.
6270 * reserve the update threshold amount for other kernel use, such
6271 * as sending SMI, MAD, and ACKs, or 3, whichever is greater,
6272 * unless we aren't enabling SDMA, in which case we want to use
6273 * all the 4k bufs for the kernel.
6274 * if this was less than the update threshold, we could wait
6275 * a long time for an update. Coded this way because we
6276 * sometimes change the update threshold for various reasons,
6277 * and we want this to remain robust.
6278 */
6279 if (dd->flags & QIB_HAS_SEND_DMA) {
6280 dd->cspec->sdmabufcnt = dd->piobcnt4k;
6281 sbufs = updthresh > 3 ? updthresh : 3;
6282 } else {
6283 dd->cspec->sdmabufcnt = 0;
6284 sbufs = dd->piobcnt4k;
6285 }
6286 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
6287 dd->cspec->sdmabufcnt;
6288 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
6289 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
6290 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ?
6291 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0;
6292
6293 /*
6294 * If we have 16 user contexts, we will have 7 sbufs
6295 * per context, so reduce the update threshold to match. We
6296 * want to update before we actually run out, at low pbufs/ctxt
6297 * so give ourselves some margin.
6298 */
6299 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh)
6300 updthresh = dd->pbufsctxt - 2;
6301 dd->cspec->updthresh_dflt = updthresh;
6302 dd->cspec->updthresh = updthresh;
6303
6304 /* before full enable, no interrupts, no locking needed */
6305 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld))
6306 << SYM_LSB(SendCtrl, AvailUpdThld)) |
6307 SYM_MASK(SendCtrl, SendBufAvailPad64Byte);
6308
6309 dd->psxmitwait_supported = 1;
6310 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE;
6311 bail:
6312 if (!dd->ctxtcnt)
6313 dd->ctxtcnt = 1; /* for other initialization code */
6314
6315 return ret;
6316 }
6317
6318 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
6319 u32 *pbufnum)
6320 {
6321 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
6322 struct qib_devdata *dd = ppd->dd;
6323
6324 /* last is same for 2k and 4k, because we use 4k if all 2k busy */
6325 if (pbc & PBC_7322_VL15_SEND) {
6326 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx;
6327 last = first;
6328 } else {
6329 if ((plen + 1) > dd->piosize2kmax_dwords)
6330 first = dd->piobcnt2k;
6331 else
6332 first = 0;
6333 last = dd->cspec->lastbuf_for_pio;
6334 }
6335 return qib_getsendbuf_range(dd, pbufnum, first, last);
6336 }
6337
6338 static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv,
6339 u32 start)
6340 {
6341 qib_write_kreg_port(ppd, krp_psinterval, intv);
6342 qib_write_kreg_port(ppd, krp_psstart, start);
6343 }
6344
6345 /*
6346 * Must be called with sdma_lock held, or before init finished.
6347 */
6348 static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
6349 {
6350 qib_write_kreg_port(ppd, krp_senddmadesccnt, cnt);
6351 }
6352
6353 static struct sdma_set_state_action sdma_7322_action_table[] = {
6354 [qib_sdma_state_s00_hw_down] = {
6355 .go_s99_running_tofalse = 1,
6356 .op_enable = 0,
6357 .op_intenable = 0,
6358 .op_halt = 0,
6359 .op_drain = 0,
6360 },
6361 [qib_sdma_state_s10_hw_start_up_wait] = {
6362 .op_enable = 0,
6363 .op_intenable = 1,
6364 .op_halt = 1,
6365 .op_drain = 0,
6366 },
6367 [qib_sdma_state_s20_idle] = {
6368 .op_enable = 1,
6369 .op_intenable = 1,
6370 .op_halt = 1,
6371 .op_drain = 0,
6372 },
6373 [qib_sdma_state_s30_sw_clean_up_wait] = {
6374 .op_enable = 0,
6375 .op_intenable = 1,
6376 .op_halt = 1,
6377 .op_drain = 0,
6378 },
6379 [qib_sdma_state_s40_hw_clean_up_wait] = {
6380 .op_enable = 1,
6381 .op_intenable = 1,
6382 .op_halt = 1,
6383 .op_drain = 0,
6384 },
6385 [qib_sdma_state_s50_hw_halt_wait] = {
6386 .op_enable = 1,
6387 .op_intenable = 1,
6388 .op_halt = 1,
6389 .op_drain = 1,
6390 },
6391 [qib_sdma_state_s99_running] = {
6392 .op_enable = 1,
6393 .op_intenable = 1,
6394 .op_halt = 0,
6395 .op_drain = 0,
6396 .go_s99_running_totrue = 1,
6397 },
6398 };
6399
6400 static void qib_7322_sdma_init_early(struct qib_pportdata *ppd)
6401 {
6402 ppd->sdma_state.set_state_action = sdma_7322_action_table;
6403 }
6404
6405 static int init_sdma_7322_regs(struct qib_pportdata *ppd)
6406 {
6407 struct qib_devdata *dd = ppd->dd;
6408 unsigned lastbuf, erstbuf;
6409 u64 senddmabufmask[3] = { 0 };
6410 int n, ret = 0;
6411
6412 qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys);
6413 qib_sdma_7322_setlengen(ppd);
6414 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
6415 qib_write_kreg_port(ppd, krp_senddmareloadcnt, sdma_idle_cnt);
6416 qib_write_kreg_port(ppd, krp_senddmadesccnt, 0);
6417 qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys);
6418
6419 if (dd->num_pports)
6420 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */
6421 else
6422 n = dd->cspec->sdmabufcnt; /* failsafe for init */
6423 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) -
6424 ((dd->num_pports == 1 || ppd->port == 2) ? n :
6425 dd->cspec->sdmabufcnt);
6426 lastbuf = erstbuf + n;
6427
6428 ppd->sdma_state.first_sendbuf = erstbuf;
6429 ppd->sdma_state.last_sendbuf = lastbuf;
6430 for (; erstbuf < lastbuf; ++erstbuf) {
6431 unsigned word = erstbuf / BITS_PER_LONG;
6432 unsigned bit = erstbuf & (BITS_PER_LONG - 1);
6433
6434 BUG_ON(word >= 3);
6435 senddmabufmask[word] |= 1ULL << bit;
6436 }
6437 qib_write_kreg_port(ppd, krp_senddmabufmask0, senddmabufmask[0]);
6438 qib_write_kreg_port(ppd, krp_senddmabufmask1, senddmabufmask[1]);
6439 qib_write_kreg_port(ppd, krp_senddmabufmask2, senddmabufmask[2]);
6440 return ret;
6441 }
6442
6443 /* sdma_lock must be held */
6444 static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd)
6445 {
6446 struct qib_devdata *dd = ppd->dd;
6447 int sane;
6448 int use_dmahead;
6449 u16 swhead;
6450 u16 swtail;
6451 u16 cnt;
6452 u16 hwhead;
6453
6454 use_dmahead = __qib_sdma_running(ppd) &&
6455 (dd->flags & QIB_HAS_SDMA_TIMEOUT);
6456 retry:
6457 hwhead = use_dmahead ?
6458 (u16) le64_to_cpu(*ppd->sdma_head_dma) :
6459 (u16) qib_read_kreg_port(ppd, krp_senddmahead);
6460
6461 swhead = ppd->sdma_descq_head;
6462 swtail = ppd->sdma_descq_tail;
6463 cnt = ppd->sdma_descq_cnt;
6464
6465 if (swhead < swtail)
6466 /* not wrapped */
6467 sane = (hwhead >= swhead) & (hwhead <= swtail);
6468 else if (swhead > swtail)
6469 /* wrapped around */
6470 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
6471 (hwhead <= swtail);
6472 else
6473 /* empty */
6474 sane = (hwhead == swhead);
6475
6476 if (unlikely(!sane)) {
6477 if (use_dmahead) {
6478 /* try one more time, directly from the register */
6479 use_dmahead = 0;
6480 goto retry;
6481 }
6482 /* proceed as if no progress */
6483 hwhead = swhead;
6484 }
6485
6486 return hwhead;
6487 }
6488
6489 static int qib_sdma_7322_busy(struct qib_pportdata *ppd)
6490 {
6491 u64 hwstatus = qib_read_kreg_port(ppd, krp_senddmastatus);
6492
6493 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) ||
6494 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) ||
6495 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) ||
6496 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty));
6497 }
6498
6499 /*
6500 * Compute the amount of delay before sending the next packet if the
6501 * port's send rate differs from the static rate set for the QP.
6502 * The delay affects the next packet and the amount of the delay is
6503 * based on the length of the this packet.
6504 */
6505 static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen,
6506 u8 srate, u8 vl)
6507 {
6508 u8 snd_mult = ppd->delay_mult;
6509 u8 rcv_mult = ib_rate_to_delay[srate];
6510 u32 ret;
6511
6512 ret = rcv_mult > snd_mult ? ((plen + 1) >> 1) * snd_mult : 0;
6513
6514 /* Indicate VL15, else set the VL in the control word */
6515 if (vl == 15)
6516 ret |= PBC_7322_VL15_SEND_CTRL;
6517 else
6518 ret |= vl << PBC_VL_NUM_LSB;
6519 ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB;
6520
6521 return ret;
6522 }
6523
6524 /*
6525 * Enable the per-port VL15 send buffers for use.
6526 * They follow the rest of the buffers, without a config parameter.
6527 * This was in initregs, but that is done before the shadow
6528 * is set up, and this has to be done after the shadow is
6529 * set up.
6530 */
6531 static void qib_7322_initvl15_bufs(struct qib_devdata *dd)
6532 {
6533 unsigned vl15bufs;
6534
6535 vl15bufs = dd->piobcnt2k + dd->piobcnt4k;
6536 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS,
6537 TXCHK_CHG_TYPE_KERN, NULL);
6538 }
6539
6540 static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd)
6541 {
6542 if (rcd->ctxt < NUM_IB_PORTS) {
6543 if (rcd->dd->num_pports > 1) {
6544 rcd->rcvegrcnt = KCTXT0_EGRCNT / 2;
6545 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0;
6546 } else {
6547 rcd->rcvegrcnt = KCTXT0_EGRCNT;
6548 rcd->rcvegr_tid_base = 0;
6549 }
6550 } else {
6551 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
6552 rcd->rcvegr_tid_base = KCTXT0_EGRCNT +
6553 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt;
6554 }
6555 }
6556
6557 #define QTXSLEEPS 5000
6558 static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start,
6559 u32 len, u32 which, struct qib_ctxtdata *rcd)
6560 {
6561 int i;
6562 const int last = start + len - 1;
6563 const int lastr = last / BITS_PER_LONG;
6564 u32 sleeps = 0;
6565 int wait = rcd != NULL;
6566 unsigned long flags;
6567
6568 while (wait) {
6569 unsigned long shadow;
6570 int cstart, previ = -1;
6571
6572 /*
6573 * when flipping from kernel to user, we can't change
6574 * the checking type if the buffer is allocated to the
6575 * driver. It's OK the other direction, because it's
6576 * from close, and we have just disarm'ed all the
6577 * buffers. All the kernel to kernel changes are also
6578 * OK.
6579 */
6580 for (cstart = start; cstart <= last; cstart++) {
6581 i = ((2 * cstart) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6582 / BITS_PER_LONG;
6583 if (i != previ) {
6584 shadow = (unsigned long)
6585 le64_to_cpu(dd->pioavailregs_dma[i]);
6586 previ = i;
6587 }
6588 if (test_bit(((2 * cstart) +
6589 QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6590 % BITS_PER_LONG, &shadow))
6591 break;
6592 }
6593
6594 if (cstart > last)
6595 break;
6596
6597 if (sleeps == QTXSLEEPS)
6598 break;
6599 /* make sure we see an updated copy next time around */
6600 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6601 sleeps++;
6602 msleep(20);
6603 }
6604
6605 switch (which) {
6606 case TXCHK_CHG_TYPE_DIS1:
6607 /*
6608 * disable checking on a range; used by diags; just
6609 * one buffer, but still written generically
6610 */
6611 for (i = start; i <= last; i++)
6612 clear_bit(i, dd->cspec->sendchkenable);
6613 break;
6614
6615 case TXCHK_CHG_TYPE_ENAB1:
6616 /*
6617 * (re)enable checking on a range; used by diags; just
6618 * one buffer, but still written generically; read
6619 * scratch to be sure buffer actually triggered, not
6620 * just flushed from processor.
6621 */
6622 qib_read_kreg32(dd, kr_scratch);
6623 for (i = start; i <= last; i++)
6624 set_bit(i, dd->cspec->sendchkenable);
6625 break;
6626
6627 case TXCHK_CHG_TYPE_KERN:
6628 /* usable by kernel */
6629 for (i = start; i <= last; i++) {
6630 set_bit(i, dd->cspec->sendibchk);
6631 clear_bit(i, dd->cspec->sendgrhchk);
6632 }
6633 spin_lock_irqsave(&dd->uctxt_lock, flags);
6634 /* see if we need to raise avail update threshold */
6635 for (i = dd->first_user_ctxt;
6636 dd->cspec->updthresh != dd->cspec->updthresh_dflt
6637 && i < dd->cfgctxts; i++)
6638 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt &&
6639 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1)
6640 < dd->cspec->updthresh_dflt)
6641 break;
6642 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
6643 if (i == dd->cfgctxts) {
6644 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6645 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
6646 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6647 dd->sendctrl |= (dd->cspec->updthresh &
6648 SYM_RMASK(SendCtrl, AvailUpdThld)) <<
6649 SYM_LSB(SendCtrl, AvailUpdThld);
6650 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6651 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6652 }
6653 break;
6654
6655 case TXCHK_CHG_TYPE_USER:
6656 /* for user process */
6657 for (i = start; i <= last; i++) {
6658 clear_bit(i, dd->cspec->sendibchk);
6659 set_bit(i, dd->cspec->sendgrhchk);
6660 }
6661 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6662 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt
6663 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
6664 dd->cspec->updthresh = (rcd->piocnt /
6665 rcd->subctxt_cnt) - 1;
6666 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6667 dd->sendctrl |= (dd->cspec->updthresh &
6668 SYM_RMASK(SendCtrl, AvailUpdThld))
6669 << SYM_LSB(SendCtrl, AvailUpdThld);
6670 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6671 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6672 } else
6673 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6674 break;
6675
6676 default:
6677 break;
6678 }
6679
6680 for (i = start / BITS_PER_LONG; which >= 2 && i <= lastr; ++i)
6681 qib_write_kreg(dd, kr_sendcheckmask + i,
6682 dd->cspec->sendchkenable[i]);
6683
6684 for (i = start / BITS_PER_LONG; which < 2 && i <= lastr; ++i) {
6685 qib_write_kreg(dd, kr_sendgrhcheckmask + i,
6686 dd->cspec->sendgrhchk[i]);
6687 qib_write_kreg(dd, kr_sendibpktmask + i,
6688 dd->cspec->sendibchk[i]);
6689 }
6690
6691 /*
6692 * Be sure whatever we did was seen by the chip and acted upon,
6693 * before we return. Mostly important for which >= 2.
6694 */
6695 qib_read_kreg32(dd, kr_scratch);
6696 }
6697
6698
6699 /* useful for trigger analyzers, etc. */
6700 static void writescratch(struct qib_devdata *dd, u32 val)
6701 {
6702 qib_write_kreg(dd, kr_scratch, val);
6703 }
6704
6705 /* Dummy for now, use chip regs soon */
6706 static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum)
6707 {
6708 return -ENXIO;
6709 }
6710
6711 /**
6712 * qib_init_iba7322_funcs - set up the chip-specific function pointers
6713 * @dev: the pci_dev for qlogic_ib device
6714 * @ent: pci_device_id struct for this dev
6715 *
6716 * Also allocates, inits, and returns the devdata struct for this
6717 * device instance
6718 *
6719 * This is global, and is called directly at init to set up the
6720 * chip-specific function pointers for later use.
6721 */
6722 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev,
6723 const struct pci_device_id *ent)
6724 {
6725 struct qib_devdata *dd;
6726 int ret, i;
6727 u32 tabsize, actual_cnt = 0;
6728
6729 dd = qib_alloc_devdata(pdev,
6730 NUM_IB_PORTS * sizeof(struct qib_pportdata) +
6731 sizeof(struct qib_chip_specific) +
6732 NUM_IB_PORTS * sizeof(struct qib_chippport_specific));
6733 if (IS_ERR(dd))
6734 goto bail;
6735
6736 dd->f_bringup_serdes = qib_7322_bringup_serdes;
6737 dd->f_cleanup = qib_setup_7322_cleanup;
6738 dd->f_clear_tids = qib_7322_clear_tids;
6739 dd->f_free_irq = qib_7322_free_irq;
6740 dd->f_get_base_info = qib_7322_get_base_info;
6741 dd->f_get_msgheader = qib_7322_get_msgheader;
6742 dd->f_getsendbuf = qib_7322_getsendbuf;
6743 dd->f_gpio_mod = gpio_7322_mod;
6744 dd->f_eeprom_wen = qib_7322_eeprom_wen;
6745 dd->f_hdrqempty = qib_7322_hdrqempty;
6746 dd->f_ib_updown = qib_7322_ib_updown;
6747 dd->f_init_ctxt = qib_7322_init_ctxt;
6748 dd->f_initvl15_bufs = qib_7322_initvl15_bufs;
6749 dd->f_intr_fallback = qib_7322_intr_fallback;
6750 dd->f_late_initreg = qib_late_7322_initreg;
6751 dd->f_setpbc_control = qib_7322_setpbc_control;
6752 dd->f_portcntr = qib_portcntr_7322;
6753 dd->f_put_tid = qib_7322_put_tid;
6754 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes;
6755 dd->f_rcvctrl = rcvctrl_7322_mod;
6756 dd->f_read_cntrs = qib_read_7322cntrs;
6757 dd->f_read_portcntrs = qib_read_7322portcntrs;
6758 dd->f_reset = qib_do_7322_reset;
6759 dd->f_init_sdma_regs = init_sdma_7322_regs;
6760 dd->f_sdma_busy = qib_sdma_7322_busy;
6761 dd->f_sdma_gethead = qib_sdma_7322_gethead;
6762 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl;
6763 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt;
6764 dd->f_sdma_update_tail = qib_sdma_update_7322_tail;
6765 dd->f_sendctrl = sendctrl_7322_mod;
6766 dd->f_set_armlaunch = qib_set_7322_armlaunch;
6767 dd->f_set_cntr_sample = qib_set_cntr_7322_sample;
6768 dd->f_iblink_state = qib_7322_iblink_state;
6769 dd->f_ibphys_portstate = qib_7322_phys_portstate;
6770 dd->f_get_ib_cfg = qib_7322_get_ib_cfg;
6771 dd->f_set_ib_cfg = qib_7322_set_ib_cfg;
6772 dd->f_set_ib_loopback = qib_7322_set_loopback;
6773 dd->f_get_ib_table = qib_7322_get_ib_table;
6774 dd->f_set_ib_table = qib_7322_set_ib_table;
6775 dd->f_set_intr_state = qib_7322_set_intr_state;
6776 dd->f_setextled = qib_setup_7322_setextled;
6777 dd->f_txchk_change = qib_7322_txchk_change;
6778 dd->f_update_usrhead = qib_update_7322_usrhead;
6779 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr;
6780 dd->f_xgxs_reset = qib_7322_mini_pcs_reset;
6781 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up;
6782 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up;
6783 dd->f_sdma_init_early = qib_7322_sdma_init_early;
6784 dd->f_writescratch = writescratch;
6785 dd->f_tempsense_rd = qib_7322_tempsense_rd;
6786 /*
6787 * Do remaining PCIe setup and save PCIe values in dd.
6788 * Any error printing is already done by the init code.
6789 * On return, we have the chip mapped, but chip registers
6790 * are not set up until start of qib_init_7322_variables.
6791 */
6792 ret = qib_pcie_ddinit(dd, pdev, ent);
6793 if (ret < 0)
6794 goto bail_free;
6795
6796 /* initialize chip-specific variables */
6797 ret = qib_init_7322_variables(dd);
6798 if (ret)
6799 goto bail_cleanup;
6800
6801 if (qib_mini_init || !dd->num_pports)
6802 goto bail;
6803
6804 /*
6805 * Determine number of vectors we want; depends on port count
6806 * and number of configured kernel receive queues actually used.
6807 * Should also depend on whether sdma is enabled or not, but
6808 * that's such a rare testing case it's not worth worrying about.
6809 */
6810 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table);
6811 for (i = 0; i < tabsize; i++)
6812 if ((i < ARRAY_SIZE(irq_table) &&
6813 irq_table[i].port <= dd->num_pports) ||
6814 (i >= ARRAY_SIZE(irq_table) &&
6815 dd->rcd[i - ARRAY_SIZE(irq_table)]))
6816 actual_cnt++;
6817 /* reduce by ctxt's < 2 */
6818 if (qib_krcvq01_no_msi)
6819 actual_cnt -= dd->num_pports;
6820
6821 tabsize = actual_cnt;
6822 dd->cspec->msix_entries = kmalloc(tabsize *
6823 sizeof(struct msix_entry), GFP_KERNEL);
6824 dd->cspec->msix_arg = kmalloc(tabsize *
6825 sizeof(void *), GFP_KERNEL);
6826 if (!dd->cspec->msix_entries || !dd->cspec->msix_arg) {
6827 qib_dev_err(dd, "No memory for MSIx table\n");
6828 tabsize = 0;
6829 }
6830 for (i = 0; i < tabsize; i++)
6831 dd->cspec->msix_entries[i].entry = i;
6832
6833 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries))
6834 qib_dev_err(dd, "Failed to setup PCIe or interrupts; "
6835 "continuing anyway\n");
6836 /* may be less than we wanted, if not enough available */
6837 dd->cspec->num_msix_entries = tabsize;
6838
6839 /* setup interrupt handler */
6840 qib_setup_7322_interrupt(dd, 1);
6841
6842 /* clear diagctrl register, in case diags were running and crashed */
6843 qib_write_kreg(dd, kr_hwdiagctrl, 0);
6844
6845 goto bail;
6846
6847 bail_cleanup:
6848 qib_pcie_ddcleanup(dd);
6849 bail_free:
6850 qib_free_devdata(dd);
6851 dd = ERR_PTR(ret);
6852 bail:
6853 return dd;
6854 }
6855
6856 /*
6857 * Set the table entry at the specified index from the table specifed.
6858 * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first
6859 * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR.
6860 * 'idx' below addresses the correct entry, while its 4 LSBs select the
6861 * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table.
6862 */
6863 #define DDS_ENT_AMP_LSB 14
6864 #define DDS_ENT_MAIN_LSB 9
6865 #define DDS_ENT_POST_LSB 5
6866 #define DDS_ENT_PRE_XTRA_LSB 3
6867 #define DDS_ENT_PRE_LSB 0
6868
6869 /*
6870 * Set one entry in the TxDDS table for spec'd port
6871 * ridx picks one of the entries, while tp points
6872 * to the appropriate table entry.
6873 */
6874 static void set_txdds(struct qib_pportdata *ppd, int ridx,
6875 const struct txdds_ent *tp)
6876 {
6877 struct qib_devdata *dd = ppd->dd;
6878 u32 pack_ent;
6879 int regidx;
6880
6881 /* Get correct offset in chip-space, and in source table */
6882 regidx = KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE) + ridx;
6883 /*
6884 * We do not use qib_write_kreg_port() because it was intended
6885 * only for registers in the lower "port specific" pages.
6886 * So do index calculation by hand.
6887 */
6888 if (ppd->hw_pidx)
6889 regidx += (dd->palign / sizeof(u64));
6890
6891 pack_ent = tp->amp << DDS_ENT_AMP_LSB;
6892 pack_ent |= tp->main << DDS_ENT_MAIN_LSB;
6893 pack_ent |= tp->pre << DDS_ENT_PRE_LSB;
6894 pack_ent |= tp->post << DDS_ENT_POST_LSB;
6895 qib_write_kreg(dd, regidx, pack_ent);
6896 /* Prevent back-to-back writes by hitting scratch */
6897 qib_write_kreg(ppd->dd, kr_scratch, 0);
6898 }
6899
6900 static const struct vendor_txdds_ent vendor_txdds[] = {
6901 { /* Amphenol 1m 30awg NoEq */
6902 { 0x41, 0x50, 0x48 }, "584470002 ",
6903 { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 },
6904 },
6905 { /* Amphenol 3m 28awg NoEq */
6906 { 0x41, 0x50, 0x48 }, "584470004 ",
6907 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 },
6908 },
6909 { /* Finisar 3m OM2 Optical */
6910 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL",
6911 { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 },
6912 },
6913 { /* Finisar 30m OM2 Optical */
6914 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL",
6915 { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 },
6916 },
6917 { /* Finisar Default OM2 Optical */
6918 { 0x00, 0x90, 0x65 }, NULL,
6919 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 },
6920 },
6921 { /* Gore 1m 30awg NoEq */
6922 { 0x00, 0x21, 0x77 }, "QSN3300-1 ",
6923 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 },
6924 },
6925 { /* Gore 2m 30awg NoEq */
6926 { 0x00, 0x21, 0x77 }, "QSN3300-2 ",
6927 { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 },
6928 },
6929 { /* Gore 1m 28awg NoEq */
6930 { 0x00, 0x21, 0x77 }, "QSN3800-1 ",
6931 { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 },
6932 },
6933 { /* Gore 3m 28awg NoEq */
6934 { 0x00, 0x21, 0x77 }, "QSN3800-3 ",
6935 { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 },
6936 },
6937 { /* Gore 5m 24awg Eq */
6938 { 0x00, 0x21, 0x77 }, "QSN7000-5 ",
6939 { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 },
6940 },
6941 { /* Gore 7m 24awg Eq */
6942 { 0x00, 0x21, 0x77 }, "QSN7000-7 ",
6943 { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 },
6944 },
6945 { /* Gore 5m 26awg Eq */
6946 { 0x00, 0x21, 0x77 }, "QSN7600-5 ",
6947 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 },
6948 },
6949 { /* Gore 7m 26awg Eq */
6950 { 0x00, 0x21, 0x77 }, "QSN7600-7 ",
6951 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 },
6952 },
6953 { /* Intersil 12m 24awg Active */
6954 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224",
6955 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 },
6956 },
6957 { /* Intersil 10m 28awg Active */
6958 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028",
6959 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 },
6960 },
6961 { /* Intersil 7m 30awg Active */
6962 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730",
6963 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 },
6964 },
6965 { /* Intersil 5m 32awg Active */
6966 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532",
6967 { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 },
6968 },
6969 { /* Intersil Default Active */
6970 { 0x00, 0x30, 0xB4 }, NULL,
6971 { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 },
6972 },
6973 { /* Luxtera 20m Active Optical */
6974 { 0x00, 0x25, 0x63 }, NULL,
6975 { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 },
6976 },
6977 { /* Molex 1M Cu loopback */
6978 { 0x00, 0x09, 0x3A }, "74763-0025 ",
6979 { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 },
6980 },
6981 { /* Molex 2m 28awg NoEq */
6982 { 0x00, 0x09, 0x3A }, "74757-2201 ",
6983 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 },
6984 },
6985 };
6986
6987 static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = {
6988 /* amp, pre, main, post */
6989 { 2, 2, 15, 6 }, /* Loopback */
6990 { 0, 0, 0, 1 }, /* 2 dB */
6991 { 0, 0, 0, 2 }, /* 3 dB */
6992 { 0, 0, 0, 3 }, /* 4 dB */
6993 { 0, 0, 0, 4 }, /* 5 dB */
6994 { 0, 0, 0, 5 }, /* 6 dB */
6995 { 0, 0, 0, 6 }, /* 7 dB */
6996 { 0, 0, 0, 7 }, /* 8 dB */
6997 { 0, 0, 0, 8 }, /* 9 dB */
6998 { 0, 0, 0, 9 }, /* 10 dB */
6999 { 0, 0, 0, 10 }, /* 11 dB */
7000 { 0, 0, 0, 11 }, /* 12 dB */
7001 { 0, 0, 0, 12 }, /* 13 dB */
7002 { 0, 0, 0, 13 }, /* 14 dB */
7003 { 0, 0, 0, 14 }, /* 15 dB */
7004 { 0, 0, 0, 15 }, /* 16 dB */
7005 };
7006
7007 static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = {
7008 /* amp, pre, main, post */
7009 { 2, 2, 15, 6 }, /* Loopback */
7010 { 0, 0, 0, 8 }, /* 2 dB */
7011 { 0, 0, 0, 8 }, /* 3 dB */
7012 { 0, 0, 0, 9 }, /* 4 dB */
7013 { 0, 0, 0, 9 }, /* 5 dB */
7014 { 0, 0, 0, 10 }, /* 6 dB */
7015 { 0, 0, 0, 10 }, /* 7 dB */
7016 { 0, 0, 0, 11 }, /* 8 dB */
7017 { 0, 0, 0, 11 }, /* 9 dB */
7018 { 0, 0, 0, 12 }, /* 10 dB */
7019 { 0, 0, 0, 12 }, /* 11 dB */
7020 { 0, 0, 0, 13 }, /* 12 dB */
7021 { 0, 0, 0, 13 }, /* 13 dB */
7022 { 0, 0, 0, 14 }, /* 14 dB */
7023 { 0, 0, 0, 14 }, /* 15 dB */
7024 { 0, 0, 0, 15 }, /* 16 dB */
7025 };
7026
7027 static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = {
7028 /* amp, pre, main, post */
7029 { 2, 2, 15, 6 }, /* Loopback */
7030 { 0, 1, 0, 7 }, /* 2 dB (also QMH7342) */
7031 { 0, 1, 0, 9 }, /* 3 dB (also QMH7342) */
7032 { 0, 1, 0, 11 }, /* 4 dB */
7033 { 0, 1, 0, 13 }, /* 5 dB */
7034 { 0, 1, 0, 15 }, /* 6 dB */
7035 { 0, 1, 3, 15 }, /* 7 dB */
7036 { 0, 1, 7, 15 }, /* 8 dB */
7037 { 0, 1, 7, 15 }, /* 9 dB */
7038 { 0, 1, 8, 15 }, /* 10 dB */
7039 { 0, 1, 9, 15 }, /* 11 dB */
7040 { 0, 1, 10, 15 }, /* 12 dB */
7041 { 0, 2, 6, 15 }, /* 13 dB */
7042 { 0, 2, 7, 15 }, /* 14 dB */
7043 { 0, 2, 8, 15 }, /* 15 dB */
7044 { 0, 2, 9, 15 }, /* 16 dB */
7045 };
7046
7047 /*
7048 * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ.
7049 * These are mostly used for mez cards going through connectors
7050 * and backplane traces, but can be used to add other "unusual"
7051 * table values as well.
7052 */
7053 static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = {
7054 /* amp, pre, main, post */
7055 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7056 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7057 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7058 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7059 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7060 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7061 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7062 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7063 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7064 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7065 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7066 { 0, 0, 0, 3 }, /* QMH7342 backplane settings */
7067 { 0, 0, 0, 4 }, /* QMH7342 backplane settings */
7068 };
7069
7070 static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = {
7071 /* amp, pre, main, post */
7072 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7073 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7074 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7075 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7076 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7077 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7078 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7079 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7080 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7081 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7082 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7083 { 0, 0, 0, 9 }, /* QMH7342 backplane settings */
7084 { 0, 0, 0, 10 }, /* QMH7342 backplane settings */
7085 };
7086
7087 static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = {
7088 /* amp, pre, main, post */
7089 { 0, 1, 0, 4 }, /* QMH7342 backplane settings */
7090 { 0, 1, 0, 5 }, /* QMH7342 backplane settings */
7091 { 0, 1, 0, 6 }, /* QMH7342 backplane settings */
7092 { 0, 1, 0, 8 }, /* QMH7342 backplane settings */
7093 { 0, 1, 12, 10 }, /* QME7342 backplane setting */
7094 { 0, 1, 12, 11 }, /* QME7342 backplane setting */
7095 { 0, 1, 12, 12 }, /* QME7342 backplane setting */
7096 { 0, 1, 12, 14 }, /* QME7342 backplane setting */
7097 { 0, 1, 12, 6 }, /* QME7342 backplane setting */
7098 { 0, 1, 12, 7 }, /* QME7342 backplane setting */
7099 { 0, 1, 12, 8 }, /* QME7342 backplane setting */
7100 { 0, 1, 0, 10 }, /* QMH7342 backplane settings */
7101 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */
7102 };
7103
7104 static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = {
7105 /* amp, pre, main, post */
7106 { 0, 0, 0, 0 }, /* QME7342 mfg settings */
7107 { 0, 0, 0, 6 }, /* QME7342 P2 mfg settings */
7108 };
7109
7110 static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds,
7111 unsigned atten)
7112 {
7113 /*
7114 * The attenuation table starts at 2dB for entry 1,
7115 * with entry 0 being the loopback entry.
7116 */
7117 if (atten <= 2)
7118 atten = 1;
7119 else if (atten > TXDDS_TABLE_SZ)
7120 atten = TXDDS_TABLE_SZ - 1;
7121 else
7122 atten--;
7123 return txdds + atten;
7124 }
7125
7126 /*
7127 * if override is set, the module parameter txselect has a value
7128 * for this specific port, so use it, rather than our normal mechanism.
7129 */
7130 static void find_best_ent(struct qib_pportdata *ppd,
7131 const struct txdds_ent **sdr_dds,
7132 const struct txdds_ent **ddr_dds,
7133 const struct txdds_ent **qdr_dds, int override)
7134 {
7135 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache;
7136 int idx;
7137
7138 /* Search table of known cables */
7139 for (idx = 0; !override && idx < ARRAY_SIZE(vendor_txdds); ++idx) {
7140 const struct vendor_txdds_ent *v = vendor_txdds + idx;
7141
7142 if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) &&
7143 (!v->partnum ||
7144 !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) {
7145 *sdr_dds = &v->sdr;
7146 *ddr_dds = &v->ddr;
7147 *qdr_dds = &v->qdr;
7148 return;
7149 }
7150 }
7151
7152 /* Lookup serdes setting by cable type and attenuation */
7153 if (!override && QSFP_IS_ACTIVE(qd->tech)) {
7154 *sdr_dds = txdds_sdr + ppd->dd->board_atten;
7155 *ddr_dds = txdds_ddr + ppd->dd->board_atten;
7156 *qdr_dds = txdds_qdr + ppd->dd->board_atten;
7157 return;
7158 }
7159
7160 if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] ||
7161 qd->atten[1])) {
7162 *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]);
7163 *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]);
7164 *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]);
7165 return;
7166 } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) {
7167 /*
7168 * If we have no (or incomplete) data from the cable
7169 * EEPROM, or no QSFP, or override is set, use the
7170 * module parameter value to index into the attentuation
7171 * table.
7172 */
7173 idx = ppd->cpspec->no_eep;
7174 *sdr_dds = &txdds_sdr[idx];
7175 *ddr_dds = &txdds_ddr[idx];
7176 *qdr_dds = &txdds_qdr[idx];
7177 } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) {
7178 /* similar to above, but index into the "extra" table. */
7179 idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ;
7180 *sdr_dds = &txdds_extra_sdr[idx];
7181 *ddr_dds = &txdds_extra_ddr[idx];
7182 *qdr_dds = &txdds_extra_qdr[idx];
7183 } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) &&
7184 ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
7185 TXDDS_MFG_SZ)) {
7186 idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ);
7187 printk(KERN_INFO QIB_DRV_NAME
7188 " IB%u:%u use idx %u into txdds_mfg\n",
7189 ppd->dd->unit, ppd->port, idx);
7190 *sdr_dds = &txdds_extra_mfg[idx];
7191 *ddr_dds = &txdds_extra_mfg[idx];
7192 *qdr_dds = &txdds_extra_mfg[idx];
7193 } else {
7194 /* this shouldn't happen, it's range checked */
7195 *sdr_dds = txdds_sdr + qib_long_atten;
7196 *ddr_dds = txdds_ddr + qib_long_atten;
7197 *qdr_dds = txdds_qdr + qib_long_atten;
7198 }
7199 }
7200
7201 static void init_txdds_table(struct qib_pportdata *ppd, int override)
7202 {
7203 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7204 struct txdds_ent *dds;
7205 int idx;
7206 int single_ent = 0;
7207
7208 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, override);
7209
7210 /* for mez cards or override, use the selected value for all entries */
7211 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override)
7212 single_ent = 1;
7213
7214 /* Fill in the first entry with the best entry found. */
7215 set_txdds(ppd, 0, sdr_dds);
7216 set_txdds(ppd, TXDDS_TABLE_SZ, ddr_dds);
7217 set_txdds(ppd, 2 * TXDDS_TABLE_SZ, qdr_dds);
7218 if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
7219 QIBL_LINKACTIVE)) {
7220 dds = (struct txdds_ent *)(ppd->link_speed_active ==
7221 QIB_IB_QDR ? qdr_dds :
7222 (ppd->link_speed_active ==
7223 QIB_IB_DDR ? ddr_dds : sdr_dds));
7224 write_tx_serdes_param(ppd, dds);
7225 }
7226
7227 /* Fill in the remaining entries with the default table values. */
7228 for (idx = 1; idx < ARRAY_SIZE(txdds_sdr); ++idx) {
7229 set_txdds(ppd, idx, single_ent ? sdr_dds : txdds_sdr + idx);
7230 set_txdds(ppd, idx + TXDDS_TABLE_SZ,
7231 single_ent ? ddr_dds : txdds_ddr + idx);
7232 set_txdds(ppd, idx + 2 * TXDDS_TABLE_SZ,
7233 single_ent ? qdr_dds : txdds_qdr + idx);
7234 }
7235 }
7236
7237 #define KR_AHB_ACC KREG_IDX(ahb_access_ctrl)
7238 #define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg)
7239 #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy)
7240 #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address)
7241 #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data)
7242 #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read)
7243 #define AHB_TRANS_TRIES 10
7244
7245 /*
7246 * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4,
7247 * 5=subsystem which is why most calls have "chan + chan >> 1"
7248 * for the channel argument.
7249 */
7250 static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr,
7251 u32 data, u32 mask)
7252 {
7253 u32 rd_data, wr_data, sz_mask;
7254 u64 trans, acc, prev_acc;
7255 u32 ret = 0xBAD0BAD;
7256 int tries;
7257
7258 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC);
7259 /* From this point on, make sure we return access */
7260 acc = (quad << 1) | 1;
7261 qib_write_kreg(dd, KR_AHB_ACC, acc);
7262
7263 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7264 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7265 if (trans & AHB_TRANS_RDY)
7266 break;
7267 }
7268 if (tries >= AHB_TRANS_TRIES) {
7269 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES);
7270 goto bail;
7271 }
7272
7273 /* If mask is not all 1s, we need to read, but different SerDes
7274 * entities have different sizes
7275 */
7276 sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1;
7277 wr_data = data & mask & sz_mask;
7278 if ((~mask & sz_mask) != 0) {
7279 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7280 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7281
7282 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7283 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7284 if (trans & AHB_TRANS_RDY)
7285 break;
7286 }
7287 if (tries >= AHB_TRANS_TRIES) {
7288 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n",
7289 AHB_TRANS_TRIES);
7290 goto bail;
7291 }
7292 /* Re-read in case host split reads and read data first */
7293 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7294 rd_data = (uint32_t)(trans >> AHB_DATA_LSB);
7295 wr_data |= (rd_data & ~mask & sz_mask);
7296 }
7297
7298 /* If mask is not zero, we need to write. */
7299 if (mask & sz_mask) {
7300 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7301 trans |= ((uint64_t)wr_data << AHB_DATA_LSB);
7302 trans |= AHB_WR;
7303 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7304
7305 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7306 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7307 if (trans & AHB_TRANS_RDY)
7308 break;
7309 }
7310 if (tries >= AHB_TRANS_TRIES) {
7311 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n",
7312 AHB_TRANS_TRIES);
7313 goto bail;
7314 }
7315 }
7316 ret = wr_data;
7317 bail:
7318 qib_write_kreg(dd, KR_AHB_ACC, prev_acc);
7319 return ret;
7320 }
7321
7322 static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data,
7323 unsigned mask)
7324 {
7325 struct qib_devdata *dd = ppd->dd;
7326 int chan;
7327 u32 rbc;
7328
7329 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7330 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr,
7331 data, mask);
7332 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7333 addr, 0, 0);
7334 }
7335 }
7336
7337 static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable)
7338 {
7339 u64 data = qib_read_kreg_port(ppd, krp_serdesctrl);
7340 u8 state = SYM_FIELD(data, IBSerdesCtrl_0, RXLOSEN);
7341
7342 if (enable && !state) {
7343 printk(KERN_INFO QIB_DRV_NAME " IB%u:%u Turning LOS on\n",
7344 ppd->dd->unit, ppd->port);
7345 data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7346 } else if (!enable && state) {
7347 printk(KERN_INFO QIB_DRV_NAME " IB%u:%u Turning LOS off\n",
7348 ppd->dd->unit, ppd->port);
7349 data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7350 }
7351 qib_write_kreg_port(ppd, krp_serdesctrl, data);
7352 }
7353
7354 static int serdes_7322_init(struct qib_pportdata *ppd)
7355 {
7356 int ret = 0;
7357 if (ppd->dd->cspec->r1)
7358 ret = serdes_7322_init_old(ppd);
7359 else
7360 ret = serdes_7322_init_new(ppd);
7361 return ret;
7362 }
7363
7364 static int serdes_7322_init_old(struct qib_pportdata *ppd)
7365 {
7366 u32 le_val;
7367
7368 /*
7369 * Initialize the Tx DDS tables. Also done every QSFP event,
7370 * for adapters with QSFP
7371 */
7372 init_txdds_table(ppd, 0);
7373
7374 /* ensure no tx overrides from earlier driver loads */
7375 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7376 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7377 reset_tx_deemphasis_override));
7378
7379 /* Patch some SerDes defaults to "Better for IB" */
7380 /* Timing Loop Bandwidth: cdr_timing[11:9] = 0 */
7381 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7382
7383 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7384 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7385 /* Enable LE2: rxle2en_r2a addr 13 bit [6] = 1 */
7386 ibsd_wr_allchans(ppd, 13, (1 << 6), (1 << 6));
7387
7388 /* May be overridden in qsfp_7322_event */
7389 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7390 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7391
7392 /* enable LE1 adaptation for all but QME, which is disabled */
7393 le_val = IS_QME(ppd->dd) ? 0 : 1;
7394 ibsd_wr_allchans(ppd, 13, (le_val << 5), (1 << 5));
7395
7396 /* Clear cmode-override, may be set from older driver */
7397 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7398
7399 /* Timing Recovery: rxtapsel addr 5 bits [9:8] = 0 */
7400 ibsd_wr_allchans(ppd, 5, (0 << 8), BMASK(9, 8));
7401
7402 /* setup LoS params; these are subsystem, so chan == 5 */
7403 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7404 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7405 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7406 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7407 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7408
7409 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7410 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7411 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7412 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7413 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7414
7415 /* LoS filter select enabled */
7416 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7417
7418 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7419 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7420 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7421 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7422
7423 serdes_7322_los_enable(ppd, 1);
7424
7425 /* rxbistena; set 0 to avoid effects of it switch later */
7426 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15);
7427
7428 /* Configure 4 DFE taps, and only they adapt */
7429 ibsd_wr_allchans(ppd, 16, 0 << 0, BMASK(1, 0));
7430
7431 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7432 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7433 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7434
7435 /*
7436 * Set receive adaptation mode. SDR and DDR adaptation are
7437 * always on, and QDR is initially enabled; later disabled.
7438 */
7439 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7440 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7441 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7442 ppd->dd->cspec->r1 ?
7443 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7444 ppd->cpspec->qdr_dfe_on = 1;
7445
7446 /* FLoop LOS gate: PPM filter enabled */
7447 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7448
7449 /* rx offset center enabled */
7450 ibsd_wr_allchans(ppd, 12, 1 << 4, 1 << 4);
7451
7452 if (!ppd->dd->cspec->r1) {
7453 ibsd_wr_allchans(ppd, 12, 1 << 12, 1 << 12);
7454 ibsd_wr_allchans(ppd, 12, 2 << 8, 0x0f << 8);
7455 }
7456
7457 /* Set the frequency loop bandwidth to 15 */
7458 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5));
7459
7460 return 0;
7461 }
7462
7463 static int serdes_7322_init_new(struct qib_pportdata *ppd)
7464 {
7465 u64 tstart;
7466 u32 le_val, rxcaldone;
7467 int chan, chan_done = (1 << SERDES_CHANS) - 1;
7468
7469 /*
7470 * Initialize the Tx DDS tables. Also done every QSFP event,
7471 * for adapters with QSFP
7472 */
7473 init_txdds_table(ppd, 0);
7474
7475 /* Clear cmode-override, may be set from older driver */
7476 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7477
7478 /* ensure no tx overrides from earlier driver loads */
7479 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7480 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7481 reset_tx_deemphasis_override));
7482
7483 /* START OF LSI SUGGESTED SERDES BRINGUP */
7484 /* Reset - Calibration Setup */
7485 /* Stop DFE adaptaion */
7486 ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1));
7487 /* Disable LE1 */
7488 ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5));
7489 /* Disable autoadapt for LE1 */
7490 ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15));
7491 /* Disable LE2 */
7492 ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6));
7493 /* Disable VGA */
7494 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
7495 /* Disable AFE Offset Cancel */
7496 ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12));
7497 /* Disable Timing Loop */
7498 ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3));
7499 /* Disable Frequency Loop */
7500 ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4));
7501 /* Disable Baseline Wander Correction */
7502 ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13));
7503 /* Disable RX Calibration */
7504 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
7505 /* Disable RX Offset Calibration */
7506 ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4));
7507 /* Select BB CDR */
7508 ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15));
7509 /* CDR Step Size */
7510 ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8));
7511 /* Enable phase Calibration */
7512 ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5));
7513 /* DFE Bandwidth [2:14-12] */
7514 ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12));
7515 /* DFE Config (4 taps only) */
7516 ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0));
7517 /* Gain Loop Bandwidth */
7518 if (!ppd->dd->cspec->r1) {
7519 ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12));
7520 ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8));
7521 } else {
7522 ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11));
7523 }
7524 /* Baseline Wander Correction Gain [13:4-0] (leave as default) */
7525 /* Baseline Wander Correction Gain [3:7-5] (leave as default) */
7526 /* Data Rate Select [5:7-6] (leave as default) */
7527 /* RX Parallel Word Width [3:10-8] (leave as default) */
7528
7529 /* RX REST */
7530 /* Single- or Multi-channel reset */
7531 /* RX Analog reset */
7532 /* RX Digital reset */
7533 ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13));
7534 msleep(20);
7535 /* RX Analog reset */
7536 ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14));
7537 msleep(20);
7538 /* RX Digital reset */
7539 ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13));
7540 msleep(20);
7541
7542 /* setup LoS params; these are subsystem, so chan == 5 */
7543 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7544 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7545 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7546 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7547 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7548
7549 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7550 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7551 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7552 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7553 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7554
7555 /* LoS filter select enabled */
7556 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7557
7558 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7559 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7560 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7561 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7562
7563 /* Turn on LOS on initial SERDES init */
7564 serdes_7322_los_enable(ppd, 1);
7565 /* FLoop LOS gate: PPM filter enabled */
7566 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7567
7568 /* RX LATCH CALIBRATION */
7569 /* Enable Eyefinder Phase Calibration latch */
7570 ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0));
7571 /* Enable RX Offset Calibration latch */
7572 ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4));
7573 msleep(20);
7574 /* Start Calibration */
7575 ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10));
7576 tstart = get_jiffies_64();
7577 while (chan_done &&
7578 !time_after64(get_jiffies_64(),
7579 tstart + msecs_to_jiffies(500))) {
7580 msleep(20);
7581 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7582 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
7583 (chan + (chan >> 1)),
7584 25, 0, 0);
7585 if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 &&
7586 (~chan_done & (1 << chan)) == 0)
7587 chan_done &= ~(1 << chan);
7588 }
7589 }
7590 if (chan_done) {
7591 printk(KERN_INFO QIB_DRV_NAME
7592 " Serdes %d calibration not done after .5 sec: 0x%x\n",
7593 IBSD(ppd->hw_pidx), chan_done);
7594 } else {
7595 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7596 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
7597 (chan + (chan >> 1)),
7598 25, 0, 0);
7599 if ((~rxcaldone & (u32)BMASK(10, 10)) == 0)
7600 printk(KERN_INFO QIB_DRV_NAME
7601 " Serdes %d chan %d calibration "
7602 "failed\n", IBSD(ppd->hw_pidx), chan);
7603 }
7604 }
7605
7606 /* Turn off Calibration */
7607 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
7608 msleep(20);
7609
7610 /* BRING RX UP */
7611 /* Set LE2 value (May be overridden in qsfp_7322_event) */
7612 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7613 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7614 /* Set LE2 Loop bandwidth */
7615 ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5));
7616 /* Enable LE2 */
7617 ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6));
7618 msleep(20);
7619 /* Enable H0 only */
7620 ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1));
7621 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7622 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7623 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7624 /* Enable VGA */
7625 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
7626 msleep(20);
7627 /* Set Frequency Loop Bandwidth */
7628 ibsd_wr_allchans(ppd, 2, (7 << 5), BMASK(8, 5));
7629 /* Enable Frequency Loop */
7630 ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4));
7631 /* Set Timing Loop Bandwidth */
7632 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7633 /* Enable Timing Loop */
7634 ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3));
7635 msleep(50);
7636 /* Enable DFE
7637 * Set receive adaptation mode. SDR and DDR adaptation are
7638 * always on, and QDR is initially enabled; later disabled.
7639 */
7640 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7641 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7642 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7643 ppd->dd->cspec->r1 ?
7644 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7645 ppd->cpspec->qdr_dfe_on = 1;
7646 /* Disable LE1 */
7647 ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5));
7648 /* Disable auto adapt for LE1 */
7649 ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15));
7650 msleep(20);
7651 /* Enable AFE Offset Cancel */
7652 ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12));
7653 /* Enable Baseline Wander Correction */
7654 ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13));
7655 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7656 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7657 /* VGA output common mode */
7658 ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2));
7659
7660 return 0;
7661 }
7662
7663 /* start adjust QMH serdes parameters */
7664
7665 static void set_man_code(struct qib_pportdata *ppd, int chan, int code)
7666 {
7667 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7668 9, code << 9, 0x3f << 9);
7669 }
7670
7671 static void set_man_mode_h1(struct qib_pportdata *ppd, int chan,
7672 int enable, u32 tapenable)
7673 {
7674 if (enable)
7675 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7676 1, 3 << 10, 0x1f << 10);
7677 else
7678 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7679 1, 0, 0x1f << 10);
7680 }
7681
7682 /* Set clock to 1, 0, 1, 0 */
7683 static void clock_man(struct qib_pportdata *ppd, int chan)
7684 {
7685 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7686 4, 0x4000, 0x4000);
7687 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7688 4, 0, 0x4000);
7689 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7690 4, 0x4000, 0x4000);
7691 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7692 4, 0, 0x4000);
7693 }
7694
7695 /*
7696 * write the current Tx serdes pre,post,main,amp settings into the serdes.
7697 * The caller must pass the settings appropriate for the current speed,
7698 * or not care if they are correct for the current speed.
7699 */
7700 static void write_tx_serdes_param(struct qib_pportdata *ppd,
7701 struct txdds_ent *txdds)
7702 {
7703 u64 deemph;
7704
7705 deemph = qib_read_kreg_port(ppd, krp_tx_deemph_override);
7706 /* field names for amp, main, post, pre, respectively */
7707 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) |
7708 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) |
7709 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) |
7710 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena));
7711
7712 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7713 tx_override_deemphasis_select);
7714 deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7715 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7716 txampcntl_d2a);
7717 deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7718 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7719 txc0_ena);
7720 deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7721 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7722 txcp1_ena);
7723 deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7724 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7725 txcn1_ena);
7726 qib_write_kreg_port(ppd, krp_tx_deemph_override, deemph);
7727 }
7728
7729 /*
7730 * Set the parameters for mez cards on link bounce, so they are
7731 * always exactly what was requested. Similar logic to init_txdds
7732 * but does just the serdes.
7733 */
7734 static void adj_tx_serdes(struct qib_pportdata *ppd)
7735 {
7736 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7737 struct txdds_ent *dds;
7738
7739 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, 1);
7740 dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ?
7741 qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ?
7742 ddr_dds : sdr_dds));
7743 write_tx_serdes_param(ppd, dds);
7744 }
7745
7746 /* set QDR forced value for H1, if needed */
7747 static void force_h1(struct qib_pportdata *ppd)
7748 {
7749 int chan;
7750
7751 ppd->cpspec->qdr_reforce = 0;
7752 if (!ppd->dd->cspec->r1)
7753 return;
7754
7755 for (chan = 0; chan < SERDES_CHANS; chan++) {
7756 set_man_mode_h1(ppd, chan, 1, 0);
7757 set_man_code(ppd, chan, ppd->cpspec->h1_val);
7758 clock_man(ppd, chan);
7759 set_man_mode_h1(ppd, chan, 0, 0);
7760 }
7761 }
7762
7763 #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN)
7764 #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en)
7765
7766 #define R_OPCODE_LSB 3
7767 #define R_OP_NOP 0
7768 #define R_OP_SHIFT 2
7769 #define R_OP_UPDATE 3
7770 #define R_TDI_LSB 2
7771 #define R_TDO_LSB 1
7772 #define R_RDY 1
7773
7774 static int qib_r_grab(struct qib_devdata *dd)
7775 {
7776 u64 val;
7777 val = SJA_EN;
7778 qib_write_kreg(dd, kr_r_access, val);
7779 qib_read_kreg32(dd, kr_scratch);
7780 return 0;
7781 }
7782
7783 /* qib_r_wait_for_rdy() not only waits for the ready bit, it
7784 * returns the current state of R_TDO
7785 */
7786 static int qib_r_wait_for_rdy(struct qib_devdata *dd)
7787 {
7788 u64 val;
7789 int timeout;
7790 for (timeout = 0; timeout < 100 ; ++timeout) {
7791 val = qib_read_kreg32(dd, kr_r_access);
7792 if (val & R_RDY)
7793 return (val >> R_TDO_LSB) & 1;
7794 }
7795 return -1;
7796 }
7797
7798 static int qib_r_shift(struct qib_devdata *dd, int bisten,
7799 int len, u8 *inp, u8 *outp)
7800 {
7801 u64 valbase, val;
7802 int ret, pos;
7803
7804 valbase = SJA_EN | (bisten << BISTEN_LSB) |
7805 (R_OP_SHIFT << R_OPCODE_LSB);
7806 ret = qib_r_wait_for_rdy(dd);
7807 if (ret < 0)
7808 goto bail;
7809 for (pos = 0; pos < len; ++pos) {
7810 val = valbase;
7811 if (outp) {
7812 outp[pos >> 3] &= ~(1 << (pos & 7));
7813 outp[pos >> 3] |= (ret << (pos & 7));
7814 }
7815 if (inp) {
7816 int tdi = inp[pos >> 3] >> (pos & 7);
7817 val |= ((tdi & 1) << R_TDI_LSB);
7818 }
7819 qib_write_kreg(dd, kr_r_access, val);
7820 qib_read_kreg32(dd, kr_scratch);
7821 ret = qib_r_wait_for_rdy(dd);
7822 if (ret < 0)
7823 break;
7824 }
7825 /* Restore to NOP between operations. */
7826 val = SJA_EN | (bisten << BISTEN_LSB);
7827 qib_write_kreg(dd, kr_r_access, val);
7828 qib_read_kreg32(dd, kr_scratch);
7829 ret = qib_r_wait_for_rdy(dd);
7830
7831 if (ret >= 0)
7832 ret = pos;
7833 bail:
7834 return ret;
7835 }
7836
7837 static int qib_r_update(struct qib_devdata *dd, int bisten)
7838 {
7839 u64 val;
7840 int ret;
7841
7842 val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB);
7843 ret = qib_r_wait_for_rdy(dd);
7844 if (ret >= 0) {
7845 qib_write_kreg(dd, kr_r_access, val);
7846 qib_read_kreg32(dd, kr_scratch);
7847 }
7848 return ret;
7849 }
7850
7851 #define BISTEN_PORT_SEL 15
7852 #define LEN_PORT_SEL 625
7853 #define BISTEN_AT 17
7854 #define LEN_AT 156
7855 #define BISTEN_ETM 16
7856 #define LEN_ETM 632
7857
7858 #define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
7859
7860 /* these are common for all IB port use cases. */
7861 static u8 reset_at[BIT2BYTE(LEN_AT)] = {
7862 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7863 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7864 };
7865 static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = {
7866 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7867 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7868 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e,
7869 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7,
7870 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70,
7871 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00,
7872 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7873 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
7874 };
7875 static u8 at[BIT2BYTE(LEN_AT)] = {
7876 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
7877 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7878 };
7879
7880 /* used for IB1 or IB2, only one in use */
7881 static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = {
7882 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7883 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7884 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7885 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00,
7886 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7887 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03,
7888 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00,
7889 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00,
7890 };
7891
7892 /* used when both IB1 and IB2 are in use */
7893 static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = {
7894 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7895 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79,
7896 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7897 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05,
7898 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
7899 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07,
7900 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00,
7901 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00,
7902 };
7903
7904 /* used when only IB1 is in use */
7905 static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = {
7906 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
7907 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
7908 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7909 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7910 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
7911 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7912 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7913 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
7914 };
7915
7916 /* used when only IB2 is in use */
7917 static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = {
7918 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39,
7919 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32,
7920 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
7921 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
7922 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32,
7923 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
7924 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
7925 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01,
7926 };
7927
7928 /* used when both IB1 and IB2 are in use */
7929 static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = {
7930 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
7931 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
7932 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7933 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7934 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
7935 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a,
7936 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7937 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
7938 };
7939
7940 /*
7941 * Do setup to properly handle IB link recovery; if port is zero, we
7942 * are initializing to cover both ports; otherwise we are initializing
7943 * to cover a single port card, or the port has reached INIT and we may
7944 * need to switch coverage types.
7945 */
7946 static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both)
7947 {
7948 u8 *portsel, *etm;
7949 struct qib_devdata *dd = ppd->dd;
7950
7951 if (!ppd->dd->cspec->r1)
7952 return;
7953 if (!both) {
7954 dd->cspec->recovery_ports_initted++;
7955 ppd->cpspec->recovery_init = 1;
7956 }
7957 if (!both && dd->cspec->recovery_ports_initted == 1) {
7958 portsel = ppd->port == 1 ? portsel_port1 : portsel_port2;
7959 etm = atetm_1port;
7960 } else {
7961 portsel = portsel_2port;
7962 etm = atetm_2port;
7963 }
7964
7965 if (qib_r_grab(dd) < 0 ||
7966 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 ||
7967 qib_r_update(dd, BISTEN_ETM) < 0 ||
7968 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 ||
7969 qib_r_update(dd, BISTEN_AT) < 0 ||
7970 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL,
7971 portsel, NULL) < 0 ||
7972 qib_r_update(dd, BISTEN_PORT_SEL) < 0 ||
7973 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 ||
7974 qib_r_update(dd, BISTEN_AT) < 0 ||
7975 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 ||
7976 qib_r_update(dd, BISTEN_ETM) < 0)
7977 qib_dev_err(dd, "Failed IB link recovery setup\n");
7978 }
7979
7980 static void check_7322_rxe_status(struct qib_pportdata *ppd)
7981 {
7982 struct qib_devdata *dd = ppd->dd;
7983 u64 fmask;
7984
7985 if (dd->cspec->recovery_ports_initted != 1)
7986 return; /* rest doesn't apply to dualport */
7987 qib_write_kreg(dd, kr_control, dd->control |
7988 SYM_MASK(Control, FreezeMode));
7989 (void)qib_read_kreg64(dd, kr_scratch);
7990 udelay(3); /* ibcreset asserted 400ns, be sure that's over */
7991 fmask = qib_read_kreg64(dd, kr_act_fmask);
7992 if (!fmask) {
7993 /*
7994 * require a powercycle before we'll work again, and make
7995 * sure we get no more interrupts, and don't turn off
7996 * freeze.
7997 */
7998 ppd->dd->cspec->stay_in_freeze = 1;
7999 qib_7322_set_intr_state(ppd->dd, 0);
8000 qib_write_kreg(dd, kr_fmask, 0ULL);
8001 qib_dev_err(dd, "HCA unusable until powercycled\n");
8002 return; /* eventually reset */
8003 }
8004
8005 qib_write_kreg(ppd->dd, kr_hwerrclear,
8006 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1));
8007
8008 /* don't do the full clear_freeze(), not needed for this */
8009 qib_write_kreg(dd, kr_control, dd->control);
8010 qib_read_kreg32(dd, kr_scratch);
8011 /* take IBC out of reset */
8012 if (ppd->link_speed_supported) {
8013 ppd->cpspec->ibcctrl_a &=
8014 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
8015 qib_write_kreg_port(ppd, krp_ibcctrl_a,
8016 ppd->cpspec->ibcctrl_a);
8017 qib_read_kreg32(dd, kr_scratch);
8018 if (ppd->lflags & QIBL_IB_LINK_DISABLED)
8019 qib_set_ib_7322_lstate(ppd, 0,
8020 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
8021 }
8022 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree