arch/mips/mm/uasm.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * A small micro-assembler. It is intentionally kept simple, does only
   7  * support a subset of instructions, and does not try to hide pipeline
   8  * effects like branch delay slots.
   9  *
  10  * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
  11  * Copyright (C) 2005, 2007  Maciej W. Rozycki
  12  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/types.h>
  17 #include <linux/init.h>
  18
  19 #include <asm/inst.h>
  20 #include <asm/elf.h>
  21 #include <asm/bugs.h>
  22 #include <asm/uasm.h>
  23
  24 enum fields {
  25         RS = 0x001,
  26         RT = 0x002,
  27         RD = 0x004,
  28         RE = 0x008,
  29         SIMM = 0x010,
  30         UIMM = 0x020,
  31         BIMM = 0x040,
  32         JIMM = 0x080,
  33         FUNC = 0x100,
  34         SET = 0x200,
  35         SCIMM = 0x400
  36 };
  37
  38 #define OP_MASK         0x3f
  39 #define OP_SH           26
  40 #define RS_MASK         0x1f
  41 #define RS_SH           21
  42 #define RT_MASK         0x1f
  43 #define RT_SH           16
  44 #define RD_MASK         0x1f
  45 #define RD_SH           11
  46 #define RE_MASK         0x1f
  47 #define RE_SH           6
  48 #define IMM_MASK        0xffff
  49 #define IMM_SH          0
  50 #define JIMM_MASK       0x3ffffff
  51 #define JIMM_SH         0
  52 #define FUNC_MASK       0x3f
  53 #define FUNC_SH         0
  54 #define SET_MASK        0x7
  55 #define SET_SH          0
  56 #define SCIMM_MASK      0xfffff
  57 #define SCIMM_SH        6
  58
  59 enum opcode {
  60         insn_invalid,
  61         insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
  62         insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
  63         insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
  64         insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
  65         insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret,
  66         insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld,
  67         insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori,
  68         insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
  69         insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp,
  70         insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
  71         insn_dins, insn_dinsm, insn_syscall, insn_bbit0, insn_bbit1,
  72         insn_lwx, insn_ldx
  73 };
  74
  75 struct insn {
  76         enum opcode opcode;
  77         u32 match;
  78         enum fields fields;
  79 };
  80
  81 /* This macro sets the non-variable bits of an instruction. */
  82 #define M(a, b, c, d, e, f)                                     \
  83         ((a) << OP_SH                                           \
  84          | (b) << RS_SH                                         \
  85          | (c) << RT_SH                                         \
  86          | (d) << RD_SH                                         \
  87          | (e) << RE_SH                                         \
  88          | (f) << FUNC_SH)
  89
  90 static struct insn insn_table[] __uasminitdata = {
  91         { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
  92         { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
  93         { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
  94         { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
  95         { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
  96         { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
  97         { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
  98         { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
  99         { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
 100         { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
 101         { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
 102         { insn_cache,  M(cache_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 103         { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
 104         { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
 105         { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
 106         { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
 107         { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
 108         { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
 109         { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
 110         { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
 111         { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
 112         { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
 113         { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
 114         { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
 115         { insn_eret,  M(cop0_op, cop_op, 0, 0, 0, eret_op),  0 },
 116         { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
 117         { insn_jal,  M(jal_op, 0, 0, 0, 0, 0),  JIMM },
 118         { insn_jr,  M(spec_op, 0, 0, 0, 0, jr_op),  RS },
 119         { insn_ld,  M(ld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 120         { insn_ll,  M(ll_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 121         { insn_lld,  M(lld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 122         { insn_lui,  M(lui_op, 0, 0, 0, 0, 0),  RT | SIMM },
 123         { insn_lw,  M(lw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 124         { insn_mfc0,  M(cop0_op, mfc_op, 0, 0, 0, 0),  RT | RD | SET},
 125         { insn_mtc0,  M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},
 126         { insn_or,  M(spec_op, 0, 0, 0, 0, or_op),  RS | RT | RD },
 127         { insn_ori,  M(ori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
 128         { insn_pref,  M(pref_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 129         { insn_rfe,  M(cop0_op, cop_op, 0, 0, 0, rfe_op),  0 },
 130         { insn_sc,  M(sc_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 131         { insn_scd,  M(scd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 132         { insn_sd,  M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 133         { insn_sll,  M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE },
 134         { insn_sra,  M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE },
 135         { insn_srl,  M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE },
 136         { insn_rotr,  M(spec_op, 1, 0, 0, 0, srl_op),  RT | RD | RE },
 137         { insn_subu,  M(spec_op, 0, 0, 0, 0, subu_op),  RS | RT | RD },
 138         { insn_sw,  M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
 139         { insn_tlbp,  M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0 },
 140         { insn_tlbr,  M(cop0_op, cop_op, 0, 0, 0, tlbr_op),  0 },
 141         { insn_tlbwi,  M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0 },
 142         { insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },
 143         { insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
 144         { insn_xori,  M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
 145         { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
 146         { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
 147         { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
 148         { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
 149         { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
 150         { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
 151         { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
 152         { insn_invalid, 0, 0 }
 153 };
 154
 155 #undef M
 156
 157 static inline __uasminit u32 build_rs(u32 arg)
 158 {
 159         if (arg & ~RS_MASK)
 160                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 161
 162         return (arg & RS_MASK) << RS_SH;
 163 }
 164
 165 static inline __uasminit u32 build_rt(u32 arg)
 166 {
 167         if (arg & ~RT_MASK)
 168                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 169
 170         return (arg & RT_MASK) << RT_SH;
 171 }
 172
 173 static inline __uasminit u32 build_rd(u32 arg)
 174 {
 175         if (arg & ~RD_MASK)
 176                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 177
 178         return (arg & RD_MASK) << RD_SH;
 179 }
 180
 181 static inline __uasminit u32 build_re(u32 arg)
 182 {
 183         if (arg & ~RE_MASK)
 184                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 185
 186         return (arg & RE_MASK) << RE_SH;
 187 }
 188
 189 static inline __uasminit u32 build_simm(s32 arg)
 190 {
 191         if (arg > 0x7fff || arg < -0x8000)
 192                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 193
 194         return arg & 0xffff;
 195 }
 196
 197 static inline __uasminit u32 build_uimm(u32 arg)
 198 {
 199         if (arg & ~IMM_MASK)
 200                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 201
 202         return arg & IMM_MASK;
 203 }
 204
 205 static inline __uasminit u32 build_bimm(s32 arg)
 206 {
 207         if (arg > 0x1ffff || arg < -0x20000)
 208                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 209
 210         if (arg & 0x3)
 211                 printk(KERN_WARNING "Invalid micro-assembler branch target\n");
 212
 213         return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
 214 }
 215
 216 static inline __uasminit u32 build_jimm(u32 arg)
 217 {
 218         if (arg & ~((JIMM_MASK) << 2))
 219                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 220
 221         return (arg >> 2) & JIMM_MASK;
 222 }
 223
 224 static inline __uasminit u32 build_scimm(u32 arg)
 225 {
 226         if (arg & ~SCIMM_MASK)
 227                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 228
 229         return (arg & SCIMM_MASK) << SCIMM_SH;
 230 }
 231
 232 static inline __uasminit u32 build_func(u32 arg)
 233 {
 234         if (arg & ~FUNC_MASK)
 235                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 236
 237         return arg & FUNC_MASK;
 238 }
 239
 240 static inline __uasminit u32 build_set(u32 arg)
 241 {
 242         if (arg & ~SET_MASK)
 243                 printk(KERN_WARNING "Micro-assembler field overflow\n");
 244
 245         return arg & SET_MASK;
 246 }
 247
 248 /*
 249  * The order of opcode arguments is implicitly left to right,
 250  * starting with RS and ending with FUNC or IMM.
 251  */
 252 static void __uasminit build_insn(u32 **buf, enum opcode opc, ...)
 253 {
 254         struct insn *ip = NULL;
 255         unsigned int i;
 256         va_list ap;
 257         u32 op;
 258
 259         for (i = 0; insn_table[i].opcode != insn_invalid; i++)
 260                 if (insn_table[i].opcode == opc) {
 261                         ip = &insn_table[i];
 262                         break;
 263                 }
 264
 265         if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
 266                 panic("Unsupported Micro-assembler instruction %d", opc);
 267
 268         op = ip->match;
 269         va_start(ap, opc);
 270         if (ip->fields & RS)
 271                 op |= build_rs(va_arg(ap, u32));
 272         if (ip->fields & RT)
 273                 op |= build_rt(va_arg(ap, u32));
 274         if (ip->fields & RD)
 275                 op |= build_rd(va_arg(ap, u32));
 276         if (ip->fields & RE)
 277                 op |= build_re(va_arg(ap, u32));
 278         if (ip->fields & SIMM)
 279                 op |= build_simm(va_arg(ap, s32));
 280         if (ip->fields & UIMM)
 281                 op |= build_uimm(va_arg(ap, u32));
 282         if (ip->fields & BIMM)
 283                 op |= build_bimm(va_arg(ap, s32));
 284         if (ip->fields & JIMM)
 285                 op |= build_jimm(va_arg(ap, u32));
 286         if (ip->fields & FUNC)
 287                 op |= build_func(va_arg(ap, u32));
 288         if (ip->fields & SET)
 289                 op |= build_set(va_arg(ap, u32));
 290         if (ip->fields & SCIMM)
 291                 op |= build_scimm(va_arg(ap, u32));
 292         va_end(ap);
 293
 294         **buf = op;
 295         (*buf)++;
 296 }
 297
 298 #define I_u1u2u3(op)                                    \
 299 Ip_u1u2u3(op)                                           \
 300 {                                                       \
 301         build_insn(buf, insn##op, a, b, c);             \
 302 }                                                       \
 303 UASM_EXPORT_SYMBOL(uasm_i##op);
 304
 305 #define I_u2u1u3(op)                                    \
 306 Ip_u2u1u3(op)                                           \
 307 {                                                       \
 308         build_insn(buf, insn##op, b, a, c);             \
 309 }                                                       \
 310 UASM_EXPORT_SYMBOL(uasm_i##op);
 311
 312 #define I_u3u1u2(op)                                    \
 313 Ip_u3u1u2(op)                                           \
 314 {                                                       \
 315         build_insn(buf, insn##op, b, c, a);             \
 316 }                                                       \
 317 UASM_EXPORT_SYMBOL(uasm_i##op);
 318
 319 #define I_u1u2s3(op)                                    \
 320 Ip_u1u2s3(op)                                           \
 321 {                                                       \
 322         build_insn(buf, insn##op, a, b, c);             \
 323 }                                                       \
 324 UASM_EXPORT_SYMBOL(uasm_i##op);
 325
 326 #define I_u2s3u1(op)                                    \
 327 Ip_u2s3u1(op)                                           \
 328 {                                                       \
 329         build_insn(buf, insn##op, c, a, b);             \
 330 }                                                       \
 331 UASM_EXPORT_SYMBOL(uasm_i##op);
 332
 333 #define I_u2u1s3(op)                                    \
 334 Ip_u2u1s3(op)                                           \
 335 {                                                       \
 336         build_insn(buf, insn##op, b, a, c);             \
 337 }                                                       \
 338 UASM_EXPORT_SYMBOL(uasm_i##op);
 339
 340 #define I_u2u1msbu3(op)                                 \
 341 Ip_u2u1msbu3(op)                                        \
 342 {                                                       \
 343         build_insn(buf, insn##op, b, a, c+d-1, c);      \
 344 }                                                       \
 345 UASM_EXPORT_SYMBOL(uasm_i##op);
 346
 347 #define I_u2u1msb32u3(op)                               \
 348 Ip_u2u1msbu3(op)                                        \
 349 {                                                       \
 350         build_insn(buf, insn##op, b, a, c+d-33, c);     \
 351 }                                                       \
 352 UASM_EXPORT_SYMBOL(uasm_i##op);
 353
 354 #define I_u1u2(op)                                      \
 355 Ip_u1u2(op)                                             \
 356 {                                                       \
 357         build_insn(buf, insn##op, a, b);                \
 358 }                                                       \
 359 UASM_EXPORT_SYMBOL(uasm_i##op);
 360
 361 #define I_u1s2(op)                                      \
 362 Ip_u1s2(op)                                             \
 363 {                                                       \
 364         build_insn(buf, insn##op, a, b);                \
 365 }                                                       \
 366 UASM_EXPORT_SYMBOL(uasm_i##op);
 367
 368 #define I_u1(op)                                        \
 369 Ip_u1(op)                                               \
 370 {                                                       \
 371         build_insn(buf, insn##op, a);                   \
 372 }                                                       \
 373 UASM_EXPORT_SYMBOL(uasm_i##op);
 374
 375 #define I_0(op)                                         \
 376 Ip_0(op)                                                \
 377 {                                                       \
 378         build_insn(buf, insn##op);                      \
 379 }                                                       \
 380 UASM_EXPORT_SYMBOL(uasm_i##op);
 381
 382 I_u2u1s3(_addiu)
 383 I_u3u1u2(_addu)
 384 I_u2u1u3(_andi)
 385 I_u3u1u2(_and)
 386 I_u1u2s3(_beq)
 387 I_u1u2s3(_beql)
 388 I_u1s2(_bgez)
 389 I_u1s2(_bgezl)
 390 I_u1s2(_bltz)
 391 I_u1s2(_bltzl)
 392 I_u1u2s3(_bne)
 393 I_u2s3u1(_cache)
 394 I_u1u2u3(_dmfc0)
 395 I_u1u2u3(_dmtc0)
 396 I_u2u1s3(_daddiu)
 397 I_u3u1u2(_daddu)
 398 I_u2u1u3(_dsll)
 399 I_u2u1u3(_dsll32)
 400 I_u2u1u3(_dsra)
 401 I_u2u1u3(_dsrl)
 402 I_u2u1u3(_dsrl32)
 403 I_u2u1u3(_drotr)
 404 I_u2u1u3(_drotr32)
 405 I_u3u1u2(_dsubu)
 406 I_0(_eret)
 407 I_u1(_j)
 408 I_u1(_jal)
 409 I_u1(_jr)
 410 I_u2s3u1(_ld)
 411 I_u2s3u1(_ll)
 412 I_u2s3u1(_lld)
 413 I_u1s2(_lui)
 414 I_u2s3u1(_lw)
 415 I_u1u2u3(_mfc0)
 416 I_u1u2u3(_mtc0)
 417 I_u2u1u3(_ori)
 418 I_u3u1u2(_or)
 419 I_0(_rfe)
 420 I_u2s3u1(_sc)
 421 I_u2s3u1(_scd)
 422 I_u2s3u1(_sd)
 423 I_u2u1u3(_sll)
 424 I_u2u1u3(_sra)
 425 I_u2u1u3(_srl)
 426 I_u2u1u3(_rotr)
 427 I_u3u1u2(_subu)
 428 I_u2s3u1(_sw)
 429 I_0(_tlbp)
 430 I_0(_tlbr)
 431 I_0(_tlbwi)
 432 I_0(_tlbwr)
 433 I_u3u1u2(_xor)
 434 I_u2u1u3(_xori)
 435 I_u2u1msbu3(_dins);
 436 I_u2u1msb32u3(_dinsm);
 437 I_u1(_syscall);
 438 I_u1u2s3(_bbit0);
 439 I_u1u2s3(_bbit1);
 440 I_u3u1u2(_lwx)
 441 I_u3u1u2(_ldx)
 442
 443 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 444 #include <asm/octeon/octeon.h>
 445 void __uasminit uasm_i_pref(u32 **buf, unsigned int a, signed int b,
 446                             unsigned int c)
 447 {
 448         if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
 449                 /*
 450                  * As per erratum Core-14449, replace prefetches 0-4,
 451                  * 6-24 with 'pref 28'.
 452                  */
 453                 build_insn(buf, insn_pref, c, 28, b);
 454         else
 455                 build_insn(buf, insn_pref, c, a, b);
 456 }
 457 UASM_EXPORT_SYMBOL(uasm_i_pref);
 458 #else
 459 I_u2s3u1(_pref)
 460 #endif
 461
 462 /* Handle labels. */
 463 void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
 464 {
 465         (*lab)->addr = addr;
 466         (*lab)->lab = lid;
 467         (*lab)++;
 468 }
 469 UASM_EXPORT_SYMBOL(uasm_build_label);
 470
 471 int __uasminit uasm_in_compat_space_p(long addr)
 472 {
 473         /* Is this address in 32bit compat space? */
 474 #ifdef CONFIG_64BIT
 475         return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
 476 #else
 477         return 1;
 478 #endif
 479 }
 480 UASM_EXPORT_SYMBOL(uasm_in_compat_space_p);
 481
 482 static int __uasminit uasm_rel_highest(long val)
 483 {
 484 #ifdef CONFIG_64BIT
 485         return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
 486 #else
 487         return 0;
 488 #endif
 489 }
 490
 491 static int __uasminit uasm_rel_higher(long val)
 492 {
 493 #ifdef CONFIG_64BIT
 494         return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
 495 #else
 496         return 0;
 497 #endif
 498 }
 499
 500 int __uasminit uasm_rel_hi(long val)
 501 {
 502         return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
 503 }
 504 UASM_EXPORT_SYMBOL(uasm_rel_hi);
 505
 506 int __uasminit uasm_rel_lo(long val)
 507 {
 508         return ((val & 0xffff) ^ 0x8000) - 0x8000;
 509 }
 510 UASM_EXPORT_SYMBOL(uasm_rel_lo);
 511
 512 void __uasminit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
 513 {
 514         if (!uasm_in_compat_space_p(addr)) {
 515                 uasm_i_lui(buf, rs, uasm_rel_highest(addr));
 516                 if (uasm_rel_higher(addr))
 517                         uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
 518                 if (uasm_rel_hi(addr)) {
 519                         uasm_i_dsll(buf, rs, rs, 16);
 520                         uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr));
 521                         uasm_i_dsll(buf, rs, rs, 16);
 522                 } else
 523                         uasm_i_dsll32(buf, rs, rs, 0);
 524         } else
 525                 uasm_i_lui(buf, rs, uasm_rel_hi(addr));
 526 }
 527 UASM_EXPORT_SYMBOL(UASM_i_LA_mostly);
 528
 529 void __uasminit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
 530 {
 531         UASM_i_LA_mostly(buf, rs, addr);
 532         if (uasm_rel_lo(addr)) {
 533                 if (!uasm_in_compat_space_p(addr))
 534                         uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr));
 535                 else
 536                         uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr));
 537         }
 538 }
 539 UASM_EXPORT_SYMBOL(UASM_i_LA);
 540
 541 /* Handle relocations. */
 542 void __uasminit
 543 uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
 544 {
 545         (*rel)->addr = addr;
 546         (*rel)->type = R_MIPS_PC16;
 547         (*rel)->lab = lid;
 548         (*rel)++;
 549 }
 550 UASM_EXPORT_SYMBOL(uasm_r_mips_pc16);
 551
 552 static inline void __uasminit
 553 __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
 554 {
 555         long laddr = (long)lab->addr;
 556         long raddr = (long)rel->addr;
 557
 558         switch (rel->type) {
 559         case R_MIPS_PC16:
 560                 *rel->addr |= build_bimm(laddr - (raddr + 4));
 561                 break;
 562
 563         default:
 564                 panic("Unsupported Micro-assembler relocation %d",
 565                       rel->type);
 566         }
 567 }
 568
 569 void __uasminit
 570 uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
 571 {
 572         struct uasm_label *l;
 573
 574         for (; rel->lab != UASM_LABEL_INVALID; rel++)
 575                 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
 576                         if (rel->lab == l->lab)
 577                                 __resolve_relocs(rel, l);
 578 }
 579 UASM_EXPORT_SYMBOL(uasm_resolve_relocs);
 580
 581 void __uasminit
 582 uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off)
 583 {
 584         for (; rel->lab != UASM_LABEL_INVALID; rel++)
 585                 if (rel->addr >= first && rel->addr < end)
 586                         rel->addr += off;
 587 }
 588 UASM_EXPORT_SYMBOL(uasm_move_relocs);
 589
 590 void __uasminit
 591 uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off)
 592 {
 593         for (; lab->lab != UASM_LABEL_INVALID; lab++)
 594                 if (lab->addr >= first && lab->addr < end)
 595                         lab->addr += off;
 596 }
 597 UASM_EXPORT_SYMBOL(uasm_move_labels);
 598
 599 void __uasminit
 600 uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
 601                   u32 *end, u32 *target)
 602 {
 603         long off = (long)(target - first);
 604
 605         memcpy(target, first, (end - first) * sizeof(u32));
 606
 607         uasm_move_relocs(rel, first, end, off);
 608         uasm_move_labels(lab, first, end, off);
 609 }
 610 UASM_EXPORT_SYMBOL(uasm_copy_handler);
 611
 612 int __uasminit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
 613 {
 614         for (; rel->lab != UASM_LABEL_INVALID; rel++) {
 615                 if (rel->addr == addr
 616                     && (rel->type == R_MIPS_PC16
 617                         || rel->type == R_MIPS_26))
 618                         return 1;
 619         }
 620
 621         return 0;
 622 }
 623 UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay);
 624
 625 /* Convenience functions for labeled branches. */
 626 void __uasminit
 627 uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 628 {
 629         uasm_r_mips_pc16(r, *p, lid);
 630         uasm_i_bltz(p, reg, 0);
 631 }
 632 UASM_EXPORT_SYMBOL(uasm_il_bltz);
 633
 634 void __uasminit
 635 uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
 636 {
 637         uasm_r_mips_pc16(r, *p, lid);
 638         uasm_i_b(p, 0);
 639 }
 640 UASM_EXPORT_SYMBOL(uasm_il_b);
 641
 642 void __uasminit
 643 uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 644 {
 645         uasm_r_mips_pc16(r, *p, lid);
 646         uasm_i_beqz(p, reg, 0);
 647 }
 648 UASM_EXPORT_SYMBOL(uasm_il_beqz);
 649
 650 void __uasminit
 651 uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 652 {
 653         uasm_r_mips_pc16(r, *p, lid);
 654         uasm_i_beqzl(p, reg, 0);
 655 }
 656 UASM_EXPORT_SYMBOL(uasm_il_beqzl);
 657
 658 void __uasminit
 659 uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
 660         unsigned int reg2, int lid)
 661 {
 662         uasm_r_mips_pc16(r, *p, lid);
 663         uasm_i_bne(p, reg1, reg2, 0);
 664 }
 665 UASM_EXPORT_SYMBOL(uasm_il_bne);
 666
 667 void __uasminit
 668 uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 669 {
 670         uasm_r_mips_pc16(r, *p, lid);
 671         uasm_i_bnez(p, reg, 0);
 672 }
 673 UASM_EXPORT_SYMBOL(uasm_il_bnez);
 674
 675 void __uasminit
 676 uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 677 {
 678         uasm_r_mips_pc16(r, *p, lid);
 679         uasm_i_bgezl(p, reg, 0);
 680 }
 681 UASM_EXPORT_SYMBOL(uasm_il_bgezl);
 682
 683 void __uasminit
 684 uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 685 {
 686         uasm_r_mips_pc16(r, *p, lid);
 687         uasm_i_bgez(p, reg, 0);
 688 }
 689 UASM_EXPORT_SYMBOL(uasm_il_bgez);
 690
 691 void __uasminit
 692 uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
 693               unsigned int bit, int lid)
 694 {
 695         uasm_r_mips_pc16(r, *p, lid);
 696         uasm_i_bbit0(p, reg, bit, 0);
 697 }
 698 UASM_EXPORT_SYMBOL(uasm_il_bbit0);
 699
 700 void __uasminit
 701 uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
 702               unsigned int bit, int lid)
 703 {
 704         uasm_r_mips_pc16(r, *p, lid);
 705         uasm_i_bbit1(p, reg, bit, 0);
 706 }
 707 UASM_EXPORT_SYMBOL(uasm_il_bbit1);