TTY: serial, move locking in uart_close
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / i2c / busses / i2c-nomadik.c
blob0c731ca69f1506d70b05da8c2d895c6493e4b1f3
1 /*
2 * Copyright (C) 2009 ST-Ericsson SA
3 * Copyright (C) 2009 STMicroelectronics
5 * I2C master mode controller driver, used in Nomadik 8815
6 * and Ux500 platforms.
8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
9 * Author: Sachin Verma <sachin.verma@st.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2, as
13 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/interrupt.h>
20 #include <linux/i2c.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
23 #include <linux/io.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/pm_runtime.h>
27 #include <plat/i2c.h>
29 #define DRIVER_NAME "nmk-i2c"
31 /* I2C Controller register offsets */
32 #define I2C_CR (0x000)
33 #define I2C_SCR (0x004)
34 #define I2C_HSMCR (0x008)
35 #define I2C_MCR (0x00C)
36 #define I2C_TFR (0x010)
37 #define I2C_SR (0x014)
38 #define I2C_RFR (0x018)
39 #define I2C_TFTR (0x01C)
40 #define I2C_RFTR (0x020)
41 #define I2C_DMAR (0x024)
42 #define I2C_BRCR (0x028)
43 #define I2C_IMSCR (0x02C)
44 #define I2C_RISR (0x030)
45 #define I2C_MISR (0x034)
46 #define I2C_ICR (0x038)
48 /* Control registers */
49 #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */
50 #define I2C_CR_OM (0x3 << 1) /* Operating mode */
51 #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */
52 #define I2C_CR_SM (0x3 << 4) /* Speed mode */
53 #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */
54 #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */
55 #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */
56 #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */
57 #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */
58 #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */
59 #define I2C_CR_LM (0x1 << 12) /* Loopback mode */
60 #define I2C_CR_FON (0x3 << 13) /* Filtering on */
61 #define I2C_CR_FS (0x3 << 15) /* Force stop enable */
63 /* Master controller (MCR) register */
64 #define I2C_MCR_OP (0x1 << 0) /* Operation */
65 #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */
66 #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */
67 #define I2C_MCR_SB (0x1 << 11) /* Extended address */
68 #define I2C_MCR_AM (0x3 << 12) /* Address type */
69 #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */
70 #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */
72 /* Status register (SR) */
73 #define I2C_SR_OP (0x3 << 0) /* Operation */
74 #define I2C_SR_STATUS (0x3 << 2) /* controller status */
75 #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */
76 #define I2C_SR_TYPE (0x3 << 7) /* Receive type */
77 #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */
79 /* Interrupt mask set/clear (IMSCR) bits */
80 #define I2C_IT_TXFE (0x1 << 0)
81 #define I2C_IT_TXFNE (0x1 << 1)
82 #define I2C_IT_TXFF (0x1 << 2)
83 #define I2C_IT_TXFOVR (0x1 << 3)
84 #define I2C_IT_RXFE (0x1 << 4)
85 #define I2C_IT_RXFNF (0x1 << 5)
86 #define I2C_IT_RXFF (0x1 << 6)
87 #define I2C_IT_RFSR (0x1 << 16)
88 #define I2C_IT_RFSE (0x1 << 17)
89 #define I2C_IT_WTSR (0x1 << 18)
90 #define I2C_IT_MTD (0x1 << 19)
91 #define I2C_IT_STD (0x1 << 20)
92 #define I2C_IT_MAL (0x1 << 24)
93 #define I2C_IT_BERR (0x1 << 25)
94 #define I2C_IT_MTDWS (0x1 << 28)
96 #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask))
98 /* some bits in ICR are reserved */
99 #define I2C_CLEAR_ALL_INTS 0x131f007f
101 /* first three msb bits are reserved */
102 #define IRQ_MASK(mask) (mask & 0x1fffffff)
104 /* maximum threshold value */
105 #define MAX_I2C_FIFO_THRESHOLD 15
107 enum i2c_status {
108 I2C_NOP,
109 I2C_ON_GOING,
110 I2C_OK,
111 I2C_ABORT
114 /* operation */
115 enum i2c_operation {
116 I2C_NO_OPERATION = 0xff,
117 I2C_WRITE = 0x00,
118 I2C_READ = 0x01
122 * struct i2c_nmk_client - client specific data
123 * @slave_adr: 7-bit slave address
124 * @count: no. bytes to be transferred
125 * @buffer: client data buffer
126 * @xfer_bytes: bytes transferred till now
127 * @operation: current I2C operation
129 struct i2c_nmk_client {
130 unsigned short slave_adr;
131 unsigned long count;
132 unsigned char *buffer;
133 unsigned long xfer_bytes;
134 enum i2c_operation operation;
138 * struct nmk_i2c_dev - private data structure of the controller
139 * @pdev: parent platform device
140 * @adap: corresponding I2C adapter
141 * @irq: interrupt line for the controller
142 * @virtbase: virtual io memory area
143 * @clk: hardware i2c block clock
144 * @cfg: machine provided controller configuration
145 * @cli: holder of client specific data
146 * @stop: stop condition
147 * @xfer_complete: acknowledge completion for a I2C message
148 * @result: controller propogated result
149 * @busy: Busy doing transfer
151 struct nmk_i2c_dev {
152 struct platform_device *pdev;
153 struct i2c_adapter adap;
154 int irq;
155 void __iomem *virtbase;
156 struct clk *clk;
157 struct nmk_i2c_controller cfg;
158 struct i2c_nmk_client cli;
159 int stop;
160 struct completion xfer_complete;
161 int result;
162 struct regulator *regulator;
163 bool busy;
166 /* controller's abort causes */
167 static const char *abort_causes[] = {
168 "no ack received after address transmission",
169 "no ack received during data phase",
170 "ack received after xmission of master code",
171 "master lost arbitration",
172 "slave restarts",
173 "slave reset",
174 "overflow, maxsize is 2047 bytes",
177 static inline void i2c_set_bit(void __iomem *reg, u32 mask)
179 writel(readl(reg) | mask, reg);
182 static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
184 writel(readl(reg) & ~mask, reg);
188 * flush_i2c_fifo() - This function flushes the I2C FIFO
189 * @dev: private data of I2C Driver
191 * This function flushes the I2C Tx and Rx FIFOs. It returns
192 * 0 on successful flushing of FIFO
194 static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
196 #define LOOP_ATTEMPTS 10
197 int i;
198 unsigned long timeout;
201 * flush the transmit and receive FIFO. The flushing
202 * operation takes several cycles before to be completed.
203 * On the completion, the I2C internal logic clears these
204 * bits, until then no one must access Tx, Rx FIFO and
205 * should poll on these bits waiting for the completion.
207 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
209 for (i = 0; i < LOOP_ATTEMPTS; i++) {
210 timeout = jiffies + dev->adap.timeout;
212 while (!time_after(jiffies, timeout)) {
213 if ((readl(dev->virtbase + I2C_CR) &
214 (I2C_CR_FTX | I2C_CR_FRX)) == 0)
215 return 0;
219 dev_err(&dev->pdev->dev, "flushing operation timed out "
220 "giving up after %d attempts", LOOP_ATTEMPTS);
222 return -ETIMEDOUT;
226 * disable_all_interrupts() - Disable all interrupts of this I2c Bus
227 * @dev: private data of I2C Driver
229 static void disable_all_interrupts(struct nmk_i2c_dev *dev)
231 u32 mask = IRQ_MASK(0);
232 writel(mask, dev->virtbase + I2C_IMSCR);
236 * clear_all_interrupts() - Clear all interrupts of I2C Controller
237 * @dev: private data of I2C Driver
239 static void clear_all_interrupts(struct nmk_i2c_dev *dev)
241 u32 mask;
242 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
243 writel(mask, dev->virtbase + I2C_ICR);
247 * init_hw() - initialize the I2C hardware
248 * @dev: private data of I2C Driver
250 static int init_hw(struct nmk_i2c_dev *dev)
252 int stat;
254 stat = flush_i2c_fifo(dev);
255 if (stat)
256 goto exit;
258 /* disable the controller */
259 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
261 disable_all_interrupts(dev);
263 clear_all_interrupts(dev);
265 dev->cli.operation = I2C_NO_OPERATION;
267 exit:
268 return stat;
271 /* enable peripheral, master mode operation */
272 #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE)
275 * load_i2c_mcr_reg() - load the MCR register
276 * @dev: private data of controller
278 static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev)
280 u32 mcr = 0;
282 /* 7-bit address transaction */
283 mcr |= GEN_MASK(1, I2C_MCR_AM, 12);
284 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
286 /* start byte procedure not applied */
287 mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
289 /* check the operation, master read/write? */
290 if (dev->cli.operation == I2C_WRITE)
291 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
292 else
293 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
295 /* stop or repeated start? */
296 if (dev->stop)
297 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
298 else
299 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
301 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
303 return mcr;
307 * setup_i2c_controller() - setup the controller
308 * @dev: private data of controller
310 static void setup_i2c_controller(struct nmk_i2c_dev *dev)
312 u32 brcr1, brcr2;
313 u32 i2c_clk, div;
315 writel(0x0, dev->virtbase + I2C_CR);
316 writel(0x0, dev->virtbase + I2C_HSMCR);
317 writel(0x0, dev->virtbase + I2C_TFTR);
318 writel(0x0, dev->virtbase + I2C_RFTR);
319 writel(0x0, dev->virtbase + I2C_DMAR);
322 * set the slsu:
324 * slsu defines the data setup time after SCL clock
325 * stretching in terms of i2c clk cycles. The
326 * needed setup time for the three modes are 250ns,
327 * 100ns, 10ns respectively thus leading to the values
328 * of 14, 6, 2 for a 48 MHz i2c clk.
330 writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR);
332 i2c_clk = clk_get_rate(dev->clk);
334 /* fallback to std. mode if machine has not provided it */
335 if (dev->cfg.clk_freq == 0)
336 dev->cfg.clk_freq = 100000;
339 * The spec says, in case of std. mode the divider is
340 * 2 whereas it is 3 for fast and fastplus mode of
341 * operation. TODO - high speed support.
343 div = (dev->cfg.clk_freq > 100000) ? 3 : 2;
346 * generate the mask for baud rate counters. The controller
347 * has two baud rate counters. One is used for High speed
348 * operation, and the other is for std, fast mode, fast mode
349 * plus operation. Currently we do not supprt high speed mode
350 * so set brcr1 to 0.
352 brcr1 = 0 << 16;
353 brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff;
355 /* set the baud rate counter register */
356 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
359 * set the speed mode. Currently we support
360 * only standard and fast mode of operation
361 * TODO - support for fast mode plus (up to 1Mb/s)
362 * and high speed (up to 3.4 Mb/s)
364 if (dev->cfg.sm > I2C_FREQ_MODE_FAST) {
365 dev_err(&dev->pdev->dev, "do not support this mode "
366 "defaulting to std. mode\n");
367 brcr2 = i2c_clk/(100000 * 2) & 0xffff;
368 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
369 writel(I2C_FREQ_MODE_STANDARD << 4,
370 dev->virtbase + I2C_CR);
372 writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR);
374 /* set the Tx and Rx FIFO threshold */
375 writel(dev->cfg.tft, dev->virtbase + I2C_TFTR);
376 writel(dev->cfg.rft, dev->virtbase + I2C_RFTR);
380 * read_i2c() - Read from I2C client device
381 * @dev: private data of I2C Driver
383 * This function reads from i2c client device when controller is in
384 * master mode. There is a completion timeout. If there is no transfer
385 * before timeout error is returned.
387 static int read_i2c(struct nmk_i2c_dev *dev)
389 u32 status = 0;
390 u32 mcr;
391 u32 irq_mask = 0;
392 int timeout;
394 mcr = load_i2c_mcr_reg(dev);
395 writel(mcr, dev->virtbase + I2C_MCR);
397 /* load the current CR value */
398 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
399 dev->virtbase + I2C_CR);
401 /* enable the controller */
402 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
404 init_completion(&dev->xfer_complete);
406 /* enable interrupts by setting the mask */
407 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
408 I2C_IT_MAL | I2C_IT_BERR);
410 if (dev->stop)
411 irq_mask |= I2C_IT_MTD;
412 else
413 irq_mask |= I2C_IT_MTDWS;
415 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
417 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
418 dev->virtbase + I2C_IMSCR);
420 timeout = wait_for_completion_interruptible_timeout(
421 &dev->xfer_complete, dev->adap.timeout);
423 if (timeout < 0) {
424 dev_err(&dev->pdev->dev,
425 "wait_for_completion_interruptible_timeout"
426 "returned %d waiting for event\n", timeout);
427 status = timeout;
430 if (timeout == 0) {
431 /* Controller timed out */
432 dev_err(&dev->pdev->dev, "read from slave 0x%x timed out\n",
433 dev->cli.slave_adr);
434 status = -ETIMEDOUT;
436 return status;
439 static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes)
441 int count;
443 for (count = (no_bytes - 2);
444 (count > 0) &&
445 (dev->cli.count != 0);
446 count--) {
447 /* write to the Tx FIFO */
448 writeb(*dev->cli.buffer,
449 dev->virtbase + I2C_TFR);
450 dev->cli.buffer++;
451 dev->cli.count--;
452 dev->cli.xfer_bytes++;
458 * write_i2c() - Write data to I2C client.
459 * @dev: private data of I2C Driver
461 * This function writes data to I2C client
463 static int write_i2c(struct nmk_i2c_dev *dev)
465 u32 status = 0;
466 u32 mcr;
467 u32 irq_mask = 0;
468 int timeout;
470 mcr = load_i2c_mcr_reg(dev);
472 writel(mcr, dev->virtbase + I2C_MCR);
474 /* load the current CR value */
475 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
476 dev->virtbase + I2C_CR);
478 /* enable the controller */
479 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
481 init_completion(&dev->xfer_complete);
483 /* enable interrupts by settings the masks */
484 irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR);
486 /* Fill the TX FIFO with transmit data */
487 fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD);
489 if (dev->cli.count != 0)
490 irq_mask |= I2C_IT_TXFNE;
493 * check if we want to transfer a single or multiple bytes, if so
494 * set the MTDWS bit (Master Transaction Done Without Stop)
495 * to start repeated start operation
497 if (dev->stop)
498 irq_mask |= I2C_IT_MTD;
499 else
500 irq_mask |= I2C_IT_MTDWS;
502 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
504 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
505 dev->virtbase + I2C_IMSCR);
507 timeout = wait_for_completion_interruptible_timeout(
508 &dev->xfer_complete, dev->adap.timeout);
510 if (timeout < 0) {
511 dev_err(&dev->pdev->dev,
512 "wait_for_completion_interruptible_timeout"
513 "returned %d waiting for event\n", timeout);
514 status = timeout;
517 if (timeout == 0) {
518 /* Controller timed out */
519 dev_err(&dev->pdev->dev, "write to slave 0x%x timed out\n",
520 dev->cli.slave_adr);
521 status = -ETIMEDOUT;
524 return status;
528 * nmk_i2c_xfer_one() - transmit a single I2C message
529 * @dev: device with a message encoded into it
530 * @flags: message flags
532 static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags)
534 int status;
536 if (flags & I2C_M_RD) {
537 /* read operation */
538 dev->cli.operation = I2C_READ;
539 status = read_i2c(dev);
540 } else {
541 /* write operation */
542 dev->cli.operation = I2C_WRITE;
543 status = write_i2c(dev);
546 if (status || (dev->result)) {
547 u32 i2c_sr;
548 u32 cause;
550 i2c_sr = readl(dev->virtbase + I2C_SR);
552 * Check if the controller I2C operation status
553 * is set to ABORT(11b).
555 if (((i2c_sr >> 2) & 0x3) == 0x3) {
556 /* get the abort cause */
557 cause = (i2c_sr >> 4) & 0x7;
558 dev_err(&dev->pdev->dev, "%s\n", cause
559 >= ARRAY_SIZE(abort_causes) ?
560 "unknown reason" :
561 abort_causes[cause]);
564 (void) init_hw(dev);
566 status = status ? status : dev->result;
569 return status;
573 * nmk_i2c_xfer() - I2C transfer function used by kernel framework
574 * @i2c_adap: Adapter pointer to the controller
575 * @msgs: Pointer to data to be written.
576 * @num_msgs: Number of messages to be executed
578 * This is the function called by the generic kernel i2c_transfer()
579 * or i2c_smbus...() API calls. Note that this code is protected by the
580 * semaphore set in the kernel i2c_transfer() function.
582 * NOTE:
583 * READ TRANSFER : We impose a restriction of the first message to be the
584 * index message for any read transaction.
585 * - a no index is coded as '0',
586 * - 2byte big endian index is coded as '3'
587 * !!! msg[0].buf holds the actual index.
588 * This is compatible with generic messages of smbus emulator
589 * that send a one byte index.
590 * eg. a I2C transation to read 2 bytes from index 0
591 * idx = 0;
592 * msg[0].addr = client->addr;
593 * msg[0].flags = 0x0;
594 * msg[0].len = 1;
595 * msg[0].buf = &idx;
597 * msg[1].addr = client->addr;
598 * msg[1].flags = I2C_M_RD;
599 * msg[1].len = 2;
600 * msg[1].buf = rd_buff
601 * i2c_transfer(adap, msg, 2);
603 * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
604 * If you want to emulate an SMBUS write transaction put the
605 * index as first byte(or first and second) in the payload.
606 * eg. a I2C transation to write 2 bytes from index 1
607 * wr_buff[0] = 0x1;
608 * wr_buff[1] = 0x23;
609 * wr_buff[2] = 0x46;
610 * msg[0].flags = 0x0;
611 * msg[0].len = 3;
612 * msg[0].buf = wr_buff;
613 * i2c_transfer(adap, msg, 1);
615 * To read or write a block of data (multiple bytes) using SMBUS emulation
616 * please use the i2c_smbus_read_i2c_block_data()
617 * or i2c_smbus_write_i2c_block_data() API
619 static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
620 struct i2c_msg msgs[], int num_msgs)
622 int status;
623 int i;
624 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
625 int j;
627 dev->busy = true;
629 if (dev->regulator)
630 regulator_enable(dev->regulator);
631 pm_runtime_get_sync(&dev->pdev->dev);
633 clk_enable(dev->clk);
635 status = init_hw(dev);
636 if (status)
637 goto out;
639 /* Attempt three times to send the message queue */
640 for (j = 0; j < 3; j++) {
641 /* setup the i2c controller */
642 setup_i2c_controller(dev);
644 for (i = 0; i < num_msgs; i++) {
645 if (unlikely(msgs[i].flags & I2C_M_TEN)) {
646 dev_err(&dev->pdev->dev, "10 bit addressing"
647 "not supported\n");
649 status = -EINVAL;
650 goto out;
652 dev->cli.slave_adr = msgs[i].addr;
653 dev->cli.buffer = msgs[i].buf;
654 dev->cli.count = msgs[i].len;
655 dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
656 dev->result = 0;
658 status = nmk_i2c_xfer_one(dev, msgs[i].flags);
659 if (status != 0)
660 break;
662 if (status == 0)
663 break;
666 out:
667 clk_disable(dev->clk);
668 pm_runtime_put_sync(&dev->pdev->dev);
669 if (dev->regulator)
670 regulator_disable(dev->regulator);
672 dev->busy = false;
674 /* return the no. messages processed */
675 if (status)
676 return status;
677 else
678 return num_msgs;
682 * disable_interrupts() - disable the interrupts
683 * @dev: private data of controller
684 * @irq: interrupt number
686 static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
688 irq = IRQ_MASK(irq);
689 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
690 dev->virtbase + I2C_IMSCR);
691 return 0;
695 * i2c_irq_handler() - interrupt routine
696 * @irq: interrupt number
697 * @arg: data passed to the handler
699 * This is the interrupt handler for the i2c driver. Currently
700 * it handles the major interrupts like Rx & Tx FIFO management
701 * interrupts, master transaction interrupts, arbitration and
702 * bus error interrupts. The rest of the interrupts are treated as
703 * unhandled.
705 static irqreturn_t i2c_irq_handler(int irq, void *arg)
707 struct nmk_i2c_dev *dev = arg;
708 u32 tft, rft;
709 u32 count;
710 u32 misr;
711 u32 src = 0;
713 /* load Tx FIFO and Rx FIFO threshold values */
714 tft = readl(dev->virtbase + I2C_TFTR);
715 rft = readl(dev->virtbase + I2C_RFTR);
717 /* read interrupt status register */
718 misr = readl(dev->virtbase + I2C_MISR);
720 src = __ffs(misr);
721 switch ((1 << src)) {
723 /* Transmit FIFO nearly empty interrupt */
724 case I2C_IT_TXFNE:
726 if (dev->cli.operation == I2C_READ) {
728 * in read operation why do we care for writing?
729 * so disable the Transmit FIFO interrupt
731 disable_interrupts(dev, I2C_IT_TXFNE);
732 } else {
733 fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft));
735 * if done, close the transfer by disabling the
736 * corresponding TXFNE interrupt
738 if (dev->cli.count == 0)
739 disable_interrupts(dev, I2C_IT_TXFNE);
742 break;
745 * Rx FIFO nearly full interrupt.
746 * This is set when the numer of entries in Rx FIFO is
747 * greater or equal than the threshold value programmed
748 * in RFT
750 case I2C_IT_RXFNF:
751 for (count = rft; count > 0; count--) {
752 /* Read the Rx FIFO */
753 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
754 dev->cli.buffer++;
756 dev->cli.count -= rft;
757 dev->cli.xfer_bytes += rft;
758 break;
760 /* Rx FIFO full */
761 case I2C_IT_RXFF:
762 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
763 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
764 dev->cli.buffer++;
766 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
767 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
768 break;
770 /* Master Transaction Done with/without stop */
771 case I2C_IT_MTD:
772 case I2C_IT_MTDWS:
773 if (dev->cli.operation == I2C_READ) {
774 while (!(readl(dev->virtbase + I2C_RISR)
775 & I2C_IT_RXFE)) {
776 if (dev->cli.count == 0)
777 break;
778 *dev->cli.buffer =
779 readb(dev->virtbase + I2C_RFR);
780 dev->cli.buffer++;
781 dev->cli.count--;
782 dev->cli.xfer_bytes++;
786 disable_all_interrupts(dev);
787 clear_all_interrupts(dev);
789 if (dev->cli.count) {
790 dev->result = -EIO;
791 dev_err(&dev->pdev->dev, "%lu bytes still remain to be"
792 "xfered\n", dev->cli.count);
793 (void) init_hw(dev);
795 complete(&dev->xfer_complete);
797 break;
799 /* Master Arbitration lost interrupt */
800 case I2C_IT_MAL:
801 dev->result = -EIO;
802 (void) init_hw(dev);
804 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
805 complete(&dev->xfer_complete);
807 break;
810 * Bus Error interrupt.
811 * This happens when an unexpected start/stop condition occurs
812 * during the transaction.
814 case I2C_IT_BERR:
815 dev->result = -EIO;
816 /* get the status */
817 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
818 (void) init_hw(dev);
820 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
821 complete(&dev->xfer_complete);
823 break;
826 * Tx FIFO overrun interrupt.
827 * This is set when a write operation in Tx FIFO is performed and
828 * the Tx FIFO is full.
830 case I2C_IT_TXFOVR:
831 dev->result = -EIO;
832 (void) init_hw(dev);
834 dev_err(&dev->pdev->dev, "Tx Fifo Over run\n");
835 complete(&dev->xfer_complete);
837 break;
839 /* unhandled interrupts by this driver - TODO*/
840 case I2C_IT_TXFE:
841 case I2C_IT_TXFF:
842 case I2C_IT_RXFE:
843 case I2C_IT_RFSR:
844 case I2C_IT_RFSE:
845 case I2C_IT_WTSR:
846 case I2C_IT_STD:
847 dev_err(&dev->pdev->dev, "unhandled Interrupt\n");
848 break;
849 default:
850 dev_err(&dev->pdev->dev, "spurious Interrupt..\n");
851 break;
854 return IRQ_HANDLED;
858 #ifdef CONFIG_PM
859 static int nmk_i2c_suspend(struct device *dev)
861 struct platform_device *pdev = to_platform_device(dev);
862 struct nmk_i2c_dev *nmk_i2c = platform_get_drvdata(pdev);
864 if (nmk_i2c->busy)
865 return -EBUSY;
867 return 0;
870 static int nmk_i2c_resume(struct device *dev)
872 return 0;
874 #else
875 #define nmk_i2c_suspend NULL
876 #define nmk_i2c_resume NULL
877 #endif
880 * We use noirq so that we suspend late and resume before the wakeup interrupt
881 * to ensure that we do the !pm_runtime_suspended() check in resume before
882 * there has been a regular pm runtime resume (via pm_runtime_get_sync()).
884 static const struct dev_pm_ops nmk_i2c_pm = {
885 .suspend_noirq = nmk_i2c_suspend,
886 .resume_noirq = nmk_i2c_resume,
889 static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
891 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
894 static const struct i2c_algorithm nmk_i2c_algo = {
895 .master_xfer = nmk_i2c_xfer,
896 .functionality = nmk_i2c_functionality
899 static int __devinit nmk_i2c_probe(struct platform_device *pdev)
901 int ret = 0;
902 struct resource *res;
903 struct nmk_i2c_controller *pdata =
904 pdev->dev.platform_data;
905 struct nmk_i2c_dev *dev;
906 struct i2c_adapter *adap;
908 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
909 if (!dev) {
910 dev_err(&pdev->dev, "cannot allocate memory\n");
911 ret = -ENOMEM;
912 goto err_no_mem;
914 dev->busy = false;
915 dev->pdev = pdev;
916 platform_set_drvdata(pdev, dev);
918 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
919 if (!res) {
920 ret = -ENOENT;
921 goto err_no_resource;
924 if (request_mem_region(res->start, resource_size(res),
925 DRIVER_NAME "I/O region") == NULL) {
926 ret = -EBUSY;
927 goto err_no_region;
930 dev->virtbase = ioremap(res->start, resource_size(res));
931 if (!dev->virtbase) {
932 ret = -ENOMEM;
933 goto err_no_ioremap;
936 dev->irq = platform_get_irq(pdev, 0);
937 ret = request_irq(dev->irq, i2c_irq_handler, IRQF_DISABLED,
938 DRIVER_NAME, dev);
939 if (ret) {
940 dev_err(&pdev->dev, "cannot claim the irq %d\n", dev->irq);
941 goto err_irq;
944 dev->regulator = regulator_get(&pdev->dev, "v-i2c");
945 if (IS_ERR(dev->regulator)) {
946 dev_warn(&pdev->dev, "could not get i2c regulator\n");
947 dev->regulator = NULL;
950 pm_suspend_ignore_children(&pdev->dev, true);
951 pm_runtime_enable(&pdev->dev);
953 dev->clk = clk_get(&pdev->dev, NULL);
954 if (IS_ERR(dev->clk)) {
955 dev_err(&pdev->dev, "could not get i2c clock\n");
956 ret = PTR_ERR(dev->clk);
957 goto err_no_clk;
960 adap = &dev->adap;
961 adap->dev.parent = &pdev->dev;
962 adap->owner = THIS_MODULE;
963 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
964 adap->algo = &nmk_i2c_algo;
965 adap->timeout = pdata->timeout ? msecs_to_jiffies(pdata->timeout) :
966 msecs_to_jiffies(20000);
967 snprintf(adap->name, sizeof(adap->name),
968 "Nomadik I2C%d at %lx", pdev->id, (unsigned long)res->start);
970 /* fetch the controller id */
971 adap->nr = pdev->id;
973 /* fetch the controller configuration from machine */
974 dev->cfg.clk_freq = pdata->clk_freq;
975 dev->cfg.slsu = pdata->slsu;
976 dev->cfg.tft = pdata->tft;
977 dev->cfg.rft = pdata->rft;
978 dev->cfg.sm = pdata->sm;
980 i2c_set_adapdata(adap, dev);
982 dev_info(&pdev->dev, "initialize %s on virtual "
983 "base %p\n", adap->name, dev->virtbase);
985 ret = i2c_add_numbered_adapter(adap);
986 if (ret) {
987 dev_err(&pdev->dev, "failed to add adapter\n");
988 goto err_add_adap;
991 return 0;
993 err_add_adap:
994 clk_put(dev->clk);
995 err_no_clk:
996 if (dev->regulator)
997 regulator_put(dev->regulator);
998 pm_runtime_disable(&pdev->dev);
999 free_irq(dev->irq, dev);
1000 err_irq:
1001 iounmap(dev->virtbase);
1002 err_no_ioremap:
1003 release_mem_region(res->start, resource_size(res));
1004 err_no_region:
1005 platform_set_drvdata(pdev, NULL);
1006 err_no_resource:
1007 kfree(dev);
1008 err_no_mem:
1010 return ret;
1013 static int __devexit nmk_i2c_remove(struct platform_device *pdev)
1015 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1016 struct nmk_i2c_dev *dev = platform_get_drvdata(pdev);
1018 i2c_del_adapter(&dev->adap);
1019 flush_i2c_fifo(dev);
1020 disable_all_interrupts(dev);
1021 clear_all_interrupts(dev);
1022 /* disable the controller */
1023 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
1024 free_irq(dev->irq, dev);
1025 iounmap(dev->virtbase);
1026 if (res)
1027 release_mem_region(res->start, resource_size(res));
1028 clk_put(dev->clk);
1029 if (dev->regulator)
1030 regulator_put(dev->regulator);
1031 pm_runtime_disable(&pdev->dev);
1032 platform_set_drvdata(pdev, NULL);
1033 kfree(dev);
1035 return 0;
1038 static struct platform_driver nmk_i2c_driver = {
1039 .driver = {
1040 .owner = THIS_MODULE,
1041 .name = DRIVER_NAME,
1042 .pm = &nmk_i2c_pm,
1044 .probe = nmk_i2c_probe,
1045 .remove = __devexit_p(nmk_i2c_remove),
1048 static int __init nmk_i2c_init(void)
1050 return platform_driver_register(&nmk_i2c_driver);
1053 static void __exit nmk_i2c_exit(void)
1055 platform_driver_unregister(&nmk_i2c_driver);
1058 subsys_initcall(nmk_i2c_init);
1059 module_exit(nmk_i2c_exit);
1061 MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR");
1062 MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
1063 MODULE_LICENSE("GPL");
1064 MODULE_ALIAS("platform:" DRIVER_NAME);