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drm/i915: Add initial bits for VGA modesetting bringup on Sandybridge.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / i915_dma.c
blob7bfded5e90bb76416d0a903ddbc226ab3ef71b0a
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include <linux/vgaarb.h>
38 #include <linux/acpi.h>
39 #include <linux/pnp.h>
40
41 /* Really want an OS-independent resettable timer. Would like to have
42 * this loop run for (eg) 3 sec, but have the timer reset every time
43 * the head pointer changes, so that EBUSY only happens if the ring
44 * actually stalls for (eg) 3 seconds.
45 */
46 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
47 {
48 drm_i915_private_t *dev_priv = dev->dev_private;
49 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
50 u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
51 u32 last_acthd = I915_READ(acthd_reg);
52 u32 acthd;
53 u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
54 int i;
55
56 trace_i915_ring_wait_begin (dev);
57
58 for (i = 0; i < 100000; i++) {
59 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
60 acthd = I915_READ(acthd_reg);
61 ring->space = ring->head - (ring->tail + 8);
62 if (ring->space < 0)
63 ring->space += ring->Size;
64 if (ring->space >= n) {
65 trace_i915_ring_wait_end (dev);
66 return 0;
67 }
68
69 if (dev->primary->master) {
70 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
71 if (master_priv->sarea_priv)
72 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
73 }
74
75
76 if (ring->head != last_head)
77 i = 0;
78 if (acthd != last_acthd)
79 i = 0;
80
81 last_head = ring->head;
82 last_acthd = acthd;
83 msleep_interruptible(10);
84
85 }
86
87 trace_i915_ring_wait_end (dev);
88 return -EBUSY;
89 }
90
91 /* As a ringbuffer is only allowed to wrap between instructions, fill
92 * the tail with NOOPs.
93 */
94 int i915_wrap_ring(struct drm_device *dev)
95 {
96 drm_i915_private_t *dev_priv = dev->dev_private;
97 volatile unsigned int *virt;
98 int rem;
99
100 rem = dev_priv->ring.Size - dev_priv->ring.tail;
101 if (dev_priv->ring.space < rem) {
102 int ret = i915_wait_ring(dev, rem, __func__);
103 if (ret)
104 return ret;
105 }
106 dev_priv->ring.space -= rem;
107
108 virt = (unsigned int *)
109 (dev_priv->ring.virtual_start + dev_priv->ring.tail);
110 rem /= 4;
111 while (rem--)
112 *virt++ = MI_NOOP;
113
114 dev_priv->ring.tail = 0;
115
116 return 0;
117 }
118
119 /**
120 * Sets up the hardware status page for devices that need a physical address
121 * in the register.
122 */
123 static int i915_init_phys_hws(struct drm_device *dev)
124 {
125 drm_i915_private_t *dev_priv = dev->dev_private;
126 /* Program Hardware Status Page */
127 dev_priv->status_page_dmah =
128 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
129
130 if (!dev_priv->status_page_dmah) {
131 DRM_ERROR("Can not allocate hardware status page\n");
132 return -ENOMEM;
133 }
134 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
135 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
136
137 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
138
139 if (IS_I965G(dev))
140 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
141 0xf0;
142
143 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
144 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
145 return 0;
146 }
147
148 /**
149 * Frees the hardware status page, whether it's a physical address or a virtual
150 * address set up by the X Server.
151 */
152 static void i915_free_hws(struct drm_device *dev)
153 {
154 drm_i915_private_t *dev_priv = dev->dev_private;
155 if (dev_priv->status_page_dmah) {
156 drm_pci_free(dev, dev_priv->status_page_dmah);
157 dev_priv->status_page_dmah = NULL;
158 }
159
160 if (dev_priv->status_gfx_addr) {
161 dev_priv->status_gfx_addr = 0;
162 drm_core_ioremapfree(&dev_priv->hws_map, dev);
163 }
164
165 /* Need to rewrite hardware status page */
166 I915_WRITE(HWS_PGA, 0x1ffff000);
167 }
168
169 void i915_kernel_lost_context(struct drm_device * dev)
170 {
171 drm_i915_private_t *dev_priv = dev->dev_private;
172 struct drm_i915_master_private *master_priv;
173 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
174
175 /*
176 * We should never lose context on the ring with modesetting
177 * as we don't expose it to userspace
178 */
179 if (drm_core_check_feature(dev, DRIVER_MODESET))
180 return;
181
182 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
183 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
184 ring->space = ring->head - (ring->tail + 8);
185 if (ring->space < 0)
186 ring->space += ring->Size;
187
188 if (!dev->primary->master)
189 return;
190
191 master_priv = dev->primary->master->driver_priv;
192 if (ring->head == ring->tail && master_priv->sarea_priv)
193 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
194 }
195
196 static int i915_dma_cleanup(struct drm_device * dev)
197 {
198 drm_i915_private_t *dev_priv = dev->dev_private;
199 /* Make sure interrupts are disabled here because the uninstall ioctl
200 * may not have been called from userspace and after dev_private
201 * is freed, it's too late.
202 */
203 if (dev->irq_enabled)
204 drm_irq_uninstall(dev);
205
206 if (dev_priv->ring.virtual_start) {
207 drm_core_ioremapfree(&dev_priv->ring.map, dev);
208 dev_priv->ring.virtual_start = NULL;
209 dev_priv->ring.map.handle = NULL;
210 dev_priv->ring.map.size = 0;
211 }
212
213 /* Clear the HWS virtual address at teardown */
214 if (I915_NEED_GFX_HWS(dev))
215 i915_free_hws(dev);
216
217 return 0;
218 }
219
220 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
221 {
222 drm_i915_private_t *dev_priv = dev->dev_private;
223 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
224
225 master_priv->sarea = drm_getsarea(dev);
226 if (master_priv->sarea) {
227 master_priv->sarea_priv = (drm_i915_sarea_t *)
228 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
229 } else {
230 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
231 }
232
233 if (init->ring_size != 0) {
234 if (dev_priv->ring.ring_obj != NULL) {
235 i915_dma_cleanup(dev);
236 DRM_ERROR("Client tried to initialize ringbuffer in "
237 "GEM mode\n");
238 return -EINVAL;
239 }
240
241 dev_priv->ring.Size = init->ring_size;
242
243 dev_priv->ring.map.offset = init->ring_start;
244 dev_priv->ring.map.size = init->ring_size;
245 dev_priv->ring.map.type = 0;
246 dev_priv->ring.map.flags = 0;
247 dev_priv->ring.map.mtrr = 0;
248
249 drm_core_ioremap_wc(&dev_priv->ring.map, dev);
250
251 if (dev_priv->ring.map.handle == NULL) {
252 i915_dma_cleanup(dev);
253 DRM_ERROR("can not ioremap virtual address for"
254 " ring buffer\n");
255 return -ENOMEM;
256 }
257 }
258
259 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
260
261 dev_priv->cpp = init->cpp;
262 dev_priv->back_offset = init->back_offset;
263 dev_priv->front_offset = init->front_offset;
264 dev_priv->current_page = 0;
265 if (master_priv->sarea_priv)
266 master_priv->sarea_priv->pf_current_page = 0;
267
268 /* Allow hardware batchbuffers unless told otherwise.
269 */
270 dev_priv->allow_batchbuffer = 1;
271
272 return 0;
273 }
274
275 static int i915_dma_resume(struct drm_device * dev)
276 {
277 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
278
279 DRM_DEBUG_DRIVER("%s\n", __func__);
280
281 if (dev_priv->ring.map.handle == NULL) {
282 DRM_ERROR("can not ioremap virtual address for"
283 " ring buffer\n");
284 return -ENOMEM;
285 }
286
287 /* Program Hardware Status Page */
288 if (!dev_priv->hw_status_page) {
289 DRM_ERROR("Can not find hardware status page\n");
290 return -EINVAL;
291 }
292 DRM_DEBUG_DRIVER("hw status page @ %p\n",
293 dev_priv->hw_status_page);
294
295 if (dev_priv->status_gfx_addr != 0)
296 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
297 else
298 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
299 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
300
301 return 0;
302 }
303
304 static int i915_dma_init(struct drm_device *dev, void *data,
305 struct drm_file *file_priv)
306 {
307 drm_i915_init_t *init = data;
308 int retcode = 0;
309
310 switch (init->func) {
311 case I915_INIT_DMA:
312 retcode = i915_initialize(dev, init);
313 break;
314 case I915_CLEANUP_DMA:
315 retcode = i915_dma_cleanup(dev);
316 break;
317 case I915_RESUME_DMA:
318 retcode = i915_dma_resume(dev);
319 break;
320 default:
321 retcode = -EINVAL;
322 break;
323 }
324
325 return retcode;
326 }
327
328 /* Implement basically the same security restrictions as hardware does
329 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
330 *
331 * Most of the calculations below involve calculating the size of a
332 * particular instruction. It's important to get the size right as
333 * that tells us where the next instruction to check is. Any illegal
334 * instruction detected will be given a size of zero, which is a
335 * signal to abort the rest of the buffer.
336 */
337 static int do_validate_cmd(int cmd)
338 {
339 switch (((cmd >> 29) & 0x7)) {
340 case 0x0:
341 switch ((cmd >> 23) & 0x3f) {
342 case 0x0:
343 return 1; /* MI_NOOP */
344 case 0x4:
345 return 1; /* MI_FLUSH */
346 default:
347 return 0; /* disallow everything else */
348 }
349 break;
350 case 0x1:
351 return 0; /* reserved */
352 case 0x2:
353 return (cmd & 0xff) + 2; /* 2d commands */
354 case 0x3:
355 if (((cmd >> 24) & 0x1f) <= 0x18)
356 return 1;
357
358 switch ((cmd >> 24) & 0x1f) {
359 case 0x1c:
360 return 1;
361 case 0x1d:
362 switch ((cmd >> 16) & 0xff) {
363 case 0x3:
364 return (cmd & 0x1f) + 2;
365 case 0x4:
366 return (cmd & 0xf) + 2;
367 default:
368 return (cmd & 0xffff) + 2;
369 }
370 case 0x1e:
371 if (cmd & (1 << 23))
372 return (cmd & 0xffff) + 1;
373 else
374 return 1;
375 case 0x1f:
376 if ((cmd & (1 << 23)) == 0) /* inline vertices */
377 return (cmd & 0x1ffff) + 2;
378 else if (cmd & (1 << 17)) /* indirect random */
379 if ((cmd & 0xffff) == 0)
380 return 0; /* unknown length, too hard */
381 else
382 return (((cmd & 0xffff) + 1) / 2) + 1;
383 else
384 return 2; /* indirect sequential */
385 default:
386 return 0;
387 }
388 default:
389 return 0;
390 }
391
392 return 0;
393 }
394
395 static int validate_cmd(int cmd)
396 {
397 int ret = do_validate_cmd(cmd);
398
399 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
400
401 return ret;
402 }
403
404 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
405 {
406 drm_i915_private_t *dev_priv = dev->dev_private;
407 int i;
408 RING_LOCALS;
409
410 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
411 return -EINVAL;
412
413 BEGIN_LP_RING((dwords+1)&~1);
414
415 for (i = 0; i < dwords;) {
416 int cmd, sz;
417
418 cmd = buffer[i];
419
420 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
421 return -EINVAL;
422
423 OUT_RING(cmd);
424
425 while (++i, --sz) {
426 OUT_RING(buffer[i]);
427 }
428 }
429
430 if (dwords & 1)
431 OUT_RING(0);
432
433 ADVANCE_LP_RING();
434
435 return 0;
436 }
437
438 int
439 i915_emit_box(struct drm_device *dev,
440 struct drm_clip_rect *boxes,
441 int i, int DR1, int DR4)
442 {
443 drm_i915_private_t *dev_priv = dev->dev_private;
444 struct drm_clip_rect box = boxes[i];
445 RING_LOCALS;
446
447 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
448 DRM_ERROR("Bad box %d,%d..%d,%d\n",
449 box.x1, box.y1, box.x2, box.y2);
450 return -EINVAL;
451 }
452
453 if (IS_I965G(dev)) {
454 BEGIN_LP_RING(4);
455 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
456 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
457 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
458 OUT_RING(DR4);
459 ADVANCE_LP_RING();
460 } else {
461 BEGIN_LP_RING(6);
462 OUT_RING(GFX_OP_DRAWRECT_INFO);
463 OUT_RING(DR1);
464 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
465 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
466 OUT_RING(DR4);
467 OUT_RING(0);
468 ADVANCE_LP_RING();
469 }
470
471 return 0;
472 }
473
474 /* XXX: Emitting the counter should really be moved to part of the IRQ
475 * emit. For now, do it in both places:
476 */
477
478 static void i915_emit_breadcrumb(struct drm_device *dev)
479 {
480 drm_i915_private_t *dev_priv = dev->dev_private;
481 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
482 RING_LOCALS;
483
484 dev_priv->counter++;
485 if (dev_priv->counter > 0x7FFFFFFFUL)
486 dev_priv->counter = 0;
487 if (master_priv->sarea_priv)
488 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
489
490 BEGIN_LP_RING(4);
491 OUT_RING(MI_STORE_DWORD_INDEX);
492 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
493 OUT_RING(dev_priv->counter);
494 OUT_RING(0);
495 ADVANCE_LP_RING();
496 }
497
498 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
499 drm_i915_cmdbuffer_t *cmd,
500 struct drm_clip_rect *cliprects,
501 void *cmdbuf)
502 {
503 int nbox = cmd->num_cliprects;
504 int i = 0, count, ret;
505
506 if (cmd->sz & 0x3) {
507 DRM_ERROR("alignment");
508 return -EINVAL;
509 }
510
511 i915_kernel_lost_context(dev);
512
513 count = nbox ? nbox : 1;
514
515 for (i = 0; i < count; i++) {
516 if (i < nbox) {
517 ret = i915_emit_box(dev, cliprects, i,
518 cmd->DR1, cmd->DR4);
519 if (ret)
520 return ret;
521 }
522
523 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
524 if (ret)
525 return ret;
526 }
527
528 i915_emit_breadcrumb(dev);
529 return 0;
530 }
531
532 static int i915_dispatch_batchbuffer(struct drm_device * dev,
533 drm_i915_batchbuffer_t * batch,
534 struct drm_clip_rect *cliprects)
535 {
536 drm_i915_private_t *dev_priv = dev->dev_private;
537 int nbox = batch->num_cliprects;
538 int i = 0, count;
539 RING_LOCALS;
540
541 if ((batch->start | batch->used) & 0x7) {
542 DRM_ERROR("alignment");
543 return -EINVAL;
544 }
545
546 i915_kernel_lost_context(dev);
547
548 count = nbox ? nbox : 1;
549
550 for (i = 0; i < count; i++) {
551 if (i < nbox) {
552 int ret = i915_emit_box(dev, cliprects, i,
553 batch->DR1, batch->DR4);
554 if (ret)
555 return ret;
556 }
557
558 if (!IS_I830(dev) && !IS_845G(dev)) {
559 BEGIN_LP_RING(2);
560 if (IS_I965G(dev)) {
561 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
562 OUT_RING(batch->start);
563 } else {
564 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
565 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
566 }
567 ADVANCE_LP_RING();
568 } else {
569 BEGIN_LP_RING(4);
570 OUT_RING(MI_BATCH_BUFFER);
571 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
572 OUT_RING(batch->start + batch->used - 4);
573 OUT_RING(0);
574 ADVANCE_LP_RING();
575 }
576 }
577
578 i915_emit_breadcrumb(dev);
579
580 return 0;
581 }
582
583 static int i915_dispatch_flip(struct drm_device * dev)
584 {
585 drm_i915_private_t *dev_priv = dev->dev_private;
586 struct drm_i915_master_private *master_priv =
587 dev->primary->master->driver_priv;
588 RING_LOCALS;
589
590 if (!master_priv->sarea_priv)
591 return -EINVAL;
592
593 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
594 __func__,
595 dev_priv->current_page,
596 master_priv->sarea_priv->pf_current_page);
597
598 i915_kernel_lost_context(dev);
599
600 BEGIN_LP_RING(2);
601 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
602 OUT_RING(0);
603 ADVANCE_LP_RING();
604
605 BEGIN_LP_RING(6);
606 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
607 OUT_RING(0);
608 if (dev_priv->current_page == 0) {
609 OUT_RING(dev_priv->back_offset);
610 dev_priv->current_page = 1;
611 } else {
612 OUT_RING(dev_priv->front_offset);
613 dev_priv->current_page = 0;
614 }
615 OUT_RING(0);
616 ADVANCE_LP_RING();
617
618 BEGIN_LP_RING(2);
619 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
620 OUT_RING(0);
621 ADVANCE_LP_RING();
622
623 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
624
625 BEGIN_LP_RING(4);
626 OUT_RING(MI_STORE_DWORD_INDEX);
627 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
628 OUT_RING(dev_priv->counter);
629 OUT_RING(0);
630 ADVANCE_LP_RING();
631
632 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
633 return 0;
634 }
635
636 static int i915_quiescent(struct drm_device * dev)
637 {
638 drm_i915_private_t *dev_priv = dev->dev_private;
639
640 i915_kernel_lost_context(dev);
641 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
642 }
643
644 static int i915_flush_ioctl(struct drm_device *dev, void *data,
645 struct drm_file *file_priv)
646 {
647 int ret;
648
649 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
650
651 mutex_lock(&dev->struct_mutex);
652 ret = i915_quiescent(dev);
653 mutex_unlock(&dev->struct_mutex);
654
655 return ret;
656 }
657
658 static int i915_batchbuffer(struct drm_device *dev, void *data,
659 struct drm_file *file_priv)
660 {
661 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
662 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
663 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
664 master_priv->sarea_priv;
665 drm_i915_batchbuffer_t *batch = data;
666 int ret;
667 struct drm_clip_rect *cliprects = NULL;
668
669 if (!dev_priv->allow_batchbuffer) {
670 DRM_ERROR("Batchbuffer ioctl disabled\n");
671 return -EINVAL;
672 }
673
674 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
675 batch->start, batch->used, batch->num_cliprects);
676
677 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
678
679 if (batch->num_cliprects < 0)
680 return -EINVAL;
681
682 if (batch->num_cliprects) {
683 cliprects = kcalloc(batch->num_cliprects,
684 sizeof(struct drm_clip_rect),
685 GFP_KERNEL);
686 if (cliprects == NULL)
687 return -ENOMEM;
688
689 ret = copy_from_user(cliprects, batch->cliprects,
690 batch->num_cliprects *
691 sizeof(struct drm_clip_rect));
692 if (ret != 0)
693 goto fail_free;
694 }
695
696 mutex_lock(&dev->struct_mutex);
697 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
698 mutex_unlock(&dev->struct_mutex);
699
700 if (sarea_priv)
701 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
702
703 fail_free:
704 kfree(cliprects);
705
706 return ret;
707 }
708
709 static int i915_cmdbuffer(struct drm_device *dev, void *data,
710 struct drm_file *file_priv)
711 {
712 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
713 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
714 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
715 master_priv->sarea_priv;
716 drm_i915_cmdbuffer_t *cmdbuf = data;
717 struct drm_clip_rect *cliprects = NULL;
718 void *batch_data;
719 int ret;
720
721 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
722 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
723
724 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
725
726 if (cmdbuf->num_cliprects < 0)
727 return -EINVAL;
728
729 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
730 if (batch_data == NULL)
731 return -ENOMEM;
732
733 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
734 if (ret != 0)
735 goto fail_batch_free;
736
737 if (cmdbuf->num_cliprects) {
738 cliprects = kcalloc(cmdbuf->num_cliprects,
739 sizeof(struct drm_clip_rect), GFP_KERNEL);
740 if (cliprects == NULL) {
741 ret = -ENOMEM;
742 goto fail_batch_free;
743 }
744
745 ret = copy_from_user(cliprects, cmdbuf->cliprects,
746 cmdbuf->num_cliprects *
747 sizeof(struct drm_clip_rect));
748 if (ret != 0)
749 goto fail_clip_free;
750 }
751
752 mutex_lock(&dev->struct_mutex);
753 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
754 mutex_unlock(&dev->struct_mutex);
755 if (ret) {
756 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
757 goto fail_clip_free;
758 }
759
760 if (sarea_priv)
761 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
762
763 fail_clip_free:
764 kfree(cliprects);
765 fail_batch_free:
766 kfree(batch_data);
767
768 return ret;
769 }
770
771 static int i915_flip_bufs(struct drm_device *dev, void *data,
772 struct drm_file *file_priv)
773 {
774 int ret;
775
776 DRM_DEBUG_DRIVER("%s\n", __func__);
777
778 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
779
780 mutex_lock(&dev->struct_mutex);
781 ret = i915_dispatch_flip(dev);
782 mutex_unlock(&dev->struct_mutex);
783
784 return ret;
785 }
786
787 static int i915_getparam(struct drm_device *dev, void *data,
788 struct drm_file *file_priv)
789 {
790 drm_i915_private_t *dev_priv = dev->dev_private;
791 drm_i915_getparam_t *param = data;
792 int value;
793
794 if (!dev_priv) {
795 DRM_ERROR("called with no initialization\n");
796 return -EINVAL;
797 }
798
799 switch (param->param) {
800 case I915_PARAM_IRQ_ACTIVE:
801 value = dev->pdev->irq ? 1 : 0;
802 break;
803 case I915_PARAM_ALLOW_BATCHBUFFER:
804 value = dev_priv->allow_batchbuffer ? 1 : 0;
805 break;
806 case I915_PARAM_LAST_DISPATCH:
807 value = READ_BREADCRUMB(dev_priv);
808 break;
809 case I915_PARAM_CHIPSET_ID:
810 value = dev->pci_device;
811 break;
812 case I915_PARAM_HAS_GEM:
813 value = dev_priv->has_gem;
814 break;
815 case I915_PARAM_NUM_FENCES_AVAIL:
816 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
817 break;
818 case I915_PARAM_HAS_OVERLAY:
819 value = dev_priv->overlay ? 1 : 0;
820 break;
821 case I915_PARAM_HAS_PAGEFLIPPING:
822 value = 1;
823 break;
824 case I915_PARAM_HAS_EXECBUF2:
825 /* depends on GEM */
826 value = dev_priv->has_gem;
827 break;
828 default:
829 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
830 param->param);
831 return -EINVAL;
832 }
833
834 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
835 DRM_ERROR("DRM_COPY_TO_USER failed\n");
836 return -EFAULT;
837 }
838
839 return 0;
840 }
841
842 static int i915_setparam(struct drm_device *dev, void *data,
843 struct drm_file *file_priv)
844 {
845 drm_i915_private_t *dev_priv = dev->dev_private;
846 drm_i915_setparam_t *param = data;
847
848 if (!dev_priv) {
849 DRM_ERROR("called with no initialization\n");
850 return -EINVAL;
851 }
852
853 switch (param->param) {
854 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
855 break;
856 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
857 dev_priv->tex_lru_log_granularity = param->value;
858 break;
859 case I915_SETPARAM_ALLOW_BATCHBUFFER:
860 dev_priv->allow_batchbuffer = param->value;
861 break;
862 case I915_SETPARAM_NUM_USED_FENCES:
863 if (param->value > dev_priv->num_fence_regs ||
864 param->value < 0)
865 return -EINVAL;
866 /* Userspace can use first N regs */
867 dev_priv->fence_reg_start = param->value;
868 break;
869 default:
870 DRM_DEBUG_DRIVER("unknown parameter %d\n",
871 param->param);
872 return -EINVAL;
873 }
874
875 return 0;
876 }
877
878 static int i915_set_status_page(struct drm_device *dev, void *data,
879 struct drm_file *file_priv)
880 {
881 drm_i915_private_t *dev_priv = dev->dev_private;
882 drm_i915_hws_addr_t *hws = data;
883
884 if (!I915_NEED_GFX_HWS(dev))
885 return -EINVAL;
886
887 if (!dev_priv) {
888 DRM_ERROR("called with no initialization\n");
889 return -EINVAL;
890 }
891
892 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
893 WARN(1, "tried to set status page when mode setting active\n");
894 return 0;
895 }
896
897 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
898
899 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
900
901 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
902 dev_priv->hws_map.size = 4*1024;
903 dev_priv->hws_map.type = 0;
904 dev_priv->hws_map.flags = 0;
905 dev_priv->hws_map.mtrr = 0;
906
907 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
908 if (dev_priv->hws_map.handle == NULL) {
909 i915_dma_cleanup(dev);
910 dev_priv->status_gfx_addr = 0;
911 DRM_ERROR("can not ioremap virtual address for"
912 " G33 hw status page\n");
913 return -ENOMEM;
914 }
915 dev_priv->hw_status_page = dev_priv->hws_map.handle;
916
917 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
918 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
919 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
920 dev_priv->status_gfx_addr);
921 DRM_DEBUG_DRIVER("load hws at %p\n",
922 dev_priv->hw_status_page);
923 return 0;
924 }
925
926 static int i915_get_bridge_dev(struct drm_device *dev)
927 {
928 struct drm_i915_private *dev_priv = dev->dev_private;
929
930 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
931 if (!dev_priv->bridge_dev) {
932 DRM_ERROR("bridge device not found\n");
933 return -1;
934 }
935 return 0;
936 }
937
938 #define MCHBAR_I915 0x44
939 #define MCHBAR_I965 0x48
940 #define MCHBAR_SIZE (4*4096)
941
942 #define DEVEN_REG 0x54
943 #define DEVEN_MCHBAR_EN (1 << 28)
944
945 /* Allocate space for the MCH regs if needed, return nonzero on error */
946 static int
947 intel_alloc_mchbar_resource(struct drm_device *dev)
948 {
949 drm_i915_private_t *dev_priv = dev->dev_private;
950 int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
951 u32 temp_lo, temp_hi = 0;
952 u64 mchbar_addr;
953 int ret = 0;
954
955 if (IS_I965G(dev))
956 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
957 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
958 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
959
960 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
961 #ifdef CONFIG_PNP
962 if (mchbar_addr &&
963 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
964 ret = 0;
965 goto out;
966 }
967 #endif
968
969 /* Get some space for it */
970 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
971 MCHBAR_SIZE, MCHBAR_SIZE,
972 PCIBIOS_MIN_MEM,
973 0, pcibios_align_resource,
974 dev_priv->bridge_dev);
975 if (ret) {
976 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
977 dev_priv->mch_res.start = 0;
978 goto out;
979 }
980
981 if (IS_I965G(dev))
982 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
983 upper_32_bits(dev_priv->mch_res.start));
984
985 pci_write_config_dword(dev_priv->bridge_dev, reg,
986 lower_32_bits(dev_priv->mch_res.start));
987 out:
988 return ret;
989 }
990
991 /* Setup MCHBAR if possible, return true if we should disable it again */
992 static void
993 intel_setup_mchbar(struct drm_device *dev)
994 {
995 drm_i915_private_t *dev_priv = dev->dev_private;
996 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
997 u32 temp;
998 bool enabled;
999
1000 dev_priv->mchbar_need_disable = false;
1001
1002 if (IS_I915G(dev) || IS_I915GM(dev)) {
1003 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1004 enabled = !!(temp & DEVEN_MCHBAR_EN);
1005 } else {
1006 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1007 enabled = temp & 1;
1008 }
1009
1010 /* If it's already enabled, don't have to do anything */
1011 if (enabled)
1012 return;
1013
1014 if (intel_alloc_mchbar_resource(dev))
1015 return;
1016
1017 dev_priv->mchbar_need_disable = true;
1018
1019 /* Space is allocated or reserved, so enable it. */
1020 if (IS_I915G(dev) || IS_I915GM(dev)) {
1021 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1022 temp | DEVEN_MCHBAR_EN);
1023 } else {
1024 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1025 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1026 }
1027 }
1028
1029 static void
1030 intel_teardown_mchbar(struct drm_device *dev)
1031 {
1032 drm_i915_private_t *dev_priv = dev->dev_private;
1033 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
1034 u32 temp;
1035
1036 if (dev_priv->mchbar_need_disable) {
1037 if (IS_I915G(dev) || IS_I915GM(dev)) {
1038 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1039 temp &= ~DEVEN_MCHBAR_EN;
1040 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1041 } else {
1042 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1043 temp &= ~1;
1044 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1045 }
1046 }
1047
1048 if (dev_priv->mch_res.start)
1049 release_resource(&dev_priv->mch_res);
1050 }
1051
1052 /**
1053 * i915_probe_agp - get AGP bootup configuration
1054 * @pdev: PCI device
1055 * @aperture_size: returns AGP aperture configured size
1056 * @preallocated_size: returns size of BIOS preallocated AGP space
1057 *
1058 * Since Intel integrated graphics are UMA, the BIOS has to set aside
1059 * some RAM for the framebuffer at early boot. This code figures out
1060 * how much was set aside so we can use it for our own purposes.
1061 */
1062 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
1063 uint32_t *preallocated_size,
1064 uint32_t *start)
1065 {
1066 struct drm_i915_private *dev_priv = dev->dev_private;
1067 u16 tmp = 0;
1068 unsigned long overhead;
1069 unsigned long stolen;
1070
1071 /* Get the fb aperture size and "stolen" memory amount. */
1072 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
1073
1074 *aperture_size = 1024 * 1024;
1075 *preallocated_size = 1024 * 1024;
1076
1077 switch (dev->pdev->device) {
1078 case PCI_DEVICE_ID_INTEL_82830_CGC:
1079 case PCI_DEVICE_ID_INTEL_82845G_IG:
1080 case PCI_DEVICE_ID_INTEL_82855GM_IG:
1081 case PCI_DEVICE_ID_INTEL_82865_IG:
1082 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
1083 *aperture_size *= 64;
1084 else
1085 *aperture_size *= 128;
1086 break;
1087 default:
1088 /* 9xx supports large sizes, just look at the length */
1089 *aperture_size = pci_resource_len(dev->pdev, 2);
1090 break;
1091 }
1092
1093 /*
1094 * Some of the preallocated space is taken by the GTT
1095 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
1096 */
1097 if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
1098 overhead = 4096;
1099 else
1100 overhead = (*aperture_size / 1024) + 4096;
1101
1102 switch (tmp & INTEL_GMCH_GMS_MASK) {
1103 case INTEL_855_GMCH_GMS_DISABLED:
1104 /* XXX: This is what my A1 silicon has. */
1105 if (IS_GEN6(dev)) {
1106 stolen = 64 * 1024 * 1024;
1107 } else {
1108 DRM_ERROR("video memory is disabled\n");
1109 return -1;
1110 }
1111 break;
1112 case INTEL_855_GMCH_GMS_STOLEN_1M:
1113 stolen = 1 * 1024 * 1024;
1114 break;
1115 case INTEL_855_GMCH_GMS_STOLEN_4M:
1116 stolen = 4 * 1024 * 1024;
1117 break;
1118 case INTEL_855_GMCH_GMS_STOLEN_8M:
1119 stolen = 8 * 1024 * 1024;
1120 break;
1121 case INTEL_855_GMCH_GMS_STOLEN_16M:
1122 stolen = 16 * 1024 * 1024;
1123 break;
1124 case INTEL_855_GMCH_GMS_STOLEN_32M:
1125 stolen = 32 * 1024 * 1024;
1126 break;
1127 case INTEL_915G_GMCH_GMS_STOLEN_48M:
1128 stolen = 48 * 1024 * 1024;
1129 break;
1130 case INTEL_915G_GMCH_GMS_STOLEN_64M:
1131 stolen = 64 * 1024 * 1024;
1132 break;
1133 case INTEL_GMCH_GMS_STOLEN_128M:
1134 stolen = 128 * 1024 * 1024;
1135 break;
1136 case INTEL_GMCH_GMS_STOLEN_256M:
1137 stolen = 256 * 1024 * 1024;
1138 break;
1139 case INTEL_GMCH_GMS_STOLEN_96M:
1140 stolen = 96 * 1024 * 1024;
1141 break;
1142 case INTEL_GMCH_GMS_STOLEN_160M:
1143 stolen = 160 * 1024 * 1024;
1144 break;
1145 case INTEL_GMCH_GMS_STOLEN_224M:
1146 stolen = 224 * 1024 * 1024;
1147 break;
1148 case INTEL_GMCH_GMS_STOLEN_352M:
1149 stolen = 352 * 1024 * 1024;
1150 break;
1151 default:
1152 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1153 tmp & INTEL_GMCH_GMS_MASK);
1154 return -1;
1155 }
1156 *preallocated_size = stolen - overhead;
1157 *start = overhead;
1158
1159 return 0;
1160 }
1161
1162 #define PTE_ADDRESS_MASK 0xfffff000
1163 #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1164 #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1165 #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1166 #define PTE_MAPPING_TYPE_CACHED (3 << 1)
1167 #define PTE_MAPPING_TYPE_MASK (3 << 1)
1168 #define PTE_VALID (1 << 0)
1169
1170 /**
1171 * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1172 * @dev: drm device
1173 * @gtt_addr: address to translate
1174 *
1175 * Some chip functions require allocations from stolen space but need the
1176 * physical address of the memory in question. We use this routine
1177 * to get a physical address suitable for register programming from a given
1178 * GTT address.
1179 */
1180 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1181 unsigned long gtt_addr)
1182 {
1183 unsigned long *gtt;
1184 unsigned long entry, phys;
1185 int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1186 int gtt_offset, gtt_size;
1187
1188 if (IS_I965G(dev)) {
1189 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1190 gtt_offset = 2*1024*1024;
1191 gtt_size = 2*1024*1024;
1192 } else {
1193 gtt_offset = 512*1024;
1194 gtt_size = 512*1024;
1195 }
1196 } else {
1197 gtt_bar = 3;
1198 gtt_offset = 0;
1199 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1200 }
1201
1202 gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1203 gtt_size);
1204 if (!gtt) {
1205 DRM_ERROR("ioremap of GTT failed\n");
1206 return 0;
1207 }
1208
1209 entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1210
1211 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1212
1213 /* Mask out these reserved bits on this hardware. */
1214 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1215 IS_I945G(dev) || IS_I945GM(dev)) {
1216 entry &= ~PTE_ADDRESS_MASK_HIGH;
1217 }
1218
1219 /* If it's not a mapping type we know, then bail. */
1220 if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1221 (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1222 iounmap(gtt);
1223 return 0;
1224 }
1225
1226 if (!(entry & PTE_VALID)) {
1227 DRM_ERROR("bad GTT entry in stolen space\n");
1228 iounmap(gtt);
1229 return 0;
1230 }
1231
1232 iounmap(gtt);
1233
1234 phys =(entry & PTE_ADDRESS_MASK) |
1235 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1236
1237 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1238
1239 return phys;
1240 }
1241
1242 static void i915_warn_stolen(struct drm_device *dev)
1243 {
1244 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1245 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1246 }
1247
1248 static void i915_setup_compression(struct drm_device *dev, int size)
1249 {
1250 struct drm_i915_private *dev_priv = dev->dev_private;
1251 struct drm_mm_node *compressed_fb, *compressed_llb;
1252 unsigned long cfb_base;
1253 unsigned long ll_base = 0;
1254
1255 /* Leave 1M for line length buffer & misc. */
1256 compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1257 if (!compressed_fb) {
1258 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1259 i915_warn_stolen(dev);
1260 return;
1261 }
1262
1263 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1264 if (!compressed_fb) {
1265 i915_warn_stolen(dev);
1266 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1267 return;
1268 }
1269
1270 cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1271 if (!cfb_base) {
1272 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1273 drm_mm_put_block(compressed_fb);
1274 }
1275
1276 if (!IS_GM45(dev)) {
1277 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1278 4096, 0);
1279 if (!compressed_llb) {
1280 i915_warn_stolen(dev);
1281 return;
1282 }
1283
1284 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1285 if (!compressed_llb) {
1286 i915_warn_stolen(dev);
1287 return;
1288 }
1289
1290 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1291 if (!ll_base) {
1292 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1293 drm_mm_put_block(compressed_fb);
1294 drm_mm_put_block(compressed_llb);
1295 }
1296 }
1297
1298 dev_priv->cfb_size = size;
1299
1300 if (IS_GM45(dev)) {
1301 g4x_disable_fbc(dev);
1302 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1303 } else {
1304 i8xx_disable_fbc(dev);
1305 I915_WRITE(FBC_CFB_BASE, cfb_base);
1306 I915_WRITE(FBC_LL_BASE, ll_base);
1307 }
1308
1309 DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1310 ll_base, size >> 20);
1311 }
1312
1313 /* true = enable decode, false = disable decoder */
1314 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1315 {
1316 struct drm_device *dev = cookie;
1317
1318 intel_modeset_vga_set_state(dev, state);
1319 if (state)
1320 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1321 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1322 else
1323 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1324 }
1325
1326 static int i915_load_modeset_init(struct drm_device *dev,
1327 unsigned long prealloc_start,
1328 unsigned long prealloc_size,
1329 unsigned long agp_size)
1330 {
1331 struct drm_i915_private *dev_priv = dev->dev_private;
1332 int fb_bar = IS_I9XX(dev) ? 2 : 0;
1333 int ret = 0;
1334
1335 dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
1336 0xff000000;
1337
1338 /* Basic memrange allocator for stolen space (aka vram) */
1339 drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1340 DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1341
1342 /* We're off and running w/KMS */
1343 dev_priv->mm.suspended = 0;
1344
1345 /* Let GEM Manage from end of prealloc space to end of aperture.
1346 *
1347 * However, leave one page at the end still bound to the scratch page.
1348 * There are a number of places where the hardware apparently
1349 * prefetches past the end of the object, and we've seen multiple
1350 * hangs with the GPU head pointer stuck in a batchbuffer bound
1351 * at the last page of the aperture. One page should be enough to
1352 * keep any prefetching inside of the aperture.
1353 */
1354 i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1355
1356 mutex_lock(&dev->struct_mutex);
1357 ret = i915_gem_init_ringbuffer(dev);
1358 mutex_unlock(&dev->struct_mutex);
1359 if (ret)
1360 goto out;
1361
1362 /* Try to set up FBC with a reasonable compressed buffer size */
1363 if (I915_HAS_FBC(dev) && i915_powersave) {
1364 int cfb_size;
1365
1366 /* Try to get an 8M buffer... */
1367 if (prealloc_size > (9*1024*1024))
1368 cfb_size = 8*1024*1024;
1369 else /* fall back to 7/8 of the stolen space */
1370 cfb_size = prealloc_size * 7 / 8;
1371 i915_setup_compression(dev, cfb_size);
1372 }
1373
1374 /* Allow hardware batchbuffers unless told otherwise.
1375 */
1376 dev_priv->allow_batchbuffer = 1;
1377
1378 ret = intel_init_bios(dev);
1379 if (ret)
1380 DRM_INFO("failed to find VBIOS tables\n");
1381
1382 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1383 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1384 if (ret)
1385 goto destroy_ringbuffer;
1386
1387 intel_modeset_init(dev);
1388
1389 ret = drm_irq_install(dev);
1390 if (ret)
1391 goto destroy_ringbuffer;
1392
1393 /* Always safe in the mode setting case. */
1394 /* FIXME: do pre/post-mode set stuff in core KMS code */
1395 dev->vblank_disable_allowed = 1;
1396
1397 /*
1398 * Initialize the hardware status page IRQ location.
1399 */
1400
1401 I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1402
1403 drm_helper_initial_config(dev);
1404
1405 return 0;
1406
1407 destroy_ringbuffer:
1408 i915_gem_cleanup_ringbuffer(dev);
1409 out:
1410 return ret;
1411 }
1412
1413 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1414 {
1415 struct drm_i915_master_private *master_priv;
1416
1417 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1418 if (!master_priv)
1419 return -ENOMEM;
1420
1421 master->driver_priv = master_priv;
1422 return 0;
1423 }
1424
1425 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1426 {
1427 struct drm_i915_master_private *master_priv = master->driver_priv;
1428
1429 if (!master_priv)
1430 return;
1431
1432 kfree(master_priv);
1433
1434 master->driver_priv = NULL;
1435 }
1436
1437 static void i915_get_mem_freq(struct drm_device *dev)
1438 {
1439 drm_i915_private_t *dev_priv = dev->dev_private;
1440 u32 tmp;
1441
1442 if (!IS_PINEVIEW(dev))
1443 return;
1444
1445 tmp = I915_READ(CLKCFG);
1446
1447 switch (tmp & CLKCFG_FSB_MASK) {
1448 case CLKCFG_FSB_533:
1449 dev_priv->fsb_freq = 533; /* 133*4 */
1450 break;
1451 case CLKCFG_FSB_800:
1452 dev_priv->fsb_freq = 800; /* 200*4 */
1453 break;
1454 case CLKCFG_FSB_667:
1455 dev_priv->fsb_freq = 667; /* 167*4 */
1456 break;
1457 case CLKCFG_FSB_400:
1458 dev_priv->fsb_freq = 400; /* 100*4 */
1459 break;
1460 }
1461
1462 switch (tmp & CLKCFG_MEM_MASK) {
1463 case CLKCFG_MEM_533:
1464 dev_priv->mem_freq = 533;
1465 break;
1466 case CLKCFG_MEM_667:
1467 dev_priv->mem_freq = 667;
1468 break;
1469 case CLKCFG_MEM_800:
1470 dev_priv->mem_freq = 800;
1471 break;
1472 }
1473 }
1474
1475 /**
1476 * i915_driver_load - setup chip and create an initial config
1477 * @dev: DRM device
1478 * @flags: startup flags
1479 *
1480 * The driver load routine has to do several things:
1481 * - drive output discovery via intel_modeset_init()
1482 * - initialize the memory manager
1483 * - allocate initial config memory
1484 * - setup the DRM framebuffer with the allocated memory
1485 */
1486 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1487 {
1488 struct drm_i915_private *dev_priv = dev->dev_private;
1489 resource_size_t base, size;
1490 int ret = 0, mmio_bar;
1491 uint32_t agp_size, prealloc_size, prealloc_start;
1492
1493 /* i915 has 4 more counters */
1494 dev->counters += 4;
1495 dev->types[6] = _DRM_STAT_IRQ;
1496 dev->types[7] = _DRM_STAT_PRIMARY;
1497 dev->types[8] = _DRM_STAT_SECONDARY;
1498 dev->types[9] = _DRM_STAT_DMA;
1499
1500 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1501 if (dev_priv == NULL)
1502 return -ENOMEM;
1503
1504 dev->dev_private = (void *)dev_priv;
1505 dev_priv->dev = dev;
1506 dev_priv->info = (struct intel_device_info *) flags;
1507
1508 /* Add register map (needed for suspend/resume) */
1509 mmio_bar = IS_I9XX(dev) ? 0 : 1;
1510 base = drm_get_resource_start(dev, mmio_bar);
1511 size = drm_get_resource_len(dev, mmio_bar);
1512
1513 if (i915_get_bridge_dev(dev)) {
1514 ret = -EIO;
1515 goto free_priv;
1516 }
1517
1518 dev_priv->regs = ioremap(base, size);
1519 if (!dev_priv->regs) {
1520 DRM_ERROR("failed to map registers\n");
1521 ret = -EIO;
1522 goto put_bridge;
1523 }
1524
1525 dev_priv->mm.gtt_mapping =
1526 io_mapping_create_wc(dev->agp->base,
1527 dev->agp->agp_info.aper_size * 1024*1024);
1528 if (dev_priv->mm.gtt_mapping == NULL) {
1529 ret = -EIO;
1530 goto out_rmmap;
1531 }
1532
1533 /* Set up a WC MTRR for non-PAT systems. This is more common than
1534 * one would think, because the kernel disables PAT on first
1535 * generation Core chips because WC PAT gets overridden by a UC
1536 * MTRR if present. Even if a UC MTRR isn't present.
1537 */
1538 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1539 dev->agp->agp_info.aper_size *
1540 1024 * 1024,
1541 MTRR_TYPE_WRCOMB, 1);
1542 if (dev_priv->mm.gtt_mtrr < 0) {
1543 DRM_INFO("MTRR allocation failed. Graphics "
1544 "performance may suffer.\n");
1545 }
1546
1547 ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
1548 if (ret)
1549 goto out_iomapfree;
1550
1551 dev_priv->wq = create_singlethread_workqueue("i915");
1552 if (dev_priv->wq == NULL) {
1553 DRM_ERROR("Failed to create our workqueue.\n");
1554 ret = -ENOMEM;
1555 goto out_iomapfree;
1556 }
1557
1558 /* enable GEM by default */
1559 dev_priv->has_gem = 1;
1560
1561 if (prealloc_size > agp_size * 3 / 4) {
1562 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
1563 "memory stolen.\n",
1564 prealloc_size / 1024, agp_size / 1024);
1565 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
1566 "updating the BIOS to fix).\n");
1567 dev_priv->has_gem = 0;
1568 }
1569
1570 dev->driver->get_vblank_counter = i915_get_vblank_counter;
1571 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1572 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1573 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1574 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1575 }
1576
1577 /* Try to make sure MCHBAR is enabled before poking at it */
1578 intel_setup_mchbar(dev);
1579
1580 i915_gem_load(dev);
1581
1582 /* Init HWS */
1583 if (!I915_NEED_GFX_HWS(dev)) {
1584 ret = i915_init_phys_hws(dev);
1585 if (ret != 0)
1586 goto out_workqueue_free;
1587 }
1588
1589 i915_get_mem_freq(dev);
1590
1591 /* On the 945G/GM, the chipset reports the MSI capability on the
1592 * integrated graphics even though the support isn't actually there
1593 * according to the published specs. It doesn't appear to function
1594 * correctly in testing on 945G.
1595 * This may be a side effect of MSI having been made available for PEG
1596 * and the registers being closely associated.
1597 *
1598 * According to chipset errata, on the 965GM, MSI interrupts may
1599 * be lost or delayed, but we use them anyways to avoid
1600 * stuck interrupts on some machines.
1601 */
1602 if (!IS_I945G(dev) && !IS_I945GM(dev))
1603 pci_enable_msi(dev->pdev);
1604
1605 spin_lock_init(&dev_priv->user_irq_lock);
1606 spin_lock_init(&dev_priv->error_lock);
1607 dev_priv->user_irq_refcount = 0;
1608 dev_priv->trace_irq_seqno = 0;
1609
1610 ret = drm_vblank_init(dev, I915_NUM_PIPE);
1611
1612 if (ret) {
1613 (void) i915_driver_unload(dev);
1614 return ret;
1615 }
1616
1617 /* Start out suspended */
1618 dev_priv->mm.suspended = 1;
1619
1620 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1621 ret = i915_load_modeset_init(dev, prealloc_start,
1622 prealloc_size, agp_size);
1623 if (ret < 0) {
1624 DRM_ERROR("failed to init modeset\n");
1625 goto out_workqueue_free;
1626 }
1627 }
1628
1629 /* Must be done after probing outputs */
1630 intel_opregion_init(dev, 0);
1631
1632 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1633 (unsigned long) dev);
1634 return 0;
1635
1636 out_workqueue_free:
1637 destroy_workqueue(dev_priv->wq);
1638 out_iomapfree:
1639 io_mapping_free(dev_priv->mm.gtt_mapping);
1640 out_rmmap:
1641 iounmap(dev_priv->regs);
1642 put_bridge:
1643 pci_dev_put(dev_priv->bridge_dev);
1644 free_priv:
1645 kfree(dev_priv);
1646 return ret;
1647 }
1648
1649 int i915_driver_unload(struct drm_device *dev)
1650 {
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652
1653 i915_destroy_error_state(dev);
1654
1655 destroy_workqueue(dev_priv->wq);
1656 del_timer_sync(&dev_priv->hangcheck_timer);
1657
1658 io_mapping_free(dev_priv->mm.gtt_mapping);
1659 if (dev_priv->mm.gtt_mtrr >= 0) {
1660 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
1661 dev->agp->agp_info.aper_size * 1024 * 1024);
1662 dev_priv->mm.gtt_mtrr = -1;
1663 }
1664
1665 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1666 /*
1667 * free the memory space allocated for the child device
1668 * config parsed from VBT
1669 */
1670 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1671 kfree(dev_priv->child_dev);
1672 dev_priv->child_dev = NULL;
1673 dev_priv->child_dev_num = 0;
1674 }
1675 drm_irq_uninstall(dev);
1676 vga_client_register(dev->pdev, NULL, NULL, NULL);
1677 }
1678
1679 if (dev->pdev->msi_enabled)
1680 pci_disable_msi(dev->pdev);
1681
1682 if (dev_priv->regs != NULL)
1683 iounmap(dev_priv->regs);
1684
1685 intel_opregion_free(dev, 0);
1686
1687 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1688 intel_modeset_cleanup(dev);
1689
1690 i915_gem_free_all_phys_object(dev);
1691
1692 mutex_lock(&dev->struct_mutex);
1693 i915_gem_cleanup_ringbuffer(dev);
1694 mutex_unlock(&dev->struct_mutex);
1695 drm_mm_takedown(&dev_priv->vram);
1696 i915_gem_lastclose(dev);
1697
1698 intel_cleanup_overlay(dev);
1699 }
1700
1701 intel_teardown_mchbar(dev);
1702
1703 pci_dev_put(dev_priv->bridge_dev);
1704 kfree(dev->dev_private);
1705
1706 return 0;
1707 }
1708
1709 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1710 {
1711 struct drm_i915_file_private *i915_file_priv;
1712
1713 DRM_DEBUG_DRIVER("\n");
1714 i915_file_priv = (struct drm_i915_file_private *)
1715 kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
1716
1717 if (!i915_file_priv)
1718 return -ENOMEM;
1719
1720 file_priv->driver_priv = i915_file_priv;
1721
1722 INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1723
1724 return 0;
1725 }
1726
1727 /**
1728 * i915_driver_lastclose - clean up after all DRM clients have exited
1729 * @dev: DRM device
1730 *
1731 * Take care of cleaning up after all DRM clients have exited. In the
1732 * mode setting case, we want to restore the kernel's initial mode (just
1733 * in case the last client left us in a bad state).
1734 *
1735 * Additionally, in the non-mode setting case, we'll tear down the AGP
1736 * and DMA structures, since the kernel won't be using them, and clea
1737 * up any GEM state.
1738 */
1739 void i915_driver_lastclose(struct drm_device * dev)
1740 {
1741 drm_i915_private_t *dev_priv = dev->dev_private;
1742
1743 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1744 drm_fb_helper_restore();
1745 return;
1746 }
1747
1748 i915_gem_lastclose(dev);
1749
1750 if (dev_priv->agp_heap)
1751 i915_mem_takedown(&(dev_priv->agp_heap));
1752
1753 i915_dma_cleanup(dev);
1754 }
1755
1756 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1757 {
1758 drm_i915_private_t *dev_priv = dev->dev_private;
1759 i915_gem_release(dev, file_priv);
1760 if (!drm_core_check_feature(dev, DRIVER_MODESET))
1761 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1762 }
1763
1764 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1765 {
1766 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1767
1768 kfree(i915_file_priv);
1769 }
1770
1771 struct drm_ioctl_desc i915_ioctls[] = {
1772 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1773 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1774 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1775 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1776 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1777 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1778 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1779 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1780 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1781 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1782 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1783 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1784 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1785 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1786 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
1787 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1788 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1789 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1790 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1791 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH),
1792 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1793 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1794 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
1795 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1796 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1797 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1798 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1799 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
1800 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
1801 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1802 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0),
1803 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
1804 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
1805 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1806 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1807 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
1808 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1809 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, 0),
1810 DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW),
1811 DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW),
1812 };
1813
1814 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1815
1816 /**
1817 * Determine if the device really is AGP or not.
1818 *
1819 * All Intel graphics chipsets are treated as AGP, even if they are really
1820 * PCI-e.
1821 *
1822 * \param dev The device to be tested.
1823 *
1824 * \returns
1825 * A value of 1 is always retured to indictate every i9x5 is AGP.
1826 */
1827 int i915_driver_device_is_agp(struct drm_device * dev)
1828 {
1829 return 1;
1830 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree