2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2007 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
45 #include <net/checksum.h>
48 #include <asm/system.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
54 #include <asm/idprom.h>
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
64 #define TG3_VLAN_TAG_USED 0
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.97"
72 #define DRV_MODULE_RELDATE "December 10, 2008"
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
90 #define TG3_TX_TIMEOUT (5 * HZ)
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
115 #define TG3_TX_RING_SIZE 512
116 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
118 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
126 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
129 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
131 /* minimum number of free TX descriptors required to wake up TX process */
132 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
134 #define TG3_RAW_IP_ALIGN 2
136 /* number of ETHTOOL_GSTATS u64's */
137 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
139 #define TG3_NUM_TEST 6
141 #define FIRMWARE_TG3 "tigon/tg3.bin"
142 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
143 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
145 static char version
[] __devinitdata
=
146 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
148 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
149 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
150 MODULE_LICENSE("GPL");
151 MODULE_VERSION(DRV_MODULE_VERSION
);
152 MODULE_FIRMWARE(FIRMWARE_TG3
);
153 MODULE_FIRMWARE(FIRMWARE_TG3TSO
);
154 MODULE_FIRMWARE(FIRMWARE_TG3TSO5
);
157 static int tg3_debug
= -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
158 module_param(tg3_debug
, int, 0);
159 MODULE_PARM_DESC(tg3_debug
, "Tigon3 bitmapped debugging message enable value");
161 static struct pci_device_id tg3_pci_tbl
[] = {
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5700
)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5701
)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702
)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703
)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704
)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702FE
)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705
)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705_2
)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M
)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M_2
)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702X
)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703X
)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S
)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702A3
)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703A3
)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5782
)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5788
)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5789
)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901
)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901_2
)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S_2
)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705F
)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5720
)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5721
)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5722
)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750
)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751
)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750M
)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751M
)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751F
)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752
)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752M
)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753
)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753M
)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753F
)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754
)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754M
)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755
)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755M
)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5756
)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5786
)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787
)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787M
)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787F
)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714
)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714S
)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715
)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715S
)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780
)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780S
)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5781
)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906
)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906M
)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5784
)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5764
)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5723
)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761
)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761E
)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761S
)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761SE
)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5785
)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57760
)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57790
)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57720
)},
227 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9DXX
)},
228 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9MXX
)},
229 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1000
)},
230 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1001
)},
231 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1003
)},
232 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC9100
)},
233 {PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_TIGON3
)},
237 MODULE_DEVICE_TABLE(pci
, tg3_pci_tbl
);
239 static const struct {
240 const char string
[ETH_GSTRING_LEN
];
241 } ethtool_stats_keys
[TG3_NUM_STATS
] = {
244 { "rx_ucast_packets" },
245 { "rx_mcast_packets" },
246 { "rx_bcast_packets" },
248 { "rx_align_errors" },
249 { "rx_xon_pause_rcvd" },
250 { "rx_xoff_pause_rcvd" },
251 { "rx_mac_ctrl_rcvd" },
252 { "rx_xoff_entered" },
253 { "rx_frame_too_long_errors" },
255 { "rx_undersize_packets" },
256 { "rx_in_length_errors" },
257 { "rx_out_length_errors" },
258 { "rx_64_or_less_octet_packets" },
259 { "rx_65_to_127_octet_packets" },
260 { "rx_128_to_255_octet_packets" },
261 { "rx_256_to_511_octet_packets" },
262 { "rx_512_to_1023_octet_packets" },
263 { "rx_1024_to_1522_octet_packets" },
264 { "rx_1523_to_2047_octet_packets" },
265 { "rx_2048_to_4095_octet_packets" },
266 { "rx_4096_to_8191_octet_packets" },
267 { "rx_8192_to_9022_octet_packets" },
274 { "tx_flow_control" },
276 { "tx_single_collisions" },
277 { "tx_mult_collisions" },
279 { "tx_excessive_collisions" },
280 { "tx_late_collisions" },
281 { "tx_collide_2times" },
282 { "tx_collide_3times" },
283 { "tx_collide_4times" },
284 { "tx_collide_5times" },
285 { "tx_collide_6times" },
286 { "tx_collide_7times" },
287 { "tx_collide_8times" },
288 { "tx_collide_9times" },
289 { "tx_collide_10times" },
290 { "tx_collide_11times" },
291 { "tx_collide_12times" },
292 { "tx_collide_13times" },
293 { "tx_collide_14times" },
294 { "tx_collide_15times" },
295 { "tx_ucast_packets" },
296 { "tx_mcast_packets" },
297 { "tx_bcast_packets" },
298 { "tx_carrier_sense_errors" },
302 { "dma_writeq_full" },
303 { "dma_write_prioq_full" },
307 { "rx_threshold_hit" },
309 { "dma_readq_full" },
310 { "dma_read_prioq_full" },
311 { "tx_comp_queue_full" },
313 { "ring_set_send_prod_index" },
314 { "ring_status_update" },
316 { "nic_avoided_irqs" },
317 { "nic_tx_threshold_hit" }
320 static const struct {
321 const char string
[ETH_GSTRING_LEN
];
322 } ethtool_test_keys
[TG3_NUM_TEST
] = {
323 { "nvram test (online) " },
324 { "link test (online) " },
325 { "register test (offline)" },
326 { "memory test (offline)" },
327 { "loopback test (offline)" },
328 { "interrupt test (offline)" },
331 static void tg3_write32(struct tg3
*tp
, u32 off
, u32 val
)
333 writel(val
, tp
->regs
+ off
);
336 static u32
tg3_read32(struct tg3
*tp
, u32 off
)
338 return (readl(tp
->regs
+ off
));
341 static void tg3_ape_write32(struct tg3
*tp
, u32 off
, u32 val
)
343 writel(val
, tp
->aperegs
+ off
);
346 static u32
tg3_ape_read32(struct tg3
*tp
, u32 off
)
348 return (readl(tp
->aperegs
+ off
));
351 static void tg3_write_indirect_reg32(struct tg3
*tp
, u32 off
, u32 val
)
355 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
356 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
357 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
358 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
361 static void tg3_write_flush_reg32(struct tg3
*tp
, u32 off
, u32 val
)
363 writel(val
, tp
->regs
+ off
);
364 readl(tp
->regs
+ off
);
367 static u32
tg3_read_indirect_reg32(struct tg3
*tp
, u32 off
)
372 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
373 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
374 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
375 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
379 static void tg3_write_indirect_mbox(struct tg3
*tp
, u32 off
, u32 val
)
383 if (off
== (MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
)) {
384 pci_write_config_dword(tp
->pdev
, TG3PCI_RCV_RET_RING_CON_IDX
+
385 TG3_64BIT_REG_LOW
, val
);
388 if (off
== (MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
)) {
389 pci_write_config_dword(tp
->pdev
, TG3PCI_STD_RING_PROD_IDX
+
390 TG3_64BIT_REG_LOW
, val
);
394 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
395 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
396 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
397 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
399 /* In indirect mode when disabling interrupts, we also need
400 * to clear the interrupt bit in the GRC local ctrl register.
402 if ((off
== (MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
)) &&
404 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_LOCAL_CTRL
,
405 tp
->grc_local_ctrl
|GRC_LCLCTRL_CLEARINT
);
409 static u32
tg3_read_indirect_mbox(struct tg3
*tp
, u32 off
)
414 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
415 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
416 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
417 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
421 /* usec_wait specifies the wait time in usec when writing to certain registers
422 * where it is unsafe to read back the register without some delay.
423 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
424 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
426 static void _tw32_flush(struct tg3
*tp
, u32 off
, u32 val
, u32 usec_wait
)
428 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) ||
429 (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
430 /* Non-posted methods */
431 tp
->write32(tp
, off
, val
);
434 tg3_write32(tp
, off
, val
);
439 /* Wait again after the read for the posted method to guarantee that
440 * the wait time is met.
446 static inline void tw32_mailbox_flush(struct tg3
*tp
, u32 off
, u32 val
)
448 tp
->write32_mbox(tp
, off
, val
);
449 if (!(tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) &&
450 !(tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
451 tp
->read32_mbox(tp
, off
);
454 static void tg3_write32_tx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
456 void __iomem
*mbox
= tp
->regs
+ off
;
458 if (tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
)
460 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
464 static u32
tg3_read32_mbox_5906(struct tg3
*tp
, u32 off
)
466 return (readl(tp
->regs
+ off
+ GRCMBOX_BASE
));
469 static void tg3_write32_mbox_5906(struct tg3
*tp
, u32 off
, u32 val
)
471 writel(val
, tp
->regs
+ off
+ GRCMBOX_BASE
);
474 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
475 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
476 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
477 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
478 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
480 #define tw32(reg,val) tp->write32(tp, reg, val)
481 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
482 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
483 #define tr32(reg) tp->read32(tp, reg)
485 static void tg3_write_mem(struct tg3
*tp
, u32 off
, u32 val
)
489 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
490 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
))
493 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
494 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
495 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
496 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
498 /* Always leave this as zero. */
499 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
501 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
502 tw32_f(TG3PCI_MEM_WIN_DATA
, val
);
504 /* Always leave this as zero. */
505 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
507 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
510 static void tg3_read_mem(struct tg3
*tp
, u32 off
, u32
*val
)
514 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
515 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
)) {
520 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
521 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
522 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
523 pci_read_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
525 /* Always leave this as zero. */
526 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
529 *val
= tr32(TG3PCI_MEM_WIN_DATA
);
531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
534 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
537 static void tg3_ape_lock_init(struct tg3
*tp
)
541 /* Make sure the driver hasn't any stale locks. */
542 for (i
= 0; i
< 8; i
++)
543 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ 4 * i
,
544 APE_LOCK_GRANT_DRIVER
);
547 static int tg3_ape_lock(struct tg3
*tp
, int locknum
)
553 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
557 case TG3_APE_LOCK_GRC
:
558 case TG3_APE_LOCK_MEM
:
566 tg3_ape_write32(tp
, TG3_APE_LOCK_REQ
+ off
, APE_LOCK_REQ_DRIVER
);
568 /* Wait for up to 1 millisecond to acquire lock. */
569 for (i
= 0; i
< 100; i
++) {
570 status
= tg3_ape_read32(tp
, TG3_APE_LOCK_GRANT
+ off
);
571 if (status
== APE_LOCK_GRANT_DRIVER
)
576 if (status
!= APE_LOCK_GRANT_DRIVER
) {
577 /* Revoke the lock request. */
578 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ off
,
579 APE_LOCK_GRANT_DRIVER
);
587 static void tg3_ape_unlock(struct tg3
*tp
, int locknum
)
591 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
595 case TG3_APE_LOCK_GRC
:
596 case TG3_APE_LOCK_MEM
:
603 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ off
, APE_LOCK_GRANT_DRIVER
);
606 static void tg3_disable_ints(struct tg3
*tp
)
608 tw32(TG3PCI_MISC_HOST_CTRL
,
609 (tp
->misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
));
610 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
613 static inline void tg3_cond_int(struct tg3
*tp
)
615 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
616 (tp
->hw_status
->status
& SD_STATUS_UPDATED
))
617 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
619 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
620 (HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
));
623 static void tg3_enable_ints(struct tg3
*tp
)
628 tw32(TG3PCI_MISC_HOST_CTRL
,
629 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
630 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
631 (tp
->last_tag
<< 24));
632 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
633 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
634 (tp
->last_tag
<< 24));
638 static inline unsigned int tg3_has_work(struct tg3
*tp
)
640 struct tg3_hw_status
*sblk
= tp
->hw_status
;
641 unsigned int work_exists
= 0;
643 /* check for phy events */
644 if (!(tp
->tg3_flags
&
645 (TG3_FLAG_USE_LINKCHG_REG
|
646 TG3_FLAG_POLL_SERDES
))) {
647 if (sblk
->status
& SD_STATUS_LINK_CHG
)
650 /* check for RX/TX work to do */
651 if (sblk
->idx
[0].tx_consumer
!= tp
->tx_cons
||
652 sblk
->idx
[0].rx_producer
!= tp
->rx_rcb_ptr
)
659 * similar to tg3_enable_ints, but it accurately determines whether there
660 * is new work pending and can return without flushing the PIO write
661 * which reenables interrupts
663 static void tg3_restart_ints(struct tg3
*tp
)
665 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
669 /* When doing tagged status, this work check is unnecessary.
670 * The last_tag we write above tells the chip which piece of
671 * work we've completed.
673 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
675 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
676 (HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
));
679 static inline void tg3_netif_stop(struct tg3
*tp
)
681 tp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
682 napi_disable(&tp
->napi
);
683 netif_tx_disable(tp
->dev
);
686 static inline void tg3_netif_start(struct tg3
*tp
)
688 netif_wake_queue(tp
->dev
);
689 /* NOTE: unconditional netif_wake_queue is only appropriate
690 * so long as all callers are assured to have free tx slots
691 * (such as after tg3_init_hw)
693 napi_enable(&tp
->napi
);
694 tp
->hw_status
->status
|= SD_STATUS_UPDATED
;
698 static void tg3_switch_clocks(struct tg3
*tp
)
700 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
);
703 if ((tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
704 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
707 orig_clock_ctrl
= clock_ctrl
;
708 clock_ctrl
&= (CLOCK_CTRL_FORCE_CLKRUN
|
709 CLOCK_CTRL_CLKRUN_OENABLE
|
711 tp
->pci_clock_ctrl
= clock_ctrl
;
713 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
714 if (orig_clock_ctrl
& CLOCK_CTRL_625_CORE
) {
715 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
716 clock_ctrl
| CLOCK_CTRL_625_CORE
, 40);
718 } else if ((orig_clock_ctrl
& CLOCK_CTRL_44MHZ_CORE
) != 0) {
719 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
721 (CLOCK_CTRL_44MHZ_CORE
| CLOCK_CTRL_ALTCLK
),
723 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
724 clock_ctrl
| (CLOCK_CTRL_ALTCLK
),
727 tw32_wait_f(TG3PCI_CLOCK_CTRL
, clock_ctrl
, 40);
730 #define PHY_BUSY_LOOPS 5000
732 static int tg3_readphy(struct tg3
*tp
, int reg
, u32
*val
)
738 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
740 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
746 frame_val
= ((PHY_ADDR
<< MI_COM_PHY_ADDR_SHIFT
) &
747 MI_COM_PHY_ADDR_MASK
);
748 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
749 MI_COM_REG_ADDR_MASK
);
750 frame_val
|= (MI_COM_CMD_READ
| MI_COM_START
);
752 tw32_f(MAC_MI_COM
, frame_val
);
754 loops
= PHY_BUSY_LOOPS
;
757 frame_val
= tr32(MAC_MI_COM
);
759 if ((frame_val
& MI_COM_BUSY
) == 0) {
761 frame_val
= tr32(MAC_MI_COM
);
769 *val
= frame_val
& MI_COM_DATA_MASK
;
773 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
774 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
781 static int tg3_writephy(struct tg3
*tp
, int reg
, u32 val
)
787 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
&&
788 (reg
== MII_TG3_CTRL
|| reg
== MII_TG3_AUX_CTRL
))
791 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
793 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
797 frame_val
= ((PHY_ADDR
<< MI_COM_PHY_ADDR_SHIFT
) &
798 MI_COM_PHY_ADDR_MASK
);
799 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
800 MI_COM_REG_ADDR_MASK
);
801 frame_val
|= (val
& MI_COM_DATA_MASK
);
802 frame_val
|= (MI_COM_CMD_WRITE
| MI_COM_START
);
804 tw32_f(MAC_MI_COM
, frame_val
);
806 loops
= PHY_BUSY_LOOPS
;
809 frame_val
= tr32(MAC_MI_COM
);
810 if ((frame_val
& MI_COM_BUSY
) == 0) {
812 frame_val
= tr32(MAC_MI_COM
);
822 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
823 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
830 static int tg3_bmcr_reset(struct tg3
*tp
)
835 /* OK, reset it, and poll the BMCR_RESET bit until it
836 * clears or we time out.
838 phy_control
= BMCR_RESET
;
839 err
= tg3_writephy(tp
, MII_BMCR
, phy_control
);
845 err
= tg3_readphy(tp
, MII_BMCR
, &phy_control
);
849 if ((phy_control
& BMCR_RESET
) == 0) {
861 static int tg3_mdio_read(struct mii_bus
*bp
, int mii_id
, int reg
)
863 struct tg3
*tp
= (struct tg3
*)bp
->priv
;
866 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_PAUSED
)
869 if (tg3_readphy(tp
, reg
, &val
))
875 static int tg3_mdio_write(struct mii_bus
*bp
, int mii_id
, int reg
, u16 val
)
877 struct tg3
*tp
= (struct tg3
*)bp
->priv
;
879 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_PAUSED
)
882 if (tg3_writephy(tp
, reg
, val
))
888 static int tg3_mdio_reset(struct mii_bus
*bp
)
893 static void tg3_mdio_config_5785(struct tg3
*tp
)
896 struct phy_device
*phydev
;
898 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
899 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
900 case TG3_PHY_ID_BCM50610
:
901 val
= MAC_PHYCFG2_50610_LED_MODES
;
903 case TG3_PHY_ID_BCMAC131
:
904 val
= MAC_PHYCFG2_AC131_LED_MODES
;
906 case TG3_PHY_ID_RTL8211C
:
907 val
= MAC_PHYCFG2_RTL8211C_LED_MODES
;
909 case TG3_PHY_ID_RTL8201E
:
910 val
= MAC_PHYCFG2_RTL8201E_LED_MODES
;
916 if (phydev
->interface
!= PHY_INTERFACE_MODE_RGMII
) {
917 tw32(MAC_PHYCFG2
, val
);
919 val
= tr32(MAC_PHYCFG1
);
920 val
&= ~MAC_PHYCFG1_RGMII_INT
;
921 tw32(MAC_PHYCFG1
, val
);
926 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
))
927 val
|= MAC_PHYCFG2_EMODE_MASK_MASK
|
928 MAC_PHYCFG2_FMODE_MASK_MASK
|
929 MAC_PHYCFG2_GMODE_MASK_MASK
|
930 MAC_PHYCFG2_ACT_MASK_MASK
|
931 MAC_PHYCFG2_QUAL_MASK_MASK
|
932 MAC_PHYCFG2_INBAND_ENABLE
;
934 tw32(MAC_PHYCFG2
, val
);
936 val
= tr32(MAC_PHYCFG1
) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC
|
937 MAC_PHYCFG1_RGMII_SND_STAT_EN
);
938 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
) {
939 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
940 val
|= MAC_PHYCFG1_RGMII_EXT_RX_DEC
;
941 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
942 val
|= MAC_PHYCFG1_RGMII_SND_STAT_EN
;
944 tw32(MAC_PHYCFG1
, val
| MAC_PHYCFG1_RGMII_INT
| MAC_PHYCFG1_TXC_DRV
);
946 val
= tr32(MAC_EXT_RGMII_MODE
);
947 val
&= ~(MAC_RGMII_MODE_RX_INT_B
|
948 MAC_RGMII_MODE_RX_QUALITY
|
949 MAC_RGMII_MODE_RX_ACTIVITY
|
950 MAC_RGMII_MODE_RX_ENG_DET
|
951 MAC_RGMII_MODE_TX_ENABLE
|
952 MAC_RGMII_MODE_TX_LOWPWR
|
953 MAC_RGMII_MODE_TX_RESET
);
954 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
)) {
955 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
956 val
|= MAC_RGMII_MODE_RX_INT_B
|
957 MAC_RGMII_MODE_RX_QUALITY
|
958 MAC_RGMII_MODE_RX_ACTIVITY
|
959 MAC_RGMII_MODE_RX_ENG_DET
;
960 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
961 val
|= MAC_RGMII_MODE_TX_ENABLE
|
962 MAC_RGMII_MODE_TX_LOWPWR
|
963 MAC_RGMII_MODE_TX_RESET
;
965 tw32(MAC_EXT_RGMII_MODE
, val
);
968 static void tg3_mdio_start(struct tg3
*tp
)
970 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
971 mutex_lock(&tp
->mdio_bus
->mdio_lock
);
972 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_PAUSED
;
973 mutex_unlock(&tp
->mdio_bus
->mdio_lock
);
976 tp
->mi_mode
&= ~MAC_MI_MODE_AUTO_POLL
;
977 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
980 if ((tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) &&
981 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
982 tg3_mdio_config_5785(tp
);
985 static void tg3_mdio_stop(struct tg3
*tp
)
987 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
988 mutex_lock(&tp
->mdio_bus
->mdio_lock
);
989 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_PAUSED
;
990 mutex_unlock(&tp
->mdio_bus
->mdio_lock
);
994 static int tg3_mdio_init(struct tg3
*tp
)
998 struct phy_device
*phydev
;
1002 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) ||
1003 (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
))
1006 tp
->mdio_bus
= mdiobus_alloc();
1007 if (tp
->mdio_bus
== NULL
)
1010 tp
->mdio_bus
->name
= "tg3 mdio bus";
1011 snprintf(tp
->mdio_bus
->id
, MII_BUS_ID_SIZE
, "%x",
1012 (tp
->pdev
->bus
->number
<< 8) | tp
->pdev
->devfn
);
1013 tp
->mdio_bus
->priv
= tp
;
1014 tp
->mdio_bus
->parent
= &tp
->pdev
->dev
;
1015 tp
->mdio_bus
->read
= &tg3_mdio_read
;
1016 tp
->mdio_bus
->write
= &tg3_mdio_write
;
1017 tp
->mdio_bus
->reset
= &tg3_mdio_reset
;
1018 tp
->mdio_bus
->phy_mask
= ~(1 << PHY_ADDR
);
1019 tp
->mdio_bus
->irq
= &tp
->mdio_irq
[0];
1021 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1022 tp
->mdio_bus
->irq
[i
] = PHY_POLL
;
1024 /* The bus registration will look for all the PHYs on the mdio bus.
1025 * Unfortunately, it does not ensure the PHY is powered up before
1026 * accessing the PHY ID registers. A chip reset is the
1027 * quickest way to bring the device back to an operational state..
1029 if (tg3_readphy(tp
, MII_BMCR
, ®
) || (reg
& BMCR_PDOWN
))
1032 i
= mdiobus_register(tp
->mdio_bus
);
1034 printk(KERN_WARNING
"%s: mdiobus_reg failed (0x%x)\n",
1036 mdiobus_free(tp
->mdio_bus
);
1040 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1042 if (!phydev
|| !phydev
->drv
) {
1043 printk(KERN_WARNING
"%s: No PHY devices\n", tp
->dev
->name
);
1044 mdiobus_unregister(tp
->mdio_bus
);
1045 mdiobus_free(tp
->mdio_bus
);
1049 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1050 case TG3_PHY_ID_BCM57780
:
1051 phydev
->interface
= PHY_INTERFACE_MODE_GMII
;
1053 case TG3_PHY_ID_BCM50610
:
1054 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
)
1055 phydev
->dev_flags
|= PHY_BRCM_STD_IBND_DISABLE
;
1056 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1057 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_RX_ENABLE
;
1058 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1059 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_TX_ENABLE
;
1061 case TG3_PHY_ID_RTL8211C
:
1062 phydev
->interface
= PHY_INTERFACE_MODE_RGMII
;
1064 case TG3_PHY_ID_RTL8201E
:
1065 case TG3_PHY_ID_BCMAC131
:
1066 phydev
->interface
= PHY_INTERFACE_MODE_MII
;
1070 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_INITED
;
1072 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1073 tg3_mdio_config_5785(tp
);
1078 static void tg3_mdio_fini(struct tg3
*tp
)
1080 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
1081 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_INITED
;
1082 mdiobus_unregister(tp
->mdio_bus
);
1083 mdiobus_free(tp
->mdio_bus
);
1084 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_PAUSED
;
1088 /* tp->lock is held. */
1089 static inline void tg3_generate_fw_event(struct tg3
*tp
)
1093 val
= tr32(GRC_RX_CPU_EVENT
);
1094 val
|= GRC_RX_CPU_DRIVER_EVENT
;
1095 tw32_f(GRC_RX_CPU_EVENT
, val
);
1097 tp
->last_event_jiffies
= jiffies
;
1100 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1102 /* tp->lock is held. */
1103 static void tg3_wait_for_event_ack(struct tg3
*tp
)
1106 unsigned int delay_cnt
;
1109 /* If enough time has passed, no wait is necessary. */
1110 time_remain
= (long)(tp
->last_event_jiffies
+ 1 +
1111 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC
)) -
1113 if (time_remain
< 0)
1116 /* Check if we can shorten the wait time. */
1117 delay_cnt
= jiffies_to_usecs(time_remain
);
1118 if (delay_cnt
> TG3_FW_EVENT_TIMEOUT_USEC
)
1119 delay_cnt
= TG3_FW_EVENT_TIMEOUT_USEC
;
1120 delay_cnt
= (delay_cnt
>> 3) + 1;
1122 for (i
= 0; i
< delay_cnt
; i
++) {
1123 if (!(tr32(GRC_RX_CPU_EVENT
) & GRC_RX_CPU_DRIVER_EVENT
))
1129 /* tp->lock is held. */
1130 static void tg3_ump_link_report(struct tg3
*tp
)
1135 if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
1136 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
1139 tg3_wait_for_event_ack(tp
);
1141 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_LINK_UPDATE
);
1143 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 14);
1146 if (!tg3_readphy(tp
, MII_BMCR
, ®
))
1148 if (!tg3_readphy(tp
, MII_BMSR
, ®
))
1149 val
|= (reg
& 0xffff);
1150 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, val
);
1153 if (!tg3_readphy(tp
, MII_ADVERTISE
, ®
))
1155 if (!tg3_readphy(tp
, MII_LPA
, ®
))
1156 val
|= (reg
& 0xffff);
1157 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 4, val
);
1160 if (!(tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)) {
1161 if (!tg3_readphy(tp
, MII_CTRL1000
, ®
))
1163 if (!tg3_readphy(tp
, MII_STAT1000
, ®
))
1164 val
|= (reg
& 0xffff);
1166 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 8, val
);
1168 if (!tg3_readphy(tp
, MII_PHYADDR
, ®
))
1172 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 12, val
);
1174 tg3_generate_fw_event(tp
);
1177 static void tg3_link_report(struct tg3
*tp
)
1179 if (!netif_carrier_ok(tp
->dev
)) {
1180 if (netif_msg_link(tp
))
1181 printk(KERN_INFO PFX
"%s: Link is down.\n",
1183 tg3_ump_link_report(tp
);
1184 } else if (netif_msg_link(tp
)) {
1185 printk(KERN_INFO PFX
"%s: Link is up at %d Mbps, %s duplex.\n",
1187 (tp
->link_config
.active_speed
== SPEED_1000
?
1189 (tp
->link_config
.active_speed
== SPEED_100
?
1191 (tp
->link_config
.active_duplex
== DUPLEX_FULL
?
1194 printk(KERN_INFO PFX
1195 "%s: Flow control is %s for TX and %s for RX.\n",
1197 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
) ?
1199 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
) ?
1201 tg3_ump_link_report(tp
);
1205 static u16
tg3_advert_flowctrl_1000T(u8 flow_ctrl
)
1209 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1210 miireg
= ADVERTISE_PAUSE_CAP
;
1211 else if (flow_ctrl
& FLOW_CTRL_TX
)
1212 miireg
= ADVERTISE_PAUSE_ASYM
;
1213 else if (flow_ctrl
& FLOW_CTRL_RX
)
1214 miireg
= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1221 static u16
tg3_advert_flowctrl_1000X(u8 flow_ctrl
)
1225 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1226 miireg
= ADVERTISE_1000XPAUSE
;
1227 else if (flow_ctrl
& FLOW_CTRL_TX
)
1228 miireg
= ADVERTISE_1000XPSE_ASYM
;
1229 else if (flow_ctrl
& FLOW_CTRL_RX
)
1230 miireg
= ADVERTISE_1000XPAUSE
| ADVERTISE_1000XPSE_ASYM
;
1237 static u8
tg3_resolve_flowctrl_1000X(u16 lcladv
, u16 rmtadv
)
1241 if (lcladv
& ADVERTISE_1000XPAUSE
) {
1242 if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1243 if (rmtadv
& LPA_1000XPAUSE
)
1244 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1245 else if (rmtadv
& LPA_1000XPAUSE_ASYM
)
1248 if (rmtadv
& LPA_1000XPAUSE
)
1249 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1251 } else if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1252 if ((rmtadv
& LPA_1000XPAUSE
) && (rmtadv
& LPA_1000XPAUSE_ASYM
))
1259 static void tg3_setup_flow_control(struct tg3
*tp
, u32 lcladv
, u32 rmtadv
)
1263 u32 old_rx_mode
= tp
->rx_mode
;
1264 u32 old_tx_mode
= tp
->tx_mode
;
1266 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
1267 autoneg
= tp
->mdio_bus
->phy_map
[PHY_ADDR
]->autoneg
;
1269 autoneg
= tp
->link_config
.autoneg
;
1271 if (autoneg
== AUTONEG_ENABLE
&&
1272 (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)) {
1273 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
1274 flowctrl
= tg3_resolve_flowctrl_1000X(lcladv
, rmtadv
);
1276 flowctrl
= mii_resolve_flowctrl_fdx(lcladv
, rmtadv
);
1278 flowctrl
= tp
->link_config
.flowctrl
;
1280 tp
->link_config
.active_flowctrl
= flowctrl
;
1282 if (flowctrl
& FLOW_CTRL_RX
)
1283 tp
->rx_mode
|= RX_MODE_FLOW_CTRL_ENABLE
;
1285 tp
->rx_mode
&= ~RX_MODE_FLOW_CTRL_ENABLE
;
1287 if (old_rx_mode
!= tp
->rx_mode
)
1288 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
1290 if (flowctrl
& FLOW_CTRL_TX
)
1291 tp
->tx_mode
|= TX_MODE_FLOW_CTRL_ENABLE
;
1293 tp
->tx_mode
&= ~TX_MODE_FLOW_CTRL_ENABLE
;
1295 if (old_tx_mode
!= tp
->tx_mode
)
1296 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
1299 static void tg3_adjust_link(struct net_device
*dev
)
1301 u8 oldflowctrl
, linkmesg
= 0;
1302 u32 mac_mode
, lcl_adv
, rmt_adv
;
1303 struct tg3
*tp
= netdev_priv(dev
);
1304 struct phy_device
*phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1306 spin_lock(&tp
->lock
);
1308 mac_mode
= tp
->mac_mode
& ~(MAC_MODE_PORT_MODE_MASK
|
1309 MAC_MODE_HALF_DUPLEX
);
1311 oldflowctrl
= tp
->link_config
.active_flowctrl
;
1317 if (phydev
->speed
== SPEED_100
|| phydev
->speed
== SPEED_10
)
1318 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1320 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1322 if (phydev
->duplex
== DUPLEX_HALF
)
1323 mac_mode
|= MAC_MODE_HALF_DUPLEX
;
1325 lcl_adv
= tg3_advert_flowctrl_1000T(
1326 tp
->link_config
.flowctrl
);
1329 rmt_adv
= LPA_PAUSE_CAP
;
1330 if (phydev
->asym_pause
)
1331 rmt_adv
|= LPA_PAUSE_ASYM
;
1334 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
1336 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1338 if (mac_mode
!= tp
->mac_mode
) {
1339 tp
->mac_mode
= mac_mode
;
1340 tw32_f(MAC_MODE
, tp
->mac_mode
);
1344 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
1345 if (phydev
->speed
== SPEED_10
)
1347 MAC_MI_STAT_10MBPS_MODE
|
1348 MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1350 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1353 if (phydev
->speed
== SPEED_1000
&& phydev
->duplex
== DUPLEX_HALF
)
1354 tw32(MAC_TX_LENGTHS
,
1355 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1356 (6 << TX_LENGTHS_IPG_SHIFT
) |
1357 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1359 tw32(MAC_TX_LENGTHS
,
1360 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1361 (6 << TX_LENGTHS_IPG_SHIFT
) |
1362 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1364 if ((phydev
->link
&& tp
->link_config
.active_speed
== SPEED_INVALID
) ||
1365 (!phydev
->link
&& tp
->link_config
.active_speed
!= SPEED_INVALID
) ||
1366 phydev
->speed
!= tp
->link_config
.active_speed
||
1367 phydev
->duplex
!= tp
->link_config
.active_duplex
||
1368 oldflowctrl
!= tp
->link_config
.active_flowctrl
)
1371 tp
->link_config
.active_speed
= phydev
->speed
;
1372 tp
->link_config
.active_duplex
= phydev
->duplex
;
1374 spin_unlock(&tp
->lock
);
1377 tg3_link_report(tp
);
1380 static int tg3_phy_init(struct tg3
*tp
)
1382 struct phy_device
*phydev
;
1384 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
)
1387 /* Bring the PHY back to a known state. */
1390 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1392 /* Attach the MAC to the PHY. */
1393 phydev
= phy_connect(tp
->dev
, dev_name(&phydev
->dev
), tg3_adjust_link
,
1394 phydev
->dev_flags
, phydev
->interface
);
1395 if (IS_ERR(phydev
)) {
1396 printk(KERN_ERR
"%s: Could not attach to PHY\n", tp
->dev
->name
);
1397 return PTR_ERR(phydev
);
1400 /* Mask with MAC supported features. */
1401 switch (phydev
->interface
) {
1402 case PHY_INTERFACE_MODE_GMII
:
1403 case PHY_INTERFACE_MODE_RGMII
:
1404 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
1405 phydev
->supported
&= (PHY_GBIT_FEATURES
|
1407 SUPPORTED_Asym_Pause
);
1411 case PHY_INTERFACE_MODE_MII
:
1412 phydev
->supported
&= (PHY_BASIC_FEATURES
|
1414 SUPPORTED_Asym_Pause
);
1417 phy_disconnect(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
1421 tp
->tg3_flags3
|= TG3_FLG3_PHY_CONNECTED
;
1423 phydev
->advertising
= phydev
->supported
;
1428 static void tg3_phy_start(struct tg3
*tp
)
1430 struct phy_device
*phydev
;
1432 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
1435 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1437 if (tp
->link_config
.phy_is_low_power
) {
1438 tp
->link_config
.phy_is_low_power
= 0;
1439 phydev
->speed
= tp
->link_config
.orig_speed
;
1440 phydev
->duplex
= tp
->link_config
.orig_duplex
;
1441 phydev
->autoneg
= tp
->link_config
.orig_autoneg
;
1442 phydev
->advertising
= tp
->link_config
.orig_advertising
;
1447 phy_start_aneg(phydev
);
1450 static void tg3_phy_stop(struct tg3
*tp
)
1452 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
1455 phy_stop(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
1458 static void tg3_phy_fini(struct tg3
*tp
)
1460 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
1461 phy_disconnect(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
1462 tp
->tg3_flags3
&= ~TG3_FLG3_PHY_CONNECTED
;
1466 static void tg3_phydsp_write(struct tg3
*tp
, u32 reg
, u32 val
)
1468 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
1469 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, val
);
1472 static void tg3_phy_toggle_apd(struct tg3
*tp
, bool enable
)
1476 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1477 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
1480 reg
= MII_TG3_MISC_SHDW_WREN
|
1481 MII_TG3_MISC_SHDW_SCR5_SEL
|
1482 MII_TG3_MISC_SHDW_SCR5_LPED
|
1483 MII_TG3_MISC_SHDW_SCR5_DLPTLM
|
1484 MII_TG3_MISC_SHDW_SCR5_SDTL
|
1485 MII_TG3_MISC_SHDW_SCR5_C125OE
;
1486 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
|| !enable
)
1487 reg
|= MII_TG3_MISC_SHDW_SCR5_DLLAPD
;
1489 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1492 reg
= MII_TG3_MISC_SHDW_WREN
|
1493 MII_TG3_MISC_SHDW_APD_SEL
|
1494 MII_TG3_MISC_SHDW_APD_WKTM_84MS
;
1496 reg
|= MII_TG3_MISC_SHDW_APD_ENABLE
;
1498 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1501 static void tg3_phy_toggle_automdix(struct tg3
*tp
, int enable
)
1505 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1506 (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
1509 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1512 if (!tg3_readphy(tp
, MII_TG3_EPHY_TEST
, &ephy
)) {
1513 tg3_writephy(tp
, MII_TG3_EPHY_TEST
,
1514 ephy
| MII_TG3_EPHY_SHADOW_EN
);
1515 if (!tg3_readphy(tp
, MII_TG3_EPHYTST_MISCCTRL
, &phy
)) {
1517 phy
|= MII_TG3_EPHYTST_MISCCTRL_MDIX
;
1519 phy
&= ~MII_TG3_EPHYTST_MISCCTRL_MDIX
;
1520 tg3_writephy(tp
, MII_TG3_EPHYTST_MISCCTRL
, phy
);
1522 tg3_writephy(tp
, MII_TG3_EPHY_TEST
, ephy
);
1525 phy
= MII_TG3_AUXCTL_MISC_RDSEL_MISC
|
1526 MII_TG3_AUXCTL_SHDWSEL_MISC
;
1527 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
) &&
1528 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy
)) {
1530 phy
|= MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1532 phy
&= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1533 phy
|= MII_TG3_AUXCTL_MISC_WREN
;
1534 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1539 static void tg3_phy_set_wirespeed(struct tg3
*tp
)
1543 if (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
)
1546 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x7007) &&
1547 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
))
1548 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
1549 (val
| (1 << 15) | (1 << 4)));
1552 static void tg3_phy_apply_otp(struct tg3
*tp
)
1561 /* Enable SM_DSP clock and tx 6dB coding. */
1562 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1563 MII_TG3_AUXCTL_ACTL_SMDSP_ENA
|
1564 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1565 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1567 phy
= ((otp
& TG3_OTP_AGCTGT_MASK
) >> TG3_OTP_AGCTGT_SHIFT
);
1568 phy
|= MII_TG3_DSP_TAP1_AGCTGT_DFLT
;
1569 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP1
, phy
);
1571 phy
= ((otp
& TG3_OTP_HPFFLTR_MASK
) >> TG3_OTP_HPFFLTR_SHIFT
) |
1572 ((otp
& TG3_OTP_HPFOVER_MASK
) >> TG3_OTP_HPFOVER_SHIFT
);
1573 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH0
, phy
);
1575 phy
= ((otp
& TG3_OTP_LPFDIS_MASK
) >> TG3_OTP_LPFDIS_SHIFT
);
1576 phy
|= MII_TG3_DSP_AADJ1CH3_ADCCKADJ
;
1577 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH3
, phy
);
1579 phy
= ((otp
& TG3_OTP_VDAC_MASK
) >> TG3_OTP_VDAC_SHIFT
);
1580 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP75
, phy
);
1582 phy
= ((otp
& TG3_OTP_10BTAMP_MASK
) >> TG3_OTP_10BTAMP_SHIFT
);
1583 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP96
, phy
);
1585 phy
= ((otp
& TG3_OTP_ROFF_MASK
) >> TG3_OTP_ROFF_SHIFT
) |
1586 ((otp
& TG3_OTP_RCOFF_MASK
) >> TG3_OTP_RCOFF_SHIFT
);
1587 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP97
, phy
);
1589 /* Turn off SM_DSP clock. */
1590 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1591 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1592 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1595 static int tg3_wait_macro_done(struct tg3
*tp
)
1602 if (!tg3_readphy(tp
, 0x16, &tmp32
)) {
1603 if ((tmp32
& 0x1000) == 0)
1613 static int tg3_phy_write_and_check_testpat(struct tg3
*tp
, int *resetp
)
1615 static const u32 test_pat
[4][6] = {
1616 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1617 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1618 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1619 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1623 for (chan
= 0; chan
< 4; chan
++) {
1626 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1627 (chan
* 0x2000) | 0x0200);
1628 tg3_writephy(tp
, 0x16, 0x0002);
1630 for (i
= 0; i
< 6; i
++)
1631 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
,
1634 tg3_writephy(tp
, 0x16, 0x0202);
1635 if (tg3_wait_macro_done(tp
)) {
1640 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1641 (chan
* 0x2000) | 0x0200);
1642 tg3_writephy(tp
, 0x16, 0x0082);
1643 if (tg3_wait_macro_done(tp
)) {
1648 tg3_writephy(tp
, 0x16, 0x0802);
1649 if (tg3_wait_macro_done(tp
)) {
1654 for (i
= 0; i
< 6; i
+= 2) {
1657 if (tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &low
) ||
1658 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &high
) ||
1659 tg3_wait_macro_done(tp
)) {
1665 if (low
!= test_pat
[chan
][i
] ||
1666 high
!= test_pat
[chan
][i
+1]) {
1667 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000b);
1668 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4001);
1669 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4005);
1679 static int tg3_phy_reset_chanpat(struct tg3
*tp
)
1683 for (chan
= 0; chan
< 4; chan
++) {
1686 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1687 (chan
* 0x2000) | 0x0200);
1688 tg3_writephy(tp
, 0x16, 0x0002);
1689 for (i
= 0; i
< 6; i
++)
1690 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x000);
1691 tg3_writephy(tp
, 0x16, 0x0202);
1692 if (tg3_wait_macro_done(tp
))
1699 static int tg3_phy_reset_5703_4_5(struct tg3
*tp
)
1701 u32 reg32
, phy9_orig
;
1702 int retries
, do_phy_reset
, err
;
1708 err
= tg3_bmcr_reset(tp
);
1714 /* Disable transmitter and interrupt. */
1715 if (tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
))
1719 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1721 /* Set full-duplex, 1000 mbps. */
1722 tg3_writephy(tp
, MII_BMCR
,
1723 BMCR_FULLDPLX
| TG3_BMCR_SPEED1000
);
1725 /* Set to master mode. */
1726 if (tg3_readphy(tp
, MII_TG3_CTRL
, &phy9_orig
))
1729 tg3_writephy(tp
, MII_TG3_CTRL
,
1730 (MII_TG3_CTRL_AS_MASTER
|
1731 MII_TG3_CTRL_ENABLE_AS_MASTER
));
1733 /* Enable SM_DSP_CLOCK and 6dB. */
1734 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1736 /* Block the PHY control access. */
1737 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
1738 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0800);
1740 err
= tg3_phy_write_and_check_testpat(tp
, &do_phy_reset
);
1743 } while (--retries
);
1745 err
= tg3_phy_reset_chanpat(tp
);
1749 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
1750 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0000);
1752 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8200);
1753 tg3_writephy(tp
, 0x16, 0x0000);
1755 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1756 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
1757 /* Set Extended packet length bit for jumbo frames */
1758 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4400);
1761 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1764 tg3_writephy(tp
, MII_TG3_CTRL
, phy9_orig
);
1766 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
)) {
1768 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1775 /* This will reset the tigon3 PHY if there is no valid
1776 * link unless the FORCE argument is non-zero.
1778 static int tg3_phy_reset(struct tg3
*tp
)
1784 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1787 val
= tr32(GRC_MISC_CFG
);
1788 tw32_f(GRC_MISC_CFG
, val
& ~GRC_MISC_CFG_EPHY_IDDQ
);
1791 err
= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1792 err
|= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1796 if (netif_running(tp
->dev
) && netif_carrier_ok(tp
->dev
)) {
1797 netif_carrier_off(tp
->dev
);
1798 tg3_link_report(tp
);
1801 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1802 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
1803 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
1804 err
= tg3_phy_reset_5703_4_5(tp
);
1811 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
1812 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
1813 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
1814 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
)
1816 cpmuctrl
& ~CPMU_CTRL_GPHY_10MB_RXONLY
);
1819 err
= tg3_bmcr_reset(tp
);
1823 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
) {
1826 phy
= MII_TG3_DSP_EXP8_AEDW
| MII_TG3_DSP_EXP8_REJ2MHz
;
1827 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP8
, phy
);
1829 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
1832 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
1833 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
1836 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
1837 if ((val
& CPMU_LSPD_1000MB_MACCLK_MASK
) ==
1838 CPMU_LSPD_1000MB_MACCLK_12_5
) {
1839 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
1841 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
1845 tg3_phy_apply_otp(tp
);
1847 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
1848 tg3_phy_toggle_apd(tp
, true);
1850 tg3_phy_toggle_apd(tp
, false);
1853 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADC_BUG
) {
1854 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1855 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
1856 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x2aaa);
1857 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1858 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0323);
1859 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1861 if (tp
->tg3_flags2
& TG3_FLG2_PHY_5704_A0_BUG
) {
1862 tg3_writephy(tp
, 0x1c, 0x8d68);
1863 tg3_writephy(tp
, 0x1c, 0x8d68);
1865 if (tp
->tg3_flags2
& TG3_FLG2_PHY_BER_BUG
) {
1866 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1867 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1868 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x310b);
1869 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
1870 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x9506);
1871 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x401f);
1872 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x14e2);
1873 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1875 else if (tp
->tg3_flags2
& TG3_FLG2_PHY_JITTER_BUG
) {
1876 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1877 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1878 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADJUST_TRIM
) {
1879 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x110b);
1880 tg3_writephy(tp
, MII_TG3_TEST1
,
1881 MII_TG3_TEST1_TRIM_EN
| 0x4);
1883 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x010b);
1884 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1886 /* Set Extended packet length bit (bit 14) on all chips that */
1887 /* support jumbo frames */
1888 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
1889 /* Cannot do read-modify-write on 5401 */
1890 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
1891 } else if (tp
->tg3_flags2
& TG3_FLG2_JUMBO_CAPABLE
) {
1894 /* Set bit 14 with read-modify-write to preserve other bits */
1895 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0007) &&
1896 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy_reg
))
1897 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy_reg
| 0x4000);
1900 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1901 * jumbo frames transmission.
1903 if (tp
->tg3_flags2
& TG3_FLG2_JUMBO_CAPABLE
) {
1906 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, &phy_reg
))
1907 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
1908 phy_reg
| MII_TG3_EXT_CTRL_FIFO_ELASTIC
);
1911 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1912 /* adjust output voltage */
1913 tg3_writephy(tp
, MII_TG3_EPHY_PTEST
, 0x12);
1916 tg3_phy_toggle_automdix(tp
, 1);
1917 tg3_phy_set_wirespeed(tp
);
1921 static void tg3_frob_aux_power(struct tg3
*tp
)
1923 struct tg3
*tp_peer
= tp
;
1925 if ((tp
->tg3_flags2
& TG3_FLG2_IS_NIC
) == 0)
1928 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
1929 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
1930 struct net_device
*dev_peer
;
1932 dev_peer
= pci_get_drvdata(tp
->pdev_peer
);
1933 /* remove_one() may have been run on the peer. */
1937 tp_peer
= netdev_priv(dev_peer
);
1940 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
1941 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0 ||
1942 (tp_peer
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
1943 (tp_peer
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
1944 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
1945 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
1946 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
1947 (GRC_LCLCTRL_GPIO_OE0
|
1948 GRC_LCLCTRL_GPIO_OE1
|
1949 GRC_LCLCTRL_GPIO_OE2
|
1950 GRC_LCLCTRL_GPIO_OUTPUT0
|
1951 GRC_LCLCTRL_GPIO_OUTPUT1
),
1953 } else if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
) {
1954 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1955 u32 grc_local_ctrl
= GRC_LCLCTRL_GPIO_OE0
|
1956 GRC_LCLCTRL_GPIO_OE1
|
1957 GRC_LCLCTRL_GPIO_OE2
|
1958 GRC_LCLCTRL_GPIO_OUTPUT0
|
1959 GRC_LCLCTRL_GPIO_OUTPUT1
|
1961 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
1963 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT2
;
1964 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
1966 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT0
;
1967 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
1970 u32 grc_local_ctrl
= 0;
1972 if (tp_peer
!= tp
&&
1973 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
1976 /* Workaround to prevent overdrawing Amps. */
1977 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
1979 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
1980 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
1981 grc_local_ctrl
, 100);
1984 /* On 5753 and variants, GPIO2 cannot be used. */
1985 no_gpio2
= tp
->nic_sram_data_cfg
&
1986 NIC_SRAM_DATA_CFG_NO_GPIO2
;
1988 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
1989 GRC_LCLCTRL_GPIO_OE1
|
1990 GRC_LCLCTRL_GPIO_OE2
|
1991 GRC_LCLCTRL_GPIO_OUTPUT1
|
1992 GRC_LCLCTRL_GPIO_OUTPUT2
;
1994 grc_local_ctrl
&= ~(GRC_LCLCTRL_GPIO_OE2
|
1995 GRC_LCLCTRL_GPIO_OUTPUT2
);
1997 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
1998 grc_local_ctrl
, 100);
2000 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT0
;
2002 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2003 grc_local_ctrl
, 100);
2006 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT2
;
2007 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2008 grc_local_ctrl
, 100);
2012 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
2013 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
2014 if (tp_peer
!= tp
&&
2015 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2018 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2019 (GRC_LCLCTRL_GPIO_OE1
|
2020 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2022 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2023 GRC_LCLCTRL_GPIO_OE1
, 100);
2025 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2026 (GRC_LCLCTRL_GPIO_OE1
|
2027 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2032 static int tg3_5700_link_polarity(struct tg3
*tp
, u32 speed
)
2034 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_2
)
2036 else if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
) {
2037 if (speed
!= SPEED_10
)
2039 } else if (speed
== SPEED_10
)
2045 static int tg3_setup_phy(struct tg3
*, int);
2047 #define RESET_KIND_SHUTDOWN 0
2048 #define RESET_KIND_INIT 1
2049 #define RESET_KIND_SUSPEND 2
2051 static void tg3_write_sig_post_reset(struct tg3
*, int);
2052 static int tg3_halt_cpu(struct tg3
*, u32
);
2053 static int tg3_nvram_lock(struct tg3
*);
2054 static void tg3_nvram_unlock(struct tg3
*);
2056 static void tg3_power_down_phy(struct tg3
*tp
, bool do_low_power
)
2060 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
2061 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2062 u32 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
2063 u32 serdes_cfg
= tr32(MAC_SERDES_CFG
);
2066 SG_DIG_USING_HW_AUTONEG
| SG_DIG_SOFT_RESET
;
2067 tw32(SG_DIG_CTRL
, sg_dig_ctrl
);
2068 tw32(MAC_SERDES_CFG
, serdes_cfg
| (1 << 15));
2073 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2075 val
= tr32(GRC_MISC_CFG
);
2076 tw32_f(GRC_MISC_CFG
, val
| GRC_MISC_CFG_EPHY_IDDQ
);
2079 } else if (do_low_power
) {
2080 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2081 MII_TG3_EXT_CTRL_FORCE_LED_OFF
);
2083 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
2084 MII_TG3_AUXCTL_SHDWSEL_PWRCTL
|
2085 MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
2086 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE
|
2087 MII_TG3_AUXCTL_PCTL_VREG_11V
);
2090 /* The PHY should not be powered down on some chips because
2093 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2094 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2095 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
&&
2096 (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)))
2099 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
2100 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
2101 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
2102 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
2103 val
|= CPMU_LSPD_1000MB_MACCLK_12_5
;
2104 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
2107 tg3_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
2110 /* tp->lock is held. */
2111 static void __tg3_set_mac_addr(struct tg3
*tp
, int skip_mac_1
)
2113 u32 addr_high
, addr_low
;
2116 addr_high
= ((tp
->dev
->dev_addr
[0] << 8) |
2117 tp
->dev
->dev_addr
[1]);
2118 addr_low
= ((tp
->dev
->dev_addr
[2] << 24) |
2119 (tp
->dev
->dev_addr
[3] << 16) |
2120 (tp
->dev
->dev_addr
[4] << 8) |
2121 (tp
->dev
->dev_addr
[5] << 0));
2122 for (i
= 0; i
< 4; i
++) {
2123 if (i
== 1 && skip_mac_1
)
2125 tw32(MAC_ADDR_0_HIGH
+ (i
* 8), addr_high
);
2126 tw32(MAC_ADDR_0_LOW
+ (i
* 8), addr_low
);
2129 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2130 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2131 for (i
= 0; i
< 12; i
++) {
2132 tw32(MAC_EXTADDR_0_HIGH
+ (i
* 8), addr_high
);
2133 tw32(MAC_EXTADDR_0_LOW
+ (i
* 8), addr_low
);
2137 addr_high
= (tp
->dev
->dev_addr
[0] +
2138 tp
->dev
->dev_addr
[1] +
2139 tp
->dev
->dev_addr
[2] +
2140 tp
->dev
->dev_addr
[3] +
2141 tp
->dev
->dev_addr
[4] +
2142 tp
->dev
->dev_addr
[5]) &
2143 TX_BACKOFF_SEED_MASK
;
2144 tw32(MAC_TX_BACKOFF_SEED
, addr_high
);
2147 static int tg3_set_power_state(struct tg3
*tp
, pci_power_t state
)
2150 bool device_should_wake
, do_low_power
;
2152 /* Make sure register accesses (indirect or otherwise)
2153 * will function correctly.
2155 pci_write_config_dword(tp
->pdev
,
2156 TG3PCI_MISC_HOST_CTRL
,
2157 tp
->misc_host_ctrl
);
2161 pci_enable_wake(tp
->pdev
, state
, false);
2162 pci_set_power_state(tp
->pdev
, PCI_D0
);
2164 /* Switch out of Vaux if it is a NIC */
2165 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
2166 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
, 100);
2176 printk(KERN_ERR PFX
"%s: Invalid power state (D%d) requested\n",
2177 tp
->dev
->name
, state
);
2181 /* Restore the CLKREQ setting. */
2182 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
2185 pci_read_config_word(tp
->pdev
,
2186 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2188 lnkctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
2189 pci_write_config_word(tp
->pdev
,
2190 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2194 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
2195 tw32(TG3PCI_MISC_HOST_CTRL
,
2196 misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
);
2198 device_should_wake
= pci_pme_capable(tp
->pdev
, state
) &&
2199 device_may_wakeup(&tp
->pdev
->dev
) &&
2200 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
2202 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
2203 do_low_power
= false;
2204 if ((tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) &&
2205 !tp
->link_config
.phy_is_low_power
) {
2206 struct phy_device
*phydev
;
2207 u32 phyid
, advertising
;
2209 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
2211 tp
->link_config
.phy_is_low_power
= 1;
2213 tp
->link_config
.orig_speed
= phydev
->speed
;
2214 tp
->link_config
.orig_duplex
= phydev
->duplex
;
2215 tp
->link_config
.orig_autoneg
= phydev
->autoneg
;
2216 tp
->link_config
.orig_advertising
= phydev
->advertising
;
2218 advertising
= ADVERTISED_TP
|
2220 ADVERTISED_Autoneg
|
2221 ADVERTISED_10baseT_Half
;
2223 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2224 device_should_wake
) {
2225 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2227 ADVERTISED_100baseT_Half
|
2228 ADVERTISED_100baseT_Full
|
2229 ADVERTISED_10baseT_Full
;
2231 advertising
|= ADVERTISED_10baseT_Full
;
2234 phydev
->advertising
= advertising
;
2236 phy_start_aneg(phydev
);
2238 phyid
= phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
;
2239 if (phyid
!= TG3_PHY_ID_BCMAC131
) {
2240 phyid
&= TG3_PHY_OUI_MASK
;
2241 if (phyid
== TG3_PHY_OUI_1
||
2242 phyid
== TG3_PHY_OUI_2
||
2243 phyid
== TG3_PHY_OUI_3
)
2244 do_low_power
= true;
2248 do_low_power
= true;
2250 if (tp
->link_config
.phy_is_low_power
== 0) {
2251 tp
->link_config
.phy_is_low_power
= 1;
2252 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
2253 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
2254 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
2257 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)) {
2258 tp
->link_config
.speed
= SPEED_10
;
2259 tp
->link_config
.duplex
= DUPLEX_HALF
;
2260 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
2261 tg3_setup_phy(tp
, 0);
2265 __tg3_set_mac_addr(tp
, 0);
2267 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2270 val
= tr32(GRC_VCPU_EXT_CTRL
);
2271 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_DISABLE_WOL
);
2272 } else if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2276 for (i
= 0; i
< 200; i
++) {
2277 tg3_read_mem(tp
, NIC_SRAM_FW_ASF_STATUS_MBOX
, &val
);
2278 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
2283 if (tp
->tg3_flags
& TG3_FLAG_WOL_CAP
)
2284 tg3_write_mem(tp
, NIC_SRAM_WOL_MBOX
, WOL_SIGNATURE
|
2285 WOL_DRV_STATE_SHUTDOWN
|
2289 if (device_should_wake
) {
2292 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
2294 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x5a);
2298 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
2299 mac_mode
= MAC_MODE_PORT_MODE_GMII
;
2301 mac_mode
= MAC_MODE_PORT_MODE_MII
;
2303 mac_mode
|= tp
->mac_mode
& MAC_MODE_LINK_POLARITY
;
2304 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2306 u32 speed
= (tp
->tg3_flags
&
2307 TG3_FLAG_WOL_SPEED_100MB
) ?
2308 SPEED_100
: SPEED_10
;
2309 if (tg3_5700_link_polarity(tp
, speed
))
2310 mac_mode
|= MAC_MODE_LINK_POLARITY
;
2312 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
2315 mac_mode
= MAC_MODE_PORT_MODE_TBI
;
2318 if (!(tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
2319 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
2321 mac_mode
|= MAC_MODE_MAGIC_PKT_ENABLE
;
2322 if (((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
2323 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) &&
2324 ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2325 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)))
2326 mac_mode
|= MAC_MODE_KEEP_FRAME_IN_WOL
;
2328 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
2329 mac_mode
|= tp
->mac_mode
&
2330 (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
2331 if (mac_mode
& MAC_MODE_APE_TX_EN
)
2332 mac_mode
|= MAC_MODE_TDE_ENABLE
;
2335 tw32_f(MAC_MODE
, mac_mode
);
2338 tw32_f(MAC_RX_MODE
, RX_MODE_ENABLE
);
2342 if (!(tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
) &&
2343 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2344 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
2347 base_val
= tp
->pci_clock_ctrl
;
2348 base_val
|= (CLOCK_CTRL_RXCLK_DISABLE
|
2349 CLOCK_CTRL_TXCLK_DISABLE
);
2351 tw32_wait_f(TG3PCI_CLOCK_CTRL
, base_val
| CLOCK_CTRL_ALTCLK
|
2352 CLOCK_CTRL_PWRDOWN_PLL133
, 40);
2353 } else if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
2354 (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
2355 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)) {
2357 } else if (!((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2358 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))) {
2359 u32 newbits1
, newbits2
;
2361 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2362 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2363 newbits1
= (CLOCK_CTRL_RXCLK_DISABLE
|
2364 CLOCK_CTRL_TXCLK_DISABLE
|
2366 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2367 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
2368 newbits1
= CLOCK_CTRL_625_CORE
;
2369 newbits2
= newbits1
| CLOCK_CTRL_ALTCLK
;
2371 newbits1
= CLOCK_CTRL_ALTCLK
;
2372 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2375 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits1
,
2378 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits2
,
2381 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
2384 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2385 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2386 newbits3
= (CLOCK_CTRL_RXCLK_DISABLE
|
2387 CLOCK_CTRL_TXCLK_DISABLE
|
2388 CLOCK_CTRL_44MHZ_CORE
);
2390 newbits3
= CLOCK_CTRL_44MHZ_CORE
;
2393 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
2394 tp
->pci_clock_ctrl
| newbits3
, 40);
2398 if (!(device_should_wake
) &&
2399 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
2400 tg3_power_down_phy(tp
, do_low_power
);
2402 tg3_frob_aux_power(tp
);
2404 /* Workaround for unstable PLL clock */
2405 if ((GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
) ||
2406 (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
)) {
2407 u32 val
= tr32(0x7d00);
2409 val
&= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2411 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2414 err
= tg3_nvram_lock(tp
);
2415 tg3_halt_cpu(tp
, RX_CPU_BASE
);
2417 tg3_nvram_unlock(tp
);
2421 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
2423 if (device_should_wake
)
2424 pci_enable_wake(tp
->pdev
, state
, true);
2426 /* Finally, set the new power state. */
2427 pci_set_power_state(tp
->pdev
, state
);
2432 static void tg3_aux_stat_to_speed_duplex(struct tg3
*tp
, u32 val
, u16
*speed
, u8
*duplex
)
2434 switch (val
& MII_TG3_AUX_STAT_SPDMASK
) {
2435 case MII_TG3_AUX_STAT_10HALF
:
2437 *duplex
= DUPLEX_HALF
;
2440 case MII_TG3_AUX_STAT_10FULL
:
2442 *duplex
= DUPLEX_FULL
;
2445 case MII_TG3_AUX_STAT_100HALF
:
2447 *duplex
= DUPLEX_HALF
;
2450 case MII_TG3_AUX_STAT_100FULL
:
2452 *duplex
= DUPLEX_FULL
;
2455 case MII_TG3_AUX_STAT_1000HALF
:
2456 *speed
= SPEED_1000
;
2457 *duplex
= DUPLEX_HALF
;
2460 case MII_TG3_AUX_STAT_1000FULL
:
2461 *speed
= SPEED_1000
;
2462 *duplex
= DUPLEX_FULL
;
2466 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2467 *speed
= (val
& MII_TG3_AUX_STAT_100
) ? SPEED_100
:
2469 *duplex
= (val
& MII_TG3_AUX_STAT_FULL
) ? DUPLEX_FULL
:
2473 *speed
= SPEED_INVALID
;
2474 *duplex
= DUPLEX_INVALID
;
2479 static void tg3_phy_copper_begin(struct tg3
*tp
)
2484 if (tp
->link_config
.phy_is_low_power
) {
2485 /* Entering low power mode. Disable gigabit and
2486 * 100baseT advertisements.
2488 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2490 new_adv
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
2491 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
2492 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2493 new_adv
|= (ADVERTISE_100HALF
| ADVERTISE_100FULL
);
2495 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2496 } else if (tp
->link_config
.speed
== SPEED_INVALID
) {
2497 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
2498 tp
->link_config
.advertising
&=
2499 ~(ADVERTISED_1000baseT_Half
|
2500 ADVERTISED_1000baseT_Full
);
2502 new_adv
= ADVERTISE_CSMA
;
2503 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Half
)
2504 new_adv
|= ADVERTISE_10HALF
;
2505 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Full
)
2506 new_adv
|= ADVERTISE_10FULL
;
2507 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Half
)
2508 new_adv
|= ADVERTISE_100HALF
;
2509 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Full
)
2510 new_adv
|= ADVERTISE_100FULL
;
2512 new_adv
|= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2514 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2516 if (tp
->link_config
.advertising
&
2517 (ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
)) {
2519 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
2520 new_adv
|= MII_TG3_CTRL_ADV_1000_HALF
;
2521 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
2522 new_adv
|= MII_TG3_CTRL_ADV_1000_FULL
;
2523 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) &&
2524 (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2525 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
))
2526 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2527 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2528 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2530 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2533 new_adv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2534 new_adv
|= ADVERTISE_CSMA
;
2536 /* Asking for a specific link mode. */
2537 if (tp
->link_config
.speed
== SPEED_1000
) {
2538 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2540 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2541 new_adv
= MII_TG3_CTRL_ADV_1000_FULL
;
2543 new_adv
= MII_TG3_CTRL_ADV_1000_HALF
;
2544 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2545 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
2546 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2547 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2549 if (tp
->link_config
.speed
== SPEED_100
) {
2550 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2551 new_adv
|= ADVERTISE_100FULL
;
2553 new_adv
|= ADVERTISE_100HALF
;
2555 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2556 new_adv
|= ADVERTISE_10FULL
;
2558 new_adv
|= ADVERTISE_10HALF
;
2560 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2565 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2568 if (tp
->link_config
.autoneg
== AUTONEG_DISABLE
&&
2569 tp
->link_config
.speed
!= SPEED_INVALID
) {
2570 u32 bmcr
, orig_bmcr
;
2572 tp
->link_config
.active_speed
= tp
->link_config
.speed
;
2573 tp
->link_config
.active_duplex
= tp
->link_config
.duplex
;
2576 switch (tp
->link_config
.speed
) {
2582 bmcr
|= BMCR_SPEED100
;
2586 bmcr
|= TG3_BMCR_SPEED1000
;
2590 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2591 bmcr
|= BMCR_FULLDPLX
;
2593 if (!tg3_readphy(tp
, MII_BMCR
, &orig_bmcr
) &&
2594 (bmcr
!= orig_bmcr
)) {
2595 tg3_writephy(tp
, MII_BMCR
, BMCR_LOOPBACK
);
2596 for (i
= 0; i
< 1500; i
++) {
2600 if (tg3_readphy(tp
, MII_BMSR
, &tmp
) ||
2601 tg3_readphy(tp
, MII_BMSR
, &tmp
))
2603 if (!(tmp
& BMSR_LSTATUS
)) {
2608 tg3_writephy(tp
, MII_BMCR
, bmcr
);
2612 tg3_writephy(tp
, MII_BMCR
,
2613 BMCR_ANENABLE
| BMCR_ANRESTART
);
2617 static int tg3_init_5401phy_dsp(struct tg3
*tp
)
2621 /* Turn off tap power management. */
2622 /* Set Extended packet length bit */
2623 err
= tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
2625 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0012);
2626 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1804);
2628 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0013);
2629 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1204);
2631 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
2632 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0132);
2634 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
2635 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0232);
2637 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
2638 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0a20);
2645 static int tg3_copper_is_advertising_all(struct tg3
*tp
, u32 mask
)
2647 u32 adv_reg
, all_mask
= 0;
2649 if (mask
& ADVERTISED_10baseT_Half
)
2650 all_mask
|= ADVERTISE_10HALF
;
2651 if (mask
& ADVERTISED_10baseT_Full
)
2652 all_mask
|= ADVERTISE_10FULL
;
2653 if (mask
& ADVERTISED_100baseT_Half
)
2654 all_mask
|= ADVERTISE_100HALF
;
2655 if (mask
& ADVERTISED_100baseT_Full
)
2656 all_mask
|= ADVERTISE_100FULL
;
2658 if (tg3_readphy(tp
, MII_ADVERTISE
, &adv_reg
))
2661 if ((adv_reg
& all_mask
) != all_mask
)
2663 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
2667 if (mask
& ADVERTISED_1000baseT_Half
)
2668 all_mask
|= ADVERTISE_1000HALF
;
2669 if (mask
& ADVERTISED_1000baseT_Full
)
2670 all_mask
|= ADVERTISE_1000FULL
;
2672 if (tg3_readphy(tp
, MII_TG3_CTRL
, &tg3_ctrl
))
2675 if ((tg3_ctrl
& all_mask
) != all_mask
)
2681 static int tg3_adv_1000T_flowctrl_ok(struct tg3
*tp
, u32
*lcladv
, u32
*rmtadv
)
2685 if (tg3_readphy(tp
, MII_ADVERTISE
, lcladv
))
2688 curadv
= *lcladv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
2689 reqadv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2691 if (tp
->link_config
.active_duplex
== DUPLEX_FULL
) {
2692 if (curadv
!= reqadv
)
2695 if (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)
2696 tg3_readphy(tp
, MII_LPA
, rmtadv
);
2698 /* Reprogram the advertisement register, even if it
2699 * does not affect the current link. If the link
2700 * gets renegotiated in the future, we can save an
2701 * additional renegotiation cycle by advertising
2702 * it correctly in the first place.
2704 if (curadv
!= reqadv
) {
2705 *lcladv
&= ~(ADVERTISE_PAUSE_CAP
|
2706 ADVERTISE_PAUSE_ASYM
);
2707 tg3_writephy(tp
, MII_ADVERTISE
, *lcladv
| reqadv
);
2714 static int tg3_setup_copper_phy(struct tg3
*tp
, int force_reset
)
2716 int current_link_up
;
2718 u32 lcl_adv
, rmt_adv
;
2726 (MAC_STATUS_SYNC_CHANGED
|
2727 MAC_STATUS_CFG_CHANGED
|
2728 MAC_STATUS_MI_COMPLETION
|
2729 MAC_STATUS_LNKSTATE_CHANGED
));
2732 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
2734 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
2738 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x02);
2740 /* Some third-party PHYs need to be reset on link going
2743 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2744 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2745 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
2746 netif_carrier_ok(tp
->dev
)) {
2747 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
2748 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
2749 !(bmsr
& BMSR_LSTATUS
))
2755 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
2756 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
2757 if (tg3_readphy(tp
, MII_BMSR
, &bmsr
) ||
2758 !(tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
))
2761 if (!(bmsr
& BMSR_LSTATUS
)) {
2762 err
= tg3_init_5401phy_dsp(tp
);
2766 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
2767 for (i
= 0; i
< 1000; i
++) {
2769 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
2770 (bmsr
& BMSR_LSTATUS
)) {
2776 if ((tp
->phy_id
& PHY_ID_REV_MASK
) == PHY_REV_BCM5401_B0
&&
2777 !(bmsr
& BMSR_LSTATUS
) &&
2778 tp
->link_config
.active_speed
== SPEED_1000
) {
2779 err
= tg3_phy_reset(tp
);
2781 err
= tg3_init_5401phy_dsp(tp
);
2786 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2787 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
) {
2788 /* 5701 {A0,B0} CRC bug workaround */
2789 tg3_writephy(tp
, 0x15, 0x0a75);
2790 tg3_writephy(tp
, 0x1c, 0x8c68);
2791 tg3_writephy(tp
, 0x1c, 0x8d68);
2792 tg3_writephy(tp
, 0x1c, 0x8c68);
2795 /* Clear pending interrupts... */
2796 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
2797 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
2799 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
)
2800 tg3_writephy(tp
, MII_TG3_IMASK
, ~MII_TG3_INT_LINKCHG
);
2801 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5906
)
2802 tg3_writephy(tp
, MII_TG3_IMASK
, ~0);
2804 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2805 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2806 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_1
)
2807 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2808 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
2810 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, 0);
2813 current_link_up
= 0;
2814 current_speed
= SPEED_INVALID
;
2815 current_duplex
= DUPLEX_INVALID
;
2817 if (tp
->tg3_flags2
& TG3_FLG2_CAPACITIVE_COUPLING
) {
2820 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4007);
2821 tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
);
2822 if (!(val
& (1 << 10))) {
2824 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
2830 for (i
= 0; i
< 100; i
++) {
2831 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
2832 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
2833 (bmsr
& BMSR_LSTATUS
))
2838 if (bmsr
& BMSR_LSTATUS
) {
2841 tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
);
2842 for (i
= 0; i
< 2000; i
++) {
2844 if (!tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
) &&
2849 tg3_aux_stat_to_speed_duplex(tp
, aux_stat
,
2854 for (i
= 0; i
< 200; i
++) {
2855 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
2856 if (tg3_readphy(tp
, MII_BMCR
, &bmcr
))
2858 if (bmcr
&& bmcr
!= 0x7fff)
2866 tp
->link_config
.active_speed
= current_speed
;
2867 tp
->link_config
.active_duplex
= current_duplex
;
2869 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
2870 if ((bmcr
& BMCR_ANENABLE
) &&
2871 tg3_copper_is_advertising_all(tp
,
2872 tp
->link_config
.advertising
)) {
2873 if (tg3_adv_1000T_flowctrl_ok(tp
, &lcl_adv
,
2875 current_link_up
= 1;
2878 if (!(bmcr
& BMCR_ANENABLE
) &&
2879 tp
->link_config
.speed
== current_speed
&&
2880 tp
->link_config
.duplex
== current_duplex
&&
2881 tp
->link_config
.flowctrl
==
2882 tp
->link_config
.active_flowctrl
) {
2883 current_link_up
= 1;
2887 if (current_link_up
== 1 &&
2888 tp
->link_config
.active_duplex
== DUPLEX_FULL
)
2889 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
2893 if (current_link_up
== 0 || tp
->link_config
.phy_is_low_power
) {
2896 tg3_phy_copper_begin(tp
);
2898 tg3_readphy(tp
, MII_BMSR
, &tmp
);
2899 if (!tg3_readphy(tp
, MII_BMSR
, &tmp
) &&
2900 (tmp
& BMSR_LSTATUS
))
2901 current_link_up
= 1;
2904 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
2905 if (current_link_up
== 1) {
2906 if (tp
->link_config
.active_speed
== SPEED_100
||
2907 tp
->link_config
.active_speed
== SPEED_10
)
2908 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
2910 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
2912 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
2914 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
2915 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
2916 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
2918 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
2919 if (current_link_up
== 1 &&
2920 tg3_5700_link_polarity(tp
, tp
->link_config
.active_speed
))
2921 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
2923 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
2926 /* ??? Without this setting Netgear GA302T PHY does not
2927 * ??? send/receive packets...
2929 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
&&
2930 tp
->pci_chip_rev_id
== CHIPREV_ID_5700_ALTIMA
) {
2931 tp
->mi_mode
|= MAC_MI_MODE_AUTO_POLL
;
2932 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
2936 tw32_f(MAC_MODE
, tp
->mac_mode
);
2939 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
2940 /* Polled via timer. */
2941 tw32_f(MAC_EVENT
, 0);
2943 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
2947 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
&&
2948 current_link_up
== 1 &&
2949 tp
->link_config
.active_speed
== SPEED_1000
&&
2950 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ||
2951 (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
))) {
2954 (MAC_STATUS_SYNC_CHANGED
|
2955 MAC_STATUS_CFG_CHANGED
));
2958 NIC_SRAM_FIRMWARE_MBOX
,
2959 NIC_SRAM_FIRMWARE_MBOX_MAGIC2
);
2962 /* Prevent send BD corruption. */
2963 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
2964 u16 oldlnkctl
, newlnkctl
;
2966 pci_read_config_word(tp
->pdev
,
2967 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2969 if (tp
->link_config
.active_speed
== SPEED_100
||
2970 tp
->link_config
.active_speed
== SPEED_10
)
2971 newlnkctl
= oldlnkctl
& ~PCI_EXP_LNKCTL_CLKREQ_EN
;
2973 newlnkctl
= oldlnkctl
| PCI_EXP_LNKCTL_CLKREQ_EN
;
2974 if (newlnkctl
!= oldlnkctl
)
2975 pci_write_config_word(tp
->pdev
,
2976 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2980 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
2981 if (current_link_up
)
2982 netif_carrier_on(tp
->dev
);
2984 netif_carrier_off(tp
->dev
);
2985 tg3_link_report(tp
);
2991 struct tg3_fiber_aneginfo
{
2993 #define ANEG_STATE_UNKNOWN 0
2994 #define ANEG_STATE_AN_ENABLE 1
2995 #define ANEG_STATE_RESTART_INIT 2
2996 #define ANEG_STATE_RESTART 3
2997 #define ANEG_STATE_DISABLE_LINK_OK 4
2998 #define ANEG_STATE_ABILITY_DETECT_INIT 5
2999 #define ANEG_STATE_ABILITY_DETECT 6
3000 #define ANEG_STATE_ACK_DETECT_INIT 7
3001 #define ANEG_STATE_ACK_DETECT 8
3002 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3003 #define ANEG_STATE_COMPLETE_ACK 10
3004 #define ANEG_STATE_IDLE_DETECT_INIT 11
3005 #define ANEG_STATE_IDLE_DETECT 12
3006 #define ANEG_STATE_LINK_OK 13
3007 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3008 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3011 #define MR_AN_ENABLE 0x00000001
3012 #define MR_RESTART_AN 0x00000002
3013 #define MR_AN_COMPLETE 0x00000004
3014 #define MR_PAGE_RX 0x00000008
3015 #define MR_NP_LOADED 0x00000010
3016 #define MR_TOGGLE_TX 0x00000020
3017 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3018 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3019 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3020 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3021 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3022 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3023 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3024 #define MR_TOGGLE_RX 0x00002000
3025 #define MR_NP_RX 0x00004000
3027 #define MR_LINK_OK 0x80000000
3029 unsigned long link_time
, cur_time
;
3031 u32 ability_match_cfg
;
3032 int ability_match_count
;
3034 char ability_match
, idle_match
, ack_match
;
3036 u32 txconfig
, rxconfig
;
3037 #define ANEG_CFG_NP 0x00000080
3038 #define ANEG_CFG_ACK 0x00000040
3039 #define ANEG_CFG_RF2 0x00000020
3040 #define ANEG_CFG_RF1 0x00000010
3041 #define ANEG_CFG_PS2 0x00000001
3042 #define ANEG_CFG_PS1 0x00008000
3043 #define ANEG_CFG_HD 0x00004000
3044 #define ANEG_CFG_FD 0x00002000
3045 #define ANEG_CFG_INVAL 0x00001f06
3050 #define ANEG_TIMER_ENAB 2
3051 #define ANEG_FAILED -1
3053 #define ANEG_STATE_SETTLE_TIME 10000
3055 static int tg3_fiber_aneg_smachine(struct tg3
*tp
,
3056 struct tg3_fiber_aneginfo
*ap
)
3059 unsigned long delta
;
3063 if (ap
->state
== ANEG_STATE_UNKNOWN
) {
3067 ap
->ability_match_cfg
= 0;
3068 ap
->ability_match_count
= 0;
3069 ap
->ability_match
= 0;
3075 if (tr32(MAC_STATUS
) & MAC_STATUS_RCVD_CFG
) {
3076 rx_cfg_reg
= tr32(MAC_RX_AUTO_NEG
);
3078 if (rx_cfg_reg
!= ap
->ability_match_cfg
) {
3079 ap
->ability_match_cfg
= rx_cfg_reg
;
3080 ap
->ability_match
= 0;
3081 ap
->ability_match_count
= 0;
3083 if (++ap
->ability_match_count
> 1) {
3084 ap
->ability_match
= 1;
3085 ap
->ability_match_cfg
= rx_cfg_reg
;
3088 if (rx_cfg_reg
& ANEG_CFG_ACK
)
3096 ap
->ability_match_cfg
= 0;
3097 ap
->ability_match_count
= 0;
3098 ap
->ability_match
= 0;
3104 ap
->rxconfig
= rx_cfg_reg
;
3108 case ANEG_STATE_UNKNOWN
:
3109 if (ap
->flags
& (MR_AN_ENABLE
| MR_RESTART_AN
))
3110 ap
->state
= ANEG_STATE_AN_ENABLE
;
3113 case ANEG_STATE_AN_ENABLE
:
3114 ap
->flags
&= ~(MR_AN_COMPLETE
| MR_PAGE_RX
);
3115 if (ap
->flags
& MR_AN_ENABLE
) {
3118 ap
->ability_match_cfg
= 0;
3119 ap
->ability_match_count
= 0;
3120 ap
->ability_match
= 0;
3124 ap
->state
= ANEG_STATE_RESTART_INIT
;
3126 ap
->state
= ANEG_STATE_DISABLE_LINK_OK
;
3130 case ANEG_STATE_RESTART_INIT
:
3131 ap
->link_time
= ap
->cur_time
;
3132 ap
->flags
&= ~(MR_NP_LOADED
);
3134 tw32(MAC_TX_AUTO_NEG
, 0);
3135 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3136 tw32_f(MAC_MODE
, tp
->mac_mode
);
3139 ret
= ANEG_TIMER_ENAB
;
3140 ap
->state
= ANEG_STATE_RESTART
;
3143 case ANEG_STATE_RESTART
:
3144 delta
= ap
->cur_time
- ap
->link_time
;
3145 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3146 ap
->state
= ANEG_STATE_ABILITY_DETECT_INIT
;
3148 ret
= ANEG_TIMER_ENAB
;
3152 case ANEG_STATE_DISABLE_LINK_OK
:
3156 case ANEG_STATE_ABILITY_DETECT_INIT
:
3157 ap
->flags
&= ~(MR_TOGGLE_TX
);
3158 ap
->txconfig
= ANEG_CFG_FD
;
3159 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3160 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3161 ap
->txconfig
|= ANEG_CFG_PS1
;
3162 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3163 ap
->txconfig
|= ANEG_CFG_PS2
;
3164 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3165 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3166 tw32_f(MAC_MODE
, tp
->mac_mode
);
3169 ap
->state
= ANEG_STATE_ABILITY_DETECT
;
3172 case ANEG_STATE_ABILITY_DETECT
:
3173 if (ap
->ability_match
!= 0 && ap
->rxconfig
!= 0) {
3174 ap
->state
= ANEG_STATE_ACK_DETECT_INIT
;
3178 case ANEG_STATE_ACK_DETECT_INIT
:
3179 ap
->txconfig
|= ANEG_CFG_ACK
;
3180 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3181 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3182 tw32_f(MAC_MODE
, tp
->mac_mode
);
3185 ap
->state
= ANEG_STATE_ACK_DETECT
;
3188 case ANEG_STATE_ACK_DETECT
:
3189 if (ap
->ack_match
!= 0) {
3190 if ((ap
->rxconfig
& ~ANEG_CFG_ACK
) ==
3191 (ap
->ability_match_cfg
& ~ANEG_CFG_ACK
)) {
3192 ap
->state
= ANEG_STATE_COMPLETE_ACK_INIT
;
3194 ap
->state
= ANEG_STATE_AN_ENABLE
;
3196 } else if (ap
->ability_match
!= 0 &&
3197 ap
->rxconfig
== 0) {
3198 ap
->state
= ANEG_STATE_AN_ENABLE
;
3202 case ANEG_STATE_COMPLETE_ACK_INIT
:
3203 if (ap
->rxconfig
& ANEG_CFG_INVAL
) {
3207 ap
->flags
&= ~(MR_LP_ADV_FULL_DUPLEX
|
3208 MR_LP_ADV_HALF_DUPLEX
|
3209 MR_LP_ADV_SYM_PAUSE
|
3210 MR_LP_ADV_ASYM_PAUSE
|
3211 MR_LP_ADV_REMOTE_FAULT1
|
3212 MR_LP_ADV_REMOTE_FAULT2
|
3213 MR_LP_ADV_NEXT_PAGE
|
3216 if (ap
->rxconfig
& ANEG_CFG_FD
)
3217 ap
->flags
|= MR_LP_ADV_FULL_DUPLEX
;
3218 if (ap
->rxconfig
& ANEG_CFG_HD
)
3219 ap
->flags
|= MR_LP_ADV_HALF_DUPLEX
;
3220 if (ap
->rxconfig
& ANEG_CFG_PS1
)
3221 ap
->flags
|= MR_LP_ADV_SYM_PAUSE
;
3222 if (ap
->rxconfig
& ANEG_CFG_PS2
)
3223 ap
->flags
|= MR_LP_ADV_ASYM_PAUSE
;
3224 if (ap
->rxconfig
& ANEG_CFG_RF1
)
3225 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT1
;
3226 if (ap
->rxconfig
& ANEG_CFG_RF2
)
3227 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT2
;
3228 if (ap
->rxconfig
& ANEG_CFG_NP
)
3229 ap
->flags
|= MR_LP_ADV_NEXT_PAGE
;
3231 ap
->link_time
= ap
->cur_time
;
3233 ap
->flags
^= (MR_TOGGLE_TX
);
3234 if (ap
->rxconfig
& 0x0008)
3235 ap
->flags
|= MR_TOGGLE_RX
;
3236 if (ap
->rxconfig
& ANEG_CFG_NP
)
3237 ap
->flags
|= MR_NP_RX
;
3238 ap
->flags
|= MR_PAGE_RX
;
3240 ap
->state
= ANEG_STATE_COMPLETE_ACK
;
3241 ret
= ANEG_TIMER_ENAB
;
3244 case ANEG_STATE_COMPLETE_ACK
:
3245 if (ap
->ability_match
!= 0 &&
3246 ap
->rxconfig
== 0) {
3247 ap
->state
= ANEG_STATE_AN_ENABLE
;
3250 delta
= ap
->cur_time
- ap
->link_time
;
3251 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3252 if (!(ap
->flags
& (MR_LP_ADV_NEXT_PAGE
))) {
3253 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3255 if ((ap
->txconfig
& ANEG_CFG_NP
) == 0 &&
3256 !(ap
->flags
& MR_NP_RX
)) {
3257 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3265 case ANEG_STATE_IDLE_DETECT_INIT
:
3266 ap
->link_time
= ap
->cur_time
;
3267 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3268 tw32_f(MAC_MODE
, tp
->mac_mode
);
3271 ap
->state
= ANEG_STATE_IDLE_DETECT
;
3272 ret
= ANEG_TIMER_ENAB
;
3275 case ANEG_STATE_IDLE_DETECT
:
3276 if (ap
->ability_match
!= 0 &&
3277 ap
->rxconfig
== 0) {
3278 ap
->state
= ANEG_STATE_AN_ENABLE
;
3281 delta
= ap
->cur_time
- ap
->link_time
;
3282 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3283 /* XXX another gem from the Broadcom driver :( */
3284 ap
->state
= ANEG_STATE_LINK_OK
;
3288 case ANEG_STATE_LINK_OK
:
3289 ap
->flags
|= (MR_AN_COMPLETE
| MR_LINK_OK
);
3293 case ANEG_STATE_NEXT_PAGE_WAIT_INIT
:
3294 /* ??? unimplemented */
3297 case ANEG_STATE_NEXT_PAGE_WAIT
:
3298 /* ??? unimplemented */
3309 static int fiber_autoneg(struct tg3
*tp
, u32
*txflags
, u32
*rxflags
)
3312 struct tg3_fiber_aneginfo aninfo
;
3313 int status
= ANEG_FAILED
;
3317 tw32_f(MAC_TX_AUTO_NEG
, 0);
3319 tmp
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
3320 tw32_f(MAC_MODE
, tmp
| MAC_MODE_PORT_MODE_GMII
);
3323 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
);
3326 memset(&aninfo
, 0, sizeof(aninfo
));
3327 aninfo
.flags
|= MR_AN_ENABLE
;
3328 aninfo
.state
= ANEG_STATE_UNKNOWN
;
3329 aninfo
.cur_time
= 0;
3331 while (++tick
< 195000) {
3332 status
= tg3_fiber_aneg_smachine(tp
, &aninfo
);
3333 if (status
== ANEG_DONE
|| status
== ANEG_FAILED
)
3339 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3340 tw32_f(MAC_MODE
, tp
->mac_mode
);
3343 *txflags
= aninfo
.txconfig
;
3344 *rxflags
= aninfo
.flags
;
3346 if (status
== ANEG_DONE
&&
3347 (aninfo
.flags
& (MR_AN_COMPLETE
| MR_LINK_OK
|
3348 MR_LP_ADV_FULL_DUPLEX
)))
3354 static void tg3_init_bcm8002(struct tg3
*tp
)
3356 u32 mac_status
= tr32(MAC_STATUS
);
3359 /* Reset when initting first time or we have a link. */
3360 if ((tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) &&
3361 !(mac_status
& MAC_STATUS_PCS_SYNCED
))
3364 /* Set PLL lock range. */
3365 tg3_writephy(tp
, 0x16, 0x8007);
3368 tg3_writephy(tp
, MII_BMCR
, BMCR_RESET
);
3370 /* Wait for reset to complete. */
3371 /* XXX schedule_timeout() ... */
3372 for (i
= 0; i
< 500; i
++)
3375 /* Config mode; select PMA/Ch 1 regs. */
3376 tg3_writephy(tp
, 0x10, 0x8411);
3378 /* Enable auto-lock and comdet, select txclk for tx. */
3379 tg3_writephy(tp
, 0x11, 0x0a10);
3381 tg3_writephy(tp
, 0x18, 0x00a0);
3382 tg3_writephy(tp
, 0x16, 0x41ff);
3384 /* Assert and deassert POR. */
3385 tg3_writephy(tp
, 0x13, 0x0400);
3387 tg3_writephy(tp
, 0x13, 0x0000);
3389 tg3_writephy(tp
, 0x11, 0x0a50);
3391 tg3_writephy(tp
, 0x11, 0x0a10);
3393 /* Wait for signal to stabilize */
3394 /* XXX schedule_timeout() ... */
3395 for (i
= 0; i
< 15000; i
++)
3398 /* Deselect the channel register so we can read the PHYID
3401 tg3_writephy(tp
, 0x10, 0x8011);
3404 static int tg3_setup_fiber_hw_autoneg(struct tg3
*tp
, u32 mac_status
)
3407 u32 sg_dig_ctrl
, sg_dig_status
;
3408 u32 serdes_cfg
, expected_sg_dig_ctrl
;
3409 int workaround
, port_a
;
3410 int current_link_up
;
3413 expected_sg_dig_ctrl
= 0;
3416 current_link_up
= 0;
3418 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A0
&&
3419 tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A1
) {
3421 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
3424 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3425 /* preserve bits 20-23 for voltage regulator */
3426 serdes_cfg
= tr32(MAC_SERDES_CFG
) & 0x00f06fff;
3429 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
3431 if (tp
->link_config
.autoneg
!= AUTONEG_ENABLE
) {
3432 if (sg_dig_ctrl
& SG_DIG_USING_HW_AUTONEG
) {
3434 u32 val
= serdes_cfg
;
3440 tw32_f(MAC_SERDES_CFG
, val
);
3443 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3445 if (mac_status
& MAC_STATUS_PCS_SYNCED
) {
3446 tg3_setup_flow_control(tp
, 0, 0);
3447 current_link_up
= 1;
3452 /* Want auto-negotiation. */
3453 expected_sg_dig_ctrl
= SG_DIG_USING_HW_AUTONEG
| SG_DIG_COMMON_SETUP
;
3455 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3456 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3457 expected_sg_dig_ctrl
|= SG_DIG_PAUSE_CAP
;
3458 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3459 expected_sg_dig_ctrl
|= SG_DIG_ASYM_PAUSE
;
3461 if (sg_dig_ctrl
!= expected_sg_dig_ctrl
) {
3462 if ((tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
) &&
3463 tp
->serdes_counter
&&
3464 ((mac_status
& (MAC_STATUS_PCS_SYNCED
|
3465 MAC_STATUS_RCVD_CFG
)) ==
3466 MAC_STATUS_PCS_SYNCED
)) {
3467 tp
->serdes_counter
--;
3468 current_link_up
= 1;
3473 tw32_f(MAC_SERDES_CFG
, serdes_cfg
| 0xc011000);
3474 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
| SG_DIG_SOFT_RESET
);
3476 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
);
3478 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3479 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3480 } else if (mac_status
& (MAC_STATUS_PCS_SYNCED
|
3481 MAC_STATUS_SIGNAL_DET
)) {
3482 sg_dig_status
= tr32(SG_DIG_STATUS
);
3483 mac_status
= tr32(MAC_STATUS
);
3485 if ((sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
) &&
3486 (mac_status
& MAC_STATUS_PCS_SYNCED
)) {
3487 u32 local_adv
= 0, remote_adv
= 0;
3489 if (sg_dig_ctrl
& SG_DIG_PAUSE_CAP
)
3490 local_adv
|= ADVERTISE_1000XPAUSE
;
3491 if (sg_dig_ctrl
& SG_DIG_ASYM_PAUSE
)
3492 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3494 if (sg_dig_status
& SG_DIG_PARTNER_PAUSE_CAPABLE
)
3495 remote_adv
|= LPA_1000XPAUSE
;
3496 if (sg_dig_status
& SG_DIG_PARTNER_ASYM_PAUSE
)
3497 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3499 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3500 current_link_up
= 1;
3501 tp
->serdes_counter
= 0;
3502 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3503 } else if (!(sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
)) {
3504 if (tp
->serdes_counter
)
3505 tp
->serdes_counter
--;
3508 u32 val
= serdes_cfg
;
3515 tw32_f(MAC_SERDES_CFG
, val
);
3518 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3521 /* Link parallel detection - link is up */
3522 /* only if we have PCS_SYNC and not */
3523 /* receiving config code words */
3524 mac_status
= tr32(MAC_STATUS
);
3525 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3526 !(mac_status
& MAC_STATUS_RCVD_CFG
)) {
3527 tg3_setup_flow_control(tp
, 0, 0);
3528 current_link_up
= 1;
3530 TG3_FLG2_PARALLEL_DETECT
;
3531 tp
->serdes_counter
=
3532 SERDES_PARALLEL_DET_TIMEOUT
;
3534 goto restart_autoneg
;
3538 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3539 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3543 return current_link_up
;
3546 static int tg3_setup_fiber_by_hand(struct tg3
*tp
, u32 mac_status
)
3548 int current_link_up
= 0;
3550 if (!(mac_status
& MAC_STATUS_PCS_SYNCED
))
3553 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3554 u32 txflags
, rxflags
;
3557 if (fiber_autoneg(tp
, &txflags
, &rxflags
)) {
3558 u32 local_adv
= 0, remote_adv
= 0;
3560 if (txflags
& ANEG_CFG_PS1
)
3561 local_adv
|= ADVERTISE_1000XPAUSE
;
3562 if (txflags
& ANEG_CFG_PS2
)
3563 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3565 if (rxflags
& MR_LP_ADV_SYM_PAUSE
)
3566 remote_adv
|= LPA_1000XPAUSE
;
3567 if (rxflags
& MR_LP_ADV_ASYM_PAUSE
)
3568 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3570 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3572 current_link_up
= 1;
3574 for (i
= 0; i
< 30; i
++) {
3577 (MAC_STATUS_SYNC_CHANGED
|
3578 MAC_STATUS_CFG_CHANGED
));
3580 if ((tr32(MAC_STATUS
) &
3581 (MAC_STATUS_SYNC_CHANGED
|
3582 MAC_STATUS_CFG_CHANGED
)) == 0)
3586 mac_status
= tr32(MAC_STATUS
);
3587 if (current_link_up
== 0 &&
3588 (mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3589 !(mac_status
& MAC_STATUS_RCVD_CFG
))
3590 current_link_up
= 1;
3592 tg3_setup_flow_control(tp
, 0, 0);
3594 /* Forcing 1000FD link up. */
3595 current_link_up
= 1;
3597 tw32_f(MAC_MODE
, (tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
));
3600 tw32_f(MAC_MODE
, tp
->mac_mode
);
3605 return current_link_up
;
3608 static int tg3_setup_fiber_phy(struct tg3
*tp
, int force_reset
)
3611 u16 orig_active_speed
;
3612 u8 orig_active_duplex
;
3614 int current_link_up
;
3617 orig_pause_cfg
= tp
->link_config
.active_flowctrl
;
3618 orig_active_speed
= tp
->link_config
.active_speed
;
3619 orig_active_duplex
= tp
->link_config
.active_duplex
;
3621 if (!(tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
) &&
3622 netif_carrier_ok(tp
->dev
) &&
3623 (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)) {
3624 mac_status
= tr32(MAC_STATUS
);
3625 mac_status
&= (MAC_STATUS_PCS_SYNCED
|
3626 MAC_STATUS_SIGNAL_DET
|
3627 MAC_STATUS_CFG_CHANGED
|
3628 MAC_STATUS_RCVD_CFG
);
3629 if (mac_status
== (MAC_STATUS_PCS_SYNCED
|
3630 MAC_STATUS_SIGNAL_DET
)) {
3631 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3632 MAC_STATUS_CFG_CHANGED
));
3637 tw32_f(MAC_TX_AUTO_NEG
, 0);
3639 tp
->mac_mode
&= ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
3640 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
3641 tw32_f(MAC_MODE
, tp
->mac_mode
);
3644 if (tp
->phy_id
== PHY_ID_BCM8002
)
3645 tg3_init_bcm8002(tp
);
3647 /* Enable link change event even when serdes polling. */
3648 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3651 current_link_up
= 0;
3652 mac_status
= tr32(MAC_STATUS
);
3654 if (tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
)
3655 current_link_up
= tg3_setup_fiber_hw_autoneg(tp
, mac_status
);
3657 current_link_up
= tg3_setup_fiber_by_hand(tp
, mac_status
);
3659 tp
->hw_status
->status
=
3660 (SD_STATUS_UPDATED
|
3661 (tp
->hw_status
->status
& ~SD_STATUS_LINK_CHG
));
3663 for (i
= 0; i
< 100; i
++) {
3664 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3665 MAC_STATUS_CFG_CHANGED
));
3667 if ((tr32(MAC_STATUS
) & (MAC_STATUS_SYNC_CHANGED
|
3668 MAC_STATUS_CFG_CHANGED
|
3669 MAC_STATUS_LNKSTATE_CHANGED
)) == 0)
3673 mac_status
= tr32(MAC_STATUS
);
3674 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) == 0) {
3675 current_link_up
= 0;
3676 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
3677 tp
->serdes_counter
== 0) {
3678 tw32_f(MAC_MODE
, (tp
->mac_mode
|
3679 MAC_MODE_SEND_CONFIGS
));
3681 tw32_f(MAC_MODE
, tp
->mac_mode
);
3685 if (current_link_up
== 1) {
3686 tp
->link_config
.active_speed
= SPEED_1000
;
3687 tp
->link_config
.active_duplex
= DUPLEX_FULL
;
3688 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
3689 LED_CTRL_LNKLED_OVERRIDE
|
3690 LED_CTRL_1000MBPS_ON
));
3692 tp
->link_config
.active_speed
= SPEED_INVALID
;
3693 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
3694 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
3695 LED_CTRL_LNKLED_OVERRIDE
|
3696 LED_CTRL_TRAFFIC_OVERRIDE
));
3699 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3700 if (current_link_up
)
3701 netif_carrier_on(tp
->dev
);
3703 netif_carrier_off(tp
->dev
);
3704 tg3_link_report(tp
);
3706 u32 now_pause_cfg
= tp
->link_config
.active_flowctrl
;
3707 if (orig_pause_cfg
!= now_pause_cfg
||
3708 orig_active_speed
!= tp
->link_config
.active_speed
||
3709 orig_active_duplex
!= tp
->link_config
.active_duplex
)
3710 tg3_link_report(tp
);
3716 static int tg3_setup_fiber_mii_phy(struct tg3
*tp
, int force_reset
)
3718 int current_link_up
, err
= 0;
3722 u32 local_adv
, remote_adv
;
3724 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3725 tw32_f(MAC_MODE
, tp
->mac_mode
);
3731 (MAC_STATUS_SYNC_CHANGED
|
3732 MAC_STATUS_CFG_CHANGED
|
3733 MAC_STATUS_MI_COMPLETION
|
3734 MAC_STATUS_LNKSTATE_CHANGED
));
3740 current_link_up
= 0;
3741 current_speed
= SPEED_INVALID
;
3742 current_duplex
= DUPLEX_INVALID
;
3744 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3745 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3746 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
3747 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
3748 bmsr
|= BMSR_LSTATUS
;
3750 bmsr
&= ~BMSR_LSTATUS
;
3753 err
|= tg3_readphy(tp
, MII_BMCR
, &bmcr
);
3755 if ((tp
->link_config
.autoneg
== AUTONEG_ENABLE
) && !force_reset
&&
3756 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
)) {
3757 /* do nothing, just check for link up at the end */
3758 } else if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3761 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
3762 new_adv
= adv
& ~(ADVERTISE_1000XFULL
| ADVERTISE_1000XHALF
|
3763 ADVERTISE_1000XPAUSE
|
3764 ADVERTISE_1000XPSE_ASYM
|
3767 new_adv
|= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3769 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
3770 new_adv
|= ADVERTISE_1000XHALF
;
3771 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
3772 new_adv
|= ADVERTISE_1000XFULL
;
3774 if ((new_adv
!= adv
) || !(bmcr
& BMCR_ANENABLE
)) {
3775 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
3776 bmcr
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
3777 tg3_writephy(tp
, MII_BMCR
, bmcr
);
3779 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3780 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5714S
;
3781 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3788 bmcr
&= ~BMCR_SPEED1000
;
3789 new_bmcr
= bmcr
& ~(BMCR_ANENABLE
| BMCR_FULLDPLX
);
3791 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
3792 new_bmcr
|= BMCR_FULLDPLX
;
3794 if (new_bmcr
!= bmcr
) {
3795 /* BMCR_SPEED1000 is a reserved bit that needs
3796 * to be set on write.
3798 new_bmcr
|= BMCR_SPEED1000
;
3800 /* Force a linkdown */
3801 if (netif_carrier_ok(tp
->dev
)) {
3804 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
3805 adv
&= ~(ADVERTISE_1000XFULL
|
3806 ADVERTISE_1000XHALF
|
3808 tg3_writephy(tp
, MII_ADVERTISE
, adv
);
3809 tg3_writephy(tp
, MII_BMCR
, bmcr
|
3813 netif_carrier_off(tp
->dev
);
3815 tg3_writephy(tp
, MII_BMCR
, new_bmcr
);
3817 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3818 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3819 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
3821 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
3822 bmsr
|= BMSR_LSTATUS
;
3824 bmsr
&= ~BMSR_LSTATUS
;
3826 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3830 if (bmsr
& BMSR_LSTATUS
) {
3831 current_speed
= SPEED_1000
;
3832 current_link_up
= 1;
3833 if (bmcr
& BMCR_FULLDPLX
)
3834 current_duplex
= DUPLEX_FULL
;
3836 current_duplex
= DUPLEX_HALF
;
3841 if (bmcr
& BMCR_ANENABLE
) {
3844 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &local_adv
);
3845 err
|= tg3_readphy(tp
, MII_LPA
, &remote_adv
);
3846 common
= local_adv
& remote_adv
;
3847 if (common
& (ADVERTISE_1000XHALF
|
3848 ADVERTISE_1000XFULL
)) {
3849 if (common
& ADVERTISE_1000XFULL
)
3850 current_duplex
= DUPLEX_FULL
;
3852 current_duplex
= DUPLEX_HALF
;
3855 current_link_up
= 0;
3859 if (current_link_up
== 1 && current_duplex
== DUPLEX_FULL
)
3860 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3862 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
3863 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
3864 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
3866 tw32_f(MAC_MODE
, tp
->mac_mode
);
3869 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3871 tp
->link_config
.active_speed
= current_speed
;
3872 tp
->link_config
.active_duplex
= current_duplex
;
3874 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3875 if (current_link_up
)
3876 netif_carrier_on(tp
->dev
);
3878 netif_carrier_off(tp
->dev
);
3879 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3881 tg3_link_report(tp
);
3886 static void tg3_serdes_parallel_detect(struct tg3
*tp
)
3888 if (tp
->serdes_counter
) {
3889 /* Give autoneg time to complete. */
3890 tp
->serdes_counter
--;
3893 if (!netif_carrier_ok(tp
->dev
) &&
3894 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)) {
3897 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
3898 if (bmcr
& BMCR_ANENABLE
) {
3901 /* Select shadow register 0x1f */
3902 tg3_writephy(tp
, 0x1c, 0x7c00);
3903 tg3_readphy(tp
, 0x1c, &phy1
);
3905 /* Select expansion interrupt status register */
3906 tg3_writephy(tp
, 0x17, 0x0f01);
3907 tg3_readphy(tp
, 0x15, &phy2
);
3908 tg3_readphy(tp
, 0x15, &phy2
);
3910 if ((phy1
& 0x10) && !(phy2
& 0x20)) {
3911 /* We have signal detect and not receiving
3912 * config code words, link is up by parallel
3916 bmcr
&= ~BMCR_ANENABLE
;
3917 bmcr
|= BMCR_SPEED1000
| BMCR_FULLDPLX
;
3918 tg3_writephy(tp
, MII_BMCR
, bmcr
);
3919 tp
->tg3_flags2
|= TG3_FLG2_PARALLEL_DETECT
;
3923 else if (netif_carrier_ok(tp
->dev
) &&
3924 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) &&
3925 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
)) {
3928 /* Select expansion interrupt status register */
3929 tg3_writephy(tp
, 0x17, 0x0f01);
3930 tg3_readphy(tp
, 0x15, &phy2
);
3934 /* Config code words received, turn on autoneg. */
3935 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
3936 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANENABLE
);
3938 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3944 static int tg3_setup_phy(struct tg3
*tp
, int force_reset
)
3948 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
3949 err
= tg3_setup_fiber_phy(tp
, force_reset
);
3950 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
3951 err
= tg3_setup_fiber_mii_phy(tp
, force_reset
);
3953 err
= tg3_setup_copper_phy(tp
, force_reset
);
3956 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
3959 val
= tr32(TG3_CPMU_CLCK_STAT
) & CPMU_CLCK_STAT_MAC_CLCK_MASK
;
3960 if (val
== CPMU_CLCK_STAT_MAC_CLCK_62_5
)
3962 else if (val
== CPMU_CLCK_STAT_MAC_CLCK_6_25
)
3967 val
= tr32(GRC_MISC_CFG
) & ~GRC_MISC_CFG_PRESCALAR_MASK
;
3968 val
|= (scale
<< GRC_MISC_CFG_PRESCALAR_SHIFT
);
3969 tw32(GRC_MISC_CFG
, val
);
3972 if (tp
->link_config
.active_speed
== SPEED_1000
&&
3973 tp
->link_config
.active_duplex
== DUPLEX_HALF
)
3974 tw32(MAC_TX_LENGTHS
,
3975 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
3976 (6 << TX_LENGTHS_IPG_SHIFT
) |
3977 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
3979 tw32(MAC_TX_LENGTHS
,
3980 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
3981 (6 << TX_LENGTHS_IPG_SHIFT
) |
3982 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
3984 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
3985 if (netif_carrier_ok(tp
->dev
)) {
3986 tw32(HOSTCC_STAT_COAL_TICKS
,
3987 tp
->coal
.stats_block_coalesce_usecs
);
3989 tw32(HOSTCC_STAT_COAL_TICKS
, 0);
3993 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
) {
3994 u32 val
= tr32(PCIE_PWR_MGMT_THRESH
);
3995 if (!netif_carrier_ok(tp
->dev
))
3996 val
= (val
& ~PCIE_PWR_MGMT_L1_THRESH_MSK
) |
3999 val
|= PCIE_PWR_MGMT_L1_THRESH_MSK
;
4000 tw32(PCIE_PWR_MGMT_THRESH
, val
);
4006 /* This is called whenever we suspect that the system chipset is re-
4007 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4008 * is bogus tx completions. We try to recover by setting the
4009 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4012 static void tg3_tx_recover(struct tg3
*tp
)
4014 BUG_ON((tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) ||
4015 tp
->write32_tx_mbox
== tg3_write_indirect_mbox
);
4017 printk(KERN_WARNING PFX
"%s: The system may be re-ordering memory-"
4018 "mapped I/O cycles to the network device, attempting to "
4019 "recover. Please report the problem to the driver maintainer "
4020 "and include system chipset information.\n", tp
->dev
->name
);
4022 spin_lock(&tp
->lock
);
4023 tp
->tg3_flags
|= TG3_FLAG_TX_RECOVERY_PENDING
;
4024 spin_unlock(&tp
->lock
);
4027 static inline u32
tg3_tx_avail(struct tg3
*tp
)
4030 return (tp
->tx_pending
-
4031 ((tp
->tx_prod
- tp
->tx_cons
) & (TG3_TX_RING_SIZE
- 1)));
4034 /* Tigon3 never reports partial packet sends. So we do not
4035 * need special logic to handle SKBs that have not had all
4036 * of their frags sent yet, like SunGEM does.
4038 static void tg3_tx(struct tg3
*tp
)
4040 u32 hw_idx
= tp
->hw_status
->idx
[0].tx_consumer
;
4041 u32 sw_idx
= tp
->tx_cons
;
4043 while (sw_idx
!= hw_idx
) {
4044 struct tx_ring_info
*ri
= &tp
->tx_buffers
[sw_idx
];
4045 struct sk_buff
*skb
= ri
->skb
;
4048 if (unlikely(skb
== NULL
)) {
4053 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
4057 sw_idx
= NEXT_TX(sw_idx
);
4059 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
4060 ri
= &tp
->tx_buffers
[sw_idx
];
4061 if (unlikely(ri
->skb
!= NULL
|| sw_idx
== hw_idx
))
4063 sw_idx
= NEXT_TX(sw_idx
);
4068 if (unlikely(tx_bug
)) {
4074 tp
->tx_cons
= sw_idx
;
4076 /* Need to make the tx_cons update visible to tg3_start_xmit()
4077 * before checking for netif_queue_stopped(). Without the
4078 * memory barrier, there is a small possibility that tg3_start_xmit()
4079 * will miss it and cause the queue to be stopped forever.
4083 if (unlikely(netif_queue_stopped(tp
->dev
) &&
4084 (tg3_tx_avail(tp
) > TG3_TX_WAKEUP_THRESH(tp
)))) {
4085 netif_tx_lock(tp
->dev
);
4086 if (netif_queue_stopped(tp
->dev
) &&
4087 (tg3_tx_avail(tp
) > TG3_TX_WAKEUP_THRESH(tp
)))
4088 netif_wake_queue(tp
->dev
);
4089 netif_tx_unlock(tp
->dev
);
4093 /* Returns size of skb allocated or < 0 on error.
4095 * We only need to fill in the address because the other members
4096 * of the RX descriptor are invariant, see tg3_init_rings.
4098 * Note the purposeful assymetry of cpu vs. chip accesses. For
4099 * posting buffers we only dirty the first cache line of the RX
4100 * descriptor (containing the address). Whereas for the RX status
4101 * buffers the cpu only reads the last cacheline of the RX descriptor
4102 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4104 static int tg3_alloc_rx_skb(struct tg3
*tp
, u32 opaque_key
,
4105 int src_idx
, u32 dest_idx_unmasked
)
4107 struct tg3_rx_buffer_desc
*desc
;
4108 struct ring_info
*map
, *src_map
;
4109 struct sk_buff
*skb
;
4111 int skb_size
, dest_idx
;
4114 switch (opaque_key
) {
4115 case RXD_OPAQUE_RING_STD
:
4116 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4117 desc
= &tp
->rx_std
[dest_idx
];
4118 map
= &tp
->rx_std_buffers
[dest_idx
];
4120 src_map
= &tp
->rx_std_buffers
[src_idx
];
4121 skb_size
= tp
->rx_pkt_buf_sz
;
4124 case RXD_OPAQUE_RING_JUMBO
:
4125 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4126 desc
= &tp
->rx_jumbo
[dest_idx
];
4127 map
= &tp
->rx_jumbo_buffers
[dest_idx
];
4129 src_map
= &tp
->rx_jumbo_buffers
[src_idx
];
4130 skb_size
= RX_JUMBO_PKT_BUF_SZ
;
4137 /* Do not overwrite any of the map or rp information
4138 * until we are sure we can commit to a new buffer.
4140 * Callers depend upon this behavior and assume that
4141 * we leave everything unchanged if we fail.
4143 skb
= netdev_alloc_skb(tp
->dev
, skb_size
);
4147 skb_reserve(skb
, tp
->rx_offset
);
4149 mapping
= pci_map_single(tp
->pdev
, skb
->data
,
4150 skb_size
- tp
->rx_offset
,
4151 PCI_DMA_FROMDEVICE
);
4154 pci_unmap_addr_set(map
, mapping
, mapping
);
4156 if (src_map
!= NULL
)
4157 src_map
->skb
= NULL
;
4159 desc
->addr_hi
= ((u64
)mapping
>> 32);
4160 desc
->addr_lo
= ((u64
)mapping
& 0xffffffff);
4165 /* We only need to move over in the address because the other
4166 * members of the RX descriptor are invariant. See notes above
4167 * tg3_alloc_rx_skb for full details.
4169 static void tg3_recycle_rx(struct tg3
*tp
, u32 opaque_key
,
4170 int src_idx
, u32 dest_idx_unmasked
)
4172 struct tg3_rx_buffer_desc
*src_desc
, *dest_desc
;
4173 struct ring_info
*src_map
, *dest_map
;
4176 switch (opaque_key
) {
4177 case RXD_OPAQUE_RING_STD
:
4178 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4179 dest_desc
= &tp
->rx_std
[dest_idx
];
4180 dest_map
= &tp
->rx_std_buffers
[dest_idx
];
4181 src_desc
= &tp
->rx_std
[src_idx
];
4182 src_map
= &tp
->rx_std_buffers
[src_idx
];
4185 case RXD_OPAQUE_RING_JUMBO
:
4186 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4187 dest_desc
= &tp
->rx_jumbo
[dest_idx
];
4188 dest_map
= &tp
->rx_jumbo_buffers
[dest_idx
];
4189 src_desc
= &tp
->rx_jumbo
[src_idx
];
4190 src_map
= &tp
->rx_jumbo_buffers
[src_idx
];
4197 dest_map
->skb
= src_map
->skb
;
4198 pci_unmap_addr_set(dest_map
, mapping
,
4199 pci_unmap_addr(src_map
, mapping
));
4200 dest_desc
->addr_hi
= src_desc
->addr_hi
;
4201 dest_desc
->addr_lo
= src_desc
->addr_lo
;
4203 src_map
->skb
= NULL
;
4206 #if TG3_VLAN_TAG_USED
4207 static int tg3_vlan_rx(struct tg3
*tp
, struct sk_buff
*skb
, u16 vlan_tag
)
4209 return vlan_hwaccel_receive_skb(skb
, tp
->vlgrp
, vlan_tag
);
4213 /* The RX ring scheme is composed of multiple rings which post fresh
4214 * buffers to the chip, and one special ring the chip uses to report
4215 * status back to the host.
4217 * The special ring reports the status of received packets to the
4218 * host. The chip does not write into the original descriptor the
4219 * RX buffer was obtained from. The chip simply takes the original
4220 * descriptor as provided by the host, updates the status and length
4221 * field, then writes this into the next status ring entry.
4223 * Each ring the host uses to post buffers to the chip is described
4224 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4225 * it is first placed into the on-chip ram. When the packet's length
4226 * is known, it walks down the TG3_BDINFO entries to select the ring.
4227 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4228 * which is within the range of the new packet's length is chosen.
4230 * The "separate ring for rx status" scheme may sound queer, but it makes
4231 * sense from a cache coherency perspective. If only the host writes
4232 * to the buffer post rings, and only the chip writes to the rx status
4233 * rings, then cache lines never move beyond shared-modified state.
4234 * If both the host and chip were to write into the same ring, cache line
4235 * eviction could occur since both entities want it in an exclusive state.
4237 static int tg3_rx(struct tg3
*tp
, int budget
)
4239 u32 work_mask
, rx_std_posted
= 0;
4240 u32 sw_idx
= tp
->rx_rcb_ptr
;
4244 hw_idx
= tp
->hw_status
->idx
[0].rx_producer
;
4246 * We need to order the read of hw_idx and the read of
4247 * the opaque cookie.
4252 while (sw_idx
!= hw_idx
&& budget
> 0) {
4253 struct tg3_rx_buffer_desc
*desc
= &tp
->rx_rcb
[sw_idx
];
4255 struct sk_buff
*skb
;
4256 dma_addr_t dma_addr
;
4257 u32 opaque_key
, desc_idx
, *post_ptr
;
4259 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
4260 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
4261 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
4262 dma_addr
= pci_unmap_addr(&tp
->rx_std_buffers
[desc_idx
],
4264 skb
= tp
->rx_std_buffers
[desc_idx
].skb
;
4265 post_ptr
= &tp
->rx_std_ptr
;
4267 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
4268 dma_addr
= pci_unmap_addr(&tp
->rx_jumbo_buffers
[desc_idx
],
4270 skb
= tp
->rx_jumbo_buffers
[desc_idx
].skb
;
4271 post_ptr
= &tp
->rx_jumbo_ptr
;
4274 goto next_pkt_nopost
;
4277 work_mask
|= opaque_key
;
4279 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
4280 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
)) {
4282 tg3_recycle_rx(tp
, opaque_key
,
4283 desc_idx
, *post_ptr
);
4285 /* Other statistics kept track of by card. */
4286 tp
->net_stats
.rx_dropped
++;
4290 len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) -
4293 if (len
> RX_COPY_THRESHOLD
4294 && tp
->rx_offset
== NET_IP_ALIGN
4295 /* rx_offset will likely not equal NET_IP_ALIGN
4296 * if this is a 5701 card running in PCI-X mode
4297 * [see tg3_get_invariants()]
4302 skb_size
= tg3_alloc_rx_skb(tp
, opaque_key
,
4303 desc_idx
, *post_ptr
);
4307 pci_unmap_single(tp
->pdev
, dma_addr
,
4308 skb_size
- tp
->rx_offset
,
4309 PCI_DMA_FROMDEVICE
);
4313 struct sk_buff
*copy_skb
;
4315 tg3_recycle_rx(tp
, opaque_key
,
4316 desc_idx
, *post_ptr
);
4318 copy_skb
= netdev_alloc_skb(tp
->dev
,
4319 len
+ TG3_RAW_IP_ALIGN
);
4320 if (copy_skb
== NULL
)
4321 goto drop_it_no_recycle
;
4323 skb_reserve(copy_skb
, TG3_RAW_IP_ALIGN
);
4324 skb_put(copy_skb
, len
);
4325 pci_dma_sync_single_for_cpu(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4326 skb_copy_from_linear_data(skb
, copy_skb
->data
, len
);
4327 pci_dma_sync_single_for_device(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4329 /* We'll reuse the original ring buffer. */
4333 if ((tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) &&
4334 (desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
4335 (((desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
4336 >> RXD_TCPCSUM_SHIFT
) == 0xffff))
4337 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4339 skb
->ip_summed
= CHECKSUM_NONE
;
4341 skb
->protocol
= eth_type_trans(skb
, tp
->dev
);
4342 #if TG3_VLAN_TAG_USED
4343 if (tp
->vlgrp
!= NULL
&&
4344 desc
->type_flags
& RXD_FLAG_VLAN
) {
4345 tg3_vlan_rx(tp
, skb
,
4346 desc
->err_vlan
& RXD_VLAN_MASK
);
4349 netif_receive_skb(skb
);
4357 if (unlikely(rx_std_posted
>= tp
->rx_std_max_post
)) {
4358 u32 idx
= *post_ptr
% TG3_RX_RING_SIZE
;
4360 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+
4361 TG3_64BIT_REG_LOW
, idx
);
4362 work_mask
&= ~RXD_OPAQUE_RING_STD
;
4367 sw_idx
&= (TG3_RX_RCB_RING_SIZE(tp
) - 1);
4369 /* Refresh hw_idx to see if there is new work */
4370 if (sw_idx
== hw_idx
) {
4371 hw_idx
= tp
->hw_status
->idx
[0].rx_producer
;
4376 /* ACK the status ring. */
4377 tp
->rx_rcb_ptr
= sw_idx
;
4378 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
, sw_idx
);
4380 /* Refill RX ring(s). */
4381 if (work_mask
& RXD_OPAQUE_RING_STD
) {
4382 sw_idx
= tp
->rx_std_ptr
% TG3_RX_RING_SIZE
;
4383 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
,
4386 if (work_mask
& RXD_OPAQUE_RING_JUMBO
) {
4387 sw_idx
= tp
->rx_jumbo_ptr
% TG3_RX_JUMBO_RING_SIZE
;
4388 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX
+ TG3_64BIT_REG_LOW
,
4396 static int tg3_poll_work(struct tg3
*tp
, int work_done
, int budget
)
4398 struct tg3_hw_status
*sblk
= tp
->hw_status
;
4400 /* handle link change and other phy events */
4401 if (!(tp
->tg3_flags
&
4402 (TG3_FLAG_USE_LINKCHG_REG
|
4403 TG3_FLAG_POLL_SERDES
))) {
4404 if (sblk
->status
& SD_STATUS_LINK_CHG
) {
4405 sblk
->status
= SD_STATUS_UPDATED
|
4406 (sblk
->status
& ~SD_STATUS_LINK_CHG
);
4407 spin_lock(&tp
->lock
);
4408 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
4410 (MAC_STATUS_SYNC_CHANGED
|
4411 MAC_STATUS_CFG_CHANGED
|
4412 MAC_STATUS_MI_COMPLETION
|
4413 MAC_STATUS_LNKSTATE_CHANGED
));
4416 tg3_setup_phy(tp
, 0);
4417 spin_unlock(&tp
->lock
);
4421 /* run TX completion thread */
4422 if (sblk
->idx
[0].tx_consumer
!= tp
->tx_cons
) {
4424 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4428 /* run RX thread, within the bounds set by NAPI.
4429 * All RX "locking" is done by ensuring outside
4430 * code synchronizes with tg3->napi.poll()
4432 if (sblk
->idx
[0].rx_producer
!= tp
->rx_rcb_ptr
)
4433 work_done
+= tg3_rx(tp
, budget
- work_done
);
4438 static int tg3_poll(struct napi_struct
*napi
, int budget
)
4440 struct tg3
*tp
= container_of(napi
, struct tg3
, napi
);
4442 struct tg3_hw_status
*sblk
= tp
->hw_status
;
4445 work_done
= tg3_poll_work(tp
, work_done
, budget
);
4447 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4450 if (unlikely(work_done
>= budget
))
4453 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
4454 /* tp->last_tag is used in tg3_restart_ints() below
4455 * to tell the hw how much work has been processed,
4456 * so we must read it before checking for more work.
4458 tp
->last_tag
= sblk
->status_tag
;
4461 sblk
->status
&= ~SD_STATUS_UPDATED
;
4463 if (likely(!tg3_has_work(tp
))) {
4464 netif_rx_complete(napi
);
4465 tg3_restart_ints(tp
);
4473 /* work_done is guaranteed to be less than budget. */
4474 netif_rx_complete(napi
);
4475 schedule_work(&tp
->reset_task
);
4479 static void tg3_irq_quiesce(struct tg3
*tp
)
4481 BUG_ON(tp
->irq_sync
);
4486 synchronize_irq(tp
->pdev
->irq
);
4489 static inline int tg3_irq_sync(struct tg3
*tp
)
4491 return tp
->irq_sync
;
4494 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4495 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4496 * with as well. Most of the time, this is not necessary except when
4497 * shutting down the device.
4499 static inline void tg3_full_lock(struct tg3
*tp
, int irq_sync
)
4501 spin_lock_bh(&tp
->lock
);
4503 tg3_irq_quiesce(tp
);
4506 static inline void tg3_full_unlock(struct tg3
*tp
)
4508 spin_unlock_bh(&tp
->lock
);
4511 /* One-shot MSI handler - Chip automatically disables interrupt
4512 * after sending MSI so driver doesn't have to do it.
4514 static irqreturn_t
tg3_msi_1shot(int irq
, void *dev_id
)
4516 struct net_device
*dev
= dev_id
;
4517 struct tg3
*tp
= netdev_priv(dev
);
4519 prefetch(tp
->hw_status
);
4520 prefetch(&tp
->rx_rcb
[tp
->rx_rcb_ptr
]);
4522 if (likely(!tg3_irq_sync(tp
)))
4523 netif_rx_schedule(&tp
->napi
);
4528 /* MSI ISR - No need to check for interrupt sharing and no need to
4529 * flush status block and interrupt mailbox. PCI ordering rules
4530 * guarantee that MSI will arrive after the status block.
4532 static irqreturn_t
tg3_msi(int irq
, void *dev_id
)
4534 struct net_device
*dev
= dev_id
;
4535 struct tg3
*tp
= netdev_priv(dev
);
4537 prefetch(tp
->hw_status
);
4538 prefetch(&tp
->rx_rcb
[tp
->rx_rcb_ptr
]);
4540 * Writing any value to intr-mbox-0 clears PCI INTA# and
4541 * chip-internal interrupt pending events.
4542 * Writing non-zero to intr-mbox-0 additional tells the
4543 * NIC to stop sending us irqs, engaging "in-intr-handler"
4546 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
4547 if (likely(!tg3_irq_sync(tp
)))
4548 netif_rx_schedule(&tp
->napi
);
4550 return IRQ_RETVAL(1);
4553 static irqreturn_t
tg3_interrupt(int irq
, void *dev_id
)
4555 struct net_device
*dev
= dev_id
;
4556 struct tg3
*tp
= netdev_priv(dev
);
4557 struct tg3_hw_status
*sblk
= tp
->hw_status
;
4558 unsigned int handled
= 1;
4560 /* In INTx mode, it is possible for the interrupt to arrive at
4561 * the CPU before the status block posted prior to the interrupt.
4562 * Reading the PCI State register will confirm whether the
4563 * interrupt is ours and will flush the status block.
4565 if (unlikely(!(sblk
->status
& SD_STATUS_UPDATED
))) {
4566 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
4567 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
4574 * Writing any value to intr-mbox-0 clears PCI INTA# and
4575 * chip-internal interrupt pending events.
4576 * Writing non-zero to intr-mbox-0 additional tells the
4577 * NIC to stop sending us irqs, engaging "in-intr-handler"
4580 * Flush the mailbox to de-assert the IRQ immediately to prevent
4581 * spurious interrupts. The flush impacts performance but
4582 * excessive spurious interrupts can be worse in some cases.
4584 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
4585 if (tg3_irq_sync(tp
))
4587 sblk
->status
&= ~SD_STATUS_UPDATED
;
4588 if (likely(tg3_has_work(tp
))) {
4589 prefetch(&tp
->rx_rcb
[tp
->rx_rcb_ptr
]);
4590 netif_rx_schedule(&tp
->napi
);
4592 /* No work, shared interrupt perhaps? re-enable
4593 * interrupts, and flush that PCI write
4595 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
4599 return IRQ_RETVAL(handled
);
4602 static irqreturn_t
tg3_interrupt_tagged(int irq
, void *dev_id
)
4604 struct net_device
*dev
= dev_id
;
4605 struct tg3
*tp
= netdev_priv(dev
);
4606 struct tg3_hw_status
*sblk
= tp
->hw_status
;
4607 unsigned int handled
= 1;
4609 /* In INTx mode, it is possible for the interrupt to arrive at
4610 * the CPU before the status block posted prior to the interrupt.
4611 * Reading the PCI State register will confirm whether the
4612 * interrupt is ours and will flush the status block.
4614 if (unlikely(sblk
->status_tag
== tp
->last_tag
)) {
4615 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
4616 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
4623 * writing any value to intr-mbox-0 clears PCI INTA# and
4624 * chip-internal interrupt pending events.
4625 * writing non-zero to intr-mbox-0 additional tells the
4626 * NIC to stop sending us irqs, engaging "in-intr-handler"
4629 * Flush the mailbox to de-assert the IRQ immediately to prevent
4630 * spurious interrupts. The flush impacts performance but
4631 * excessive spurious interrupts can be worse in some cases.
4633 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
4634 if (tg3_irq_sync(tp
))
4636 if (netif_rx_schedule_prep(&tp
->napi
)) {
4637 prefetch(&tp
->rx_rcb
[tp
->rx_rcb_ptr
]);
4638 /* Update last_tag to mark that this status has been
4639 * seen. Because interrupt may be shared, we may be
4640 * racing with tg3_poll(), so only update last_tag
4641 * if tg3_poll() is not scheduled.
4643 tp
->last_tag
= sblk
->status_tag
;
4644 __netif_rx_schedule(&tp
->napi
);
4647 return IRQ_RETVAL(handled
);
4650 /* ISR for interrupt test */
4651 static irqreturn_t
tg3_test_isr(int irq
, void *dev_id
)
4653 struct net_device
*dev
= dev_id
;
4654 struct tg3
*tp
= netdev_priv(dev
);
4655 struct tg3_hw_status
*sblk
= tp
->hw_status
;
4657 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
4658 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
4659 tg3_disable_ints(tp
);
4660 return IRQ_RETVAL(1);
4662 return IRQ_RETVAL(0);
4665 static int tg3_init_hw(struct tg3
*, int);
4666 static int tg3_halt(struct tg3
*, int, int);
4668 /* Restart hardware after configuration changes, self-test, etc.
4669 * Invoked with tp->lock held.
4671 static int tg3_restart_hw(struct tg3
*tp
, int reset_phy
)
4672 __releases(tp
->lock
)
4673 __acquires(tp
->lock
)
4677 err
= tg3_init_hw(tp
, reset_phy
);
4679 printk(KERN_ERR PFX
"%s: Failed to re-initialize device, "
4680 "aborting.\n", tp
->dev
->name
);
4681 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
4682 tg3_full_unlock(tp
);
4683 del_timer_sync(&tp
->timer
);
4685 napi_enable(&tp
->napi
);
4687 tg3_full_lock(tp
, 0);
4692 #ifdef CONFIG_NET_POLL_CONTROLLER
4693 static void tg3_poll_controller(struct net_device
*dev
)
4695 struct tg3
*tp
= netdev_priv(dev
);
4697 tg3_interrupt(tp
->pdev
->irq
, dev
);
4701 static void tg3_reset_task(struct work_struct
*work
)
4703 struct tg3
*tp
= container_of(work
, struct tg3
, reset_task
);
4705 unsigned int restart_timer
;
4707 tg3_full_lock(tp
, 0);
4709 if (!netif_running(tp
->dev
)) {
4710 tg3_full_unlock(tp
);
4714 tg3_full_unlock(tp
);
4720 tg3_full_lock(tp
, 1);
4722 restart_timer
= tp
->tg3_flags2
& TG3_FLG2_RESTART_TIMER
;
4723 tp
->tg3_flags2
&= ~TG3_FLG2_RESTART_TIMER
;
4725 if (tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
) {
4726 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
4727 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
4728 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
4729 tp
->tg3_flags
&= ~TG3_FLAG_TX_RECOVERY_PENDING
;
4732 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
4733 err
= tg3_init_hw(tp
, 1);
4737 tg3_netif_start(tp
);
4740 mod_timer(&tp
->timer
, jiffies
+ 1);
4743 tg3_full_unlock(tp
);
4749 static void tg3_dump_short_state(struct tg3
*tp
)
4751 printk(KERN_ERR PFX
"DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4752 tr32(MAC_TX_STATUS
), tr32(MAC_RX_STATUS
));
4753 printk(KERN_ERR PFX
"DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4754 tr32(RDMAC_STATUS
), tr32(WDMAC_STATUS
));
4757 static void tg3_tx_timeout(struct net_device
*dev
)
4759 struct tg3
*tp
= netdev_priv(dev
);
4761 if (netif_msg_tx_err(tp
)) {
4762 printk(KERN_ERR PFX
"%s: transmit timed out, resetting\n",
4764 tg3_dump_short_state(tp
);
4767 schedule_work(&tp
->reset_task
);
4770 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4771 static inline int tg3_4g_overflow_test(dma_addr_t mapping
, int len
)
4773 u32 base
= (u32
) mapping
& 0xffffffff;
4775 return ((base
> 0xffffdcc0) &&
4776 (base
+ len
+ 8 < base
));
4779 /* Test for DMA addresses > 40-bit */
4780 static inline int tg3_40bit_overflow_test(struct tg3
*tp
, dma_addr_t mapping
,
4783 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4784 if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
)
4785 return (((u64
) mapping
+ len
) > DMA_40BIT_MASK
);
4792 static void tg3_set_txd(struct tg3
*, int, dma_addr_t
, int, u32
, u32
);
4794 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4795 static int tigon3_dma_hwbug_workaround(struct tg3
*tp
, struct sk_buff
*skb
,
4796 u32 last_plus_one
, u32
*start
,
4797 u32 base_flags
, u32 mss
)
4799 struct sk_buff
*new_skb
;
4800 dma_addr_t new_addr
= 0;
4804 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
4805 new_skb
= skb_copy(skb
, GFP_ATOMIC
);
4807 int more_headroom
= 4 - ((unsigned long)skb
->data
& 3);
4809 new_skb
= skb_copy_expand(skb
,
4810 skb_headroom(skb
) + more_headroom
,
4811 skb_tailroom(skb
), GFP_ATOMIC
);
4817 /* New SKB is guaranteed to be linear. */
4819 ret
= skb_dma_map(&tp
->pdev
->dev
, new_skb
, DMA_TO_DEVICE
);
4820 new_addr
= skb_shinfo(new_skb
)->dma_maps
[0];
4822 /* Make sure new skb does not cross any 4G boundaries.
4823 * Drop the packet if it does.
4825 if (ret
|| tg3_4g_overflow_test(new_addr
, new_skb
->len
)) {
4827 skb_dma_unmap(&tp
->pdev
->dev
, new_skb
,
4830 dev_kfree_skb(new_skb
);
4833 tg3_set_txd(tp
, entry
, new_addr
, new_skb
->len
,
4834 base_flags
, 1 | (mss
<< 1));
4835 *start
= NEXT_TX(entry
);
4839 /* Now clean up the sw ring entries. */
4841 while (entry
!= last_plus_one
) {
4843 tp
->tx_buffers
[entry
].skb
= new_skb
;
4845 tp
->tx_buffers
[entry
].skb
= NULL
;
4847 entry
= NEXT_TX(entry
);
4851 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
4857 static void tg3_set_txd(struct tg3
*tp
, int entry
,
4858 dma_addr_t mapping
, int len
, u32 flags
,
4861 struct tg3_tx_buffer_desc
*txd
= &tp
->tx_ring
[entry
];
4862 int is_end
= (mss_and_is_end
& 0x1);
4863 u32 mss
= (mss_and_is_end
>> 1);
4867 flags
|= TXD_FLAG_END
;
4868 if (flags
& TXD_FLAG_VLAN
) {
4869 vlan_tag
= flags
>> 16;
4872 vlan_tag
|= (mss
<< TXD_MSS_SHIFT
);
4874 txd
->addr_hi
= ((u64
) mapping
>> 32);
4875 txd
->addr_lo
= ((u64
) mapping
& 0xffffffff);
4876 txd
->len_flags
= (len
<< TXD_LEN_SHIFT
) | flags
;
4877 txd
->vlan_tag
= vlan_tag
<< TXD_VLAN_TAG_SHIFT
;
4880 /* hard_start_xmit for devices that don't have any bugs and
4881 * support TG3_FLG2_HW_TSO_2 only.
4883 static int tg3_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
4885 struct tg3
*tp
= netdev_priv(dev
);
4886 u32 len
, entry
, base_flags
, mss
;
4887 struct skb_shared_info
*sp
;
4890 len
= skb_headlen(skb
);
4892 /* We are running in BH disabled context with netif_tx_lock
4893 * and TX reclaim runs via tp->napi.poll inside of a software
4894 * interrupt. Furthermore, IRQ processing runs lockless so we have
4895 * no IRQ context deadlocks to worry about either. Rejoice!
4897 if (unlikely(tg3_tx_avail(tp
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
4898 if (!netif_queue_stopped(dev
)) {
4899 netif_stop_queue(dev
);
4901 /* This is a hard error, log it. */
4902 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when "
4903 "queue awake!\n", dev
->name
);
4905 return NETDEV_TX_BUSY
;
4908 entry
= tp
->tx_prod
;
4911 if ((mss
= skb_shinfo(skb
)->gso_size
) != 0) {
4912 int tcp_opt_len
, ip_tcp_len
;
4914 if (skb_header_cloned(skb
) &&
4915 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
4920 if (skb_shinfo(skb
)->gso_type
& SKB_GSO_TCPV6
)
4921 mss
|= (skb_headlen(skb
) - ETH_HLEN
) << 9;
4923 struct iphdr
*iph
= ip_hdr(skb
);
4925 tcp_opt_len
= tcp_optlen(skb
);
4926 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
4929 iph
->tot_len
= htons(mss
+ ip_tcp_len
+ tcp_opt_len
);
4930 mss
|= (ip_tcp_len
+ tcp_opt_len
) << 9;
4933 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
4934 TXD_FLAG_CPU_POST_DMA
);
4936 tcp_hdr(skb
)->check
= 0;
4939 else if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
4940 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
4941 #if TG3_VLAN_TAG_USED
4942 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
4943 base_flags
|= (TXD_FLAG_VLAN
|
4944 (vlan_tx_tag_get(skb
) << 16));
4947 if (skb_dma_map(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
4952 sp
= skb_shinfo(skb
);
4954 mapping
= sp
->dma_maps
[0];
4956 tp
->tx_buffers
[entry
].skb
= skb
;
4958 tg3_set_txd(tp
, entry
, mapping
, len
, base_flags
,
4959 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
4961 entry
= NEXT_TX(entry
);
4963 /* Now loop through additional data fragments, and queue them. */
4964 if (skb_shinfo(skb
)->nr_frags
> 0) {
4965 unsigned int i
, last
;
4967 last
= skb_shinfo(skb
)->nr_frags
- 1;
4968 for (i
= 0; i
<= last
; i
++) {
4969 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
4972 mapping
= sp
->dma_maps
[i
+ 1];
4973 tp
->tx_buffers
[entry
].skb
= NULL
;
4975 tg3_set_txd(tp
, entry
, mapping
, len
,
4976 base_flags
, (i
== last
) | (mss
<< 1));
4978 entry
= NEXT_TX(entry
);
4982 /* Packets are ready, update Tx producer idx local and on card. */
4983 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
), entry
);
4985 tp
->tx_prod
= entry
;
4986 if (unlikely(tg3_tx_avail(tp
) <= (MAX_SKB_FRAGS
+ 1))) {
4987 netif_stop_queue(dev
);
4988 if (tg3_tx_avail(tp
) > TG3_TX_WAKEUP_THRESH(tp
))
4989 netif_wake_queue(tp
->dev
);
4995 dev
->trans_start
= jiffies
;
4997 return NETDEV_TX_OK
;
5000 static int tg3_start_xmit_dma_bug(struct sk_buff
*, struct net_device
*);
5002 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5003 * TSO header is greater than 80 bytes.
5005 static int tg3_tso_bug(struct tg3
*tp
, struct sk_buff
*skb
)
5007 struct sk_buff
*segs
, *nskb
;
5009 /* Estimate the number of fragments in the worst case */
5010 if (unlikely(tg3_tx_avail(tp
) <= (skb_shinfo(skb
)->gso_segs
* 3))) {
5011 netif_stop_queue(tp
->dev
);
5012 if (tg3_tx_avail(tp
) <= (skb_shinfo(skb
)->gso_segs
* 3))
5013 return NETDEV_TX_BUSY
;
5015 netif_wake_queue(tp
->dev
);
5018 segs
= skb_gso_segment(skb
, tp
->dev
->features
& ~NETIF_F_TSO
);
5020 goto tg3_tso_bug_end
;
5026 tg3_start_xmit_dma_bug(nskb
, tp
->dev
);
5032 return NETDEV_TX_OK
;
5035 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5036 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5038 static int tg3_start_xmit_dma_bug(struct sk_buff
*skb
, struct net_device
*dev
)
5040 struct tg3
*tp
= netdev_priv(dev
);
5041 u32 len
, entry
, base_flags
, mss
;
5042 struct skb_shared_info
*sp
;
5043 int would_hit_hwbug
;
5046 len
= skb_headlen(skb
);
5048 /* We are running in BH disabled context with netif_tx_lock
5049 * and TX reclaim runs via tp->napi.poll inside of a software
5050 * interrupt. Furthermore, IRQ processing runs lockless so we have
5051 * no IRQ context deadlocks to worry about either. Rejoice!
5053 if (unlikely(tg3_tx_avail(tp
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5054 if (!netif_queue_stopped(dev
)) {
5055 netif_stop_queue(dev
);
5057 /* This is a hard error, log it. */
5058 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when "
5059 "queue awake!\n", dev
->name
);
5061 return NETDEV_TX_BUSY
;
5064 entry
= tp
->tx_prod
;
5066 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5067 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5069 if ((mss
= skb_shinfo(skb
)->gso_size
) != 0) {
5071 int tcp_opt_len
, ip_tcp_len
, hdr_len
;
5073 if (skb_header_cloned(skb
) &&
5074 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5079 tcp_opt_len
= tcp_optlen(skb
);
5080 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5082 hdr_len
= ip_tcp_len
+ tcp_opt_len
;
5083 if (unlikely((ETH_HLEN
+ hdr_len
) > 80) &&
5084 (tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
))
5085 return (tg3_tso_bug(tp
, skb
));
5087 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5088 TXD_FLAG_CPU_POST_DMA
);
5092 iph
->tot_len
= htons(mss
+ hdr_len
);
5093 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
5094 tcp_hdr(skb
)->check
= 0;
5095 base_flags
&= ~TXD_FLAG_TCPUDP_CSUM
;
5097 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5102 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) ||
5103 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)) {
5104 if (tcp_opt_len
|| iph
->ihl
> 5) {
5107 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5108 mss
|= (tsflags
<< 11);
5111 if (tcp_opt_len
|| iph
->ihl
> 5) {
5114 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5115 base_flags
|= tsflags
<< 12;
5119 #if TG3_VLAN_TAG_USED
5120 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5121 base_flags
|= (TXD_FLAG_VLAN
|
5122 (vlan_tx_tag_get(skb
) << 16));
5125 if (skb_dma_map(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
5130 sp
= skb_shinfo(skb
);
5132 mapping
= sp
->dma_maps
[0];
5134 tp
->tx_buffers
[entry
].skb
= skb
;
5136 would_hit_hwbug
= 0;
5138 if (tp
->tg3_flags3
& TG3_FLG3_5701_DMA_BUG
)
5139 would_hit_hwbug
= 1;
5140 else if (tg3_4g_overflow_test(mapping
, len
))
5141 would_hit_hwbug
= 1;
5143 tg3_set_txd(tp
, entry
, mapping
, len
, base_flags
,
5144 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5146 entry
= NEXT_TX(entry
);
5148 /* Now loop through additional data fragments, and queue them. */
5149 if (skb_shinfo(skb
)->nr_frags
> 0) {
5150 unsigned int i
, last
;
5152 last
= skb_shinfo(skb
)->nr_frags
- 1;
5153 for (i
= 0; i
<= last
; i
++) {
5154 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5157 mapping
= sp
->dma_maps
[i
+ 1];
5159 tp
->tx_buffers
[entry
].skb
= NULL
;
5161 if (tg3_4g_overflow_test(mapping
, len
))
5162 would_hit_hwbug
= 1;
5164 if (tg3_40bit_overflow_test(tp
, mapping
, len
))
5165 would_hit_hwbug
= 1;
5167 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
5168 tg3_set_txd(tp
, entry
, mapping
, len
,
5169 base_flags
, (i
== last
)|(mss
<< 1));
5171 tg3_set_txd(tp
, entry
, mapping
, len
,
5172 base_flags
, (i
== last
));
5174 entry
= NEXT_TX(entry
);
5178 if (would_hit_hwbug
) {
5179 u32 last_plus_one
= entry
;
5182 start
= entry
- 1 - skb_shinfo(skb
)->nr_frags
;
5183 start
&= (TG3_TX_RING_SIZE
- 1);
5185 /* If the workaround fails due to memory/mapping
5186 * failure, silently drop this packet.
5188 if (tigon3_dma_hwbug_workaround(tp
, skb
, last_plus_one
,
5189 &start
, base_flags
, mss
))
5195 /* Packets are ready, update Tx producer idx local and on card. */
5196 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
), entry
);
5198 tp
->tx_prod
= entry
;
5199 if (unlikely(tg3_tx_avail(tp
) <= (MAX_SKB_FRAGS
+ 1))) {
5200 netif_stop_queue(dev
);
5201 if (tg3_tx_avail(tp
) > TG3_TX_WAKEUP_THRESH(tp
))
5202 netif_wake_queue(tp
->dev
);
5208 dev
->trans_start
= jiffies
;
5210 return NETDEV_TX_OK
;
5213 static inline void tg3_set_mtu(struct net_device
*dev
, struct tg3
*tp
,
5218 if (new_mtu
> ETH_DATA_LEN
) {
5219 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
5220 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
5221 ethtool_op_set_tso(dev
, 0);
5224 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
5226 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
5227 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
5228 tp
->tg3_flags
&= ~TG3_FLAG_JUMBO_RING_ENABLE
;
5232 static int tg3_change_mtu(struct net_device
*dev
, int new_mtu
)
5234 struct tg3
*tp
= netdev_priv(dev
);
5237 if (new_mtu
< TG3_MIN_MTU
|| new_mtu
> TG3_MAX_MTU(tp
))
5240 if (!netif_running(dev
)) {
5241 /* We'll just catch it later when the
5244 tg3_set_mtu(dev
, tp
, new_mtu
);
5252 tg3_full_lock(tp
, 1);
5254 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
5256 tg3_set_mtu(dev
, tp
, new_mtu
);
5258 err
= tg3_restart_hw(tp
, 0);
5261 tg3_netif_start(tp
);
5263 tg3_full_unlock(tp
);
5271 /* Free up pending packets in all rx/tx rings.
5273 * The chip has been shut down and the driver detached from
5274 * the networking, so no interrupts or new tx packets will
5275 * end up in the driver. tp->{tx,}lock is not held and we are not
5276 * in an interrupt context and thus may sleep.
5278 static void tg3_free_rings(struct tg3
*tp
)
5280 struct ring_info
*rxp
;
5283 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
5284 rxp
= &tp
->rx_std_buffers
[i
];
5286 if (rxp
->skb
== NULL
)
5288 pci_unmap_single(tp
->pdev
,
5289 pci_unmap_addr(rxp
, mapping
),
5290 tp
->rx_pkt_buf_sz
- tp
->rx_offset
,
5291 PCI_DMA_FROMDEVICE
);
5292 dev_kfree_skb_any(rxp
->skb
);
5296 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
5297 rxp
= &tp
->rx_jumbo_buffers
[i
];
5299 if (rxp
->skb
== NULL
)
5301 pci_unmap_single(tp
->pdev
,
5302 pci_unmap_addr(rxp
, mapping
),
5303 RX_JUMBO_PKT_BUF_SZ
- tp
->rx_offset
,
5304 PCI_DMA_FROMDEVICE
);
5305 dev_kfree_skb_any(rxp
->skb
);
5309 for (i
= 0; i
< TG3_TX_RING_SIZE
; ) {
5310 struct tx_ring_info
*txp
;
5311 struct sk_buff
*skb
;
5313 txp
= &tp
->tx_buffers
[i
];
5321 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
5325 i
+= skb_shinfo(skb
)->nr_frags
+ 1;
5327 dev_kfree_skb_any(skb
);
5331 /* Initialize tx/rx rings for packet processing.
5333 * The chip has been shut down and the driver detached from
5334 * the networking, so no interrupts or new tx packets will
5335 * end up in the driver. tp->{tx,}lock are held and thus
5338 static int tg3_init_rings(struct tg3
*tp
)
5342 /* Free up all the SKBs. */
5345 /* Zero out all descriptors. */
5346 memset(tp
->rx_std
, 0, TG3_RX_RING_BYTES
);
5347 memset(tp
->rx_jumbo
, 0, TG3_RX_JUMBO_RING_BYTES
);
5348 memset(tp
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
5349 memset(tp
->tx_ring
, 0, TG3_TX_RING_BYTES
);
5351 tp
->rx_pkt_buf_sz
= RX_PKT_BUF_SZ
;
5352 if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) &&
5353 (tp
->dev
->mtu
> ETH_DATA_LEN
))
5354 tp
->rx_pkt_buf_sz
= RX_JUMBO_PKT_BUF_SZ
;
5356 /* Initialize invariants of the rings, we only set this
5357 * stuff once. This works because the card does not
5358 * write into the rx buffer posting rings.
5360 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
5361 struct tg3_rx_buffer_desc
*rxd
;
5363 rxd
= &tp
->rx_std
[i
];
5364 rxd
->idx_len
= (tp
->rx_pkt_buf_sz
- tp
->rx_offset
- 64)
5366 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
);
5367 rxd
->opaque
= (RXD_OPAQUE_RING_STD
|
5368 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
5371 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
5372 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
5373 struct tg3_rx_buffer_desc
*rxd
;
5375 rxd
= &tp
->rx_jumbo
[i
];
5376 rxd
->idx_len
= (RX_JUMBO_PKT_BUF_SZ
- tp
->rx_offset
- 64)
5378 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
) |
5380 rxd
->opaque
= (RXD_OPAQUE_RING_JUMBO
|
5381 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
5385 /* Now allocate fresh SKBs for each rx ring. */
5386 for (i
= 0; i
< tp
->rx_pending
; i
++) {
5387 if (tg3_alloc_rx_skb(tp
, RXD_OPAQUE_RING_STD
, -1, i
) < 0) {
5388 printk(KERN_WARNING PFX
5389 "%s: Using a smaller RX standard ring, "
5390 "only %d out of %d buffers were allocated "
5392 tp
->dev
->name
, i
, tp
->rx_pending
);
5400 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
5401 for (i
= 0; i
< tp
->rx_jumbo_pending
; i
++) {
5402 if (tg3_alloc_rx_skb(tp
, RXD_OPAQUE_RING_JUMBO
,
5404 printk(KERN_WARNING PFX
5405 "%s: Using a smaller RX jumbo ring, "
5406 "only %d out of %d buffers were "
5407 "allocated successfully.\n",
5408 tp
->dev
->name
, i
, tp
->rx_jumbo_pending
);
5413 tp
->rx_jumbo_pending
= i
;
5422 * Must not be invoked with interrupt sources disabled and
5423 * the hardware shutdown down.
5425 static void tg3_free_consistent(struct tg3
*tp
)
5427 kfree(tp
->rx_std_buffers
);
5428 tp
->rx_std_buffers
= NULL
;
5430 pci_free_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
5431 tp
->rx_std
, tp
->rx_std_mapping
);
5435 pci_free_consistent(tp
->pdev
, TG3_RX_JUMBO_RING_BYTES
,
5436 tp
->rx_jumbo
, tp
->rx_jumbo_mapping
);
5437 tp
->rx_jumbo
= NULL
;
5440 pci_free_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
5441 tp
->rx_rcb
, tp
->rx_rcb_mapping
);
5445 pci_free_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
5446 tp
->tx_ring
, tp
->tx_desc_mapping
);
5449 if (tp
->hw_status
) {
5450 pci_free_consistent(tp
->pdev
, TG3_HW_STATUS_SIZE
,
5451 tp
->hw_status
, tp
->status_mapping
);
5452 tp
->hw_status
= NULL
;
5455 pci_free_consistent(tp
->pdev
, sizeof(struct tg3_hw_stats
),
5456 tp
->hw_stats
, tp
->stats_mapping
);
5457 tp
->hw_stats
= NULL
;
5462 * Must not be invoked with interrupt sources disabled and
5463 * the hardware shutdown down. Can sleep.
5465 static int tg3_alloc_consistent(struct tg3
*tp
)
5467 tp
->rx_std_buffers
= kzalloc((sizeof(struct ring_info
) *
5469 TG3_RX_JUMBO_RING_SIZE
)) +
5470 (sizeof(struct tx_ring_info
) *
5473 if (!tp
->rx_std_buffers
)
5476 tp
->rx_jumbo_buffers
= &tp
->rx_std_buffers
[TG3_RX_RING_SIZE
];
5477 tp
->tx_buffers
= (struct tx_ring_info
*)
5478 &tp
->rx_jumbo_buffers
[TG3_RX_JUMBO_RING_SIZE
];
5480 tp
->rx_std
= pci_alloc_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
5481 &tp
->rx_std_mapping
);
5485 tp
->rx_jumbo
= pci_alloc_consistent(tp
->pdev
, TG3_RX_JUMBO_RING_BYTES
,
5486 &tp
->rx_jumbo_mapping
);
5491 tp
->rx_rcb
= pci_alloc_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
5492 &tp
->rx_rcb_mapping
);
5496 tp
->tx_ring
= pci_alloc_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
5497 &tp
->tx_desc_mapping
);
5501 tp
->hw_status
= pci_alloc_consistent(tp
->pdev
,
5503 &tp
->status_mapping
);
5507 tp
->hw_stats
= pci_alloc_consistent(tp
->pdev
,
5508 sizeof(struct tg3_hw_stats
),
5509 &tp
->stats_mapping
);
5513 memset(tp
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
5514 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
5519 tg3_free_consistent(tp
);
5523 #define MAX_WAIT_CNT 1000
5525 /* To stop a block, clear the enable bit and poll till it
5526 * clears. tp->lock is held.
5528 static int tg3_stop_block(struct tg3
*tp
, unsigned long ofs
, u32 enable_bit
, int silent
)
5533 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
5540 /* We can't enable/disable these bits of the
5541 * 5705/5750, just say success.
5554 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
5557 if ((val
& enable_bit
) == 0)
5561 if (i
== MAX_WAIT_CNT
&& !silent
) {
5562 printk(KERN_ERR PFX
"tg3_stop_block timed out, "
5563 "ofs=%lx enable_bit=%x\n",
5571 /* tp->lock is held. */
5572 static int tg3_abort_hw(struct tg3
*tp
, int silent
)
5576 tg3_disable_ints(tp
);
5578 tp
->rx_mode
&= ~RX_MODE_ENABLE
;
5579 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
5582 err
= tg3_stop_block(tp
, RCVBDI_MODE
, RCVBDI_MODE_ENABLE
, silent
);
5583 err
|= tg3_stop_block(tp
, RCVLPC_MODE
, RCVLPC_MODE_ENABLE
, silent
);
5584 err
|= tg3_stop_block(tp
, RCVLSC_MODE
, RCVLSC_MODE_ENABLE
, silent
);
5585 err
|= tg3_stop_block(tp
, RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
, silent
);
5586 err
|= tg3_stop_block(tp
, RCVDCC_MODE
, RCVDCC_MODE_ENABLE
, silent
);
5587 err
|= tg3_stop_block(tp
, RCVCC_MODE
, RCVCC_MODE_ENABLE
, silent
);
5589 err
|= tg3_stop_block(tp
, SNDBDS_MODE
, SNDBDS_MODE_ENABLE
, silent
);
5590 err
|= tg3_stop_block(tp
, SNDBDI_MODE
, SNDBDI_MODE_ENABLE
, silent
);
5591 err
|= tg3_stop_block(tp
, SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
, silent
);
5592 err
|= tg3_stop_block(tp
, RDMAC_MODE
, RDMAC_MODE_ENABLE
, silent
);
5593 err
|= tg3_stop_block(tp
, SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
, silent
);
5594 err
|= tg3_stop_block(tp
, DMAC_MODE
, DMAC_MODE_ENABLE
, silent
);
5595 err
|= tg3_stop_block(tp
, SNDBDC_MODE
, SNDBDC_MODE_ENABLE
, silent
);
5597 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
5598 tw32_f(MAC_MODE
, tp
->mac_mode
);
5601 tp
->tx_mode
&= ~TX_MODE_ENABLE
;
5602 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
5604 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
5606 if (!(tr32(MAC_TX_MODE
) & TX_MODE_ENABLE
))
5609 if (i
>= MAX_WAIT_CNT
) {
5610 printk(KERN_ERR PFX
"tg3_abort_hw timed out for %s, "
5611 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5612 tp
->dev
->name
, tr32(MAC_TX_MODE
));
5616 err
|= tg3_stop_block(tp
, HOSTCC_MODE
, HOSTCC_MODE_ENABLE
, silent
);
5617 err
|= tg3_stop_block(tp
, WDMAC_MODE
, WDMAC_MODE_ENABLE
, silent
);
5618 err
|= tg3_stop_block(tp
, MBFREE_MODE
, MBFREE_MODE_ENABLE
, silent
);
5620 tw32(FTQ_RESET
, 0xffffffff);
5621 tw32(FTQ_RESET
, 0x00000000);
5623 err
|= tg3_stop_block(tp
, BUFMGR_MODE
, BUFMGR_MODE_ENABLE
, silent
);
5624 err
|= tg3_stop_block(tp
, MEMARB_MODE
, MEMARB_MODE_ENABLE
, silent
);
5627 memset(tp
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
5629 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
5634 /* tp->lock is held. */
5635 static int tg3_nvram_lock(struct tg3
*tp
)
5637 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
5640 if (tp
->nvram_lock_cnt
== 0) {
5641 tw32(NVRAM_SWARB
, SWARB_REQ_SET1
);
5642 for (i
= 0; i
< 8000; i
++) {
5643 if (tr32(NVRAM_SWARB
) & SWARB_GNT1
)
5648 tw32(NVRAM_SWARB
, SWARB_REQ_CLR1
);
5652 tp
->nvram_lock_cnt
++;
5657 /* tp->lock is held. */
5658 static void tg3_nvram_unlock(struct tg3
*tp
)
5660 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
5661 if (tp
->nvram_lock_cnt
> 0)
5662 tp
->nvram_lock_cnt
--;
5663 if (tp
->nvram_lock_cnt
== 0)
5664 tw32_f(NVRAM_SWARB
, SWARB_REQ_CLR1
);
5668 /* tp->lock is held. */
5669 static void tg3_enable_nvram_access(struct tg3
*tp
)
5671 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
5672 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
)) {
5673 u32 nvaccess
= tr32(NVRAM_ACCESS
);
5675 tw32(NVRAM_ACCESS
, nvaccess
| ACCESS_ENABLE
);
5679 /* tp->lock is held. */
5680 static void tg3_disable_nvram_access(struct tg3
*tp
)
5682 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
5683 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
)) {
5684 u32 nvaccess
= tr32(NVRAM_ACCESS
);
5686 tw32(NVRAM_ACCESS
, nvaccess
& ~ACCESS_ENABLE
);
5690 static void tg3_ape_send_event(struct tg3
*tp
, u32 event
)
5695 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
5696 if (apedata
!= APE_SEG_SIG_MAGIC
)
5699 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
5700 if (!(apedata
& APE_FW_STATUS_READY
))
5703 /* Wait for up to 1 millisecond for APE to service previous event. */
5704 for (i
= 0; i
< 10; i
++) {
5705 if (tg3_ape_lock(tp
, TG3_APE_LOCK_MEM
))
5708 apedata
= tg3_ape_read32(tp
, TG3_APE_EVENT_STATUS
);
5710 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
5711 tg3_ape_write32(tp
, TG3_APE_EVENT_STATUS
,
5712 event
| APE_EVENT_STATUS_EVENT_PENDING
);
5714 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
5716 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
5722 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
5723 tg3_ape_write32(tp
, TG3_APE_EVENT
, APE_EVENT_1
);
5726 static void tg3_ape_driver_state_change(struct tg3
*tp
, int kind
)
5731 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
5735 case RESET_KIND_INIT
:
5736 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
,
5737 APE_HOST_SEG_SIG_MAGIC
);
5738 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_LEN
,
5739 APE_HOST_SEG_LEN_MAGIC
);
5740 apedata
= tg3_ape_read32(tp
, TG3_APE_HOST_INIT_COUNT
);
5741 tg3_ape_write32(tp
, TG3_APE_HOST_INIT_COUNT
, ++apedata
);
5742 tg3_ape_write32(tp
, TG3_APE_HOST_DRIVER_ID
,
5743 APE_HOST_DRIVER_ID_MAGIC
);
5744 tg3_ape_write32(tp
, TG3_APE_HOST_BEHAVIOR
,
5745 APE_HOST_BEHAV_NO_PHYLOCK
);
5747 event
= APE_EVENT_STATUS_STATE_START
;
5749 case RESET_KIND_SHUTDOWN
:
5750 /* With the interface we are currently using,
5751 * APE does not track driver state. Wiping
5752 * out the HOST SEGMENT SIGNATURE forces
5753 * the APE to assume OS absent status.
5755 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
, 0x0);
5757 event
= APE_EVENT_STATUS_STATE_UNLOAD
;
5759 case RESET_KIND_SUSPEND
:
5760 event
= APE_EVENT_STATUS_STATE_SUSPEND
;
5766 event
|= APE_EVENT_STATUS_DRIVER_EVNT
| APE_EVENT_STATUS_STATE_CHNGE
;
5768 tg3_ape_send_event(tp
, event
);
5771 /* tp->lock is held. */
5772 static void tg3_write_sig_pre_reset(struct tg3
*tp
, int kind
)
5774 tg3_write_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
,
5775 NIC_SRAM_FIRMWARE_MBOX_MAGIC1
);
5777 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
5779 case RESET_KIND_INIT
:
5780 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5784 case RESET_KIND_SHUTDOWN
:
5785 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5789 case RESET_KIND_SUSPEND
:
5790 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5799 if (kind
== RESET_KIND_INIT
||
5800 kind
== RESET_KIND_SUSPEND
)
5801 tg3_ape_driver_state_change(tp
, kind
);
5804 /* tp->lock is held. */
5805 static void tg3_write_sig_post_reset(struct tg3
*tp
, int kind
)
5807 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
5809 case RESET_KIND_INIT
:
5810 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5811 DRV_STATE_START_DONE
);
5814 case RESET_KIND_SHUTDOWN
:
5815 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5816 DRV_STATE_UNLOAD_DONE
);
5824 if (kind
== RESET_KIND_SHUTDOWN
)
5825 tg3_ape_driver_state_change(tp
, kind
);
5828 /* tp->lock is held. */
5829 static void tg3_write_sig_legacy(struct tg3
*tp
, int kind
)
5831 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
5833 case RESET_KIND_INIT
:
5834 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5838 case RESET_KIND_SHUTDOWN
:
5839 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5843 case RESET_KIND_SUSPEND
:
5844 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
5854 static int tg3_poll_fw(struct tg3
*tp
)
5859 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
5860 /* Wait up to 20ms for init done. */
5861 for (i
= 0; i
< 200; i
++) {
5862 if (tr32(VCPU_STATUS
) & VCPU_STATUS_INIT_DONE
)
5869 /* Wait for firmware initialization to complete. */
5870 for (i
= 0; i
< 100000; i
++) {
5871 tg3_read_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
, &val
);
5872 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
5877 /* Chip might not be fitted with firmware. Some Sun onboard
5878 * parts are configured like that. So don't signal the timeout
5879 * of the above loop as an error, but do report the lack of
5880 * running firmware once.
5883 !(tp
->tg3_flags2
& TG3_FLG2_NO_FWARE_REPORTED
)) {
5884 tp
->tg3_flags2
|= TG3_FLG2_NO_FWARE_REPORTED
;
5886 printk(KERN_INFO PFX
"%s: No firmware running.\n",
5893 /* Save PCI command register before chip reset */
5894 static void tg3_save_pci_state(struct tg3
*tp
)
5896 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &tp
->pci_cmd
);
5899 /* Restore PCI state after chip reset */
5900 static void tg3_restore_pci_state(struct tg3
*tp
)
5904 /* Re-enable indirect register accesses. */
5905 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
5906 tp
->misc_host_ctrl
);
5908 /* Set MAX PCI retry to zero. */
5909 val
= (PCISTATE_ROM_ENABLE
| PCISTATE_ROM_RETRY_ENABLE
);
5910 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
5911 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
))
5912 val
|= PCISTATE_RETRY_SAME_DMA
;
5913 /* Allow reads and writes to the APE register and memory space. */
5914 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
5915 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
5916 PCISTATE_ALLOW_APE_SHMEM_WR
;
5917 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, val
);
5919 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, tp
->pci_cmd
);
5921 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
) {
5922 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
5923 pcie_set_readrq(tp
->pdev
, 4096);
5925 pci_write_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
5926 tp
->pci_cacheline_sz
);
5927 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
5932 /* Make sure PCI-X relaxed ordering bit is clear. */
5933 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
5936 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
5938 pcix_cmd
&= ~PCI_X_CMD_ERO
;
5939 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
5943 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
5945 /* Chip reset on 5780 will reset MSI enable bit,
5946 * so need to restore it.
5948 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
5951 pci_read_config_word(tp
->pdev
,
5952 tp
->msi_cap
+ PCI_MSI_FLAGS
,
5954 pci_write_config_word(tp
->pdev
,
5955 tp
->msi_cap
+ PCI_MSI_FLAGS
,
5956 ctrl
| PCI_MSI_FLAGS_ENABLE
);
5957 val
= tr32(MSGINT_MODE
);
5958 tw32(MSGINT_MODE
, val
| MSGINT_MODE_ENABLE
);
5963 static void tg3_stop_fw(struct tg3
*);
5965 /* tp->lock is held. */
5966 static int tg3_chip_reset(struct tg3
*tp
)
5969 void (*write_op
)(struct tg3
*, u32
, u32
);
5976 tg3_ape_lock(tp
, TG3_APE_LOCK_GRC
);
5978 /* No matching tg3_nvram_unlock() after this because
5979 * chip reset below will undo the nvram lock.
5981 tp
->nvram_lock_cnt
= 0;
5983 /* GRC_MISC_CFG core clock reset will clear the memory
5984 * enable bit in PCI register 4 and the MSI enable bit
5985 * on some chips, so we save relevant registers here.
5987 tg3_save_pci_state(tp
);
5989 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
5990 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
))
5991 tw32(GRC_FASTBOOT_PC
, 0);
5994 * We must avoid the readl() that normally takes place.
5995 * It locks machines, causes machine checks, and other
5996 * fun things. So, temporarily disable the 5701
5997 * hardware workaround, while we do the reset.
5999 write_op
= tp
->write32
;
6000 if (write_op
== tg3_write_flush_reg32
)
6001 tp
->write32
= tg3_write32
;
6003 /* Prevent the irq handler from reading or writing PCI registers
6004 * during chip reset when the memory enable bit in the PCI command
6005 * register may be cleared. The chip does not generate interrupt
6006 * at this time, but the irq handler may still be called due to irq
6007 * sharing or irqpoll.
6009 tp
->tg3_flags
|= TG3_FLAG_CHIP_RESETTING
;
6010 if (tp
->hw_status
) {
6011 tp
->hw_status
->status
= 0;
6012 tp
->hw_status
->status_tag
= 0;
6016 synchronize_irq(tp
->pdev
->irq
);
6019 val
= GRC_MISC_CFG_CORECLK_RESET
;
6021 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
6022 if (tr32(0x7e2c) == 0x60) {
6025 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
6026 tw32(GRC_MISC_CFG
, (1 << 29));
6031 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6032 tw32(VCPU_STATUS
, tr32(VCPU_STATUS
) | VCPU_STATUS_DRV_RESET
);
6033 tw32(GRC_VCPU_EXT_CTRL
,
6034 tr32(GRC_VCPU_EXT_CTRL
) & ~GRC_VCPU_EXT_CTRL_HALT_CPU
);
6037 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
6038 val
|= GRC_MISC_CFG_KEEP_GPHY_POWER
;
6039 tw32(GRC_MISC_CFG
, val
);
6041 /* restore 5701 hardware bug workaround write method */
6042 tp
->write32
= write_op
;
6044 /* Unfortunately, we have to delay before the PCI read back.
6045 * Some 575X chips even will not respond to a PCI cfg access
6046 * when the reset command is given to the chip.
6048 * How do these hardware designers expect things to work
6049 * properly if the PCI write is posted for a long period
6050 * of time? It is always necessary to have some method by
6051 * which a register read back can occur to push the write
6052 * out which does the reset.
6054 * For most tg3 variants the trick below was working.
6059 /* Flush PCI posted writes. The normal MMIO registers
6060 * are inaccessible at this time so this is the only
6061 * way to make this reliably (actually, this is no longer
6062 * the case, see above). I tried to use indirect
6063 * register read/write but this upset some 5701 variants.
6065 pci_read_config_dword(tp
->pdev
, PCI_COMMAND
, &val
);
6069 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) && tp
->pcie_cap
) {
6070 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
) {
6074 /* Wait for link training to complete. */
6075 for (i
= 0; i
< 5000; i
++)
6078 pci_read_config_dword(tp
->pdev
, 0xc4, &cfg_val
);
6079 pci_write_config_dword(tp
->pdev
, 0xc4,
6080 cfg_val
| (1 << 15));
6083 /* Set PCIE max payload size to 128 bytes and
6084 * clear the "no snoop" and "relaxed ordering" bits.
6086 pci_write_config_word(tp
->pdev
,
6087 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
6090 pcie_set_readrq(tp
->pdev
, 4096);
6092 /* Clear error status */
6093 pci_write_config_word(tp
->pdev
,
6094 tp
->pcie_cap
+ PCI_EXP_DEVSTA
,
6095 PCI_EXP_DEVSTA_CED
|
6096 PCI_EXP_DEVSTA_NFED
|
6097 PCI_EXP_DEVSTA_FED
|
6098 PCI_EXP_DEVSTA_URD
);
6101 tg3_restore_pci_state(tp
);
6103 tp
->tg3_flags
&= ~TG3_FLAG_CHIP_RESETTING
;
6106 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
6107 val
= tr32(MEMARB_MODE
);
6108 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
6110 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A3
) {
6112 tw32(0x5000, 0x400);
6115 tw32(GRC_MODE
, tp
->grc_mode
);
6117 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
) {
6120 tw32(0xc4, val
| (1 << 15));
6123 if ((tp
->nic_sram_data_cfg
& NIC_SRAM_DATA_CFG_MINI_PCI
) != 0 &&
6124 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
6125 tp
->pci_clock_ctrl
|= CLOCK_CTRL_CLKRUN_OENABLE
;
6126 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
)
6127 tp
->pci_clock_ctrl
|= CLOCK_CTRL_FORCE_CLKRUN
;
6128 tw32(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
6131 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
6132 tp
->mac_mode
= MAC_MODE_PORT_MODE_TBI
;
6133 tw32_f(MAC_MODE
, tp
->mac_mode
);
6134 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
6135 tp
->mac_mode
= MAC_MODE_PORT_MODE_GMII
;
6136 tw32_f(MAC_MODE
, tp
->mac_mode
);
6137 } else if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
6138 tp
->mac_mode
&= (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
6139 if (tp
->mac_mode
& MAC_MODE_APE_TX_EN
)
6140 tp
->mac_mode
|= MAC_MODE_TDE_ENABLE
;
6141 tw32_f(MAC_MODE
, tp
->mac_mode
);
6143 tw32_f(MAC_MODE
, 0);
6148 tg3_ape_unlock(tp
, TG3_APE_LOCK_GRC
);
6150 err
= tg3_poll_fw(tp
);
6154 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
6155 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
6158 tw32(0x7c00, val
| (1 << 25));
6161 /* Reprobe ASF enable state. */
6162 tp
->tg3_flags
&= ~TG3_FLAG_ENABLE_ASF
;
6163 tp
->tg3_flags2
&= ~TG3_FLG2_ASF_NEW_HANDSHAKE
;
6164 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
6165 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
6168 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
6169 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
6170 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
6171 tp
->last_event_jiffies
= jiffies
;
6172 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
6173 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
6180 /* tp->lock is held. */
6181 static void tg3_stop_fw(struct tg3
*tp
)
6183 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
6184 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
6185 /* Wait for RX cpu to ACK the previous event. */
6186 tg3_wait_for_event_ack(tp
);
6188 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_PAUSE_FW
);
6190 tg3_generate_fw_event(tp
);
6192 /* Wait for RX cpu to ACK this event. */
6193 tg3_wait_for_event_ack(tp
);
6197 /* tp->lock is held. */
6198 static int tg3_halt(struct tg3
*tp
, int kind
, int silent
)
6204 tg3_write_sig_pre_reset(tp
, kind
);
6206 tg3_abort_hw(tp
, silent
);
6207 err
= tg3_chip_reset(tp
);
6209 tg3_write_sig_legacy(tp
, kind
);
6210 tg3_write_sig_post_reset(tp
, kind
);
6218 #define RX_CPU_SCRATCH_BASE 0x30000
6219 #define RX_CPU_SCRATCH_SIZE 0x04000
6220 #define TX_CPU_SCRATCH_BASE 0x34000
6221 #define TX_CPU_SCRATCH_SIZE 0x04000
6223 /* tp->lock is held. */
6224 static int tg3_halt_cpu(struct tg3
*tp
, u32 offset
)
6228 BUG_ON(offset
== TX_CPU_BASE
&&
6229 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
));
6231 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6232 u32 val
= tr32(GRC_VCPU_EXT_CTRL
);
6234 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_HALT_CPU
);
6237 if (offset
== RX_CPU_BASE
) {
6238 for (i
= 0; i
< 10000; i
++) {
6239 tw32(offset
+ CPU_STATE
, 0xffffffff);
6240 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
6241 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
6245 tw32(offset
+ CPU_STATE
, 0xffffffff);
6246 tw32_f(offset
+ CPU_MODE
, CPU_MODE_HALT
);
6249 for (i
= 0; i
< 10000; i
++) {
6250 tw32(offset
+ CPU_STATE
, 0xffffffff);
6251 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
6252 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
6258 printk(KERN_ERR PFX
"tg3_reset_cpu timed out for %s, "
6261 (offset
== RX_CPU_BASE
? "RX" : "TX"));
6265 /* Clear firmware's nvram arbitration. */
6266 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
6267 tw32(NVRAM_SWARB
, SWARB_REQ_CLR0
);
6272 unsigned int fw_base
;
6273 unsigned int fw_len
;
6274 const __be32
*fw_data
;
6277 /* tp->lock is held. */
6278 static int tg3_load_firmware_cpu(struct tg3
*tp
, u32 cpu_base
, u32 cpu_scratch_base
,
6279 int cpu_scratch_size
, struct fw_info
*info
)
6281 int err
, lock_err
, i
;
6282 void (*write_op
)(struct tg3
*, u32
, u32
);
6284 if (cpu_base
== TX_CPU_BASE
&&
6285 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6286 printk(KERN_ERR PFX
"tg3_load_firmware_cpu: Trying to load "
6287 "TX cpu firmware on %s which is 5705.\n",
6292 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
6293 write_op
= tg3_write_mem
;
6295 write_op
= tg3_write_indirect_reg32
;
6297 /* It is possible that bootcode is still loading at this point.
6298 * Get the nvram lock first before halting the cpu.
6300 lock_err
= tg3_nvram_lock(tp
);
6301 err
= tg3_halt_cpu(tp
, cpu_base
);
6303 tg3_nvram_unlock(tp
);
6307 for (i
= 0; i
< cpu_scratch_size
; i
+= sizeof(u32
))
6308 write_op(tp
, cpu_scratch_base
+ i
, 0);
6309 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6310 tw32(cpu_base
+ CPU_MODE
, tr32(cpu_base
+CPU_MODE
)|CPU_MODE_HALT
);
6311 for (i
= 0; i
< (info
->fw_len
/ sizeof(u32
)); i
++)
6312 write_op(tp
, (cpu_scratch_base
+
6313 (info
->fw_base
& 0xffff) +
6315 be32_to_cpu(info
->fw_data
[i
]));
6323 /* tp->lock is held. */
6324 static int tg3_load_5701_a0_firmware_fix(struct tg3
*tp
)
6326 struct fw_info info
;
6327 const __be32
*fw_data
;
6330 fw_data
= (void *)tp
->fw
->data
;
6332 /* Firmware blob starts with version numbers, followed by
6333 start address and length. We are setting complete length.
6334 length = end_address_of_bss - start_address_of_text.
6335 Remainder is the blob to be loaded contiguously
6336 from start address. */
6338 info
.fw_base
= be32_to_cpu(fw_data
[1]);
6339 info
.fw_len
= tp
->fw
->size
- 12;
6340 info
.fw_data
= &fw_data
[3];
6342 err
= tg3_load_firmware_cpu(tp
, RX_CPU_BASE
,
6343 RX_CPU_SCRATCH_BASE
, RX_CPU_SCRATCH_SIZE
,
6348 err
= tg3_load_firmware_cpu(tp
, TX_CPU_BASE
,
6349 TX_CPU_SCRATCH_BASE
, TX_CPU_SCRATCH_SIZE
,
6354 /* Now startup only the RX cpu. */
6355 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
6356 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
6358 for (i
= 0; i
< 5; i
++) {
6359 if (tr32(RX_CPU_BASE
+ CPU_PC
) == info
.fw_base
)
6361 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
6362 tw32(RX_CPU_BASE
+ CPU_MODE
, CPU_MODE_HALT
);
6363 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
6367 printk(KERN_ERR PFX
"tg3_load_firmware fails for %s "
6368 "to set RX CPU PC, is %08x should be %08x\n",
6369 tp
->dev
->name
, tr32(RX_CPU_BASE
+ CPU_PC
),
6373 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
6374 tw32_f(RX_CPU_BASE
+ CPU_MODE
, 0x00000000);
6379 /* 5705 needs a special version of the TSO firmware. */
6381 /* tp->lock is held. */
6382 static int tg3_load_tso_firmware(struct tg3
*tp
)
6384 struct fw_info info
;
6385 const __be32
*fw_data
;
6386 unsigned long cpu_base
, cpu_scratch_base
, cpu_scratch_size
;
6389 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
6392 fw_data
= (void *)tp
->fw
->data
;
6394 /* Firmware blob starts with version numbers, followed by
6395 start address and length. We are setting complete length.
6396 length = end_address_of_bss - start_address_of_text.
6397 Remainder is the blob to be loaded contiguously
6398 from start address. */
6400 info
.fw_base
= be32_to_cpu(fw_data
[1]);
6401 cpu_scratch_size
= tp
->fw_len
;
6402 info
.fw_len
= tp
->fw
->size
- 12;
6403 info
.fw_data
= &fw_data
[3];
6405 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
6406 cpu_base
= RX_CPU_BASE
;
6407 cpu_scratch_base
= NIC_SRAM_MBUF_POOL_BASE5705
;
6409 cpu_base
= TX_CPU_BASE
;
6410 cpu_scratch_base
= TX_CPU_SCRATCH_BASE
;
6411 cpu_scratch_size
= TX_CPU_SCRATCH_SIZE
;
6414 err
= tg3_load_firmware_cpu(tp
, cpu_base
,
6415 cpu_scratch_base
, cpu_scratch_size
,
6420 /* Now startup the cpu. */
6421 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6422 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
6424 for (i
= 0; i
< 5; i
++) {
6425 if (tr32(cpu_base
+ CPU_PC
) == info
.fw_base
)
6427 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6428 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
6429 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
6433 printk(KERN_ERR PFX
"tg3_load_tso_firmware fails for %s "
6434 "to set CPU PC, is %08x should be %08x\n",
6435 tp
->dev
->name
, tr32(cpu_base
+ CPU_PC
),
6439 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6440 tw32_f(cpu_base
+ CPU_MODE
, 0x00000000);
6445 static int tg3_set_mac_addr(struct net_device
*dev
, void *p
)
6447 struct tg3
*tp
= netdev_priv(dev
);
6448 struct sockaddr
*addr
= p
;
6449 int err
= 0, skip_mac_1
= 0;
6451 if (!is_valid_ether_addr(addr
->sa_data
))
6454 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
6456 if (!netif_running(dev
))
6459 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
6460 u32 addr0_high
, addr0_low
, addr1_high
, addr1_low
;
6462 addr0_high
= tr32(MAC_ADDR_0_HIGH
);
6463 addr0_low
= tr32(MAC_ADDR_0_LOW
);
6464 addr1_high
= tr32(MAC_ADDR_1_HIGH
);
6465 addr1_low
= tr32(MAC_ADDR_1_LOW
);
6467 /* Skip MAC addr 1 if ASF is using it. */
6468 if ((addr0_high
!= addr1_high
|| addr0_low
!= addr1_low
) &&
6469 !(addr1_high
== 0 && addr1_low
== 0))
6472 spin_lock_bh(&tp
->lock
);
6473 __tg3_set_mac_addr(tp
, skip_mac_1
);
6474 spin_unlock_bh(&tp
->lock
);
6479 /* tp->lock is held. */
6480 static void tg3_set_bdinfo(struct tg3
*tp
, u32 bdinfo_addr
,
6481 dma_addr_t mapping
, u32 maxlen_flags
,
6485 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
6486 ((u64
) mapping
>> 32));
6488 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
),
6489 ((u64
) mapping
& 0xffffffff));
6491 (bdinfo_addr
+ TG3_BDINFO_MAXLEN_FLAGS
),
6494 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
6496 (bdinfo_addr
+ TG3_BDINFO_NIC_ADDR
),
6500 static void __tg3_set_rx_mode(struct net_device
*);
6501 static void __tg3_set_coalesce(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
6503 tw32(HOSTCC_RXCOL_TICKS
, ec
->rx_coalesce_usecs
);
6504 tw32(HOSTCC_TXCOL_TICKS
, ec
->tx_coalesce_usecs
);
6505 tw32(HOSTCC_RXMAX_FRAMES
, ec
->rx_max_coalesced_frames
);
6506 tw32(HOSTCC_TXMAX_FRAMES
, ec
->tx_max_coalesced_frames
);
6507 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6508 tw32(HOSTCC_RXCOAL_TICK_INT
, ec
->rx_coalesce_usecs_irq
);
6509 tw32(HOSTCC_TXCOAL_TICK_INT
, ec
->tx_coalesce_usecs_irq
);
6511 tw32(HOSTCC_RXCOAL_MAXF_INT
, ec
->rx_max_coalesced_frames_irq
);
6512 tw32(HOSTCC_TXCOAL_MAXF_INT
, ec
->tx_max_coalesced_frames_irq
);
6513 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6514 u32 val
= ec
->stats_block_coalesce_usecs
;
6516 if (!netif_carrier_ok(tp
->dev
))
6519 tw32(HOSTCC_STAT_COAL_TICKS
, val
);
6523 /* tp->lock is held. */
6524 static int tg3_reset_hw(struct tg3
*tp
, int reset_phy
)
6526 u32 val
, rdmac_mode
;
6529 tg3_disable_ints(tp
);
6533 tg3_write_sig_pre_reset(tp
, RESET_KIND_INIT
);
6535 if (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) {
6536 tg3_abort_hw(tp
, 1);
6540 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
))
6543 err
= tg3_chip_reset(tp
);
6547 tg3_write_sig_legacy(tp
, RESET_KIND_INIT
);
6549 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
6550 val
= tr32(TG3_CPMU_CTRL
);
6551 val
&= ~(CPMU_CTRL_LINK_AWARE_MODE
| CPMU_CTRL_LINK_IDLE_MODE
);
6552 tw32(TG3_CPMU_CTRL
, val
);
6554 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
6555 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
6556 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
6557 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
6559 val
= tr32(TG3_CPMU_LNK_AWARE_PWRMD
);
6560 val
&= ~CPMU_LNK_AWARE_MACCLK_MASK
;
6561 val
|= CPMU_LNK_AWARE_MACCLK_6_25
;
6562 tw32(TG3_CPMU_LNK_AWARE_PWRMD
, val
);
6564 val
= tr32(TG3_CPMU_HST_ACC
);
6565 val
&= ~CPMU_HST_ACC_MACCLK_MASK
;
6566 val
|= CPMU_HST_ACC_MACCLK_6_25
;
6567 tw32(TG3_CPMU_HST_ACC
, val
);
6570 /* This works around an issue with Athlon chipsets on
6571 * B3 tigon3 silicon. This bit has no effect on any
6572 * other revision. But do not set this on PCI Express
6573 * chips and don't even touch the clocks if the CPMU is present.
6575 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)) {
6576 if (!(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
6577 tp
->pci_clock_ctrl
|= CLOCK_CTRL_DELAY_PCI_GRANT
;
6578 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
6581 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
6582 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
6583 val
= tr32(TG3PCI_PCISTATE
);
6584 val
|= PCISTATE_RETRY_SAME_DMA
;
6585 tw32(TG3PCI_PCISTATE
, val
);
6588 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
6589 /* Allow reads and writes to the
6590 * APE register and memory space.
6592 val
= tr32(TG3PCI_PCISTATE
);
6593 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
6594 PCISTATE_ALLOW_APE_SHMEM_WR
;
6595 tw32(TG3PCI_PCISTATE
, val
);
6598 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_BX
) {
6599 /* Enable some hw fixes. */
6600 val
= tr32(TG3PCI_MSI_DATA
);
6601 val
|= (1 << 26) | (1 << 28) | (1 << 29);
6602 tw32(TG3PCI_MSI_DATA
, val
);
6605 /* Descriptor ring init may make accesses to the
6606 * NIC SRAM area to setup the TX descriptors, so we
6607 * can only do this after the hardware has been
6608 * successfully reset.
6610 err
= tg3_init_rings(tp
);
6614 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
&&
6615 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5761
) {
6616 /* This value is determined during the probe time DMA
6617 * engine test, tg3_test_dma.
6619 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
6622 tp
->grc_mode
&= ~(GRC_MODE_HOST_SENDBDS
|
6623 GRC_MODE_4X_NIC_SEND_RINGS
|
6624 GRC_MODE_NO_TX_PHDR_CSUM
|
6625 GRC_MODE_NO_RX_PHDR_CSUM
);
6626 tp
->grc_mode
|= GRC_MODE_HOST_SENDBDS
;
6628 /* Pseudo-header checksum is done by hardware logic and not
6629 * the offload processers, so make the chip do the pseudo-
6630 * header checksums on receive. For transmit it is more
6631 * convenient to do the pseudo-header checksum in software
6632 * as Linux does that on transmit for us in all cases.
6634 tp
->grc_mode
|= GRC_MODE_NO_TX_PHDR_CSUM
;
6638 (GRC_MODE_IRQ_ON_MAC_ATTN
| GRC_MODE_HOST_STACKUP
));
6640 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6641 val
= tr32(GRC_MISC_CFG
);
6643 val
|= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT
);
6644 tw32(GRC_MISC_CFG
, val
);
6646 /* Initialize MBUF/DESC pool. */
6647 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
6649 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5705
) {
6650 tw32(BUFMGR_MB_POOL_ADDR
, NIC_SRAM_MBUF_POOL_BASE
);
6651 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
6652 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE64
);
6654 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE96
);
6655 tw32(BUFMGR_DMA_DESC_POOL_ADDR
, NIC_SRAM_DMA_DESC_POOL_BASE
);
6656 tw32(BUFMGR_DMA_DESC_POOL_SIZE
, NIC_SRAM_DMA_DESC_POOL_SIZE
);
6658 else if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
6661 fw_len
= tp
->fw_len
;
6662 fw_len
= (fw_len
+ (0x80 - 1)) & ~(0x80 - 1);
6663 tw32(BUFMGR_MB_POOL_ADDR
,
6664 NIC_SRAM_MBUF_POOL_BASE5705
+ fw_len
);
6665 tw32(BUFMGR_MB_POOL_SIZE
,
6666 NIC_SRAM_MBUF_POOL_SIZE5705
- fw_len
- 0xa00);
6669 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
6670 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
6671 tp
->bufmgr_config
.mbuf_read_dma_low_water
);
6672 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
6673 tp
->bufmgr_config
.mbuf_mac_rx_low_water
);
6674 tw32(BUFMGR_MB_HIGH_WATER
,
6675 tp
->bufmgr_config
.mbuf_high_water
);
6677 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
6678 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
);
6679 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
6680 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
);
6681 tw32(BUFMGR_MB_HIGH_WATER
,
6682 tp
->bufmgr_config
.mbuf_high_water_jumbo
);
6684 tw32(BUFMGR_DMA_LOW_WATER
,
6685 tp
->bufmgr_config
.dma_low_water
);
6686 tw32(BUFMGR_DMA_HIGH_WATER
,
6687 tp
->bufmgr_config
.dma_high_water
);
6689 tw32(BUFMGR_MODE
, BUFMGR_MODE_ENABLE
| BUFMGR_MODE_ATTN_ENABLE
);
6690 for (i
= 0; i
< 2000; i
++) {
6691 if (tr32(BUFMGR_MODE
) & BUFMGR_MODE_ENABLE
)
6696 printk(KERN_ERR PFX
"tg3_reset_hw cannot enable BUFMGR for %s.\n",
6701 /* Setup replenish threshold. */
6702 val
= tp
->rx_pending
/ 8;
6705 else if (val
> tp
->rx_std_max_post
)
6706 val
= tp
->rx_std_max_post
;
6707 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6708 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5906_A1
)
6709 tw32(ISO_PKT_TX
, (tr32(ISO_PKT_TX
) & ~0x3) | 0x2);
6711 if (val
> (TG3_RX_INTERNAL_RING_SZ_5906
/ 2))
6712 val
= TG3_RX_INTERNAL_RING_SZ_5906
/ 2;
6715 tw32(RCVBDI_STD_THRESH
, val
);
6717 /* Initialize TG3_BDINFO's at:
6718 * RCVDBDI_STD_BD: standard eth size rx ring
6719 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6720 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6723 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6724 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6725 * ring attribute flags
6726 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6728 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6729 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6731 * The size of each ring is fixed in the firmware, but the location is
6734 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
6735 ((u64
) tp
->rx_std_mapping
>> 32));
6736 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
6737 ((u64
) tp
->rx_std_mapping
& 0xffffffff));
6738 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_NIC_ADDR
,
6739 NIC_SRAM_RX_BUFFER_DESC
);
6741 /* Don't even try to program the JUMBO/MINI buffer descriptor
6744 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
6745 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
6746 RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
);
6748 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
6749 RX_STD_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
);
6751 tw32(RCVDBDI_MINI_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
6752 BDINFO_FLAGS_DISABLED
);
6754 /* Setup replenish threshold. */
6755 tw32(RCVBDI_JUMBO_THRESH
, tp
->rx_jumbo_pending
/ 8);
6757 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
6758 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
6759 ((u64
) tp
->rx_jumbo_mapping
>> 32));
6760 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
6761 ((u64
) tp
->rx_jumbo_mapping
& 0xffffffff));
6762 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
6763 RX_JUMBO_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
);
6764 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_NIC_ADDR
,
6765 NIC_SRAM_RX_JUMBO_BUFFER_DESC
);
6767 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
6768 BDINFO_FLAGS_DISABLED
);
6773 /* There is only one send ring on 5705/5750, no need to explicitly
6774 * disable the others.
6776 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6777 /* Clear out send RCB ring in SRAM. */
6778 for (i
= NIC_SRAM_SEND_RCB
; i
< NIC_SRAM_RCV_RET_RCB
; i
+= TG3_BDINFO_SIZE
)
6779 tg3_write_mem(tp
, i
+ TG3_BDINFO_MAXLEN_FLAGS
,
6780 BDINFO_FLAGS_DISABLED
);
6785 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
, 0);
6786 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0
+ TG3_64BIT_REG_LOW
, 0);
6788 tg3_set_bdinfo(tp
, NIC_SRAM_SEND_RCB
,
6789 tp
->tx_desc_mapping
,
6790 (TG3_TX_RING_SIZE
<<
6791 BDINFO_FLAGS_MAXLEN_SHIFT
),
6792 NIC_SRAM_TX_BUFFER_DESC
);
6794 /* There is only one receive return ring on 5705/5750, no need
6795 * to explicitly disable the others.
6797 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6798 for (i
= NIC_SRAM_RCV_RET_RCB
; i
< NIC_SRAM_STATS_BLK
;
6799 i
+= TG3_BDINFO_SIZE
) {
6800 tg3_write_mem(tp
, i
+ TG3_BDINFO_MAXLEN_FLAGS
,
6801 BDINFO_FLAGS_DISABLED
);
6806 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
, 0);
6808 tg3_set_bdinfo(tp
, NIC_SRAM_RCV_RET_RCB
,
6810 (TG3_RX_RCB_RING_SIZE(tp
) <<
6811 BDINFO_FLAGS_MAXLEN_SHIFT
),
6814 tp
->rx_std_ptr
= tp
->rx_pending
;
6815 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
,
6818 tp
->rx_jumbo_ptr
= (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) ?
6819 tp
->rx_jumbo_pending
: 0;
6820 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX
+ TG3_64BIT_REG_LOW
,
6823 /* Initialize MAC address and backoff seed. */
6824 __tg3_set_mac_addr(tp
, 0);
6826 /* MTU + ethernet header + FCS + optional VLAN tag */
6827 tw32(MAC_RX_MTU_SIZE
, tp
->dev
->mtu
+ ETH_HLEN
+ 8);
6829 /* The slot time is changed by tg3_setup_phy if we
6830 * run at gigabit with half duplex.
6832 tw32(MAC_TX_LENGTHS
,
6833 (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
6834 (6 << TX_LENGTHS_IPG_SHIFT
) |
6835 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
));
6837 /* Receive rules. */
6838 tw32(MAC_RCV_RULE_CFG
, RCV_RULE_CFG_DEFAULT_CLASS
);
6839 tw32(RCVLPC_CONFIG
, 0x0181);
6841 /* Calculate RDMAC_MODE setting early, we need it to determine
6842 * the RCVLPC_STATE_ENABLE mask.
6844 rdmac_mode
= (RDMAC_MODE_ENABLE
| RDMAC_MODE_TGTABORT_ENAB
|
6845 RDMAC_MODE_MSTABORT_ENAB
| RDMAC_MODE_PARITYERR_ENAB
|
6846 RDMAC_MODE_ADDROFLOW_ENAB
| RDMAC_MODE_FIFOOFLOW_ENAB
|
6847 RDMAC_MODE_FIFOURUN_ENAB
| RDMAC_MODE_FIFOOREAD_ENAB
|
6848 RDMAC_MODE_LNGREAD_ENAB
);
6850 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
6851 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
6852 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
6853 rdmac_mode
|= RDMAC_MODE_BD_SBD_CRPT_ENAB
|
6854 RDMAC_MODE_MBUF_RBD_CRPT_ENAB
|
6855 RDMAC_MODE_MBUF_SBD_CRPT_ENAB
;
6857 /* If statement applies to 5705 and 5750 PCI devices only */
6858 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
6859 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
6860 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)) {
6861 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
&&
6862 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
6863 rdmac_mode
|= RDMAC_MODE_FIFO_SIZE_128
;
6864 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
6865 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
)) {
6866 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
6870 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
6871 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
6873 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
6874 rdmac_mode
|= RDMAC_MODE_IPV4_LSO_EN
;
6876 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
6877 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
6878 rdmac_mode
|= RDMAC_MODE_IPV6_LSO_EN
;
6880 /* Receive/send statistics. */
6881 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
6882 val
= tr32(RCVLPC_STATS_ENABLE
);
6883 val
&= ~RCVLPC_STATSENAB_DACK_FIX
;
6884 tw32(RCVLPC_STATS_ENABLE
, val
);
6885 } else if ((rdmac_mode
& RDMAC_MODE_FIFO_SIZE_128
) &&
6886 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
6887 val
= tr32(RCVLPC_STATS_ENABLE
);
6888 val
&= ~RCVLPC_STATSENAB_LNGBRST_RFIX
;
6889 tw32(RCVLPC_STATS_ENABLE
, val
);
6891 tw32(RCVLPC_STATS_ENABLE
, 0xffffff);
6893 tw32(RCVLPC_STATSCTRL
, RCVLPC_STATSCTRL_ENABLE
);
6894 tw32(SNDDATAI_STATSENAB
, 0xffffff);
6895 tw32(SNDDATAI_STATSCTRL
,
6896 (SNDDATAI_SCTRL_ENABLE
|
6897 SNDDATAI_SCTRL_FASTUPD
));
6899 /* Setup host coalescing engine. */
6900 tw32(HOSTCC_MODE
, 0);
6901 for (i
= 0; i
< 2000; i
++) {
6902 if (!(tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
))
6907 __tg3_set_coalesce(tp
, &tp
->coal
);
6909 /* set status block DMA address */
6910 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
6911 ((u64
) tp
->status_mapping
>> 32));
6912 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
6913 ((u64
) tp
->status_mapping
& 0xffffffff));
6915 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6916 /* Status/statistics block address. See tg3_timer,
6917 * the tg3_periodic_fetch_stats call there, and
6918 * tg3_get_stats to see how this works for 5705/5750 chips.
6920 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
6921 ((u64
) tp
->stats_mapping
>> 32));
6922 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
6923 ((u64
) tp
->stats_mapping
& 0xffffffff));
6924 tw32(HOSTCC_STATS_BLK_NIC_ADDR
, NIC_SRAM_STATS_BLK
);
6925 tw32(HOSTCC_STATUS_BLK_NIC_ADDR
, NIC_SRAM_STATUS_BLK
);
6928 tw32(HOSTCC_MODE
, HOSTCC_MODE_ENABLE
| tp
->coalesce_mode
);
6930 tw32(RCVCC_MODE
, RCVCC_MODE_ENABLE
| RCVCC_MODE_ATTN_ENABLE
);
6931 tw32(RCVLPC_MODE
, RCVLPC_MODE_ENABLE
);
6932 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
6933 tw32(RCVLSC_MODE
, RCVLSC_MODE_ENABLE
| RCVLSC_MODE_ATTN_ENABLE
);
6935 /* Clear statistics/status block in chip, and status block in ram. */
6936 for (i
= NIC_SRAM_STATS_BLK
;
6937 i
< NIC_SRAM_STATUS_BLK
+ TG3_HW_STATUS_SIZE
;
6939 tg3_write_mem(tp
, i
, 0);
6942 memset(tp
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6944 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
6945 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
6946 /* reset to prevent losing 1st rx packet intermittently */
6947 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
6951 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
6952 tp
->mac_mode
&= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
6955 tp
->mac_mode
|= MAC_MODE_TXSTAT_ENABLE
| MAC_MODE_RXSTAT_ENABLE
|
6956 MAC_MODE_TDE_ENABLE
| MAC_MODE_RDE_ENABLE
| MAC_MODE_FHDE_ENABLE
;
6957 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
6958 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
6959 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
)
6960 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
6961 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_RXSTAT_CLEAR
| MAC_MODE_TXSTAT_CLEAR
);
6964 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6965 * If TG3_FLG2_IS_NIC is zero, we should read the
6966 * register to preserve the GPIO settings for LOMs. The GPIOs,
6967 * whether used as inputs or outputs, are set by boot code after
6970 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)) {
6973 gpio_mask
= GRC_LCLCTRL_GPIO_OE0
| GRC_LCLCTRL_GPIO_OE1
|
6974 GRC_LCLCTRL_GPIO_OE2
| GRC_LCLCTRL_GPIO_OUTPUT0
|
6975 GRC_LCLCTRL_GPIO_OUTPUT1
| GRC_LCLCTRL_GPIO_OUTPUT2
;
6977 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
6978 gpio_mask
|= GRC_LCLCTRL_GPIO_OE3
|
6979 GRC_LCLCTRL_GPIO_OUTPUT3
;
6981 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
6982 gpio_mask
|= GRC_LCLCTRL_GPIO_UART_SEL
;
6984 tp
->grc_local_ctrl
&= ~gpio_mask
;
6985 tp
->grc_local_ctrl
|= tr32(GRC_LOCAL_CTRL
) & gpio_mask
;
6987 /* GPIO1 must be driven high for eeprom write protect */
6988 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
)
6989 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
6990 GRC_LCLCTRL_GPIO_OUTPUT1
);
6992 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
6995 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0);
6998 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6999 tw32_f(DMAC_MODE
, DMAC_MODE_ENABLE
);
7003 val
= (WDMAC_MODE_ENABLE
| WDMAC_MODE_TGTABORT_ENAB
|
7004 WDMAC_MODE_MSTABORT_ENAB
| WDMAC_MODE_PARITYERR_ENAB
|
7005 WDMAC_MODE_ADDROFLOW_ENAB
| WDMAC_MODE_FIFOOFLOW_ENAB
|
7006 WDMAC_MODE_FIFOURUN_ENAB
| WDMAC_MODE_FIFOOREAD_ENAB
|
7007 WDMAC_MODE_LNGREAD_ENAB
);
7009 /* If statement applies to 5705 and 5750 PCI devices only */
7010 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
7011 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
7012 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) {
7013 if ((tp
->tg3_flags
& TG3_FLG2_TSO_CAPABLE
) &&
7014 (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
||
7015 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A2
)) {
7017 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
7018 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
7019 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
7020 val
|= WDMAC_MODE_RX_ACCEL
;
7024 /* Enable host coalescing bug fix */
7025 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
7026 val
|= WDMAC_MODE_STATUS_TAG_FIX
;
7028 tw32_f(WDMAC_MODE
, val
);
7031 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
7034 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
7036 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
) {
7037 pcix_cmd
&= ~PCI_X_CMD_MAX_READ
;
7038 pcix_cmd
|= PCI_X_CMD_READ_2K
;
7039 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
7040 pcix_cmd
&= ~(PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
);
7041 pcix_cmd
|= PCI_X_CMD_READ_2K
;
7043 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
7047 tw32_f(RDMAC_MODE
, rdmac_mode
);
7050 tw32(RCVDCC_MODE
, RCVDCC_MODE_ENABLE
| RCVDCC_MODE_ATTN_ENABLE
);
7051 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7052 tw32(MBFREE_MODE
, MBFREE_MODE_ENABLE
);
7054 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
7056 SNDDATAC_MODE_ENABLE
| SNDDATAC_MODE_CDELAY
);
7058 tw32(SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
);
7060 tw32(SNDBDC_MODE
, SNDBDC_MODE_ENABLE
| SNDBDC_MODE_ATTN_ENABLE
);
7061 tw32(RCVBDI_MODE
, RCVBDI_MODE_ENABLE
| RCVBDI_MODE_RCB_ATTN_ENAB
);
7062 tw32(RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
| RCVDBDI_MODE_INV_RING_SZ
);
7063 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
);
7064 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7065 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
| 0x8);
7066 tw32(SNDBDI_MODE
, SNDBDI_MODE_ENABLE
| SNDBDI_MODE_ATTN_ENABLE
);
7067 tw32(SNDBDS_MODE
, SNDBDS_MODE_ENABLE
| SNDBDS_MODE_ATTN_ENABLE
);
7069 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
7070 err
= tg3_load_5701_a0_firmware_fix(tp
);
7075 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
7076 err
= tg3_load_tso_firmware(tp
);
7081 tp
->tx_mode
= TX_MODE_ENABLE
;
7082 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
7085 tp
->rx_mode
= RX_MODE_ENABLE
;
7086 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
7087 tp
->rx_mode
|= RX_MODE_IPV6_CSUM_ENABLE
;
7089 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
7092 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
7094 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
7095 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
7096 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
7099 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
7102 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
7103 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) &&
7104 !(tp
->tg3_flags2
& TG3_FLG2_SERDES_PREEMPHASIS
)) {
7105 /* Set drive transmission level to 1.2V */
7106 /* only if the signal pre-emphasis bit is not set */
7107 val
= tr32(MAC_SERDES_CFG
);
7110 tw32(MAC_SERDES_CFG
, val
);
7112 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
)
7113 tw32(MAC_SERDES_CFG
, 0x616000);
7116 /* Prevent chip from dropping frames when flow control
7119 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME
, 2);
7121 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
7122 (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
7123 /* Use hardware link auto-negotiation */
7124 tp
->tg3_flags2
|= TG3_FLG2_HW_AUTONEG
;
7127 if ((tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) &&
7128 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
7131 tmp
= tr32(SERDES_RX_CTRL
);
7132 tw32(SERDES_RX_CTRL
, tmp
| SERDES_RX_SIG_DETECT
);
7133 tp
->grc_local_ctrl
&= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT
;
7134 tp
->grc_local_ctrl
|= GRC_LCLCTRL_USE_SIG_DETECT
;
7135 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
7138 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
7139 if (tp
->link_config
.phy_is_low_power
) {
7140 tp
->link_config
.phy_is_low_power
= 0;
7141 tp
->link_config
.speed
= tp
->link_config
.orig_speed
;
7142 tp
->link_config
.duplex
= tp
->link_config
.orig_duplex
;
7143 tp
->link_config
.autoneg
= tp
->link_config
.orig_autoneg
;
7146 err
= tg3_setup_phy(tp
, 0);
7150 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
7151 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5906
) {
7154 /* Clear CRC stats. */
7155 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &tmp
)) {
7156 tg3_writephy(tp
, MII_TG3_TEST1
,
7157 tmp
| MII_TG3_TEST1_CRC_EN
);
7158 tg3_readphy(tp
, 0x14, &tmp
);
7163 __tg3_set_rx_mode(tp
->dev
);
7165 /* Initialize receive rules. */
7166 tw32(MAC_RCV_RULE_0
, 0xc2000000 & RCV_RULE_DISABLE_MASK
);
7167 tw32(MAC_RCV_VALUE_0
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
7168 tw32(MAC_RCV_RULE_1
, 0x86000004 & RCV_RULE_DISABLE_MASK
);
7169 tw32(MAC_RCV_VALUE_1
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
7171 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
7172 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
7176 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
7180 tw32(MAC_RCV_RULE_15
, 0); tw32(MAC_RCV_VALUE_15
, 0);
7182 tw32(MAC_RCV_RULE_14
, 0); tw32(MAC_RCV_VALUE_14
, 0);
7184 tw32(MAC_RCV_RULE_13
, 0); tw32(MAC_RCV_VALUE_13
, 0);
7186 tw32(MAC_RCV_RULE_12
, 0); tw32(MAC_RCV_VALUE_12
, 0);
7188 tw32(MAC_RCV_RULE_11
, 0); tw32(MAC_RCV_VALUE_11
, 0);
7190 tw32(MAC_RCV_RULE_10
, 0); tw32(MAC_RCV_VALUE_10
, 0);
7192 tw32(MAC_RCV_RULE_9
, 0); tw32(MAC_RCV_VALUE_9
, 0);
7194 tw32(MAC_RCV_RULE_8
, 0); tw32(MAC_RCV_VALUE_8
, 0);
7196 tw32(MAC_RCV_RULE_7
, 0); tw32(MAC_RCV_VALUE_7
, 0);
7198 tw32(MAC_RCV_RULE_6
, 0); tw32(MAC_RCV_VALUE_6
, 0);
7200 tw32(MAC_RCV_RULE_5
, 0); tw32(MAC_RCV_VALUE_5
, 0);
7202 tw32(MAC_RCV_RULE_4
, 0); tw32(MAC_RCV_VALUE_4
, 0);
7204 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7206 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7214 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
7215 /* Write our heartbeat update interval to APE. */
7216 tg3_ape_write32(tp
, TG3_APE_HOST_HEARTBEAT_INT_MS
,
7217 APE_HOST_HEARTBEAT_INT_DISABLE
);
7219 tg3_write_sig_post_reset(tp
, RESET_KIND_INIT
);
7224 /* Called at device open time to get the chip ready for
7225 * packet processing. Invoked with tp->lock held.
7227 static int tg3_init_hw(struct tg3
*tp
, int reset_phy
)
7229 tg3_switch_clocks(tp
);
7231 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
7233 return tg3_reset_hw(tp
, reset_phy
);
7236 #define TG3_STAT_ADD32(PSTAT, REG) \
7237 do { u32 __val = tr32(REG); \
7238 (PSTAT)->low += __val; \
7239 if ((PSTAT)->low < __val) \
7240 (PSTAT)->high += 1; \
7243 static void tg3_periodic_fetch_stats(struct tg3
*tp
)
7245 struct tg3_hw_stats
*sp
= tp
->hw_stats
;
7247 if (!netif_carrier_ok(tp
->dev
))
7250 TG3_STAT_ADD32(&sp
->tx_octets
, MAC_TX_STATS_OCTETS
);
7251 TG3_STAT_ADD32(&sp
->tx_collisions
, MAC_TX_STATS_COLLISIONS
);
7252 TG3_STAT_ADD32(&sp
->tx_xon_sent
, MAC_TX_STATS_XON_SENT
);
7253 TG3_STAT_ADD32(&sp
->tx_xoff_sent
, MAC_TX_STATS_XOFF_SENT
);
7254 TG3_STAT_ADD32(&sp
->tx_mac_errors
, MAC_TX_STATS_MAC_ERRORS
);
7255 TG3_STAT_ADD32(&sp
->tx_single_collisions
, MAC_TX_STATS_SINGLE_COLLISIONS
);
7256 TG3_STAT_ADD32(&sp
->tx_mult_collisions
, MAC_TX_STATS_MULT_COLLISIONS
);
7257 TG3_STAT_ADD32(&sp
->tx_deferred
, MAC_TX_STATS_DEFERRED
);
7258 TG3_STAT_ADD32(&sp
->tx_excessive_collisions
, MAC_TX_STATS_EXCESSIVE_COL
);
7259 TG3_STAT_ADD32(&sp
->tx_late_collisions
, MAC_TX_STATS_LATE_COL
);
7260 TG3_STAT_ADD32(&sp
->tx_ucast_packets
, MAC_TX_STATS_UCAST
);
7261 TG3_STAT_ADD32(&sp
->tx_mcast_packets
, MAC_TX_STATS_MCAST
);
7262 TG3_STAT_ADD32(&sp
->tx_bcast_packets
, MAC_TX_STATS_BCAST
);
7264 TG3_STAT_ADD32(&sp
->rx_octets
, MAC_RX_STATS_OCTETS
);
7265 TG3_STAT_ADD32(&sp
->rx_fragments
, MAC_RX_STATS_FRAGMENTS
);
7266 TG3_STAT_ADD32(&sp
->rx_ucast_packets
, MAC_RX_STATS_UCAST
);
7267 TG3_STAT_ADD32(&sp
->rx_mcast_packets
, MAC_RX_STATS_MCAST
);
7268 TG3_STAT_ADD32(&sp
->rx_bcast_packets
, MAC_RX_STATS_BCAST
);
7269 TG3_STAT_ADD32(&sp
->rx_fcs_errors
, MAC_RX_STATS_FCS_ERRORS
);
7270 TG3_STAT_ADD32(&sp
->rx_align_errors
, MAC_RX_STATS_ALIGN_ERRORS
);
7271 TG3_STAT_ADD32(&sp
->rx_xon_pause_rcvd
, MAC_RX_STATS_XON_PAUSE_RECVD
);
7272 TG3_STAT_ADD32(&sp
->rx_xoff_pause_rcvd
, MAC_RX_STATS_XOFF_PAUSE_RECVD
);
7273 TG3_STAT_ADD32(&sp
->rx_mac_ctrl_rcvd
, MAC_RX_STATS_MAC_CTRL_RECVD
);
7274 TG3_STAT_ADD32(&sp
->rx_xoff_entered
, MAC_RX_STATS_XOFF_ENTERED
);
7275 TG3_STAT_ADD32(&sp
->rx_frame_too_long_errors
, MAC_RX_STATS_FRAME_TOO_LONG
);
7276 TG3_STAT_ADD32(&sp
->rx_jabbers
, MAC_RX_STATS_JABBERS
);
7277 TG3_STAT_ADD32(&sp
->rx_undersize_packets
, MAC_RX_STATS_UNDERSIZE
);
7279 TG3_STAT_ADD32(&sp
->rxbds_empty
, RCVLPC_NO_RCV_BD_CNT
);
7280 TG3_STAT_ADD32(&sp
->rx_discards
, RCVLPC_IN_DISCARDS_CNT
);
7281 TG3_STAT_ADD32(&sp
->rx_errors
, RCVLPC_IN_ERRORS_CNT
);
7284 static void tg3_timer(unsigned long __opaque
)
7286 struct tg3
*tp
= (struct tg3
*) __opaque
;
7291 spin_lock(&tp
->lock
);
7293 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
7294 /* All of this garbage is because when using non-tagged
7295 * IRQ status the mailbox/status_block protocol the chip
7296 * uses with the cpu is race prone.
7298 if (tp
->hw_status
->status
& SD_STATUS_UPDATED
) {
7299 tw32(GRC_LOCAL_CTRL
,
7300 tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
7302 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
7303 (HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
));
7306 if (!(tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
7307 tp
->tg3_flags2
|= TG3_FLG2_RESTART_TIMER
;
7308 spin_unlock(&tp
->lock
);
7309 schedule_work(&tp
->reset_task
);
7314 /* This part only runs once per second. */
7315 if (!--tp
->timer_counter
) {
7316 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
7317 tg3_periodic_fetch_stats(tp
);
7319 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
7323 mac_stat
= tr32(MAC_STATUS
);
7326 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) {
7327 if (mac_stat
& MAC_STATUS_MI_INTERRUPT
)
7329 } else if (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)
7333 tg3_setup_phy(tp
, 0);
7334 } else if (tp
->tg3_flags
& TG3_FLAG_POLL_SERDES
) {
7335 u32 mac_stat
= tr32(MAC_STATUS
);
7338 if (netif_carrier_ok(tp
->dev
) &&
7339 (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)) {
7342 if (! netif_carrier_ok(tp
->dev
) &&
7343 (mac_stat
& (MAC_STATUS_PCS_SYNCED
|
7344 MAC_STATUS_SIGNAL_DET
))) {
7348 if (!tp
->serdes_counter
) {
7351 ~MAC_MODE_PORT_MODE_MASK
));
7353 tw32_f(MAC_MODE
, tp
->mac_mode
);
7356 tg3_setup_phy(tp
, 0);
7358 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
7359 tg3_serdes_parallel_detect(tp
);
7361 tp
->timer_counter
= tp
->timer_multiplier
;
7364 /* Heartbeat is only sent once every 2 seconds.
7366 * The heartbeat is to tell the ASF firmware that the host
7367 * driver is still alive. In the event that the OS crashes,
7368 * ASF needs to reset the hardware to free up the FIFO space
7369 * that may be filled with rx packets destined for the host.
7370 * If the FIFO is full, ASF will no longer function properly.
7372 * Unintended resets have been reported on real time kernels
7373 * where the timer doesn't run on time. Netpoll will also have
7376 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7377 * to check the ring condition when the heartbeat is expiring
7378 * before doing the reset. This will prevent most unintended
7381 if (!--tp
->asf_counter
) {
7382 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
7383 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
7384 tg3_wait_for_event_ack(tp
);
7386 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
,
7387 FWCMD_NICDRV_ALIVE3
);
7388 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 4);
7389 /* 5 seconds timeout */
7390 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, 5);
7392 tg3_generate_fw_event(tp
);
7394 tp
->asf_counter
= tp
->asf_multiplier
;
7397 spin_unlock(&tp
->lock
);
7400 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
7401 add_timer(&tp
->timer
);
7404 static int tg3_request_irq(struct tg3
*tp
)
7407 unsigned long flags
;
7408 struct net_device
*dev
= tp
->dev
;
7410 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7412 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
7414 flags
= IRQF_SAMPLE_RANDOM
;
7417 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
7418 fn
= tg3_interrupt_tagged
;
7419 flags
= IRQF_SHARED
| IRQF_SAMPLE_RANDOM
;
7421 return (request_irq(tp
->pdev
->irq
, fn
, flags
, dev
->name
, dev
));
7424 static int tg3_test_interrupt(struct tg3
*tp
)
7426 struct net_device
*dev
= tp
->dev
;
7427 int err
, i
, intr_ok
= 0;
7429 if (!netif_running(dev
))
7432 tg3_disable_ints(tp
);
7434 free_irq(tp
->pdev
->irq
, dev
);
7436 err
= request_irq(tp
->pdev
->irq
, tg3_test_isr
,
7437 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
, dev
->name
, dev
);
7441 tp
->hw_status
->status
&= ~SD_STATUS_UPDATED
;
7442 tg3_enable_ints(tp
);
7444 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
7447 for (i
= 0; i
< 5; i
++) {
7448 u32 int_mbox
, misc_host_ctrl
;
7450 int_mbox
= tr32_mailbox(MAILBOX_INTERRUPT_0
+
7452 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
7454 if ((int_mbox
!= 0) ||
7455 (misc_host_ctrl
& MISC_HOST_CTRL_MASK_PCI_INT
)) {
7463 tg3_disable_ints(tp
);
7465 free_irq(tp
->pdev
->irq
, dev
);
7467 err
= tg3_request_irq(tp
);
7478 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7479 * successfully restored
7481 static int tg3_test_msi(struct tg3
*tp
)
7483 struct net_device
*dev
= tp
->dev
;
7487 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSI
))
7490 /* Turn off SERR reporting in case MSI terminates with Master
7493 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
7494 pci_write_config_word(tp
->pdev
, PCI_COMMAND
,
7495 pci_cmd
& ~PCI_COMMAND_SERR
);
7497 err
= tg3_test_interrupt(tp
);
7499 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
7504 /* other failures */
7508 /* MSI test failed, go back to INTx mode */
7509 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
7510 "switching to INTx mode. Please report this failure to "
7511 "the PCI maintainer and include system chipset information.\n",
7514 free_irq(tp
->pdev
->irq
, dev
);
7515 pci_disable_msi(tp
->pdev
);
7517 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
7519 err
= tg3_request_irq(tp
);
7523 /* Need to reset the chip because the MSI cycle may have terminated
7524 * with Master Abort.
7526 tg3_full_lock(tp
, 1);
7528 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
7529 err
= tg3_init_hw(tp
, 1);
7531 tg3_full_unlock(tp
);
7534 free_irq(tp
->pdev
->irq
, dev
);
7539 static int tg3_request_firmware(struct tg3
*tp
)
7541 const __be32
*fw_data
;
7543 if (request_firmware(&tp
->fw
, tp
->fw_needed
, &tp
->pdev
->dev
)) {
7544 printk(KERN_ERR
"%s: Failed to load firmware \"%s\"\n",
7545 tp
->dev
->name
, tp
->fw_needed
);
7549 fw_data
= (void *)tp
->fw
->data
;
7551 /* Firmware blob starts with version numbers, followed by
7552 * start address and _full_ length including BSS sections
7553 * (which must be longer than the actual data, of course
7556 tp
->fw_len
= be32_to_cpu(fw_data
[2]); /* includes bss */
7557 if (tp
->fw_len
< (tp
->fw
->size
- 12)) {
7558 printk(KERN_ERR
"%s: bogus length %d in \"%s\"\n",
7559 tp
->dev
->name
, tp
->fw_len
, tp
->fw_needed
);
7560 release_firmware(tp
->fw
);
7565 /* We no longer need firmware; we have it. */
7566 tp
->fw_needed
= NULL
;
7570 static int tg3_open(struct net_device
*dev
)
7572 struct tg3
*tp
= netdev_priv(dev
);
7575 if (tp
->fw_needed
) {
7576 err
= tg3_request_firmware(tp
);
7577 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
7581 printk(KERN_WARNING
"%s: TSO capability disabled.\n",
7583 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
7584 } else if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
7585 printk(KERN_NOTICE
"%s: TSO capability restored.\n",
7587 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
7591 netif_carrier_off(tp
->dev
);
7593 err
= tg3_set_power_state(tp
, PCI_D0
);
7597 tg3_full_lock(tp
, 0);
7599 tg3_disable_ints(tp
);
7600 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
7602 tg3_full_unlock(tp
);
7604 /* The placement of this call is tied
7605 * to the setup and use of Host TX descriptors.
7607 err
= tg3_alloc_consistent(tp
);
7611 if (tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI
) {
7612 /* All MSI supporting chips should support tagged
7613 * status. Assert that this is the case.
7615 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
7616 printk(KERN_WARNING PFX
"%s: MSI without TAGGED? "
7617 "Not using MSI.\n", tp
->dev
->name
);
7618 } else if (pci_enable_msi(tp
->pdev
) == 0) {
7621 msi_mode
= tr32(MSGINT_MODE
);
7622 tw32(MSGINT_MODE
, msi_mode
| MSGINT_MODE_ENABLE
);
7623 tp
->tg3_flags2
|= TG3_FLG2_USING_MSI
;
7626 err
= tg3_request_irq(tp
);
7629 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7630 pci_disable_msi(tp
->pdev
);
7631 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
7633 tg3_free_consistent(tp
);
7637 napi_enable(&tp
->napi
);
7639 tg3_full_lock(tp
, 0);
7641 err
= tg3_init_hw(tp
, 1);
7643 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
7646 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
7647 tp
->timer_offset
= HZ
;
7649 tp
->timer_offset
= HZ
/ 10;
7651 BUG_ON(tp
->timer_offset
> HZ
);
7652 tp
->timer_counter
= tp
->timer_multiplier
=
7653 (HZ
/ tp
->timer_offset
);
7654 tp
->asf_counter
= tp
->asf_multiplier
=
7655 ((HZ
/ tp
->timer_offset
) * 2);
7657 init_timer(&tp
->timer
);
7658 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
7659 tp
->timer
.data
= (unsigned long) tp
;
7660 tp
->timer
.function
= tg3_timer
;
7663 tg3_full_unlock(tp
);
7666 napi_disable(&tp
->napi
);
7667 free_irq(tp
->pdev
->irq
, dev
);
7668 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7669 pci_disable_msi(tp
->pdev
);
7670 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
7672 tg3_free_consistent(tp
);
7676 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7677 err
= tg3_test_msi(tp
);
7680 tg3_full_lock(tp
, 0);
7682 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7683 pci_disable_msi(tp
->pdev
);
7684 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
7686 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
7688 tg3_free_consistent(tp
);
7690 tg3_full_unlock(tp
);
7692 napi_disable(&tp
->napi
);
7697 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7698 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
) {
7699 u32 val
= tr32(PCIE_TRANSACTION_CFG
);
7701 tw32(PCIE_TRANSACTION_CFG
,
7702 val
| PCIE_TRANS_CFG_1SHOT_MSI
);
7709 tg3_full_lock(tp
, 0);
7711 add_timer(&tp
->timer
);
7712 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
7713 tg3_enable_ints(tp
);
7715 tg3_full_unlock(tp
);
7717 netif_start_queue(dev
);
7723 /*static*/ void tg3_dump_state(struct tg3
*tp
)
7725 u32 val32
, val32_2
, val32_3
, val32_4
, val32_5
;
7729 pci_read_config_word(tp
->pdev
, PCI_STATUS
, &val16
);
7730 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, &val32
);
7731 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7735 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7736 tr32(MAC_MODE
), tr32(MAC_STATUS
));
7737 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7738 tr32(MAC_EVENT
), tr32(MAC_LED_CTRL
));
7739 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7740 tr32(MAC_TX_MODE
), tr32(MAC_TX_STATUS
));
7741 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7742 tr32(MAC_RX_MODE
), tr32(MAC_RX_STATUS
));
7744 /* Send data initiator control block */
7745 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7746 tr32(SNDDATAI_MODE
), tr32(SNDDATAI_STATUS
));
7747 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7748 tr32(SNDDATAI_STATSCTRL
));
7750 /* Send data completion control block */
7751 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE
));
7753 /* Send BD ring selector block */
7754 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7755 tr32(SNDBDS_MODE
), tr32(SNDBDS_STATUS
));
7757 /* Send BD initiator control block */
7758 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7759 tr32(SNDBDI_MODE
), tr32(SNDBDI_STATUS
));
7761 /* Send BD completion control block */
7762 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE
));
7764 /* Receive list placement control block */
7765 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7766 tr32(RCVLPC_MODE
), tr32(RCVLPC_STATUS
));
7767 printk(" RCVLPC_STATSCTRL[%08x]\n",
7768 tr32(RCVLPC_STATSCTRL
));
7770 /* Receive data and receive BD initiator control block */
7771 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7772 tr32(RCVDBDI_MODE
), tr32(RCVDBDI_STATUS
));
7774 /* Receive data completion control block */
7775 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7778 /* Receive BD initiator control block */
7779 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7780 tr32(RCVBDI_MODE
), tr32(RCVBDI_STATUS
));
7782 /* Receive BD completion control block */
7783 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7784 tr32(RCVCC_MODE
), tr32(RCVCC_STATUS
));
7786 /* Receive list selector control block */
7787 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7788 tr32(RCVLSC_MODE
), tr32(RCVLSC_STATUS
));
7790 /* Mbuf cluster free block */
7791 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7792 tr32(MBFREE_MODE
), tr32(MBFREE_STATUS
));
7794 /* Host coalescing control block */
7795 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7796 tr32(HOSTCC_MODE
), tr32(HOSTCC_STATUS
));
7797 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7798 tr32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
7799 tr32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
));
7800 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7801 tr32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
7802 tr32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
));
7803 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7804 tr32(HOSTCC_STATS_BLK_NIC_ADDR
));
7805 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7806 tr32(HOSTCC_STATUS_BLK_NIC_ADDR
));
7808 /* Memory arbiter control block */
7809 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7810 tr32(MEMARB_MODE
), tr32(MEMARB_STATUS
));
7812 /* Buffer manager control block */
7813 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7814 tr32(BUFMGR_MODE
), tr32(BUFMGR_STATUS
));
7815 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7816 tr32(BUFMGR_MB_POOL_ADDR
), tr32(BUFMGR_MB_POOL_SIZE
));
7817 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7818 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7819 tr32(BUFMGR_DMA_DESC_POOL_ADDR
),
7820 tr32(BUFMGR_DMA_DESC_POOL_SIZE
));
7822 /* Read DMA control block */
7823 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7824 tr32(RDMAC_MODE
), tr32(RDMAC_STATUS
));
7826 /* Write DMA control block */
7827 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7828 tr32(WDMAC_MODE
), tr32(WDMAC_STATUS
));
7830 /* DMA completion block */
7831 printk("DEBUG: DMAC_MODE[%08x]\n",
7835 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7836 tr32(GRC_MODE
), tr32(GRC_MISC_CFG
));
7837 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7838 tr32(GRC_LOCAL_CTRL
));
7841 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7842 tr32(RCVDBDI_JUMBO_BD
+ 0x0),
7843 tr32(RCVDBDI_JUMBO_BD
+ 0x4),
7844 tr32(RCVDBDI_JUMBO_BD
+ 0x8),
7845 tr32(RCVDBDI_JUMBO_BD
+ 0xc));
7846 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7847 tr32(RCVDBDI_STD_BD
+ 0x0),
7848 tr32(RCVDBDI_STD_BD
+ 0x4),
7849 tr32(RCVDBDI_STD_BD
+ 0x8),
7850 tr32(RCVDBDI_STD_BD
+ 0xc));
7851 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7852 tr32(RCVDBDI_MINI_BD
+ 0x0),
7853 tr32(RCVDBDI_MINI_BD
+ 0x4),
7854 tr32(RCVDBDI_MINI_BD
+ 0x8),
7855 tr32(RCVDBDI_MINI_BD
+ 0xc));
7857 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x0, &val32
);
7858 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x4, &val32_2
);
7859 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x8, &val32_3
);
7860 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0xc, &val32_4
);
7861 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7862 val32
, val32_2
, val32_3
, val32_4
);
7864 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x0, &val32
);
7865 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x4, &val32_2
);
7866 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x8, &val32_3
);
7867 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0xc, &val32_4
);
7868 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7869 val32
, val32_2
, val32_3
, val32_4
);
7871 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x0, &val32
);
7872 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x4, &val32_2
);
7873 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x8, &val32_3
);
7874 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0xc, &val32_4
);
7875 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x10, &val32_5
);
7876 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7877 val32
, val32_2
, val32_3
, val32_4
, val32_5
);
7879 /* SW status block */
7880 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7881 tp
->hw_status
->status
,
7882 tp
->hw_status
->status_tag
,
7883 tp
->hw_status
->rx_jumbo_consumer
,
7884 tp
->hw_status
->rx_consumer
,
7885 tp
->hw_status
->rx_mini_consumer
,
7886 tp
->hw_status
->idx
[0].rx_producer
,
7887 tp
->hw_status
->idx
[0].tx_consumer
);
7889 /* SW statistics block */
7890 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7891 ((u32
*)tp
->hw_stats
)[0],
7892 ((u32
*)tp
->hw_stats
)[1],
7893 ((u32
*)tp
->hw_stats
)[2],
7894 ((u32
*)tp
->hw_stats
)[3]);
7897 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7898 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ 0x0),
7899 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ 0x4),
7900 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0
+ 0x0),
7901 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0
+ 0x4));
7903 /* NIC side send descriptors. */
7904 for (i
= 0; i
< 6; i
++) {
7907 txd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_TX_BUFFER_DESC
7908 + (i
* sizeof(struct tg3_tx_buffer_desc
));
7909 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7911 readl(txd
+ 0x0), readl(txd
+ 0x4),
7912 readl(txd
+ 0x8), readl(txd
+ 0xc));
7915 /* NIC side RX descriptors. */
7916 for (i
= 0; i
< 6; i
++) {
7919 rxd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_RX_BUFFER_DESC
7920 + (i
* sizeof(struct tg3_rx_buffer_desc
));
7921 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7923 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
7924 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
7925 rxd
+= (4 * sizeof(u32
));
7926 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7928 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
7929 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
7932 for (i
= 0; i
< 6; i
++) {
7935 rxd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_RX_JUMBO_BUFFER_DESC
7936 + (i
* sizeof(struct tg3_rx_buffer_desc
));
7937 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7939 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
7940 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
7941 rxd
+= (4 * sizeof(u32
));
7942 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7944 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
7945 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
7950 static struct net_device_stats
*tg3_get_stats(struct net_device
*);
7951 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*);
7953 static int tg3_close(struct net_device
*dev
)
7955 struct tg3
*tp
= netdev_priv(dev
);
7957 napi_disable(&tp
->napi
);
7958 cancel_work_sync(&tp
->reset_task
);
7960 netif_stop_queue(dev
);
7962 del_timer_sync(&tp
->timer
);
7964 tg3_full_lock(tp
, 1);
7969 tg3_disable_ints(tp
);
7971 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
7973 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
7975 tg3_full_unlock(tp
);
7977 free_irq(tp
->pdev
->irq
, dev
);
7978 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7979 pci_disable_msi(tp
->pdev
);
7980 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
7983 memcpy(&tp
->net_stats_prev
, tg3_get_stats(tp
->dev
),
7984 sizeof(tp
->net_stats_prev
));
7985 memcpy(&tp
->estats_prev
, tg3_get_estats(tp
),
7986 sizeof(tp
->estats_prev
));
7988 tg3_free_consistent(tp
);
7990 tg3_set_power_state(tp
, PCI_D3hot
);
7992 netif_carrier_off(tp
->dev
);
7997 static inline unsigned long get_stat64(tg3_stat64_t
*val
)
8001 #if (BITS_PER_LONG == 32)
8004 ret
= ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
8009 static inline u64
get_estat64(tg3_stat64_t
*val
)
8011 return ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
8014 static unsigned long calc_crc_errors(struct tg3
*tp
)
8016 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
8018 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
8019 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
8020 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
8023 spin_lock_bh(&tp
->lock
);
8024 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &val
)) {
8025 tg3_writephy(tp
, MII_TG3_TEST1
,
8026 val
| MII_TG3_TEST1_CRC_EN
);
8027 tg3_readphy(tp
, 0x14, &val
);
8030 spin_unlock_bh(&tp
->lock
);
8032 tp
->phy_crc_errors
+= val
;
8034 return tp
->phy_crc_errors
;
8037 return get_stat64(&hw_stats
->rx_fcs_errors
);
8040 #define ESTAT_ADD(member) \
8041 estats->member = old_estats->member + \
8042 get_estat64(&hw_stats->member)
8044 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*tp
)
8046 struct tg3_ethtool_stats
*estats
= &tp
->estats
;
8047 struct tg3_ethtool_stats
*old_estats
= &tp
->estats_prev
;
8048 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
8053 ESTAT_ADD(rx_octets
);
8054 ESTAT_ADD(rx_fragments
);
8055 ESTAT_ADD(rx_ucast_packets
);
8056 ESTAT_ADD(rx_mcast_packets
);
8057 ESTAT_ADD(rx_bcast_packets
);
8058 ESTAT_ADD(rx_fcs_errors
);
8059 ESTAT_ADD(rx_align_errors
);
8060 ESTAT_ADD(rx_xon_pause_rcvd
);
8061 ESTAT_ADD(rx_xoff_pause_rcvd
);
8062 ESTAT_ADD(rx_mac_ctrl_rcvd
);
8063 ESTAT_ADD(rx_xoff_entered
);
8064 ESTAT_ADD(rx_frame_too_long_errors
);
8065 ESTAT_ADD(rx_jabbers
);
8066 ESTAT_ADD(rx_undersize_packets
);
8067 ESTAT_ADD(rx_in_length_errors
);
8068 ESTAT_ADD(rx_out_length_errors
);
8069 ESTAT_ADD(rx_64_or_less_octet_packets
);
8070 ESTAT_ADD(rx_65_to_127_octet_packets
);
8071 ESTAT_ADD(rx_128_to_255_octet_packets
);
8072 ESTAT_ADD(rx_256_to_511_octet_packets
);
8073 ESTAT_ADD(rx_512_to_1023_octet_packets
);
8074 ESTAT_ADD(rx_1024_to_1522_octet_packets
);
8075 ESTAT_ADD(rx_1523_to_2047_octet_packets
);
8076 ESTAT_ADD(rx_2048_to_4095_octet_packets
);
8077 ESTAT_ADD(rx_4096_to_8191_octet_packets
);
8078 ESTAT_ADD(rx_8192_to_9022_octet_packets
);
8080 ESTAT_ADD(tx_octets
);
8081 ESTAT_ADD(tx_collisions
);
8082 ESTAT_ADD(tx_xon_sent
);
8083 ESTAT_ADD(tx_xoff_sent
);
8084 ESTAT_ADD(tx_flow_control
);
8085 ESTAT_ADD(tx_mac_errors
);
8086 ESTAT_ADD(tx_single_collisions
);
8087 ESTAT_ADD(tx_mult_collisions
);
8088 ESTAT_ADD(tx_deferred
);
8089 ESTAT_ADD(tx_excessive_collisions
);
8090 ESTAT_ADD(tx_late_collisions
);
8091 ESTAT_ADD(tx_collide_2times
);
8092 ESTAT_ADD(tx_collide_3times
);
8093 ESTAT_ADD(tx_collide_4times
);
8094 ESTAT_ADD(tx_collide_5times
);
8095 ESTAT_ADD(tx_collide_6times
);
8096 ESTAT_ADD(tx_collide_7times
);
8097 ESTAT_ADD(tx_collide_8times
);
8098 ESTAT_ADD(tx_collide_9times
);
8099 ESTAT_ADD(tx_collide_10times
);
8100 ESTAT_ADD(tx_collide_11times
);
8101 ESTAT_ADD(tx_collide_12times
);
8102 ESTAT_ADD(tx_collide_13times
);
8103 ESTAT_ADD(tx_collide_14times
);
8104 ESTAT_ADD(tx_collide_15times
);
8105 ESTAT_ADD(tx_ucast_packets
);
8106 ESTAT_ADD(tx_mcast_packets
);
8107 ESTAT_ADD(tx_bcast_packets
);
8108 ESTAT_ADD(tx_carrier_sense_errors
);
8109 ESTAT_ADD(tx_discards
);
8110 ESTAT_ADD(tx_errors
);
8112 ESTAT_ADD(dma_writeq_full
);
8113 ESTAT_ADD(dma_write_prioq_full
);
8114 ESTAT_ADD(rxbds_empty
);
8115 ESTAT_ADD(rx_discards
);
8116 ESTAT_ADD(rx_errors
);
8117 ESTAT_ADD(rx_threshold_hit
);
8119 ESTAT_ADD(dma_readq_full
);
8120 ESTAT_ADD(dma_read_prioq_full
);
8121 ESTAT_ADD(tx_comp_queue_full
);
8123 ESTAT_ADD(ring_set_send_prod_index
);
8124 ESTAT_ADD(ring_status_update
);
8125 ESTAT_ADD(nic_irqs
);
8126 ESTAT_ADD(nic_avoided_irqs
);
8127 ESTAT_ADD(nic_tx_threshold_hit
);
8132 static struct net_device_stats
*tg3_get_stats(struct net_device
*dev
)
8134 struct tg3
*tp
= netdev_priv(dev
);
8135 struct net_device_stats
*stats
= &tp
->net_stats
;
8136 struct net_device_stats
*old_stats
= &tp
->net_stats_prev
;
8137 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
8142 stats
->rx_packets
= old_stats
->rx_packets
+
8143 get_stat64(&hw_stats
->rx_ucast_packets
) +
8144 get_stat64(&hw_stats
->rx_mcast_packets
) +
8145 get_stat64(&hw_stats
->rx_bcast_packets
);
8147 stats
->tx_packets
= old_stats
->tx_packets
+
8148 get_stat64(&hw_stats
->tx_ucast_packets
) +
8149 get_stat64(&hw_stats
->tx_mcast_packets
) +
8150 get_stat64(&hw_stats
->tx_bcast_packets
);
8152 stats
->rx_bytes
= old_stats
->rx_bytes
+
8153 get_stat64(&hw_stats
->rx_octets
);
8154 stats
->tx_bytes
= old_stats
->tx_bytes
+
8155 get_stat64(&hw_stats
->tx_octets
);
8157 stats
->rx_errors
= old_stats
->rx_errors
+
8158 get_stat64(&hw_stats
->rx_errors
);
8159 stats
->tx_errors
= old_stats
->tx_errors
+
8160 get_stat64(&hw_stats
->tx_errors
) +
8161 get_stat64(&hw_stats
->tx_mac_errors
) +
8162 get_stat64(&hw_stats
->tx_carrier_sense_errors
) +
8163 get_stat64(&hw_stats
->tx_discards
);
8165 stats
->multicast
= old_stats
->multicast
+
8166 get_stat64(&hw_stats
->rx_mcast_packets
);
8167 stats
->collisions
= old_stats
->collisions
+
8168 get_stat64(&hw_stats
->tx_collisions
);
8170 stats
->rx_length_errors
= old_stats
->rx_length_errors
+
8171 get_stat64(&hw_stats
->rx_frame_too_long_errors
) +
8172 get_stat64(&hw_stats
->rx_undersize_packets
);
8174 stats
->rx_over_errors
= old_stats
->rx_over_errors
+
8175 get_stat64(&hw_stats
->rxbds_empty
);
8176 stats
->rx_frame_errors
= old_stats
->rx_frame_errors
+
8177 get_stat64(&hw_stats
->rx_align_errors
);
8178 stats
->tx_aborted_errors
= old_stats
->tx_aborted_errors
+
8179 get_stat64(&hw_stats
->tx_discards
);
8180 stats
->tx_carrier_errors
= old_stats
->tx_carrier_errors
+
8181 get_stat64(&hw_stats
->tx_carrier_sense_errors
);
8183 stats
->rx_crc_errors
= old_stats
->rx_crc_errors
+
8184 calc_crc_errors(tp
);
8186 stats
->rx_missed_errors
= old_stats
->rx_missed_errors
+
8187 get_stat64(&hw_stats
->rx_discards
);
8192 static inline u32
calc_crc(unsigned char *buf
, int len
)
8200 for (j
= 0; j
< len
; j
++) {
8203 for (k
= 0; k
< 8; k
++) {
8217 static void tg3_set_multi(struct tg3
*tp
, unsigned int accept_all
)
8219 /* accept or reject all multicast frames */
8220 tw32(MAC_HASH_REG_0
, accept_all
? 0xffffffff : 0);
8221 tw32(MAC_HASH_REG_1
, accept_all
? 0xffffffff : 0);
8222 tw32(MAC_HASH_REG_2
, accept_all
? 0xffffffff : 0);
8223 tw32(MAC_HASH_REG_3
, accept_all
? 0xffffffff : 0);
8226 static void __tg3_set_rx_mode(struct net_device
*dev
)
8228 struct tg3
*tp
= netdev_priv(dev
);
8231 rx_mode
= tp
->rx_mode
& ~(RX_MODE_PROMISC
|
8232 RX_MODE_KEEP_VLAN_TAG
);
8234 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8237 #if TG3_VLAN_TAG_USED
8239 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
8240 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
8242 /* By definition, VLAN is disabled always in this
8245 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
8246 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
8249 if (dev
->flags
& IFF_PROMISC
) {
8250 /* Promiscuous mode. */
8251 rx_mode
|= RX_MODE_PROMISC
;
8252 } else if (dev
->flags
& IFF_ALLMULTI
) {
8253 /* Accept all multicast. */
8254 tg3_set_multi (tp
, 1);
8255 } else if (dev
->mc_count
< 1) {
8256 /* Reject all multicast. */
8257 tg3_set_multi (tp
, 0);
8259 /* Accept one or more multicast(s). */
8260 struct dev_mc_list
*mclist
;
8262 u32 mc_filter
[4] = { 0, };
8267 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
8268 i
++, mclist
= mclist
->next
) {
8270 crc
= calc_crc (mclist
->dmi_addr
, ETH_ALEN
);
8272 regidx
= (bit
& 0x60) >> 5;
8274 mc_filter
[regidx
] |= (1 << bit
);
8277 tw32(MAC_HASH_REG_0
, mc_filter
[0]);
8278 tw32(MAC_HASH_REG_1
, mc_filter
[1]);
8279 tw32(MAC_HASH_REG_2
, mc_filter
[2]);
8280 tw32(MAC_HASH_REG_3
, mc_filter
[3]);
8283 if (rx_mode
!= tp
->rx_mode
) {
8284 tp
->rx_mode
= rx_mode
;
8285 tw32_f(MAC_RX_MODE
, rx_mode
);
8290 static void tg3_set_rx_mode(struct net_device
*dev
)
8292 struct tg3
*tp
= netdev_priv(dev
);
8294 if (!netif_running(dev
))
8297 tg3_full_lock(tp
, 0);
8298 __tg3_set_rx_mode(dev
);
8299 tg3_full_unlock(tp
);
8302 #define TG3_REGDUMP_LEN (32 * 1024)
8304 static int tg3_get_regs_len(struct net_device
*dev
)
8306 return TG3_REGDUMP_LEN
;
8309 static void tg3_get_regs(struct net_device
*dev
,
8310 struct ethtool_regs
*regs
, void *_p
)
8313 struct tg3
*tp
= netdev_priv(dev
);
8319 memset(p
, 0, TG3_REGDUMP_LEN
);
8321 if (tp
->link_config
.phy_is_low_power
)
8324 tg3_full_lock(tp
, 0);
8326 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
8327 #define GET_REG32_LOOP(base,len) \
8328 do { p = (u32 *)(orig_p + (base)); \
8329 for (i = 0; i < len; i += 4) \
8330 __GET_REG32((base) + i); \
8332 #define GET_REG32_1(reg) \
8333 do { p = (u32 *)(orig_p + (reg)); \
8334 __GET_REG32((reg)); \
8337 GET_REG32_LOOP(TG3PCI_VENDOR
, 0xb0);
8338 GET_REG32_LOOP(MAILBOX_INTERRUPT_0
, 0x200);
8339 GET_REG32_LOOP(MAC_MODE
, 0x4f0);
8340 GET_REG32_LOOP(SNDDATAI_MODE
, 0xe0);
8341 GET_REG32_1(SNDDATAC_MODE
);
8342 GET_REG32_LOOP(SNDBDS_MODE
, 0x80);
8343 GET_REG32_LOOP(SNDBDI_MODE
, 0x48);
8344 GET_REG32_1(SNDBDC_MODE
);
8345 GET_REG32_LOOP(RCVLPC_MODE
, 0x20);
8346 GET_REG32_LOOP(RCVLPC_SELLST_BASE
, 0x15c);
8347 GET_REG32_LOOP(RCVDBDI_MODE
, 0x0c);
8348 GET_REG32_LOOP(RCVDBDI_JUMBO_BD
, 0x3c);
8349 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0
, 0x44);
8350 GET_REG32_1(RCVDCC_MODE
);
8351 GET_REG32_LOOP(RCVBDI_MODE
, 0x20);
8352 GET_REG32_LOOP(RCVCC_MODE
, 0x14);
8353 GET_REG32_LOOP(RCVLSC_MODE
, 0x08);
8354 GET_REG32_1(MBFREE_MODE
);
8355 GET_REG32_LOOP(HOSTCC_MODE
, 0x100);
8356 GET_REG32_LOOP(MEMARB_MODE
, 0x10);
8357 GET_REG32_LOOP(BUFMGR_MODE
, 0x58);
8358 GET_REG32_LOOP(RDMAC_MODE
, 0x08);
8359 GET_REG32_LOOP(WDMAC_MODE
, 0x08);
8360 GET_REG32_1(RX_CPU_MODE
);
8361 GET_REG32_1(RX_CPU_STATE
);
8362 GET_REG32_1(RX_CPU_PGMCTR
);
8363 GET_REG32_1(RX_CPU_HWBKPT
);
8364 GET_REG32_1(TX_CPU_MODE
);
8365 GET_REG32_1(TX_CPU_STATE
);
8366 GET_REG32_1(TX_CPU_PGMCTR
);
8367 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0
, 0x110);
8368 GET_REG32_LOOP(FTQ_RESET
, 0x120);
8369 GET_REG32_LOOP(MSGINT_MODE
, 0x0c);
8370 GET_REG32_1(DMAC_MODE
);
8371 GET_REG32_LOOP(GRC_MODE
, 0x4c);
8372 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
8373 GET_REG32_LOOP(NVRAM_CMD
, 0x24);
8376 #undef GET_REG32_LOOP
8379 tg3_full_unlock(tp
);
8382 static int tg3_get_eeprom_len(struct net_device
*dev
)
8384 struct tg3
*tp
= netdev_priv(dev
);
8386 return tp
->nvram_size
;
8389 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
);
8390 static int tg3_nvram_read_le(struct tg3
*tp
, u32 offset
, __le32
*val
);
8391 static int tg3_nvram_read_swab(struct tg3
*tp
, u32 offset
, u32
*val
);
8393 static int tg3_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
8395 struct tg3
*tp
= netdev_priv(dev
);
8398 u32 i
, offset
, len
, b_offset
, b_count
;
8401 if (tp
->link_config
.phy_is_low_power
)
8404 offset
= eeprom
->offset
;
8408 eeprom
->magic
= TG3_EEPROM_MAGIC
;
8411 /* adjustments to start on required 4 byte boundary */
8412 b_offset
= offset
& 3;
8413 b_count
= 4 - b_offset
;
8414 if (b_count
> len
) {
8415 /* i.e. offset=1 len=2 */
8418 ret
= tg3_nvram_read_le(tp
, offset
-b_offset
, &val
);
8421 memcpy(data
, ((char*)&val
) + b_offset
, b_count
);
8424 eeprom
->len
+= b_count
;
8427 /* read bytes upto the last 4 byte boundary */
8428 pd
= &data
[eeprom
->len
];
8429 for (i
= 0; i
< (len
- (len
& 3)); i
+= 4) {
8430 ret
= tg3_nvram_read_le(tp
, offset
+ i
, &val
);
8435 memcpy(pd
+ i
, &val
, 4);
8440 /* read last bytes not ending on 4 byte boundary */
8441 pd
= &data
[eeprom
->len
];
8443 b_offset
= offset
+ len
- b_count
;
8444 ret
= tg3_nvram_read_le(tp
, b_offset
, &val
);
8447 memcpy(pd
, &val
, b_count
);
8448 eeprom
->len
+= b_count
;
8453 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
);
8455 static int tg3_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
8457 struct tg3
*tp
= netdev_priv(dev
);
8459 u32 offset
, len
, b_offset
, odd_len
;
8463 if (tp
->link_config
.phy_is_low_power
)
8466 if (eeprom
->magic
!= TG3_EEPROM_MAGIC
)
8469 offset
= eeprom
->offset
;
8472 if ((b_offset
= (offset
& 3))) {
8473 /* adjustments to start on required 4 byte boundary */
8474 ret
= tg3_nvram_read_le(tp
, offset
-b_offset
, &start
);
8485 /* adjustments to end on required 4 byte boundary */
8487 len
= (len
+ 3) & ~3;
8488 ret
= tg3_nvram_read_le(tp
, offset
+len
-4, &end
);
8494 if (b_offset
|| odd_len
) {
8495 buf
= kmalloc(len
, GFP_KERNEL
);
8499 memcpy(buf
, &start
, 4);
8501 memcpy(buf
+len
-4, &end
, 4);
8502 memcpy(buf
+ b_offset
, data
, eeprom
->len
);
8505 ret
= tg3_nvram_write_block(tp
, offset
, len
, buf
);
8513 static int tg3_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
8515 struct tg3
*tp
= netdev_priv(dev
);
8517 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
8518 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
8520 return phy_ethtool_gset(tp
->mdio_bus
->phy_map
[PHY_ADDR
], cmd
);
8523 cmd
->supported
= (SUPPORTED_Autoneg
);
8525 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
8526 cmd
->supported
|= (SUPPORTED_1000baseT_Half
|
8527 SUPPORTED_1000baseT_Full
);
8529 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)) {
8530 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
8531 SUPPORTED_100baseT_Full
|
8532 SUPPORTED_10baseT_Half
|
8533 SUPPORTED_10baseT_Full
|
8535 cmd
->port
= PORT_TP
;
8537 cmd
->supported
|= SUPPORTED_FIBRE
;
8538 cmd
->port
= PORT_FIBRE
;
8541 cmd
->advertising
= tp
->link_config
.advertising
;
8542 if (netif_running(dev
)) {
8543 cmd
->speed
= tp
->link_config
.active_speed
;
8544 cmd
->duplex
= tp
->link_config
.active_duplex
;
8546 cmd
->phy_address
= PHY_ADDR
;
8547 cmd
->transceiver
= 0;
8548 cmd
->autoneg
= tp
->link_config
.autoneg
;
8554 static int tg3_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
8556 struct tg3
*tp
= netdev_priv(dev
);
8558 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
8559 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
8561 return phy_ethtool_sset(tp
->mdio_bus
->phy_map
[PHY_ADDR
], cmd
);
8564 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) {
8565 /* These are the only valid advertisement bits allowed. */
8566 if (cmd
->autoneg
== AUTONEG_ENABLE
&&
8567 (cmd
->advertising
& ~(ADVERTISED_1000baseT_Half
|
8568 ADVERTISED_1000baseT_Full
|
8569 ADVERTISED_Autoneg
|
8572 /* Fiber can only do SPEED_1000. */
8573 else if ((cmd
->autoneg
!= AUTONEG_ENABLE
) &&
8574 (cmd
->speed
!= SPEED_1000
))
8576 /* Copper cannot force SPEED_1000. */
8577 } else if ((cmd
->autoneg
!= AUTONEG_ENABLE
) &&
8578 (cmd
->speed
== SPEED_1000
))
8580 else if ((cmd
->speed
== SPEED_1000
) &&
8581 (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
8584 tg3_full_lock(tp
, 0);
8586 tp
->link_config
.autoneg
= cmd
->autoneg
;
8587 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
8588 tp
->link_config
.advertising
= (cmd
->advertising
|
8589 ADVERTISED_Autoneg
);
8590 tp
->link_config
.speed
= SPEED_INVALID
;
8591 tp
->link_config
.duplex
= DUPLEX_INVALID
;
8593 tp
->link_config
.advertising
= 0;
8594 tp
->link_config
.speed
= cmd
->speed
;
8595 tp
->link_config
.duplex
= cmd
->duplex
;
8598 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
8599 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
8600 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
8602 if (netif_running(dev
))
8603 tg3_setup_phy(tp
, 1);
8605 tg3_full_unlock(tp
);
8610 static void tg3_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
8612 struct tg3
*tp
= netdev_priv(dev
);
8614 strcpy(info
->driver
, DRV_MODULE_NAME
);
8615 strcpy(info
->version
, DRV_MODULE_VERSION
);
8616 strcpy(info
->fw_version
, tp
->fw_ver
);
8617 strcpy(info
->bus_info
, pci_name(tp
->pdev
));
8620 static void tg3_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
8622 struct tg3
*tp
= netdev_priv(dev
);
8624 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
8625 device_can_wakeup(&tp
->pdev
->dev
))
8626 wol
->supported
= WAKE_MAGIC
;
8630 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) &&
8631 device_can_wakeup(&tp
->pdev
->dev
))
8632 wol
->wolopts
= WAKE_MAGIC
;
8633 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
8636 static int tg3_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
8638 struct tg3
*tp
= netdev_priv(dev
);
8639 struct device
*dp
= &tp
->pdev
->dev
;
8641 if (wol
->wolopts
& ~WAKE_MAGIC
)
8643 if ((wol
->wolopts
& WAKE_MAGIC
) &&
8644 !((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) && device_can_wakeup(dp
)))
8647 spin_lock_bh(&tp
->lock
);
8648 if (wol
->wolopts
& WAKE_MAGIC
) {
8649 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
8650 device_set_wakeup_enable(dp
, true);
8652 tp
->tg3_flags
&= ~TG3_FLAG_WOL_ENABLE
;
8653 device_set_wakeup_enable(dp
, false);
8655 spin_unlock_bh(&tp
->lock
);
8660 static u32
tg3_get_msglevel(struct net_device
*dev
)
8662 struct tg3
*tp
= netdev_priv(dev
);
8663 return tp
->msg_enable
;
8666 static void tg3_set_msglevel(struct net_device
*dev
, u32 value
)
8668 struct tg3
*tp
= netdev_priv(dev
);
8669 tp
->msg_enable
= value
;
8672 static int tg3_set_tso(struct net_device
*dev
, u32 value
)
8674 struct tg3
*tp
= netdev_priv(dev
);
8676 if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8681 if ((dev
->features
& NETIF_F_IPV6_CSUM
) &&
8682 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
)) {
8684 dev
->features
|= NETIF_F_TSO6
;
8685 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
8686 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
8687 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
8688 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
8689 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
8690 dev
->features
|= NETIF_F_TSO_ECN
;
8692 dev
->features
&= ~(NETIF_F_TSO6
| NETIF_F_TSO_ECN
);
8694 return ethtool_op_set_tso(dev
, value
);
8697 static int tg3_nway_reset(struct net_device
*dev
)
8699 struct tg3
*tp
= netdev_priv(dev
);
8702 if (!netif_running(dev
))
8705 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
8708 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
8709 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
8711 r
= phy_start_aneg(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
8715 spin_lock_bh(&tp
->lock
);
8717 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
8718 if (!tg3_readphy(tp
, MII_BMCR
, &bmcr
) &&
8719 ((bmcr
& BMCR_ANENABLE
) ||
8720 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
))) {
8721 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
|
8725 spin_unlock_bh(&tp
->lock
);
8731 static void tg3_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
8733 struct tg3
*tp
= netdev_priv(dev
);
8735 ering
->rx_max_pending
= TG3_RX_RING_SIZE
- 1;
8736 ering
->rx_mini_max_pending
= 0;
8737 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
8738 ering
->rx_jumbo_max_pending
= TG3_RX_JUMBO_RING_SIZE
- 1;
8740 ering
->rx_jumbo_max_pending
= 0;
8742 ering
->tx_max_pending
= TG3_TX_RING_SIZE
- 1;
8744 ering
->rx_pending
= tp
->rx_pending
;
8745 ering
->rx_mini_pending
= 0;
8746 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
8747 ering
->rx_jumbo_pending
= tp
->rx_jumbo_pending
;
8749 ering
->rx_jumbo_pending
= 0;
8751 ering
->tx_pending
= tp
->tx_pending
;
8754 static int tg3_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
8756 struct tg3
*tp
= netdev_priv(dev
);
8757 int irq_sync
= 0, err
= 0;
8759 if ((ering
->rx_pending
> TG3_RX_RING_SIZE
- 1) ||
8760 (ering
->rx_jumbo_pending
> TG3_RX_JUMBO_RING_SIZE
- 1) ||
8761 (ering
->tx_pending
> TG3_TX_RING_SIZE
- 1) ||
8762 (ering
->tx_pending
<= MAX_SKB_FRAGS
) ||
8763 ((tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
) &&
8764 (ering
->tx_pending
<= (MAX_SKB_FRAGS
* 3))))
8767 if (netif_running(dev
)) {
8773 tg3_full_lock(tp
, irq_sync
);
8775 tp
->rx_pending
= ering
->rx_pending
;
8777 if ((tp
->tg3_flags2
& TG3_FLG2_MAX_RXPEND_64
) &&
8778 tp
->rx_pending
> 63)
8779 tp
->rx_pending
= 63;
8780 tp
->rx_jumbo_pending
= ering
->rx_jumbo_pending
;
8781 tp
->tx_pending
= ering
->tx_pending
;
8783 if (netif_running(dev
)) {
8784 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8785 err
= tg3_restart_hw(tp
, 1);
8787 tg3_netif_start(tp
);
8790 tg3_full_unlock(tp
);
8792 if (irq_sync
&& !err
)
8798 static void tg3_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
8800 struct tg3
*tp
= netdev_priv(dev
);
8802 epause
->autoneg
= (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
) != 0;
8804 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
)
8805 epause
->rx_pause
= 1;
8807 epause
->rx_pause
= 0;
8809 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
)
8810 epause
->tx_pause
= 1;
8812 epause
->tx_pause
= 0;
8815 static int tg3_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
8817 struct tg3
*tp
= netdev_priv(dev
);
8820 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
8821 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
8824 if (epause
->autoneg
) {
8826 struct phy_device
*phydev
;
8828 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
8830 if (epause
->rx_pause
) {
8831 if (epause
->tx_pause
)
8832 newadv
= ADVERTISED_Pause
;
8834 newadv
= ADVERTISED_Pause
|
8835 ADVERTISED_Asym_Pause
;
8836 } else if (epause
->tx_pause
) {
8837 newadv
= ADVERTISED_Asym_Pause
;
8841 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
8842 u32 oldadv
= phydev
->advertising
&
8844 ADVERTISED_Asym_Pause
);
8845 if (oldadv
!= newadv
) {
8846 phydev
->advertising
&=
8847 ~(ADVERTISED_Pause
|
8848 ADVERTISED_Asym_Pause
);
8849 phydev
->advertising
|= newadv
;
8850 err
= phy_start_aneg(phydev
);
8853 tp
->link_config
.advertising
&=
8854 ~(ADVERTISED_Pause
|
8855 ADVERTISED_Asym_Pause
);
8856 tp
->link_config
.advertising
|= newadv
;
8859 if (epause
->rx_pause
)
8860 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
8862 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
8864 if (epause
->tx_pause
)
8865 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
8867 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
8869 if (netif_running(dev
))
8870 tg3_setup_flow_control(tp
, 0, 0);
8875 if (netif_running(dev
)) {
8880 tg3_full_lock(tp
, irq_sync
);
8882 if (epause
->autoneg
)
8883 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
8885 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
8886 if (epause
->rx_pause
)
8887 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
8889 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
8890 if (epause
->tx_pause
)
8891 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
8893 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
8895 if (netif_running(dev
)) {
8896 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8897 err
= tg3_restart_hw(tp
, 1);
8899 tg3_netif_start(tp
);
8902 tg3_full_unlock(tp
);
8908 static u32
tg3_get_rx_csum(struct net_device
*dev
)
8910 struct tg3
*tp
= netdev_priv(dev
);
8911 return (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0;
8914 static int tg3_set_rx_csum(struct net_device
*dev
, u32 data
)
8916 struct tg3
*tp
= netdev_priv(dev
);
8918 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
8924 spin_lock_bh(&tp
->lock
);
8926 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
8928 tp
->tg3_flags
&= ~TG3_FLAG_RX_CHECKSUMS
;
8929 spin_unlock_bh(&tp
->lock
);
8934 static int tg3_set_tx_csum(struct net_device
*dev
, u32 data
)
8936 struct tg3
*tp
= netdev_priv(dev
);
8938 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
8944 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
8945 ethtool_op_set_tx_ipv6_csum(dev
, data
);
8947 ethtool_op_set_tx_csum(dev
, data
);
8952 static int tg3_get_sset_count (struct net_device
*dev
, int sset
)
8956 return TG3_NUM_TEST
;
8958 return TG3_NUM_STATS
;
8964 static void tg3_get_strings (struct net_device
*dev
, u32 stringset
, u8
*buf
)
8966 switch (stringset
) {
8968 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
8971 memcpy(buf
, ðtool_test_keys
, sizeof(ethtool_test_keys
));
8974 WARN_ON(1); /* we need a WARN() */
8979 static int tg3_phys_id(struct net_device
*dev
, u32 data
)
8981 struct tg3
*tp
= netdev_priv(dev
);
8984 if (!netif_running(tp
->dev
))
8988 data
= UINT_MAX
/ 2;
8990 for (i
= 0; i
< (data
* 2); i
++) {
8992 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
8993 LED_CTRL_1000MBPS_ON
|
8994 LED_CTRL_100MBPS_ON
|
8995 LED_CTRL_10MBPS_ON
|
8996 LED_CTRL_TRAFFIC_OVERRIDE
|
8997 LED_CTRL_TRAFFIC_BLINK
|
8998 LED_CTRL_TRAFFIC_LED
);
9001 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
9002 LED_CTRL_TRAFFIC_OVERRIDE
);
9004 if (msleep_interruptible(500))
9007 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
9011 static void tg3_get_ethtool_stats (struct net_device
*dev
,
9012 struct ethtool_stats
*estats
, u64
*tmp_stats
)
9014 struct tg3
*tp
= netdev_priv(dev
);
9015 memcpy(tmp_stats
, tg3_get_estats(tp
), sizeof(tp
->estats
));
9018 #define NVRAM_TEST_SIZE 0x100
9019 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9020 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9021 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
9022 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9023 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9025 static int tg3_test_nvram(struct tg3
*tp
)
9029 int i
, j
, k
, err
= 0, size
;
9031 if (tg3_nvram_read_swab(tp
, 0, &magic
) != 0)
9034 if (magic
== TG3_EEPROM_MAGIC
)
9035 size
= NVRAM_TEST_SIZE
;
9036 else if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
) {
9037 if ((magic
& TG3_EEPROM_SB_FORMAT_MASK
) ==
9038 TG3_EEPROM_SB_FORMAT_1
) {
9039 switch (magic
& TG3_EEPROM_SB_REVISION_MASK
) {
9040 case TG3_EEPROM_SB_REVISION_0
:
9041 size
= NVRAM_SELFBOOT_FORMAT1_0_SIZE
;
9043 case TG3_EEPROM_SB_REVISION_2
:
9044 size
= NVRAM_SELFBOOT_FORMAT1_2_SIZE
;
9046 case TG3_EEPROM_SB_REVISION_3
:
9047 size
= NVRAM_SELFBOOT_FORMAT1_3_SIZE
;
9054 } else if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
9055 size
= NVRAM_SELFBOOT_HW_SIZE
;
9059 buf
= kmalloc(size
, GFP_KERNEL
);
9064 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
9065 if ((err
= tg3_nvram_read_le(tp
, i
, &buf
[j
])) != 0)
9071 /* Selfboot format */
9072 magic
= swab32(le32_to_cpu(buf
[0]));
9073 if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) ==
9074 TG3_EEPROM_MAGIC_FW
) {
9075 u8
*buf8
= (u8
*) buf
, csum8
= 0;
9077 if ((magic
& TG3_EEPROM_SB_REVISION_MASK
) ==
9078 TG3_EEPROM_SB_REVISION_2
) {
9079 /* For rev 2, the csum doesn't include the MBA. */
9080 for (i
= 0; i
< TG3_EEPROM_SB_F1R2_MBA_OFF
; i
++)
9082 for (i
= TG3_EEPROM_SB_F1R2_MBA_OFF
+ 4; i
< size
; i
++)
9085 for (i
= 0; i
< size
; i
++)
9098 if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) ==
9099 TG3_EEPROM_MAGIC_HW
) {
9100 u8 data
[NVRAM_SELFBOOT_DATA_SIZE
];
9101 u8 parity
[NVRAM_SELFBOOT_DATA_SIZE
];
9102 u8
*buf8
= (u8
*) buf
;
9104 /* Separate the parity bits and the data bytes. */
9105 for (i
= 0, j
= 0, k
= 0; i
< NVRAM_SELFBOOT_HW_SIZE
; i
++) {
9106 if ((i
== 0) || (i
== 8)) {
9110 for (l
= 0, msk
= 0x80; l
< 7; l
++, msk
>>= 1)
9111 parity
[k
++] = buf8
[i
] & msk
;
9118 for (l
= 0, msk
= 0x20; l
< 6; l
++, msk
>>= 1)
9119 parity
[k
++] = buf8
[i
] & msk
;
9122 for (l
= 0, msk
= 0x80; l
< 8; l
++, msk
>>= 1)
9123 parity
[k
++] = buf8
[i
] & msk
;
9126 data
[j
++] = buf8
[i
];
9130 for (i
= 0; i
< NVRAM_SELFBOOT_DATA_SIZE
; i
++) {
9131 u8 hw8
= hweight8(data
[i
]);
9133 if ((hw8
& 0x1) && parity
[i
])
9135 else if (!(hw8
& 0x1) && !parity
[i
])
9142 /* Bootstrap checksum at offset 0x10 */
9143 csum
= calc_crc((unsigned char *) buf
, 0x10);
9144 if(csum
!= le32_to_cpu(buf
[0x10/4]))
9147 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9148 csum
= calc_crc((unsigned char *) &buf
[0x74/4], 0x88);
9149 if (csum
!= le32_to_cpu(buf
[0xfc/4]))
9159 #define TG3_SERDES_TIMEOUT_SEC 2
9160 #define TG3_COPPER_TIMEOUT_SEC 6
9162 static int tg3_test_link(struct tg3
*tp
)
9166 if (!netif_running(tp
->dev
))
9169 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
9170 max
= TG3_SERDES_TIMEOUT_SEC
;
9172 max
= TG3_COPPER_TIMEOUT_SEC
;
9174 for (i
= 0; i
< max
; i
++) {
9175 if (netif_carrier_ok(tp
->dev
))
9178 if (msleep_interruptible(1000))
9185 /* Only test the commonly used registers */
9186 static int tg3_test_registers(struct tg3
*tp
)
9188 int i
, is_5705
, is_5750
;
9189 u32 offset
, read_mask
, write_mask
, val
, save_val
, read_val
;
9193 #define TG3_FL_5705 0x1
9194 #define TG3_FL_NOT_5705 0x2
9195 #define TG3_FL_NOT_5788 0x4
9196 #define TG3_FL_NOT_5750 0x8
9200 /* MAC Control Registers */
9201 { MAC_MODE
, TG3_FL_NOT_5705
,
9202 0x00000000, 0x00ef6f8c },
9203 { MAC_MODE
, TG3_FL_5705
,
9204 0x00000000, 0x01ef6b8c },
9205 { MAC_STATUS
, TG3_FL_NOT_5705
,
9206 0x03800107, 0x00000000 },
9207 { MAC_STATUS
, TG3_FL_5705
,
9208 0x03800100, 0x00000000 },
9209 { MAC_ADDR_0_HIGH
, 0x0000,
9210 0x00000000, 0x0000ffff },
9211 { MAC_ADDR_0_LOW
, 0x0000,
9212 0x00000000, 0xffffffff },
9213 { MAC_RX_MTU_SIZE
, 0x0000,
9214 0x00000000, 0x0000ffff },
9215 { MAC_TX_MODE
, 0x0000,
9216 0x00000000, 0x00000070 },
9217 { MAC_TX_LENGTHS
, 0x0000,
9218 0x00000000, 0x00003fff },
9219 { MAC_RX_MODE
, TG3_FL_NOT_5705
,
9220 0x00000000, 0x000007fc },
9221 { MAC_RX_MODE
, TG3_FL_5705
,
9222 0x00000000, 0x000007dc },
9223 { MAC_HASH_REG_0
, 0x0000,
9224 0x00000000, 0xffffffff },
9225 { MAC_HASH_REG_1
, 0x0000,
9226 0x00000000, 0xffffffff },
9227 { MAC_HASH_REG_2
, 0x0000,
9228 0x00000000, 0xffffffff },
9229 { MAC_HASH_REG_3
, 0x0000,
9230 0x00000000, 0xffffffff },
9232 /* Receive Data and Receive BD Initiator Control Registers. */
9233 { RCVDBDI_JUMBO_BD
+0, TG3_FL_NOT_5705
,
9234 0x00000000, 0xffffffff },
9235 { RCVDBDI_JUMBO_BD
+4, TG3_FL_NOT_5705
,
9236 0x00000000, 0xffffffff },
9237 { RCVDBDI_JUMBO_BD
+8, TG3_FL_NOT_5705
,
9238 0x00000000, 0x00000003 },
9239 { RCVDBDI_JUMBO_BD
+0xc, TG3_FL_NOT_5705
,
9240 0x00000000, 0xffffffff },
9241 { RCVDBDI_STD_BD
+0, 0x0000,
9242 0x00000000, 0xffffffff },
9243 { RCVDBDI_STD_BD
+4, 0x0000,
9244 0x00000000, 0xffffffff },
9245 { RCVDBDI_STD_BD
+8, 0x0000,
9246 0x00000000, 0xffff0002 },
9247 { RCVDBDI_STD_BD
+0xc, 0x0000,
9248 0x00000000, 0xffffffff },
9250 /* Receive BD Initiator Control Registers. */
9251 { RCVBDI_STD_THRESH
, TG3_FL_NOT_5705
,
9252 0x00000000, 0xffffffff },
9253 { RCVBDI_STD_THRESH
, TG3_FL_5705
,
9254 0x00000000, 0x000003ff },
9255 { RCVBDI_JUMBO_THRESH
, TG3_FL_NOT_5705
,
9256 0x00000000, 0xffffffff },
9258 /* Host Coalescing Control Registers. */
9259 { HOSTCC_MODE
, TG3_FL_NOT_5705
,
9260 0x00000000, 0x00000004 },
9261 { HOSTCC_MODE
, TG3_FL_5705
,
9262 0x00000000, 0x000000f6 },
9263 { HOSTCC_RXCOL_TICKS
, TG3_FL_NOT_5705
,
9264 0x00000000, 0xffffffff },
9265 { HOSTCC_RXCOL_TICKS
, TG3_FL_5705
,
9266 0x00000000, 0x000003ff },
9267 { HOSTCC_TXCOL_TICKS
, TG3_FL_NOT_5705
,
9268 0x00000000, 0xffffffff },
9269 { HOSTCC_TXCOL_TICKS
, TG3_FL_5705
,
9270 0x00000000, 0x000003ff },
9271 { HOSTCC_RXMAX_FRAMES
, TG3_FL_NOT_5705
,
9272 0x00000000, 0xffffffff },
9273 { HOSTCC_RXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9274 0x00000000, 0x000000ff },
9275 { HOSTCC_TXMAX_FRAMES
, TG3_FL_NOT_5705
,
9276 0x00000000, 0xffffffff },
9277 { HOSTCC_TXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9278 0x00000000, 0x000000ff },
9279 { HOSTCC_RXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
9280 0x00000000, 0xffffffff },
9281 { HOSTCC_TXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
9282 0x00000000, 0xffffffff },
9283 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
9284 0x00000000, 0xffffffff },
9285 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9286 0x00000000, 0x000000ff },
9287 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
9288 0x00000000, 0xffffffff },
9289 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9290 0x00000000, 0x000000ff },
9291 { HOSTCC_STAT_COAL_TICKS
, TG3_FL_NOT_5705
,
9292 0x00000000, 0xffffffff },
9293 { HOSTCC_STATS_BLK_HOST_ADDR
, TG3_FL_NOT_5705
,
9294 0x00000000, 0xffffffff },
9295 { HOSTCC_STATS_BLK_HOST_ADDR
+4, TG3_FL_NOT_5705
,
9296 0x00000000, 0xffffffff },
9297 { HOSTCC_STATUS_BLK_HOST_ADDR
, 0x0000,
9298 0x00000000, 0xffffffff },
9299 { HOSTCC_STATUS_BLK_HOST_ADDR
+4, 0x0000,
9300 0x00000000, 0xffffffff },
9301 { HOSTCC_STATS_BLK_NIC_ADDR
, 0x0000,
9302 0xffffffff, 0x00000000 },
9303 { HOSTCC_STATUS_BLK_NIC_ADDR
, 0x0000,
9304 0xffffffff, 0x00000000 },
9306 /* Buffer Manager Control Registers. */
9307 { BUFMGR_MB_POOL_ADDR
, TG3_FL_NOT_5750
,
9308 0x00000000, 0x007fff80 },
9309 { BUFMGR_MB_POOL_SIZE
, TG3_FL_NOT_5750
,
9310 0x00000000, 0x007fffff },
9311 { BUFMGR_MB_RDMA_LOW_WATER
, 0x0000,
9312 0x00000000, 0x0000003f },
9313 { BUFMGR_MB_MACRX_LOW_WATER
, 0x0000,
9314 0x00000000, 0x000001ff },
9315 { BUFMGR_MB_HIGH_WATER
, 0x0000,
9316 0x00000000, 0x000001ff },
9317 { BUFMGR_DMA_DESC_POOL_ADDR
, TG3_FL_NOT_5705
,
9318 0xffffffff, 0x00000000 },
9319 { BUFMGR_DMA_DESC_POOL_SIZE
, TG3_FL_NOT_5705
,
9320 0xffffffff, 0x00000000 },
9322 /* Mailbox Registers */
9323 { GRCMBOX_RCVSTD_PROD_IDX
+4, 0x0000,
9324 0x00000000, 0x000001ff },
9325 { GRCMBOX_RCVJUMBO_PROD_IDX
+4, TG3_FL_NOT_5705
,
9326 0x00000000, 0x000001ff },
9327 { GRCMBOX_RCVRET_CON_IDX_0
+4, 0x0000,
9328 0x00000000, 0x000007ff },
9329 { GRCMBOX_SNDHOST_PROD_IDX_0
+4, 0x0000,
9330 0x00000000, 0x000001ff },
9332 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9335 is_5705
= is_5750
= 0;
9336 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
9338 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
9342 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
9343 if (is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5705
))
9346 if (!is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_5705
))
9349 if ((tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
9350 (reg_tbl
[i
].flags
& TG3_FL_NOT_5788
))
9353 if (is_5750
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5750
))
9356 offset
= (u32
) reg_tbl
[i
].offset
;
9357 read_mask
= reg_tbl
[i
].read_mask
;
9358 write_mask
= reg_tbl
[i
].write_mask
;
9360 /* Save the original register content */
9361 save_val
= tr32(offset
);
9363 /* Determine the read-only value. */
9364 read_val
= save_val
& read_mask
;
9366 /* Write zero to the register, then make sure the read-only bits
9367 * are not changed and the read/write bits are all zeros.
9373 /* Test the read-only and read/write bits. */
9374 if (((val
& read_mask
) != read_val
) || (val
& write_mask
))
9377 /* Write ones to all the bits defined by RdMask and WrMask, then
9378 * make sure the read-only bits are not changed and the
9379 * read/write bits are all ones.
9381 tw32(offset
, read_mask
| write_mask
);
9385 /* Test the read-only bits. */
9386 if ((val
& read_mask
) != read_val
)
9389 /* Test the read/write bits. */
9390 if ((val
& write_mask
) != write_mask
)
9393 tw32(offset
, save_val
);
9399 if (netif_msg_hw(tp
))
9400 printk(KERN_ERR PFX
"Register test failed at offset %x\n",
9402 tw32(offset
, save_val
);
9406 static int tg3_do_mem_test(struct tg3
*tp
, u32 offset
, u32 len
)
9408 static const u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9412 for (i
= 0; i
< ARRAY_SIZE(test_pattern
); i
++) {
9413 for (j
= 0; j
< len
; j
+= 4) {
9416 tg3_write_mem(tp
, offset
+ j
, test_pattern
[i
]);
9417 tg3_read_mem(tp
, offset
+ j
, &val
);
9418 if (val
!= test_pattern
[i
])
9425 static int tg3_test_memory(struct tg3
*tp
)
9427 static struct mem_entry
{
9430 } mem_tbl_570x
[] = {
9431 { 0x00000000, 0x00b50},
9432 { 0x00002000, 0x1c000},
9433 { 0xffffffff, 0x00000}
9434 }, mem_tbl_5705
[] = {
9435 { 0x00000100, 0x0000c},
9436 { 0x00000200, 0x00008},
9437 { 0x00004000, 0x00800},
9438 { 0x00006000, 0x01000},
9439 { 0x00008000, 0x02000},
9440 { 0x00010000, 0x0e000},
9441 { 0xffffffff, 0x00000}
9442 }, mem_tbl_5755
[] = {
9443 { 0x00000200, 0x00008},
9444 { 0x00004000, 0x00800},
9445 { 0x00006000, 0x00800},
9446 { 0x00008000, 0x02000},
9447 { 0x00010000, 0x0c000},
9448 { 0xffffffff, 0x00000}
9449 }, mem_tbl_5906
[] = {
9450 { 0x00000200, 0x00008},
9451 { 0x00004000, 0x00400},
9452 { 0x00006000, 0x00400},
9453 { 0x00008000, 0x01000},
9454 { 0x00010000, 0x01000},
9455 { 0xffffffff, 0x00000}
9457 struct mem_entry
*mem_tbl
;
9461 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
9462 mem_tbl
= mem_tbl_5755
;
9463 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
9464 mem_tbl
= mem_tbl_5906
;
9465 else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
9466 mem_tbl
= mem_tbl_5705
;
9468 mem_tbl
= mem_tbl_570x
;
9470 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
9471 if ((err
= tg3_do_mem_test(tp
, mem_tbl
[i
].offset
,
9472 mem_tbl
[i
].len
)) != 0)
9479 #define TG3_MAC_LOOPBACK 0
9480 #define TG3_PHY_LOOPBACK 1
9482 static int tg3_run_loopback(struct tg3
*tp
, int loopback_mode
)
9484 u32 mac_mode
, rx_start_idx
, rx_idx
, tx_idx
, opaque_key
;
9486 struct sk_buff
*skb
, *rx_skb
;
9489 int num_pkts
, tx_len
, rx_len
, i
, err
;
9490 struct tg3_rx_buffer_desc
*desc
;
9492 if (loopback_mode
== TG3_MAC_LOOPBACK
) {
9493 /* HW errata - mac loopback fails in some cases on 5780.
9494 * Normal traffic and PHY loopback are not affected by
9497 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
)
9500 mac_mode
= (tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
) |
9501 MAC_MODE_PORT_INT_LPBACK
;
9502 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
9503 mac_mode
|= MAC_MODE_LINK_POLARITY
;
9504 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
9505 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
9507 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
9508 tw32(MAC_MODE
, mac_mode
);
9509 } else if (loopback_mode
== TG3_PHY_LOOPBACK
) {
9512 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
9515 if (!tg3_readphy(tp
, MII_TG3_EPHY_TEST
, &phytest
)) {
9518 tg3_writephy(tp
, MII_TG3_EPHY_TEST
,
9519 phytest
| MII_TG3_EPHY_SHADOW_EN
);
9520 if (!tg3_readphy(tp
, 0x1b, &phy
))
9521 tg3_writephy(tp
, 0x1b, phy
& ~0x20);
9522 tg3_writephy(tp
, MII_TG3_EPHY_TEST
, phytest
);
9524 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED100
;
9526 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED1000
;
9528 tg3_phy_toggle_automdix(tp
, 0);
9530 tg3_writephy(tp
, MII_BMCR
, val
);
9533 mac_mode
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
9534 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
9535 tg3_writephy(tp
, MII_TG3_EPHY_PTEST
, 0x1800);
9536 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
9538 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
9540 /* reset to prevent losing 1st rx packet intermittently */
9541 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
9542 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
9544 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
9546 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
9547 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
)
9548 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
9549 else if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
)
9550 mac_mode
|= MAC_MODE_LINK_POLARITY
;
9551 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
9552 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
9554 tw32(MAC_MODE
, mac_mode
);
9562 skb
= netdev_alloc_skb(tp
->dev
, tx_len
);
9566 tx_data
= skb_put(skb
, tx_len
);
9567 memcpy(tx_data
, tp
->dev
->dev_addr
, 6);
9568 memset(tx_data
+ 6, 0x0, 8);
9570 tw32(MAC_RX_MTU_SIZE
, tx_len
+ 4);
9572 for (i
= 14; i
< tx_len
; i
++)
9573 tx_data
[i
] = (u8
) (i
& 0xff);
9575 map
= pci_map_single(tp
->pdev
, skb
->data
, tx_len
, PCI_DMA_TODEVICE
);
9577 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
9582 rx_start_idx
= tp
->hw_status
->idx
[0].rx_producer
;
9586 tg3_set_txd(tp
, tp
->tx_prod
, map
, tx_len
, 0, 1);
9591 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
,
9593 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
);
9597 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9598 for (i
= 0; i
< 25; i
++) {
9599 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
9604 tx_idx
= tp
->hw_status
->idx
[0].tx_consumer
;
9605 rx_idx
= tp
->hw_status
->idx
[0].rx_producer
;
9606 if ((tx_idx
== tp
->tx_prod
) &&
9607 (rx_idx
== (rx_start_idx
+ num_pkts
)))
9611 pci_unmap_single(tp
->pdev
, map
, tx_len
, PCI_DMA_TODEVICE
);
9614 if (tx_idx
!= tp
->tx_prod
)
9617 if (rx_idx
!= rx_start_idx
+ num_pkts
)
9620 desc
= &tp
->rx_rcb
[rx_start_idx
];
9621 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
9622 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
9623 if (opaque_key
!= RXD_OPAQUE_RING_STD
)
9626 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
9627 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
))
9630 rx_len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) - 4;
9631 if (rx_len
!= tx_len
)
9634 rx_skb
= tp
->rx_std_buffers
[desc_idx
].skb
;
9636 map
= pci_unmap_addr(&tp
->rx_std_buffers
[desc_idx
], mapping
);
9637 pci_dma_sync_single_for_cpu(tp
->pdev
, map
, rx_len
, PCI_DMA_FROMDEVICE
);
9639 for (i
= 14; i
< tx_len
; i
++) {
9640 if (*(rx_skb
->data
+ i
) != (u8
) (i
& 0xff))
9645 /* tg3_free_rings will unmap and free the rx_skb */
9650 #define TG3_MAC_LOOPBACK_FAILED 1
9651 #define TG3_PHY_LOOPBACK_FAILED 2
9652 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9653 TG3_PHY_LOOPBACK_FAILED)
9655 static int tg3_test_loopback(struct tg3
*tp
)
9660 if (!netif_running(tp
->dev
))
9661 return TG3_LOOPBACK_FAILED
;
9663 err
= tg3_reset_hw(tp
, 1);
9665 return TG3_LOOPBACK_FAILED
;
9667 /* Turn off gphy autopowerdown. */
9668 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
9669 tg3_phy_toggle_apd(tp
, false);
9671 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
9675 tw32(TG3_CPMU_MUTEX_REQ
, CPMU_MUTEX_REQ_DRIVER
);
9677 /* Wait for up to 40 microseconds to acquire lock. */
9678 for (i
= 0; i
< 4; i
++) {
9679 status
= tr32(TG3_CPMU_MUTEX_GNT
);
9680 if (status
== CPMU_MUTEX_GNT_DRIVER
)
9685 if (status
!= CPMU_MUTEX_GNT_DRIVER
)
9686 return TG3_LOOPBACK_FAILED
;
9688 /* Turn off link-based power management. */
9689 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
9691 cpmuctrl
& ~(CPMU_CTRL_LINK_SPEED_MODE
|
9692 CPMU_CTRL_LINK_AWARE_MODE
));
9695 if (tg3_run_loopback(tp
, TG3_MAC_LOOPBACK
))
9696 err
|= TG3_MAC_LOOPBACK_FAILED
;
9698 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
9699 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
9701 /* Release the mutex */
9702 tw32(TG3_CPMU_MUTEX_GNT
, CPMU_MUTEX_GNT_DRIVER
);
9705 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
9706 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
9707 if (tg3_run_loopback(tp
, TG3_PHY_LOOPBACK
))
9708 err
|= TG3_PHY_LOOPBACK_FAILED
;
9711 /* Re-enable gphy autopowerdown. */
9712 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
9713 tg3_phy_toggle_apd(tp
, true);
9718 static void tg3_self_test(struct net_device
*dev
, struct ethtool_test
*etest
,
9721 struct tg3
*tp
= netdev_priv(dev
);
9723 if (tp
->link_config
.phy_is_low_power
)
9724 tg3_set_power_state(tp
, PCI_D0
);
9726 memset(data
, 0, sizeof(u64
) * TG3_NUM_TEST
);
9728 if (tg3_test_nvram(tp
) != 0) {
9729 etest
->flags
|= ETH_TEST_FL_FAILED
;
9732 if (tg3_test_link(tp
) != 0) {
9733 etest
->flags
|= ETH_TEST_FL_FAILED
;
9736 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
9737 int err
, err2
= 0, irq_sync
= 0;
9739 if (netif_running(dev
)) {
9745 tg3_full_lock(tp
, irq_sync
);
9747 tg3_halt(tp
, RESET_KIND_SUSPEND
, 1);
9748 err
= tg3_nvram_lock(tp
);
9749 tg3_halt_cpu(tp
, RX_CPU_BASE
);
9750 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
9751 tg3_halt_cpu(tp
, TX_CPU_BASE
);
9753 tg3_nvram_unlock(tp
);
9755 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
9758 if (tg3_test_registers(tp
) != 0) {
9759 etest
->flags
|= ETH_TEST_FL_FAILED
;
9762 if (tg3_test_memory(tp
) != 0) {
9763 etest
->flags
|= ETH_TEST_FL_FAILED
;
9766 if ((data
[4] = tg3_test_loopback(tp
)) != 0)
9767 etest
->flags
|= ETH_TEST_FL_FAILED
;
9769 tg3_full_unlock(tp
);
9771 if (tg3_test_interrupt(tp
) != 0) {
9772 etest
->flags
|= ETH_TEST_FL_FAILED
;
9776 tg3_full_lock(tp
, 0);
9778 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9779 if (netif_running(dev
)) {
9780 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
9781 err2
= tg3_restart_hw(tp
, 1);
9783 tg3_netif_start(tp
);
9786 tg3_full_unlock(tp
);
9788 if (irq_sync
&& !err2
)
9791 if (tp
->link_config
.phy_is_low_power
)
9792 tg3_set_power_state(tp
, PCI_D3hot
);
9796 static int tg3_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
9798 struct mii_ioctl_data
*data
= if_mii(ifr
);
9799 struct tg3
*tp
= netdev_priv(dev
);
9802 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9803 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9805 return phy_mii_ioctl(tp
->mdio_bus
->phy_map
[PHY_ADDR
], data
, cmd
);
9810 data
->phy_id
= PHY_ADDR
;
9816 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
9817 break; /* We have no PHY */
9819 if (tp
->link_config
.phy_is_low_power
)
9822 spin_lock_bh(&tp
->lock
);
9823 err
= tg3_readphy(tp
, data
->reg_num
& 0x1f, &mii_regval
);
9824 spin_unlock_bh(&tp
->lock
);
9826 data
->val_out
= mii_regval
;
9832 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
9833 break; /* We have no PHY */
9835 if (!capable(CAP_NET_ADMIN
))
9838 if (tp
->link_config
.phy_is_low_power
)
9841 spin_lock_bh(&tp
->lock
);
9842 err
= tg3_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
9843 spin_unlock_bh(&tp
->lock
);
9854 #if TG3_VLAN_TAG_USED
9855 static void tg3_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
9857 struct tg3
*tp
= netdev_priv(dev
);
9859 if (netif_running(dev
))
9862 tg3_full_lock(tp
, 0);
9866 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9867 __tg3_set_rx_mode(dev
);
9869 if (netif_running(dev
))
9870 tg3_netif_start(tp
);
9872 tg3_full_unlock(tp
);
9876 static int tg3_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
9878 struct tg3
*tp
= netdev_priv(dev
);
9880 memcpy(ec
, &tp
->coal
, sizeof(*ec
));
9884 static int tg3_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
9886 struct tg3
*tp
= netdev_priv(dev
);
9887 u32 max_rxcoal_tick_int
= 0, max_txcoal_tick_int
= 0;
9888 u32 max_stat_coal_ticks
= 0, min_stat_coal_ticks
= 0;
9890 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
9891 max_rxcoal_tick_int
= MAX_RXCOAL_TICK_INT
;
9892 max_txcoal_tick_int
= MAX_TXCOAL_TICK_INT
;
9893 max_stat_coal_ticks
= MAX_STAT_COAL_TICKS
;
9894 min_stat_coal_ticks
= MIN_STAT_COAL_TICKS
;
9897 if ((ec
->rx_coalesce_usecs
> MAX_RXCOL_TICKS
) ||
9898 (ec
->tx_coalesce_usecs
> MAX_TXCOL_TICKS
) ||
9899 (ec
->rx_max_coalesced_frames
> MAX_RXMAX_FRAMES
) ||
9900 (ec
->tx_max_coalesced_frames
> MAX_TXMAX_FRAMES
) ||
9901 (ec
->rx_coalesce_usecs_irq
> max_rxcoal_tick_int
) ||
9902 (ec
->tx_coalesce_usecs_irq
> max_txcoal_tick_int
) ||
9903 (ec
->rx_max_coalesced_frames_irq
> MAX_RXCOAL_MAXF_INT
) ||
9904 (ec
->tx_max_coalesced_frames_irq
> MAX_TXCOAL_MAXF_INT
) ||
9905 (ec
->stats_block_coalesce_usecs
> max_stat_coal_ticks
) ||
9906 (ec
->stats_block_coalesce_usecs
< min_stat_coal_ticks
))
9909 /* No rx interrupts will be generated if both are zero */
9910 if ((ec
->rx_coalesce_usecs
== 0) &&
9911 (ec
->rx_max_coalesced_frames
== 0))
9914 /* No tx interrupts will be generated if both are zero */
9915 if ((ec
->tx_coalesce_usecs
== 0) &&
9916 (ec
->tx_max_coalesced_frames
== 0))
9919 /* Only copy relevant parameters, ignore all others. */
9920 tp
->coal
.rx_coalesce_usecs
= ec
->rx_coalesce_usecs
;
9921 tp
->coal
.tx_coalesce_usecs
= ec
->tx_coalesce_usecs
;
9922 tp
->coal
.rx_max_coalesced_frames
= ec
->rx_max_coalesced_frames
;
9923 tp
->coal
.tx_max_coalesced_frames
= ec
->tx_max_coalesced_frames
;
9924 tp
->coal
.rx_coalesce_usecs_irq
= ec
->rx_coalesce_usecs_irq
;
9925 tp
->coal
.tx_coalesce_usecs_irq
= ec
->tx_coalesce_usecs_irq
;
9926 tp
->coal
.rx_max_coalesced_frames_irq
= ec
->rx_max_coalesced_frames_irq
;
9927 tp
->coal
.tx_max_coalesced_frames_irq
= ec
->tx_max_coalesced_frames_irq
;
9928 tp
->coal
.stats_block_coalesce_usecs
= ec
->stats_block_coalesce_usecs
;
9930 if (netif_running(dev
)) {
9931 tg3_full_lock(tp
, 0);
9932 __tg3_set_coalesce(tp
, &tp
->coal
);
9933 tg3_full_unlock(tp
);
9938 static const struct ethtool_ops tg3_ethtool_ops
= {
9939 .get_settings
= tg3_get_settings
,
9940 .set_settings
= tg3_set_settings
,
9941 .get_drvinfo
= tg3_get_drvinfo
,
9942 .get_regs_len
= tg3_get_regs_len
,
9943 .get_regs
= tg3_get_regs
,
9944 .get_wol
= tg3_get_wol
,
9945 .set_wol
= tg3_set_wol
,
9946 .get_msglevel
= tg3_get_msglevel
,
9947 .set_msglevel
= tg3_set_msglevel
,
9948 .nway_reset
= tg3_nway_reset
,
9949 .get_link
= ethtool_op_get_link
,
9950 .get_eeprom_len
= tg3_get_eeprom_len
,
9951 .get_eeprom
= tg3_get_eeprom
,
9952 .set_eeprom
= tg3_set_eeprom
,
9953 .get_ringparam
= tg3_get_ringparam
,
9954 .set_ringparam
= tg3_set_ringparam
,
9955 .get_pauseparam
= tg3_get_pauseparam
,
9956 .set_pauseparam
= tg3_set_pauseparam
,
9957 .get_rx_csum
= tg3_get_rx_csum
,
9958 .set_rx_csum
= tg3_set_rx_csum
,
9959 .set_tx_csum
= tg3_set_tx_csum
,
9960 .set_sg
= ethtool_op_set_sg
,
9961 .set_tso
= tg3_set_tso
,
9962 .self_test
= tg3_self_test
,
9963 .get_strings
= tg3_get_strings
,
9964 .phys_id
= tg3_phys_id
,
9965 .get_ethtool_stats
= tg3_get_ethtool_stats
,
9966 .get_coalesce
= tg3_get_coalesce
,
9967 .set_coalesce
= tg3_set_coalesce
,
9968 .get_sset_count
= tg3_get_sset_count
,
9971 static void __devinit
tg3_get_eeprom_size(struct tg3
*tp
)
9973 u32 cursize
, val
, magic
;
9975 tp
->nvram_size
= EEPROM_CHIP_SIZE
;
9977 if (tg3_nvram_read_swab(tp
, 0, &magic
) != 0)
9980 if ((magic
!= TG3_EEPROM_MAGIC
) &&
9981 ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) != TG3_EEPROM_MAGIC_FW
) &&
9982 ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) != TG3_EEPROM_MAGIC_HW
))
9986 * Size the chip by reading offsets at increasing powers of two.
9987 * When we encounter our validation signature, we know the addressing
9988 * has wrapped around, and thus have our chip size.
9992 while (cursize
< tp
->nvram_size
) {
9993 if (tg3_nvram_read_swab(tp
, cursize
, &val
) != 0)
10002 tp
->nvram_size
= cursize
;
10005 static void __devinit
tg3_get_nvram_size(struct tg3
*tp
)
10009 if (tg3_nvram_read_swab(tp
, 0, &val
) != 0)
10012 /* Selfboot format */
10013 if (val
!= TG3_EEPROM_MAGIC
) {
10014 tg3_get_eeprom_size(tp
);
10018 if (tg3_nvram_read(tp
, 0xf0, &val
) == 0) {
10020 tp
->nvram_size
= (val
>> 16) * 1024;
10024 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10027 static void __devinit
tg3_get_nvram_info(struct tg3
*tp
)
10031 nvcfg1
= tr32(NVRAM_CFG1
);
10032 if (nvcfg1
& NVRAM_CFG1_FLASHIF_ENAB
) {
10033 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10036 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10037 tw32(NVRAM_CFG1
, nvcfg1
);
10040 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) ||
10041 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
10042 switch (nvcfg1
& NVRAM_CFG1_VENDOR_MASK
) {
10043 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED
:
10044 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10045 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
10046 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10048 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED
:
10049 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10050 tp
->nvram_pagesize
= ATMEL_AT25F512_PAGE_SIZE
;
10052 case FLASH_VENDOR_ATMEL_EEPROM
:
10053 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10054 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10055 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10057 case FLASH_VENDOR_ST
:
10058 tp
->nvram_jedecnum
= JEDEC_ST
;
10059 tp
->nvram_pagesize
= ST_M45PEX0_PAGE_SIZE
;
10060 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10062 case FLASH_VENDOR_SAIFUN
:
10063 tp
->nvram_jedecnum
= JEDEC_SAIFUN
;
10064 tp
->nvram_pagesize
= SAIFUN_SA25F0XX_PAGE_SIZE
;
10066 case FLASH_VENDOR_SST_SMALL
:
10067 case FLASH_VENDOR_SST_LARGE
:
10068 tp
->nvram_jedecnum
= JEDEC_SST
;
10069 tp
->nvram_pagesize
= SST_25VF0X0_PAGE_SIZE
;
10074 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10075 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
10076 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10080 static void __devinit
tg3_get_5752_nvram_info(struct tg3
*tp
)
10084 nvcfg1
= tr32(NVRAM_CFG1
);
10086 /* NVRAM protection for TPM */
10087 if (nvcfg1
& (1 << 27))
10088 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
10090 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10091 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ
:
10092 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ
:
10093 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10094 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10096 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10097 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10098 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10099 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10101 case FLASH_5752VENDOR_ST_M45PE10
:
10102 case FLASH_5752VENDOR_ST_M45PE20
:
10103 case FLASH_5752VENDOR_ST_M45PE40
:
10104 tp
->nvram_jedecnum
= JEDEC_ST
;
10105 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10106 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10110 if (tp
->tg3_flags2
& TG3_FLG2_FLASH
) {
10111 switch (nvcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
10112 case FLASH_5752PAGE_SIZE_256
:
10113 tp
->nvram_pagesize
= 256;
10115 case FLASH_5752PAGE_SIZE_512
:
10116 tp
->nvram_pagesize
= 512;
10118 case FLASH_5752PAGE_SIZE_1K
:
10119 tp
->nvram_pagesize
= 1024;
10121 case FLASH_5752PAGE_SIZE_2K
:
10122 tp
->nvram_pagesize
= 2048;
10124 case FLASH_5752PAGE_SIZE_4K
:
10125 tp
->nvram_pagesize
= 4096;
10127 case FLASH_5752PAGE_SIZE_264
:
10128 tp
->nvram_pagesize
= 264;
10133 /* For eeprom, set pagesize to maximum eeprom size */
10134 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10136 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10137 tw32(NVRAM_CFG1
, nvcfg1
);
10141 static void __devinit
tg3_get_5755_nvram_info(struct tg3
*tp
)
10143 u32 nvcfg1
, protect
= 0;
10145 nvcfg1
= tr32(NVRAM_CFG1
);
10147 /* NVRAM protection for TPM */
10148 if (nvcfg1
& (1 << 27)) {
10149 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
10153 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
10155 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
10156 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
10157 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
10158 case FLASH_5755VENDOR_ATMEL_FLASH_5
:
10159 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10160 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10161 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10162 tp
->nvram_pagesize
= 264;
10163 if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_1
||
10164 nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_5
)
10165 tp
->nvram_size
= (protect
? 0x3e200 :
10166 TG3_NVRAM_SIZE_512KB
);
10167 else if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_2
)
10168 tp
->nvram_size
= (protect
? 0x1f200 :
10169 TG3_NVRAM_SIZE_256KB
);
10171 tp
->nvram_size
= (protect
? 0x1f200 :
10172 TG3_NVRAM_SIZE_128KB
);
10174 case FLASH_5752VENDOR_ST_M45PE10
:
10175 case FLASH_5752VENDOR_ST_M45PE20
:
10176 case FLASH_5752VENDOR_ST_M45PE40
:
10177 tp
->nvram_jedecnum
= JEDEC_ST
;
10178 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10179 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10180 tp
->nvram_pagesize
= 256;
10181 if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE10
)
10182 tp
->nvram_size
= (protect
?
10183 TG3_NVRAM_SIZE_64KB
:
10184 TG3_NVRAM_SIZE_128KB
);
10185 else if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE20
)
10186 tp
->nvram_size
= (protect
?
10187 TG3_NVRAM_SIZE_64KB
:
10188 TG3_NVRAM_SIZE_256KB
);
10190 tp
->nvram_size
= (protect
?
10191 TG3_NVRAM_SIZE_128KB
:
10192 TG3_NVRAM_SIZE_512KB
);
10197 static void __devinit
tg3_get_5787_nvram_info(struct tg3
*tp
)
10201 nvcfg1
= tr32(NVRAM_CFG1
);
10203 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10204 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ
:
10205 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
10206 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ
:
10207 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
10208 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10209 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10210 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10212 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10213 tw32(NVRAM_CFG1
, nvcfg1
);
10215 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10216 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
10217 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
10218 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
10219 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10220 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10221 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10222 tp
->nvram_pagesize
= 264;
10224 case FLASH_5752VENDOR_ST_M45PE10
:
10225 case FLASH_5752VENDOR_ST_M45PE20
:
10226 case FLASH_5752VENDOR_ST_M45PE40
:
10227 tp
->nvram_jedecnum
= JEDEC_ST
;
10228 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10229 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10230 tp
->nvram_pagesize
= 256;
10235 static void __devinit
tg3_get_5761_nvram_info(struct tg3
*tp
)
10237 u32 nvcfg1
, protect
= 0;
10239 nvcfg1
= tr32(NVRAM_CFG1
);
10241 /* NVRAM protection for TPM */
10242 if (nvcfg1
& (1 << 27)) {
10243 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
10247 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
10249 case FLASH_5761VENDOR_ATMEL_ADB021D
:
10250 case FLASH_5761VENDOR_ATMEL_ADB041D
:
10251 case FLASH_5761VENDOR_ATMEL_ADB081D
:
10252 case FLASH_5761VENDOR_ATMEL_ADB161D
:
10253 case FLASH_5761VENDOR_ATMEL_MDB021D
:
10254 case FLASH_5761VENDOR_ATMEL_MDB041D
:
10255 case FLASH_5761VENDOR_ATMEL_MDB081D
:
10256 case FLASH_5761VENDOR_ATMEL_MDB161D
:
10257 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10258 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10259 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10260 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10261 tp
->nvram_pagesize
= 256;
10263 case FLASH_5761VENDOR_ST_A_M45PE20
:
10264 case FLASH_5761VENDOR_ST_A_M45PE40
:
10265 case FLASH_5761VENDOR_ST_A_M45PE80
:
10266 case FLASH_5761VENDOR_ST_A_M45PE16
:
10267 case FLASH_5761VENDOR_ST_M_M45PE20
:
10268 case FLASH_5761VENDOR_ST_M_M45PE40
:
10269 case FLASH_5761VENDOR_ST_M_M45PE80
:
10270 case FLASH_5761VENDOR_ST_M_M45PE16
:
10271 tp
->nvram_jedecnum
= JEDEC_ST
;
10272 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10273 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10274 tp
->nvram_pagesize
= 256;
10279 tp
->nvram_size
= tr32(NVRAM_ADDR_LOCKOUT
);
10282 case FLASH_5761VENDOR_ATMEL_ADB161D
:
10283 case FLASH_5761VENDOR_ATMEL_MDB161D
:
10284 case FLASH_5761VENDOR_ST_A_M45PE16
:
10285 case FLASH_5761VENDOR_ST_M_M45PE16
:
10286 tp
->nvram_size
= TG3_NVRAM_SIZE_2MB
;
10288 case FLASH_5761VENDOR_ATMEL_ADB081D
:
10289 case FLASH_5761VENDOR_ATMEL_MDB081D
:
10290 case FLASH_5761VENDOR_ST_A_M45PE80
:
10291 case FLASH_5761VENDOR_ST_M_M45PE80
:
10292 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
10294 case FLASH_5761VENDOR_ATMEL_ADB041D
:
10295 case FLASH_5761VENDOR_ATMEL_MDB041D
:
10296 case FLASH_5761VENDOR_ST_A_M45PE40
:
10297 case FLASH_5761VENDOR_ST_M_M45PE40
:
10298 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10300 case FLASH_5761VENDOR_ATMEL_ADB021D
:
10301 case FLASH_5761VENDOR_ATMEL_MDB021D
:
10302 case FLASH_5761VENDOR_ST_A_M45PE20
:
10303 case FLASH_5761VENDOR_ST_M_M45PE20
:
10304 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
10310 static void __devinit
tg3_get_5906_nvram_info(struct tg3
*tp
)
10312 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10313 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10314 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10317 static void __devinit
tg3_get_57780_nvram_info(struct tg3
*tp
)
10321 nvcfg1
= tr32(NVRAM_CFG1
);
10323 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10324 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
10325 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
10326 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10327 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10328 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10330 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10331 tw32(NVRAM_CFG1
, nvcfg1
);
10333 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10334 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
10335 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
10336 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
10337 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
10338 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
10339 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
10340 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10341 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10342 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10344 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10345 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10346 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
10347 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
10348 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
10350 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
10351 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
10352 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
10354 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
10355 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
10356 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10360 case FLASH_5752VENDOR_ST_M45PE10
:
10361 case FLASH_5752VENDOR_ST_M45PE20
:
10362 case FLASH_5752VENDOR_ST_M45PE40
:
10363 tp
->nvram_jedecnum
= JEDEC_ST
;
10364 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10365 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10367 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10368 case FLASH_5752VENDOR_ST_M45PE10
:
10369 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
10371 case FLASH_5752VENDOR_ST_M45PE20
:
10372 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
10374 case FLASH_5752VENDOR_ST_M45PE40
:
10375 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10383 switch (nvcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
10384 case FLASH_5752PAGE_SIZE_256
:
10385 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10386 tp
->nvram_pagesize
= 256;
10388 case FLASH_5752PAGE_SIZE_512
:
10389 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10390 tp
->nvram_pagesize
= 512;
10392 case FLASH_5752PAGE_SIZE_1K
:
10393 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10394 tp
->nvram_pagesize
= 1024;
10396 case FLASH_5752PAGE_SIZE_2K
:
10397 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10398 tp
->nvram_pagesize
= 2048;
10400 case FLASH_5752PAGE_SIZE_4K
:
10401 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10402 tp
->nvram_pagesize
= 4096;
10404 case FLASH_5752PAGE_SIZE_264
:
10405 tp
->nvram_pagesize
= 264;
10407 case FLASH_5752PAGE_SIZE_528
:
10408 tp
->nvram_pagesize
= 528;
10413 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10414 static void __devinit
tg3_nvram_init(struct tg3
*tp
)
10416 tw32_f(GRC_EEPROM_ADDR
,
10417 (EEPROM_ADDR_FSM_RESET
|
10418 (EEPROM_DEFAULT_CLOCK_PERIOD
<<
10419 EEPROM_ADDR_CLKPERD_SHIFT
)));
10423 /* Enable seeprom accesses. */
10424 tw32_f(GRC_LOCAL_CTRL
,
10425 tr32(GRC_LOCAL_CTRL
) | GRC_LCLCTRL_AUTO_SEEPROM
);
10428 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
10429 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
10430 tp
->tg3_flags
|= TG3_FLAG_NVRAM
;
10432 if (tg3_nvram_lock(tp
)) {
10433 printk(KERN_WARNING PFX
"%s: Cannot get nvarm lock, "
10434 "tg3_nvram_init failed.\n", tp
->dev
->name
);
10437 tg3_enable_nvram_access(tp
);
10439 tp
->nvram_size
= 0;
10441 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
10442 tg3_get_5752_nvram_info(tp
);
10443 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
10444 tg3_get_5755_nvram_info(tp
);
10445 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
10446 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
10447 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
10448 tg3_get_5787_nvram_info(tp
);
10449 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
10450 tg3_get_5761_nvram_info(tp
);
10451 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
10452 tg3_get_5906_nvram_info(tp
);
10453 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
10454 tg3_get_57780_nvram_info(tp
);
10456 tg3_get_nvram_info(tp
);
10458 if (tp
->nvram_size
== 0)
10459 tg3_get_nvram_size(tp
);
10461 tg3_disable_nvram_access(tp
);
10462 tg3_nvram_unlock(tp
);
10465 tp
->tg3_flags
&= ~(TG3_FLAG_NVRAM
| TG3_FLAG_NVRAM_BUFFERED
);
10467 tg3_get_eeprom_size(tp
);
10471 static int tg3_nvram_read_using_eeprom(struct tg3
*tp
,
10472 u32 offset
, u32
*val
)
10477 if (offset
> EEPROM_ADDR_ADDR_MASK
||
10481 tmp
= tr32(GRC_EEPROM_ADDR
) & ~(EEPROM_ADDR_ADDR_MASK
|
10482 EEPROM_ADDR_DEVID_MASK
|
10484 tw32(GRC_EEPROM_ADDR
,
10486 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
10487 ((offset
<< EEPROM_ADDR_ADDR_SHIFT
) &
10488 EEPROM_ADDR_ADDR_MASK
) |
10489 EEPROM_ADDR_READ
| EEPROM_ADDR_START
);
10491 for (i
= 0; i
< 1000; i
++) {
10492 tmp
= tr32(GRC_EEPROM_ADDR
);
10494 if (tmp
& EEPROM_ADDR_COMPLETE
)
10498 if (!(tmp
& EEPROM_ADDR_COMPLETE
))
10501 *val
= tr32(GRC_EEPROM_DATA
);
10505 #define NVRAM_CMD_TIMEOUT 10000
10507 static int tg3_nvram_exec_cmd(struct tg3
*tp
, u32 nvram_cmd
)
10511 tw32(NVRAM_CMD
, nvram_cmd
);
10512 for (i
= 0; i
< NVRAM_CMD_TIMEOUT
; i
++) {
10514 if (tr32(NVRAM_CMD
) & NVRAM_CMD_DONE
) {
10519 if (i
== NVRAM_CMD_TIMEOUT
) {
10525 static u32
tg3_nvram_phys_addr(struct tg3
*tp
, u32 addr
)
10527 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
10528 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
10529 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
10530 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
10531 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
10533 addr
= ((addr
/ tp
->nvram_pagesize
) <<
10534 ATMEL_AT45DB0X1B_PAGE_POS
) +
10535 (addr
% tp
->nvram_pagesize
);
10540 static u32
tg3_nvram_logical_addr(struct tg3
*tp
, u32 addr
)
10542 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
10543 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
10544 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
10545 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
10546 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
10548 addr
= ((addr
>> ATMEL_AT45DB0X1B_PAGE_POS
) *
10549 tp
->nvram_pagesize
) +
10550 (addr
& ((1 << ATMEL_AT45DB0X1B_PAGE_POS
) - 1));
10555 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
)
10559 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
))
10560 return tg3_nvram_read_using_eeprom(tp
, offset
, val
);
10562 offset
= tg3_nvram_phys_addr(tp
, offset
);
10564 if (offset
> NVRAM_ADDR_MSK
)
10567 ret
= tg3_nvram_lock(tp
);
10571 tg3_enable_nvram_access(tp
);
10573 tw32(NVRAM_ADDR
, offset
);
10574 ret
= tg3_nvram_exec_cmd(tp
, NVRAM_CMD_RD
| NVRAM_CMD_GO
|
10575 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_DONE
);
10578 *val
= swab32(tr32(NVRAM_RDDATA
));
10580 tg3_disable_nvram_access(tp
);
10582 tg3_nvram_unlock(tp
);
10587 static int tg3_nvram_read_le(struct tg3
*tp
, u32 offset
, __le32
*val
)
10590 int res
= tg3_nvram_read(tp
, offset
, &v
);
10592 *val
= cpu_to_le32(v
);
10596 static int tg3_nvram_read_swab(struct tg3
*tp
, u32 offset
, u32
*val
)
10601 err
= tg3_nvram_read(tp
, offset
, &tmp
);
10602 *val
= swab32(tmp
);
10606 static int tg3_nvram_write_block_using_eeprom(struct tg3
*tp
,
10607 u32 offset
, u32 len
, u8
*buf
)
10612 for (i
= 0; i
< len
; i
+= 4) {
10618 memcpy(&data
, buf
+ i
, 4);
10620 tw32(GRC_EEPROM_DATA
, le32_to_cpu(data
));
10622 val
= tr32(GRC_EEPROM_ADDR
);
10623 tw32(GRC_EEPROM_ADDR
, val
| EEPROM_ADDR_COMPLETE
);
10625 val
&= ~(EEPROM_ADDR_ADDR_MASK
| EEPROM_ADDR_DEVID_MASK
|
10627 tw32(GRC_EEPROM_ADDR
, val
|
10628 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
10629 (addr
& EEPROM_ADDR_ADDR_MASK
) |
10630 EEPROM_ADDR_START
|
10631 EEPROM_ADDR_WRITE
);
10633 for (j
= 0; j
< 1000; j
++) {
10634 val
= tr32(GRC_EEPROM_ADDR
);
10636 if (val
& EEPROM_ADDR_COMPLETE
)
10640 if (!(val
& EEPROM_ADDR_COMPLETE
)) {
10649 /* offset and length are dword aligned */
10650 static int tg3_nvram_write_block_unbuffered(struct tg3
*tp
, u32 offset
, u32 len
,
10654 u32 pagesize
= tp
->nvram_pagesize
;
10655 u32 pagemask
= pagesize
- 1;
10659 tmp
= kmalloc(pagesize
, GFP_KERNEL
);
10665 u32 phy_addr
, page_off
, size
;
10667 phy_addr
= offset
& ~pagemask
;
10669 for (j
= 0; j
< pagesize
; j
+= 4) {
10670 if ((ret
= tg3_nvram_read_le(tp
, phy_addr
+ j
,
10671 (__le32
*) (tmp
+ j
))))
10677 page_off
= offset
& pagemask
;
10684 memcpy(tmp
+ page_off
, buf
, size
);
10686 offset
= offset
+ (pagesize
- page_off
);
10688 tg3_enable_nvram_access(tp
);
10691 * Before we can erase the flash page, we need
10692 * to issue a special "write enable" command.
10694 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
10696 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
10699 /* Erase the target page */
10700 tw32(NVRAM_ADDR
, phy_addr
);
10702 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
|
10703 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_ERASE
;
10705 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
10708 /* Issue another write enable to start the write. */
10709 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
10711 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
10714 for (j
= 0; j
< pagesize
; j
+= 4) {
10717 data
= *((__be32
*) (tmp
+ j
));
10718 /* swab32(le32_to_cpu(data)), actually */
10719 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
10721 tw32(NVRAM_ADDR
, phy_addr
+ j
);
10723 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
|
10727 nvram_cmd
|= NVRAM_CMD_FIRST
;
10728 else if (j
== (pagesize
- 4))
10729 nvram_cmd
|= NVRAM_CMD_LAST
;
10731 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
10738 nvram_cmd
= NVRAM_CMD_WRDI
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
10739 tg3_nvram_exec_cmd(tp
, nvram_cmd
);
10746 /* offset and length are dword aligned */
10747 static int tg3_nvram_write_block_buffered(struct tg3
*tp
, u32 offset
, u32 len
,
10752 for (i
= 0; i
< len
; i
+= 4, offset
+= 4) {
10753 u32 page_off
, phy_addr
, nvram_cmd
;
10756 memcpy(&data
, buf
+ i
, 4);
10757 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
10759 page_off
= offset
% tp
->nvram_pagesize
;
10761 phy_addr
= tg3_nvram_phys_addr(tp
, offset
);
10763 tw32(NVRAM_ADDR
, phy_addr
);
10765 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
;
10767 if ((page_off
== 0) || (i
== 0))
10768 nvram_cmd
|= NVRAM_CMD_FIRST
;
10769 if (page_off
== (tp
->nvram_pagesize
- 4))
10770 nvram_cmd
|= NVRAM_CMD_LAST
;
10772 if (i
== (len
- 4))
10773 nvram_cmd
|= NVRAM_CMD_LAST
;
10775 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5752
&&
10776 !(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
10777 (tp
->nvram_jedecnum
== JEDEC_ST
) &&
10778 (nvram_cmd
& NVRAM_CMD_FIRST
)) {
10780 if ((ret
= tg3_nvram_exec_cmd(tp
,
10781 NVRAM_CMD_WREN
| NVRAM_CMD_GO
|
10786 if (!(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
10787 /* We always do complete word writes to eeprom. */
10788 nvram_cmd
|= (NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
);
10791 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
10797 /* offset and length are dword aligned */
10798 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
)
10802 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
10803 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
&
10804 ~GRC_LCLCTRL_GPIO_OUTPUT1
);
10808 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
)) {
10809 ret
= tg3_nvram_write_block_using_eeprom(tp
, offset
, len
, buf
);
10814 ret
= tg3_nvram_lock(tp
);
10818 tg3_enable_nvram_access(tp
);
10819 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
10820 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
))
10821 tw32(NVRAM_WRITE1
, 0x406);
10823 grc_mode
= tr32(GRC_MODE
);
10824 tw32(GRC_MODE
, grc_mode
| GRC_MODE_NVRAM_WR_ENABLE
);
10826 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) ||
10827 !(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
10829 ret
= tg3_nvram_write_block_buffered(tp
, offset
, len
,
10833 ret
= tg3_nvram_write_block_unbuffered(tp
, offset
, len
,
10837 grc_mode
= tr32(GRC_MODE
);
10838 tw32(GRC_MODE
, grc_mode
& ~GRC_MODE_NVRAM_WR_ENABLE
);
10840 tg3_disable_nvram_access(tp
);
10841 tg3_nvram_unlock(tp
);
10844 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
10845 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
10852 struct subsys_tbl_ent
{
10853 u16 subsys_vendor
, subsys_devid
;
10857 static struct subsys_tbl_ent subsys_id_to_phy_id
[] = {
10858 /* Broadcom boards. */
10859 { PCI_VENDOR_ID_BROADCOM
, 0x1644, PHY_ID_BCM5401
}, /* BCM95700A6 */
10860 { PCI_VENDOR_ID_BROADCOM
, 0x0001, PHY_ID_BCM5701
}, /* BCM95701A5 */
10861 { PCI_VENDOR_ID_BROADCOM
, 0x0002, PHY_ID_BCM8002
}, /* BCM95700T6 */
10862 { PCI_VENDOR_ID_BROADCOM
, 0x0003, 0 }, /* BCM95700A9 */
10863 { PCI_VENDOR_ID_BROADCOM
, 0x0005, PHY_ID_BCM5701
}, /* BCM95701T1 */
10864 { PCI_VENDOR_ID_BROADCOM
, 0x0006, PHY_ID_BCM5701
}, /* BCM95701T8 */
10865 { PCI_VENDOR_ID_BROADCOM
, 0x0007, 0 }, /* BCM95701A7 */
10866 { PCI_VENDOR_ID_BROADCOM
, 0x0008, PHY_ID_BCM5701
}, /* BCM95701A10 */
10867 { PCI_VENDOR_ID_BROADCOM
, 0x8008, PHY_ID_BCM5701
}, /* BCM95701A12 */
10868 { PCI_VENDOR_ID_BROADCOM
, 0x0009, PHY_ID_BCM5703
}, /* BCM95703Ax1 */
10869 { PCI_VENDOR_ID_BROADCOM
, 0x8009, PHY_ID_BCM5703
}, /* BCM95703Ax2 */
10872 { PCI_VENDOR_ID_3COM
, 0x1000, PHY_ID_BCM5401
}, /* 3C996T */
10873 { PCI_VENDOR_ID_3COM
, 0x1006, PHY_ID_BCM5701
}, /* 3C996BT */
10874 { PCI_VENDOR_ID_3COM
, 0x1004, 0 }, /* 3C996SX */
10875 { PCI_VENDOR_ID_3COM
, 0x1007, PHY_ID_BCM5701
}, /* 3C1000T */
10876 { PCI_VENDOR_ID_3COM
, 0x1008, PHY_ID_BCM5701
}, /* 3C940BR01 */
10879 { PCI_VENDOR_ID_DELL
, 0x00d1, PHY_ID_BCM5401
}, /* VIPER */
10880 { PCI_VENDOR_ID_DELL
, 0x0106, PHY_ID_BCM5401
}, /* JAGUAR */
10881 { PCI_VENDOR_ID_DELL
, 0x0109, PHY_ID_BCM5411
}, /* MERLOT */
10882 { PCI_VENDOR_ID_DELL
, 0x010a, PHY_ID_BCM5411
}, /* SLIM_MERLOT */
10884 /* Compaq boards. */
10885 { PCI_VENDOR_ID_COMPAQ
, 0x007c, PHY_ID_BCM5701
}, /* BANSHEE */
10886 { PCI_VENDOR_ID_COMPAQ
, 0x009a, PHY_ID_BCM5701
}, /* BANSHEE_2 */
10887 { PCI_VENDOR_ID_COMPAQ
, 0x007d, 0 }, /* CHANGELING */
10888 { PCI_VENDOR_ID_COMPAQ
, 0x0085, PHY_ID_BCM5701
}, /* NC7780 */
10889 { PCI_VENDOR_ID_COMPAQ
, 0x0099, PHY_ID_BCM5701
}, /* NC7780_2 */
10892 { PCI_VENDOR_ID_IBM
, 0x0281, 0 } /* IBM??? */
10895 static inline struct subsys_tbl_ent
*lookup_by_subsys(struct tg3
*tp
)
10899 for (i
= 0; i
< ARRAY_SIZE(subsys_id_to_phy_id
); i
++) {
10900 if ((subsys_id_to_phy_id
[i
].subsys_vendor
==
10901 tp
->pdev
->subsystem_vendor
) &&
10902 (subsys_id_to_phy_id
[i
].subsys_devid
==
10903 tp
->pdev
->subsystem_device
))
10904 return &subsys_id_to_phy_id
[i
];
10909 static void __devinit
tg3_get_eeprom_hw_cfg(struct tg3
*tp
)
10914 /* On some early chips the SRAM cannot be accessed in D3hot state,
10915 * so need make sure we're in D0.
10917 pci_read_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
10918 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
10919 pci_write_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
10922 /* Make sure register accesses (indirect or otherwise)
10923 * will function correctly.
10925 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
10926 tp
->misc_host_ctrl
);
10928 /* The memory arbiter has to be enabled in order for SRAM accesses
10929 * to succeed. Normally on powerup the tg3 chip firmware will make
10930 * sure it is enabled, but other entities such as system netboot
10931 * code might disable it.
10933 val
= tr32(MEMARB_MODE
);
10934 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
10936 tp
->phy_id
= PHY_ID_INVALID
;
10937 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
10939 /* Assume an onboard device and WOL capable by default. */
10940 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
| TG3_FLAG_WOL_CAP
;
10942 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
10943 if (!(tr32(PCIE_TRANSACTION_CFG
) & PCIE_TRANS_CFG_LOM
)) {
10944 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
10945 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
10947 val
= tr32(VCPU_CFGSHDW
);
10948 if (val
& VCPU_CFGSHDW_ASPM_DBNC
)
10949 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
10950 if ((val
& VCPU_CFGSHDW_WOL_ENABLE
) &&
10951 (val
& VCPU_CFGSHDW_WOL_MAGPKT
))
10952 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
10956 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
10957 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
10958 u32 nic_cfg
, led_cfg
;
10959 u32 nic_phy_id
, ver
, cfg2
= 0, cfg4
= 0, eeprom_phy_id
;
10960 int eeprom_phy_serdes
= 0;
10962 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
10963 tp
->nic_sram_data_cfg
= nic_cfg
;
10965 tg3_read_mem(tp
, NIC_SRAM_DATA_VER
, &ver
);
10966 ver
>>= NIC_SRAM_DATA_VER_SHIFT
;
10967 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
) &&
10968 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) &&
10969 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5703
) &&
10970 (ver
> 0) && (ver
< 0x100))
10971 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_2
, &cfg2
);
10973 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
10974 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_4
, &cfg4
);
10976 if ((nic_cfg
& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK
) ==
10977 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER
)
10978 eeprom_phy_serdes
= 1;
10980 tg3_read_mem(tp
, NIC_SRAM_DATA_PHY_ID
, &nic_phy_id
);
10981 if (nic_phy_id
!= 0) {
10982 u32 id1
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID1_MASK
;
10983 u32 id2
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID2_MASK
;
10985 eeprom_phy_id
= (id1
>> 16) << 10;
10986 eeprom_phy_id
|= (id2
& 0xfc00) << 16;
10987 eeprom_phy_id
|= (id2
& 0x03ff) << 0;
10991 tp
->phy_id
= eeprom_phy_id
;
10992 if (eeprom_phy_serdes
) {
10993 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
10994 tp
->tg3_flags2
|= TG3_FLG2_MII_SERDES
;
10996 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
10999 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
11000 led_cfg
= cfg2
& (NIC_SRAM_DATA_CFG_LED_MODE_MASK
|
11001 SHASTA_EXT_LED_MODE_MASK
);
11003 led_cfg
= nic_cfg
& NIC_SRAM_DATA_CFG_LED_MODE_MASK
;
11007 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1
:
11008 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11011 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2
:
11012 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
11015 case NIC_SRAM_DATA_CFG_LED_MODE_MAC
:
11016 tp
->led_ctrl
= LED_CTRL_MODE_MAC
;
11018 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11019 * read on some older 5700/5701 bootcode.
11021 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
11023 GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
11025 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11029 case SHASTA_EXT_LED_SHARED
:
11030 tp
->led_ctrl
= LED_CTRL_MODE_SHARED
;
11031 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
11032 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A1
)
11033 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
11034 LED_CTRL_MODE_PHY_2
);
11037 case SHASTA_EXT_LED_MAC
:
11038 tp
->led_ctrl
= LED_CTRL_MODE_SHASTA_MAC
;
11041 case SHASTA_EXT_LED_COMBO
:
11042 tp
->led_ctrl
= LED_CTRL_MODE_COMBO
;
11043 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
)
11044 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
11045 LED_CTRL_MODE_PHY_2
);
11050 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
11051 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) &&
11052 tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
11053 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
11055 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
)
11056 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11058 if (nic_cfg
& NIC_SRAM_DATA_CFG_EEPROM_WP
) {
11059 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
;
11060 if ((tp
->pdev
->subsystem_vendor
==
11061 PCI_VENDOR_ID_ARIMA
) &&
11062 (tp
->pdev
->subsystem_device
== 0x205a ||
11063 tp
->pdev
->subsystem_device
== 0x2063))
11064 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
11066 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
11067 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
11070 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
11071 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
11072 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
11073 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
11076 if ((nic_cfg
& NIC_SRAM_DATA_CFG_APE_ENABLE
) &&
11077 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
11078 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_APE
;
11080 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
&&
11081 !(nic_cfg
& NIC_SRAM_DATA_CFG_FIBER_WOL
))
11082 tp
->tg3_flags
&= ~TG3_FLAG_WOL_CAP
;
11084 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
11085 (nic_cfg
& NIC_SRAM_DATA_CFG_WOL_ENABLE
))
11086 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
11088 if (cfg2
& (1 << 17))
11089 tp
->tg3_flags2
|= TG3_FLG2_CAPACITIVE_COUPLING
;
11091 /* serdes signal pre-emphasis in register 0x590 set by */
11092 /* bootcode if bit 18 is set */
11093 if (cfg2
& (1 << 18))
11094 tp
->tg3_flags2
|= TG3_FLG2_SERDES_PREEMPHASIS
;
11096 if (((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
11097 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
)) &&
11098 (cfg2
& NIC_SRAM_DATA_CFG_2_APD_EN
))
11099 tp
->tg3_flags3
|= TG3_FLG3_PHY_ENABLE_APD
;
11101 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
11104 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_3
, &cfg3
);
11105 if (cfg3
& NIC_SRAM_ASPM_DEBOUNCE
)
11106 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
11109 if (cfg4
& NIC_SRAM_RGMII_STD_IBND_DISABLE
)
11110 tp
->tg3_flags3
|= TG3_FLG3_RGMII_STD_IBND_DISABLE
;
11111 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_RX_EN
)
11112 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_RX_EN
;
11113 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_TX_EN
)
11114 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_TX_EN
;
11117 device_init_wakeup(&tp
->pdev
->dev
, tp
->tg3_flags
& TG3_FLAG_WOL_CAP
);
11118 device_set_wakeup_enable(&tp
->pdev
->dev
,
11119 tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
11122 static int __devinit
tg3_issue_otp_command(struct tg3
*tp
, u32 cmd
)
11127 tw32(OTP_CTRL
, cmd
| OTP_CTRL_OTP_CMD_START
);
11128 tw32(OTP_CTRL
, cmd
);
11130 /* Wait for up to 1 ms for command to execute. */
11131 for (i
= 0; i
< 100; i
++) {
11132 val
= tr32(OTP_STATUS
);
11133 if (val
& OTP_STATUS_CMD_DONE
)
11138 return (val
& OTP_STATUS_CMD_DONE
) ? 0 : -EBUSY
;
11141 /* Read the gphy configuration from the OTP region of the chip. The gphy
11142 * configuration is a 32-bit value that straddles the alignment boundary.
11143 * We do two 32-bit reads and then shift and merge the results.
11145 static u32 __devinit
tg3_read_otp_phycfg(struct tg3
*tp
)
11147 u32 bhalf_otp
, thalf_otp
;
11149 tw32(OTP_MODE
, OTP_MODE_OTP_THRU_GRC
);
11151 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_INIT
))
11154 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC1
);
11156 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
11159 thalf_otp
= tr32(OTP_READ_DATA
);
11161 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC2
);
11163 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
11166 bhalf_otp
= tr32(OTP_READ_DATA
);
11168 return ((thalf_otp
& 0x0000ffff) << 16) | (bhalf_otp
>> 16);
11171 static int __devinit
tg3_phy_probe(struct tg3
*tp
)
11173 u32 hw_phy_id_1
, hw_phy_id_2
;
11174 u32 hw_phy_id
, hw_phy_id_masked
;
11177 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
11178 return tg3_phy_init(tp
);
11180 /* Reading the PHY ID register can conflict with ASF
11181 * firwmare access to the PHY hardware.
11184 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
11185 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
11186 hw_phy_id
= hw_phy_id_masked
= PHY_ID_INVALID
;
11188 /* Now read the physical PHY_ID from the chip and verify
11189 * that it is sane. If it doesn't look good, we fall back
11190 * to either the hard-coded table based PHY_ID and failing
11191 * that the value found in the eeprom area.
11193 err
|= tg3_readphy(tp
, MII_PHYSID1
, &hw_phy_id_1
);
11194 err
|= tg3_readphy(tp
, MII_PHYSID2
, &hw_phy_id_2
);
11196 hw_phy_id
= (hw_phy_id_1
& 0xffff) << 10;
11197 hw_phy_id
|= (hw_phy_id_2
& 0xfc00) << 16;
11198 hw_phy_id
|= (hw_phy_id_2
& 0x03ff) << 0;
11200 hw_phy_id_masked
= hw_phy_id
& PHY_ID_MASK
;
11203 if (!err
&& KNOWN_PHY_ID(hw_phy_id_masked
)) {
11204 tp
->phy_id
= hw_phy_id
;
11205 if (hw_phy_id_masked
== PHY_ID_BCM8002
)
11206 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
11208 tp
->tg3_flags2
&= ~TG3_FLG2_PHY_SERDES
;
11210 if (tp
->phy_id
!= PHY_ID_INVALID
) {
11211 /* Do nothing, phy ID already set up in
11212 * tg3_get_eeprom_hw_cfg().
11215 struct subsys_tbl_ent
*p
;
11217 /* No eeprom signature? Try the hardcoded
11218 * subsys device table.
11220 p
= lookup_by_subsys(tp
);
11224 tp
->phy_id
= p
->phy_id
;
11226 tp
->phy_id
== PHY_ID_BCM8002
)
11227 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
11231 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) &&
11232 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) &&
11233 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
11234 u32 bmsr
, adv_reg
, tg3_ctrl
, mask
;
11236 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
11237 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
11238 (bmsr
& BMSR_LSTATUS
))
11239 goto skip_phy_reset
;
11241 err
= tg3_phy_reset(tp
);
11245 adv_reg
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
11246 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
11247 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
11249 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
11250 tg3_ctrl
= (MII_TG3_CTRL_ADV_1000_HALF
|
11251 MII_TG3_CTRL_ADV_1000_FULL
);
11252 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
11253 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
11254 tg3_ctrl
|= (MII_TG3_CTRL_AS_MASTER
|
11255 MII_TG3_CTRL_ENABLE_AS_MASTER
);
11258 mask
= (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
11259 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
11260 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
);
11261 if (!tg3_copper_is_advertising_all(tp
, mask
)) {
11262 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
11264 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
11265 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
11267 tg3_writephy(tp
, MII_BMCR
,
11268 BMCR_ANENABLE
| BMCR_ANRESTART
);
11270 tg3_phy_set_wirespeed(tp
);
11272 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
11273 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
11274 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
11278 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
11279 err
= tg3_init_5401phy_dsp(tp
);
11284 if (!err
&& ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
)) {
11285 err
= tg3_init_5401phy_dsp(tp
);
11288 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
11289 tp
->link_config
.advertising
=
11290 (ADVERTISED_1000baseT_Half
|
11291 ADVERTISED_1000baseT_Full
|
11292 ADVERTISED_Autoneg
|
11294 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
11295 tp
->link_config
.advertising
&=
11296 ~(ADVERTISED_1000baseT_Half
|
11297 ADVERTISED_1000baseT_Full
);
11302 static void __devinit
tg3_read_partno(struct tg3
*tp
)
11304 unsigned char vpd_data
[256];
11308 if (tg3_nvram_read_swab(tp
, 0x0, &magic
))
11309 goto out_not_found
;
11311 if (magic
== TG3_EEPROM_MAGIC
) {
11312 for (i
= 0; i
< 256; i
+= 4) {
11315 if (tg3_nvram_read(tp
, 0x100 + i
, &tmp
))
11316 goto out_not_found
;
11318 vpd_data
[i
+ 0] = ((tmp
>> 0) & 0xff);
11319 vpd_data
[i
+ 1] = ((tmp
>> 8) & 0xff);
11320 vpd_data
[i
+ 2] = ((tmp
>> 16) & 0xff);
11321 vpd_data
[i
+ 3] = ((tmp
>> 24) & 0xff);
11326 vpd_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_VPD
);
11327 for (i
= 0; i
< 256; i
+= 4) {
11332 pci_write_config_word(tp
->pdev
, vpd_cap
+ PCI_VPD_ADDR
,
11334 while (j
++ < 100) {
11335 pci_read_config_word(tp
->pdev
, vpd_cap
+
11336 PCI_VPD_ADDR
, &tmp16
);
11337 if (tmp16
& 0x8000)
11341 if (!(tmp16
& 0x8000))
11342 goto out_not_found
;
11344 pci_read_config_dword(tp
->pdev
, vpd_cap
+ PCI_VPD_DATA
,
11346 v
= cpu_to_le32(tmp
);
11347 memcpy(&vpd_data
[i
], &v
, 4);
11351 /* Now parse and find the part number. */
11352 for (i
= 0; i
< 254; ) {
11353 unsigned char val
= vpd_data
[i
];
11354 unsigned int block_end
;
11356 if (val
== 0x82 || val
== 0x91) {
11359 (vpd_data
[i
+ 2] << 8)));
11364 goto out_not_found
;
11366 block_end
= (i
+ 3 +
11368 (vpd_data
[i
+ 2] << 8)));
11371 if (block_end
> 256)
11372 goto out_not_found
;
11374 while (i
< (block_end
- 2)) {
11375 if (vpd_data
[i
+ 0] == 'P' &&
11376 vpd_data
[i
+ 1] == 'N') {
11377 int partno_len
= vpd_data
[i
+ 2];
11380 if (partno_len
> 24 || (partno_len
+ i
) > 256)
11381 goto out_not_found
;
11383 memcpy(tp
->board_part_number
,
11384 &vpd_data
[i
], partno_len
);
11389 i
+= 3 + vpd_data
[i
+ 2];
11392 /* Part number not found. */
11393 goto out_not_found
;
11397 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
11398 strcpy(tp
->board_part_number
, "BCM95906");
11400 strcpy(tp
->board_part_number
, "none");
11403 static int __devinit
tg3_fw_img_is_valid(struct tg3
*tp
, u32 offset
)
11407 if (tg3_nvram_read_swab(tp
, offset
, &val
) ||
11408 (val
& 0xfc000000) != 0x0c000000 ||
11409 tg3_nvram_read_swab(tp
, offset
+ 4, &val
) ||
11416 static void __devinit
tg3_read_sb_ver(struct tg3
*tp
, u32 val
)
11418 u32 offset
, major
, minor
, build
;
11420 tp
->fw_ver
[0] = 's';
11421 tp
->fw_ver
[1] = 'b';
11422 tp
->fw_ver
[2] = '\0';
11424 if ((val
& TG3_EEPROM_SB_FORMAT_MASK
) != TG3_EEPROM_SB_FORMAT_1
)
11427 switch (val
& TG3_EEPROM_SB_REVISION_MASK
) {
11428 case TG3_EEPROM_SB_REVISION_0
:
11429 offset
= TG3_EEPROM_SB_F1R0_EDH_OFF
;
11431 case TG3_EEPROM_SB_REVISION_2
:
11432 offset
= TG3_EEPROM_SB_F1R2_EDH_OFF
;
11434 case TG3_EEPROM_SB_REVISION_3
:
11435 offset
= TG3_EEPROM_SB_F1R3_EDH_OFF
;
11441 if (tg3_nvram_read_swab(tp
, offset
, &val
))
11444 build
= (val
& TG3_EEPROM_SB_EDH_BLD_MASK
) >>
11445 TG3_EEPROM_SB_EDH_BLD_SHFT
;
11446 major
= (val
& TG3_EEPROM_SB_EDH_MAJ_MASK
) >>
11447 TG3_EEPROM_SB_EDH_MAJ_SHFT
;
11448 minor
= val
& TG3_EEPROM_SB_EDH_MIN_MASK
;
11450 if (minor
> 99 || build
> 26)
11453 snprintf(&tp
->fw_ver
[2], 30, " v%d.%02d", major
, minor
);
11456 tp
->fw_ver
[8] = 'a' + build
- 1;
11457 tp
->fw_ver
[9] = '\0';
11461 static void __devinit
tg3_read_fw_ver(struct tg3
*tp
)
11463 u32 val
, offset
, start
;
11467 if (tg3_nvram_read_swab(tp
, 0, &val
))
11470 if (val
!= TG3_EEPROM_MAGIC
) {
11471 if ((val
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
)
11472 tg3_read_sb_ver(tp
, val
);
11477 if (tg3_nvram_read_swab(tp
, 0xc, &offset
) ||
11478 tg3_nvram_read_swab(tp
, 0x4, &start
))
11481 offset
= tg3_nvram_logical_addr(tp
, offset
);
11483 if (!tg3_fw_img_is_valid(tp
, offset
) ||
11484 tg3_nvram_read_swab(tp
, offset
+ 8, &ver_offset
))
11487 offset
= offset
+ ver_offset
- start
;
11488 for (i
= 0; i
< 16; i
+= 4) {
11490 if (tg3_nvram_read_le(tp
, offset
+ i
, &v
))
11493 memcpy(tp
->fw_ver
+ i
, &v
, 4);
11496 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
11497 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
11500 for (offset
= TG3_NVM_DIR_START
;
11501 offset
< TG3_NVM_DIR_END
;
11502 offset
+= TG3_NVM_DIRENT_SIZE
) {
11503 if (tg3_nvram_read_swab(tp
, offset
, &val
))
11506 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) == TG3_NVM_DIRTYPE_ASFINI
)
11510 if (offset
== TG3_NVM_DIR_END
)
11513 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
11514 start
= 0x08000000;
11515 else if (tg3_nvram_read_swab(tp
, offset
- 4, &start
))
11518 if (tg3_nvram_read_swab(tp
, offset
+ 4, &offset
) ||
11519 !tg3_fw_img_is_valid(tp
, offset
) ||
11520 tg3_nvram_read_swab(tp
, offset
+ 8, &val
))
11523 offset
+= val
- start
;
11525 bcnt
= strlen(tp
->fw_ver
);
11527 tp
->fw_ver
[bcnt
++] = ',';
11528 tp
->fw_ver
[bcnt
++] = ' ';
11530 for (i
= 0; i
< 4; i
++) {
11532 if (tg3_nvram_read_le(tp
, offset
, &v
))
11535 offset
+= sizeof(v
);
11537 if (bcnt
> TG3_VER_SIZE
- sizeof(v
)) {
11538 memcpy(&tp
->fw_ver
[bcnt
], &v
, TG3_VER_SIZE
- bcnt
);
11542 memcpy(&tp
->fw_ver
[bcnt
], &v
, sizeof(v
));
11546 tp
->fw_ver
[TG3_VER_SIZE
- 1] = 0;
11549 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*);
11551 static int __devinit
tg3_get_invariants(struct tg3
*tp
)
11553 static struct pci_device_id write_reorder_chipsets
[] = {
11554 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
11555 PCI_DEVICE_ID_AMD_FE_GATE_700C
) },
11556 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
11557 PCI_DEVICE_ID_AMD_8131_BRIDGE
) },
11558 { PCI_DEVICE(PCI_VENDOR_ID_VIA
,
11559 PCI_DEVICE_ID_VIA_8385_0
) },
11563 u32 pci_state_reg
, grc_misc_cfg
;
11568 /* Force memory write invalidate off. If we leave it on,
11569 * then on 5700_BX chips we have to enable a workaround.
11570 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11571 * to match the cacheline size. The Broadcom driver have this
11572 * workaround but turns MWI off all the times so never uses
11573 * it. This seems to suggest that the workaround is insufficient.
11575 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
11576 pci_cmd
&= ~PCI_COMMAND_INVALIDATE
;
11577 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
11579 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11580 * has the register indirect write enable bit set before
11581 * we try to access any of the MMIO registers. It is also
11582 * critical that the PCI-X hw workaround situation is decided
11583 * before that as well.
11585 pci_read_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
11588 tp
->pci_chip_rev_id
= (misc_ctrl_reg
>>
11589 MISC_HOST_CTRL_CHIPREV_SHIFT
);
11590 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_USE_PROD_ID_REG
) {
11591 u32 prod_id_asic_rev
;
11593 pci_read_config_dword(tp
->pdev
, TG3PCI_PRODID_ASICREV
,
11594 &prod_id_asic_rev
);
11595 tp
->pci_chip_rev_id
= prod_id_asic_rev
;
11598 /* Wrong chip ID in 5752 A0. This code can be removed later
11599 * as A0 is not in production.
11601 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5752_A0_HW
)
11602 tp
->pci_chip_rev_id
= CHIPREV_ID_5752_A0
;
11604 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11605 * we need to disable memory and use config. cycles
11606 * only to access all registers. The 5702/03 chips
11607 * can mistakenly decode the special cycles from the
11608 * ICH chipsets as memory write cycles, causing corruption
11609 * of register and memory space. Only certain ICH bridges
11610 * will drive special cycles with non-zero data during the
11611 * address phase which can fall within the 5703's address
11612 * range. This is not an ICH bug as the PCI spec allows
11613 * non-zero address during special cycles. However, only
11614 * these ICH bridges are known to drive non-zero addresses
11615 * during special cycles.
11617 * Since special cycles do not cross PCI bridges, we only
11618 * enable this workaround if the 5703 is on the secondary
11619 * bus of these ICH bridges.
11621 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
) ||
11622 (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A2
)) {
11623 static struct tg3_dev_id
{
11627 } ich_chipsets
[] = {
11628 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_8
,
11630 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_8
,
11632 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_11
,
11634 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_6
,
11638 struct tg3_dev_id
*pci_id
= &ich_chipsets
[0];
11639 struct pci_dev
*bridge
= NULL
;
11641 while (pci_id
->vendor
!= 0) {
11642 bridge
= pci_get_device(pci_id
->vendor
, pci_id
->device
,
11648 if (pci_id
->rev
!= PCI_ANY_ID
) {
11649 if (bridge
->revision
> pci_id
->rev
)
11652 if (bridge
->subordinate
&&
11653 (bridge
->subordinate
->number
==
11654 tp
->pdev
->bus
->number
)) {
11656 tp
->tg3_flags2
|= TG3_FLG2_ICH_WORKAROUND
;
11657 pci_dev_put(bridge
);
11663 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
11664 static struct tg3_dev_id
{
11667 } bridge_chipsets
[] = {
11668 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
},
11669 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
},
11672 struct tg3_dev_id
*pci_id
= &bridge_chipsets
[0];
11673 struct pci_dev
*bridge
= NULL
;
11675 while (pci_id
->vendor
!= 0) {
11676 bridge
= pci_get_device(pci_id
->vendor
,
11683 if (bridge
->subordinate
&&
11684 (bridge
->subordinate
->number
<=
11685 tp
->pdev
->bus
->number
) &&
11686 (bridge
->subordinate
->subordinate
>=
11687 tp
->pdev
->bus
->number
)) {
11688 tp
->tg3_flags3
|= TG3_FLG3_5701_DMA_BUG
;
11689 pci_dev_put(bridge
);
11695 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11696 * DMA addresses > 40-bit. This bridge may have other additional
11697 * 57xx devices behind it in some 4-port NIC designs for example.
11698 * Any tg3 device found behind the bridge will also need the 40-bit
11701 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
||
11702 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
11703 tp
->tg3_flags2
|= TG3_FLG2_5780_CLASS
;
11704 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
11705 tp
->msi_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_MSI
);
11708 struct pci_dev
*bridge
= NULL
;
11711 bridge
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
11712 PCI_DEVICE_ID_SERVERWORKS_EPB
,
11714 if (bridge
&& bridge
->subordinate
&&
11715 (bridge
->subordinate
->number
<=
11716 tp
->pdev
->bus
->number
) &&
11717 (bridge
->subordinate
->subordinate
>=
11718 tp
->pdev
->bus
->number
)) {
11719 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
11720 pci_dev_put(bridge
);
11726 /* Initialize misc host control in PCI block. */
11727 tp
->misc_host_ctrl
|= (misc_ctrl_reg
&
11728 MISC_HOST_CTRL_CHIPREV
);
11729 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
11730 tp
->misc_host_ctrl
);
11732 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
11733 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
))
11734 tp
->pdev_peer
= tg3_find_peer(tp
);
11736 /* Intentionally exclude ASIC_REV_5906 */
11737 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
11738 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
11739 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
11740 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
11741 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
11742 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
11743 tp
->tg3_flags3
|= TG3_FLG3_5755_PLUS
;
11745 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
11746 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
11747 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
11748 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
11749 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
11750 tp
->tg3_flags2
|= TG3_FLG2_5750_PLUS
;
11752 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) ||
11753 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
11754 tp
->tg3_flags2
|= TG3_FLG2_5705_PLUS
;
11756 /* 5700 B0 chips do not support checksumming correctly due
11757 * to hardware bugs.
11759 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5700_B0
)
11760 tp
->tg3_flags
|= TG3_FLAG_BROKEN_CHECKSUMS
;
11762 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
11763 tp
->dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
11764 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
11765 tp
->dev
->features
|= NETIF_F_IPV6_CSUM
;
11768 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
11769 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSI
;
11770 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
||
11771 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
||
11772 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
&&
11773 tp
->pci_chip_rev_id
<= CHIPREV_ID_5714_A2
&&
11774 tp
->pdev_peer
== tp
->pdev
))
11775 tp
->tg3_flags
&= ~TG3_FLAG_SUPPORT_MSI
;
11777 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
11778 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
11779 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_2
;
11780 tp
->tg3_flags2
|= TG3_FLG2_1SHOT_MSI
;
11782 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_1
| TG3_FLG2_TSO_BUG
;
11783 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
11785 tp
->pci_chip_rev_id
>= CHIPREV_ID_5750_C2
)
11786 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_BUG
;
11790 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
11791 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
11792 tp
->tg3_flags2
|= TG3_FLG2_JUMBO_CAPABLE
;
11794 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
11797 tp
->pcie_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_EXP
);
11798 if (tp
->pcie_cap
!= 0) {
11801 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
11803 pcie_set_readrq(tp
->pdev
, 4096);
11805 pci_read_config_word(tp
->pdev
,
11806 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
11808 if (lnkctl
& PCI_EXP_LNKCTL_CLKREQ_EN
) {
11809 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
11810 tp
->tg3_flags2
&= ~TG3_FLG2_HW_TSO_2
;
11811 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
11812 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
11813 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
11814 tp
->tg3_flags3
|= TG3_FLG3_CLKREQ_BUG
;
11816 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
11817 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
11818 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
11819 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
11820 tp
->pcix_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_PCIX
);
11821 if (!tp
->pcix_cap
) {
11822 printk(KERN_ERR PFX
"Cannot find PCI-X "
11823 "capability, aborting.\n");
11827 if (!(pci_state_reg
& PCISTATE_CONV_PCI_MODE
))
11828 tp
->tg3_flags
|= TG3_FLAG_PCIX_MODE
;
11831 /* If we have an AMD 762 or VIA K8T800 chipset, write
11832 * reordering to the mailbox registers done by the host
11833 * controller can cause major troubles. We read back from
11834 * every mailbox register write to force the writes to be
11835 * posted to the chip in order.
11837 if (pci_dev_present(write_reorder_chipsets
) &&
11838 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
11839 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
11841 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
11842 &tp
->pci_cacheline_sz
);
11843 pci_read_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
11844 &tp
->pci_lat_timer
);
11845 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
11846 tp
->pci_lat_timer
< 64) {
11847 tp
->pci_lat_timer
= 64;
11848 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
11849 tp
->pci_lat_timer
);
11852 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5700_BX
) {
11853 /* 5700 BX chips need to have their TX producer index
11854 * mailboxes written twice to workaround a bug.
11856 tp
->tg3_flags
|= TG3_FLAG_TXD_MBOX_HWBUG
;
11858 /* If we are in PCI-X mode, enable register write workaround.
11860 * The workaround is to use indirect register accesses
11861 * for all chip writes not to mailbox registers.
11863 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
11866 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
11868 /* The chip can have it's power management PCI config
11869 * space registers clobbered due to this bug.
11870 * So explicitly force the chip into D0 here.
11872 pci_read_config_dword(tp
->pdev
,
11873 tp
->pm_cap
+ PCI_PM_CTRL
,
11875 pm_reg
&= ~PCI_PM_CTRL_STATE_MASK
;
11876 pm_reg
|= PCI_PM_CTRL_PME_ENABLE
| 0 /* D0 */;
11877 pci_write_config_dword(tp
->pdev
,
11878 tp
->pm_cap
+ PCI_PM_CTRL
,
11881 /* Also, force SERR#/PERR# in PCI command. */
11882 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
11883 pci_cmd
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
11884 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
11888 if ((pci_state_reg
& PCISTATE_BUS_SPEED_HIGH
) != 0)
11889 tp
->tg3_flags
|= TG3_FLAG_PCI_HIGH_SPEED
;
11890 if ((pci_state_reg
& PCISTATE_BUS_32BIT
) != 0)
11891 tp
->tg3_flags
|= TG3_FLAG_PCI_32BIT
;
11893 /* Chip-specific fixup from Broadcom driver */
11894 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
) &&
11895 (!(pci_state_reg
& PCISTATE_RETRY_SAME_DMA
))) {
11896 pci_state_reg
|= PCISTATE_RETRY_SAME_DMA
;
11897 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, pci_state_reg
);
11900 /* Default fast path register access methods */
11901 tp
->read32
= tg3_read32
;
11902 tp
->write32
= tg3_write32
;
11903 tp
->read32_mbox
= tg3_read32
;
11904 tp
->write32_mbox
= tg3_write32
;
11905 tp
->write32_tx_mbox
= tg3_write32
;
11906 tp
->write32_rx_mbox
= tg3_write32
;
11908 /* Various workaround register access methods */
11909 if (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
)
11910 tp
->write32
= tg3_write_indirect_reg32
;
11911 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
11912 ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
11913 tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
)) {
11915 * Back to back register writes can cause problems on these
11916 * chips, the workaround is to read back all reg writes
11917 * except those to mailbox regs.
11919 * See tg3_write_indirect_reg32().
11921 tp
->write32
= tg3_write_flush_reg32
;
11925 if ((tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
) ||
11926 (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)) {
11927 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
11928 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
11929 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
11932 if (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
) {
11933 tp
->read32
= tg3_read_indirect_reg32
;
11934 tp
->write32
= tg3_write_indirect_reg32
;
11935 tp
->read32_mbox
= tg3_read_indirect_mbox
;
11936 tp
->write32_mbox
= tg3_write_indirect_mbox
;
11937 tp
->write32_tx_mbox
= tg3_write_indirect_mbox
;
11938 tp
->write32_rx_mbox
= tg3_write_indirect_mbox
;
11943 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
11944 pci_cmd
&= ~PCI_COMMAND_MEMORY
;
11945 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
11947 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
11948 tp
->read32_mbox
= tg3_read32_mbox_5906
;
11949 tp
->write32_mbox
= tg3_write32_mbox_5906
;
11950 tp
->write32_tx_mbox
= tg3_write32_mbox_5906
;
11951 tp
->write32_rx_mbox
= tg3_write32_mbox_5906
;
11954 if (tp
->write32
== tg3_write_indirect_reg32
||
11955 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
11956 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
11957 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)))
11958 tp
->tg3_flags
|= TG3_FLAG_SRAM_USE_CONFIG
;
11960 /* Get eeprom hw config before calling tg3_set_power_state().
11961 * In particular, the TG3_FLG2_IS_NIC flag must be
11962 * determined before calling tg3_set_power_state() so that
11963 * we know whether or not to switch out of Vaux power.
11964 * When the flag is set, it means that GPIO1 is used for eeprom
11965 * write protect and also implies that it is a LOM where GPIOs
11966 * are not used to switch power.
11968 tg3_get_eeprom_hw_cfg(tp
);
11970 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
11971 /* Allow reads and writes to the
11972 * APE register and memory space.
11974 pci_state_reg
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
11975 PCISTATE_ALLOW_APE_SHMEM_WR
;
11976 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
11980 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
11981 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
11982 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
11983 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
11984 tp
->tg3_flags
|= TG3_FLAG_CPMU_PRESENT
;
11986 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
11987 * GPIO1 driven high will bring 5700's external PHY out of reset.
11988 * It is also used as eeprom write protect on LOMs.
11990 tp
->grc_local_ctrl
= GRC_LCLCTRL_INT_ON_ATTN
| GRC_LCLCTRL_AUTO_SEEPROM
;
11991 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
11992 (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
))
11993 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
11994 GRC_LCLCTRL_GPIO_OUTPUT1
);
11995 /* Unused GPIO3 must be driven as output on 5752 because there
11996 * are no pull-up resistors on unused GPIO pins.
11998 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
11999 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
12001 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
12002 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
12003 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
12005 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
) {
12006 /* Turn off the debug UART. */
12007 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
12008 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
12009 /* Keep VMain power. */
12010 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
12011 GRC_LCLCTRL_GPIO_OUTPUT0
;
12014 /* Force the chip into D0. */
12015 err
= tg3_set_power_state(tp
, PCI_D0
);
12017 printk(KERN_ERR PFX
"(%s) transition to D0 failed\n",
12018 pci_name(tp
->pdev
));
12022 /* Derive initial jumbo mode from MTU assigned in
12023 * ether_setup() via the alloc_etherdev() call
12025 if (tp
->dev
->mtu
> ETH_DATA_LEN
&&
12026 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
12027 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
12029 /* Determine WakeOnLan speed to use. */
12030 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12031 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
12032 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
||
12033 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B2
) {
12034 tp
->tg3_flags
&= ~(TG3_FLAG_WOL_SPEED_100MB
);
12036 tp
->tg3_flags
|= TG3_FLAG_WOL_SPEED_100MB
;
12039 /* A few boards don't want Ethernet@WireSpeed phy feature */
12040 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
12041 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
12042 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) &&
12043 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A1
)) ||
12044 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) ||
12045 (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
12046 tp
->tg3_flags2
|= TG3_FLG2_NO_ETH_WIRE_SPEED
;
12048 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5703_AX
||
12049 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_AX
)
12050 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADC_BUG
;
12051 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
)
12052 tp
->tg3_flags2
|= TG3_FLG2_PHY_5704_A0_BUG
;
12054 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
12055 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5906
&&
12056 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
12057 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57780
) {
12058 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
12059 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
12060 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12061 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
12062 if (tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5756
&&
12063 tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5722
)
12064 tp
->tg3_flags2
|= TG3_FLG2_PHY_JITTER_BUG
;
12065 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5755M
)
12066 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADJUST_TRIM
;
12068 tp
->tg3_flags2
|= TG3_FLG2_PHY_BER_BUG
;
12071 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
12072 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
12073 tp
->phy_otp
= tg3_read_otp_phycfg(tp
);
12074 if (tp
->phy_otp
== 0)
12075 tp
->phy_otp
= TG3_OTP_DEFAULT
;
12078 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)
12079 tp
->mi_mode
= MAC_MI_MODE_500KHZ_CONST
;
12081 tp
->mi_mode
= MAC_MI_MODE_BASE
;
12083 tp
->coalesce_mode
= 0;
12084 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_AX
&&
12085 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_BX
)
12086 tp
->coalesce_mode
|= HOSTCC_MODE_32BYTE
;
12088 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
12089 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
12090 tp
->tg3_flags3
|= TG3_FLG3_USE_PHYLIB
;
12092 err
= tg3_mdio_init(tp
);
12096 /* Initialize data/descriptor byte/word swapping. */
12097 val
= tr32(GRC_MODE
);
12098 val
&= GRC_MODE_HOST_STACKUP
;
12099 tw32(GRC_MODE
, val
| tp
->grc_mode
);
12101 tg3_switch_clocks(tp
);
12103 /* Clear this out for sanity. */
12104 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
12106 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
12108 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0 &&
12109 (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) == 0) {
12110 u32 chiprevid
= GET_CHIP_REV_ID(tp
->misc_host_ctrl
);
12112 if (chiprevid
== CHIPREV_ID_5701_A0
||
12113 chiprevid
== CHIPREV_ID_5701_B0
||
12114 chiprevid
== CHIPREV_ID_5701_B2
||
12115 chiprevid
== CHIPREV_ID_5701_B5
) {
12116 void __iomem
*sram_base
;
12118 /* Write some dummy words into the SRAM status block
12119 * area, see if it reads back correctly. If the return
12120 * value is bad, force enable the PCIX workaround.
12122 sram_base
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_STATS_BLK
;
12124 writel(0x00000000, sram_base
);
12125 writel(0x00000000, sram_base
+ 4);
12126 writel(0xffffffff, sram_base
+ 4);
12127 if (readl(sram_base
) != 0x00000000)
12128 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
12133 tg3_nvram_init(tp
);
12135 grc_misc_cfg
= tr32(GRC_MISC_CFG
);
12136 grc_misc_cfg
&= GRC_MISC_CFG_BOARD_ID_MASK
;
12138 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
12139 (grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788
||
12140 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788M
))
12141 tp
->tg3_flags2
|= TG3_FLG2_IS_5788
;
12143 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
12144 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
))
12145 tp
->tg3_flags
|= TG3_FLAG_TAGGED_STATUS
;
12146 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
12147 tp
->coalesce_mode
|= (HOSTCC_MODE_CLRTICK_RXBD
|
12148 HOSTCC_MODE_CLRTICK_TXBD
);
12150 tp
->misc_host_ctrl
|= MISC_HOST_CTRL_TAGGED_STATUS
;
12151 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12152 tp
->misc_host_ctrl
);
12155 /* Preserve the APE MAC_MODE bits */
12156 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
12157 tp
->mac_mode
= tr32(MAC_MODE
) |
12158 MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
12160 tp
->mac_mode
= TG3_DEF_MAC_MODE
;
12162 /* these are limited to 10/100 only */
12163 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
12164 (grc_misc_cfg
== 0x8000 || grc_misc_cfg
== 0x4000)) ||
12165 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
12166 tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
12167 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901
||
12168 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901_2
||
12169 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5705F
)) ||
12170 (tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
12171 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5751F
||
12172 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5753F
||
12173 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5787F
)) ||
12174 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
||
12175 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12176 tp
->tg3_flags
|= TG3_FLAG_10_100_ONLY
;
12178 err
= tg3_phy_probe(tp
);
12180 printk(KERN_ERR PFX
"(%s) phy probe failed, err %d\n",
12181 pci_name(tp
->pdev
), err
);
12182 /* ... but do not return immediately ... */
12186 tg3_read_partno(tp
);
12187 tg3_read_fw_ver(tp
);
12189 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
12190 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
12192 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
12193 tp
->tg3_flags
|= TG3_FLAG_USE_MI_INTERRUPT
;
12195 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
12198 /* 5700 {AX,BX} chips have a broken status block link
12199 * change bit implementation, so we must use the
12200 * status register in those cases.
12202 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
12203 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
12205 tp
->tg3_flags
&= ~TG3_FLAG_USE_LINKCHG_REG
;
12207 /* The led_ctrl is set during tg3_phy_probe, here we might
12208 * have to force the link status polling mechanism based
12209 * upon subsystem IDs.
12211 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
12212 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
12213 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
12214 tp
->tg3_flags
|= (TG3_FLAG_USE_MI_INTERRUPT
|
12215 TG3_FLAG_USE_LINKCHG_REG
);
12218 /* For all SERDES we poll the MAC status register. */
12219 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
12220 tp
->tg3_flags
|= TG3_FLAG_POLL_SERDES
;
12222 tp
->tg3_flags
&= ~TG3_FLAG_POLL_SERDES
;
12224 tp
->rx_offset
= NET_IP_ALIGN
;
12225 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
12226 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) != 0)
12229 tp
->rx_std_max_post
= TG3_RX_RING_SIZE
;
12231 /* Increment the rx prod index on the rx std ring by at most
12232 * 8 for these chips to workaround hw errata.
12234 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
12235 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
12236 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
12237 tp
->rx_std_max_post
= 8;
12239 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
)
12240 tp
->pwrmgmt_thresh
= tr32(PCIE_PWR_MGMT_THRESH
) &
12241 PCIE_PWR_MGMT_L1_THRESH_MSK
;
12246 #ifdef CONFIG_SPARC
12247 static int __devinit
tg3_get_macaddr_sparc(struct tg3
*tp
)
12249 struct net_device
*dev
= tp
->dev
;
12250 struct pci_dev
*pdev
= tp
->pdev
;
12251 struct device_node
*dp
= pci_device_to_OF_node(pdev
);
12252 const unsigned char *addr
;
12255 addr
= of_get_property(dp
, "local-mac-address", &len
);
12256 if (addr
&& len
== 6) {
12257 memcpy(dev
->dev_addr
, addr
, 6);
12258 memcpy(dev
->perm_addr
, dev
->dev_addr
, 6);
12264 static int __devinit
tg3_get_default_macaddr_sparc(struct tg3
*tp
)
12266 struct net_device
*dev
= tp
->dev
;
12268 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
12269 memcpy(dev
->perm_addr
, idprom
->id_ethaddr
, 6);
12274 static int __devinit
tg3_get_device_address(struct tg3
*tp
)
12276 struct net_device
*dev
= tp
->dev
;
12277 u32 hi
, lo
, mac_offset
;
12280 #ifdef CONFIG_SPARC
12281 if (!tg3_get_macaddr_sparc(tp
))
12286 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
12287 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
12288 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
12290 if (tg3_nvram_lock(tp
))
12291 tw32_f(NVRAM_CMD
, NVRAM_CMD_RESET
);
12293 tg3_nvram_unlock(tp
);
12295 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12298 /* First try to get it from MAC address mailbox. */
12299 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_HIGH_MBOX
, &hi
);
12300 if ((hi
>> 16) == 0x484b) {
12301 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
12302 dev
->dev_addr
[1] = (hi
>> 0) & 0xff;
12304 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_LOW_MBOX
, &lo
);
12305 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
12306 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
12307 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
12308 dev
->dev_addr
[5] = (lo
>> 0) & 0xff;
12310 /* Some old bootcode may report a 0 MAC address in SRAM */
12311 addr_ok
= is_valid_ether_addr(&dev
->dev_addr
[0]);
12314 /* Next, try NVRAM. */
12315 if (!tg3_nvram_read(tp
, mac_offset
+ 0, &hi
) &&
12316 !tg3_nvram_read(tp
, mac_offset
+ 4, &lo
)) {
12317 dev
->dev_addr
[0] = ((hi
>> 16) & 0xff);
12318 dev
->dev_addr
[1] = ((hi
>> 24) & 0xff);
12319 dev
->dev_addr
[2] = ((lo
>> 0) & 0xff);
12320 dev
->dev_addr
[3] = ((lo
>> 8) & 0xff);
12321 dev
->dev_addr
[4] = ((lo
>> 16) & 0xff);
12322 dev
->dev_addr
[5] = ((lo
>> 24) & 0xff);
12324 /* Finally just fetch it out of the MAC control regs. */
12326 hi
= tr32(MAC_ADDR_0_HIGH
);
12327 lo
= tr32(MAC_ADDR_0_LOW
);
12329 dev
->dev_addr
[5] = lo
& 0xff;
12330 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
12331 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
12332 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
12333 dev
->dev_addr
[1] = hi
& 0xff;
12334 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
12338 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
12339 #ifdef CONFIG_SPARC
12340 if (!tg3_get_default_macaddr_sparc(tp
))
12345 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
12349 #define BOUNDARY_SINGLE_CACHELINE 1
12350 #define BOUNDARY_MULTI_CACHELINE 2
12352 static u32 __devinit
tg3_calc_dma_bndry(struct tg3
*tp
, u32 val
)
12354 int cacheline_size
;
12358 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
12360 cacheline_size
= 1024;
12362 cacheline_size
= (int) byte
* 4;
12364 /* On 5703 and later chips, the boundary bits have no
12367 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
12368 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
12369 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
12372 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12373 goal
= BOUNDARY_MULTI_CACHELINE
;
12375 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12376 goal
= BOUNDARY_SINGLE_CACHELINE
;
12385 /* PCI controllers on most RISC systems tend to disconnect
12386 * when a device tries to burst across a cache-line boundary.
12387 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12389 * Unfortunately, for PCI-E there are only limited
12390 * write-side controls for this, and thus for reads
12391 * we will still get the disconnects. We'll also waste
12392 * these PCI cycles for both read and write for chips
12393 * other than 5700 and 5701 which do not implement the
12396 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
12397 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
12398 switch (cacheline_size
) {
12403 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12404 val
|= (DMA_RWCTRL_READ_BNDRY_128_PCIX
|
12405 DMA_RWCTRL_WRITE_BNDRY_128_PCIX
);
12407 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
12408 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
12413 val
|= (DMA_RWCTRL_READ_BNDRY_256_PCIX
|
12414 DMA_RWCTRL_WRITE_BNDRY_256_PCIX
);
12418 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
12419 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
12422 } else if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
12423 switch (cacheline_size
) {
12427 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12428 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
12429 val
|= DMA_RWCTRL_WRITE_BNDRY_64_PCIE
;
12435 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
12436 val
|= DMA_RWCTRL_WRITE_BNDRY_128_PCIE
;
12440 switch (cacheline_size
) {
12442 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12443 val
|= (DMA_RWCTRL_READ_BNDRY_16
|
12444 DMA_RWCTRL_WRITE_BNDRY_16
);
12449 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12450 val
|= (DMA_RWCTRL_READ_BNDRY_32
|
12451 DMA_RWCTRL_WRITE_BNDRY_32
);
12456 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12457 val
|= (DMA_RWCTRL_READ_BNDRY_64
|
12458 DMA_RWCTRL_WRITE_BNDRY_64
);
12463 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12464 val
|= (DMA_RWCTRL_READ_BNDRY_128
|
12465 DMA_RWCTRL_WRITE_BNDRY_128
);
12470 val
|= (DMA_RWCTRL_READ_BNDRY_256
|
12471 DMA_RWCTRL_WRITE_BNDRY_256
);
12474 val
|= (DMA_RWCTRL_READ_BNDRY_512
|
12475 DMA_RWCTRL_WRITE_BNDRY_512
);
12479 val
|= (DMA_RWCTRL_READ_BNDRY_1024
|
12480 DMA_RWCTRL_WRITE_BNDRY_1024
);
12489 static int __devinit
tg3_do_test_dma(struct tg3
*tp
, u32
*buf
, dma_addr_t buf_dma
, int size
, int to_device
)
12491 struct tg3_internal_buffer_desc test_desc
;
12492 u32 sram_dma_descs
;
12495 sram_dma_descs
= NIC_SRAM_DMA_DESC_POOL_BASE
;
12497 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
, 0);
12498 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
, 0);
12499 tw32(RDMAC_STATUS
, 0);
12500 tw32(WDMAC_STATUS
, 0);
12502 tw32(BUFMGR_MODE
, 0);
12503 tw32(FTQ_RESET
, 0);
12505 test_desc
.addr_hi
= ((u64
) buf_dma
) >> 32;
12506 test_desc
.addr_lo
= buf_dma
& 0xffffffff;
12507 test_desc
.nic_mbuf
= 0x00002100;
12508 test_desc
.len
= size
;
12511 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12512 * the *second* time the tg3 driver was getting loaded after an
12515 * Broadcom tells me:
12516 * ...the DMA engine is connected to the GRC block and a DMA
12517 * reset may affect the GRC block in some unpredictable way...
12518 * The behavior of resets to individual blocks has not been tested.
12520 * Broadcom noted the GRC reset will also reset all sub-components.
12523 test_desc
.cqid_sqid
= (13 << 8) | 2;
12525 tw32_f(RDMAC_MODE
, RDMAC_MODE_ENABLE
);
12528 test_desc
.cqid_sqid
= (16 << 8) | 7;
12530 tw32_f(WDMAC_MODE
, WDMAC_MODE_ENABLE
);
12533 test_desc
.flags
= 0x00000005;
12535 for (i
= 0; i
< (sizeof(test_desc
) / sizeof(u32
)); i
++) {
12538 val
= *(((u32
*)&test_desc
) + i
);
12539 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
,
12540 sram_dma_descs
+ (i
* sizeof(u32
)));
12541 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
12543 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
12546 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ
, sram_dma_descs
);
12548 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ
, sram_dma_descs
);
12552 for (i
= 0; i
< 40; i
++) {
12556 val
= tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
);
12558 val
= tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
);
12559 if ((val
& 0xffff) == sram_dma_descs
) {
12570 #define TEST_BUFFER_SIZE 0x2000
12572 static int __devinit
tg3_test_dma(struct tg3
*tp
)
12574 dma_addr_t buf_dma
;
12575 u32
*buf
, saved_dma_rwctrl
;
12578 buf
= pci_alloc_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, &buf_dma
);
12584 tp
->dma_rwctrl
= ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
) |
12585 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT
));
12587 tp
->dma_rwctrl
= tg3_calc_dma_bndry(tp
, tp
->dma_rwctrl
);
12589 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
12590 /* DMA read watermark not used on PCIE */
12591 tp
->dma_rwctrl
|= 0x00180000;
12592 } else if (!(tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
12593 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
||
12594 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)
12595 tp
->dma_rwctrl
|= 0x003f0000;
12597 tp
->dma_rwctrl
|= 0x003f000f;
12599 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
12600 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
12601 u32 ccval
= (tr32(TG3PCI_CLOCK_CTRL
) & 0x1f);
12602 u32 read_water
= 0x7;
12604 /* If the 5704 is behind the EPB bridge, we can
12605 * do the less restrictive ONE_DMA workaround for
12606 * better performance.
12608 if ((tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) &&
12609 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
12610 tp
->dma_rwctrl
|= 0x8000;
12611 else if (ccval
== 0x6 || ccval
== 0x7)
12612 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
12614 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
)
12616 /* Set bit 23 to enable PCIX hw bug fix */
12618 (read_water
<< DMA_RWCTRL_READ_WATER_SHIFT
) |
12619 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT
) |
12621 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
) {
12622 /* 5780 always in PCIX mode */
12623 tp
->dma_rwctrl
|= 0x00144000;
12624 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
12625 /* 5714 always in PCIX mode */
12626 tp
->dma_rwctrl
|= 0x00148000;
12628 tp
->dma_rwctrl
|= 0x001b000f;
12632 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
12633 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
12634 tp
->dma_rwctrl
&= 0xfffffff0;
12636 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12637 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
12638 /* Remove this if it causes problems for some boards. */
12639 tp
->dma_rwctrl
|= DMA_RWCTRL_USE_MEM_READ_MULT
;
12641 /* On 5700/5701 chips, we need to set this bit.
12642 * Otherwise the chip will issue cacheline transactions
12643 * to streamable DMA memory with not all the byte
12644 * enables turned on. This is an error on several
12645 * RISC PCI controllers, in particular sparc64.
12647 * On 5703/5704 chips, this bit has been reassigned
12648 * a different meaning. In particular, it is used
12649 * on those chips to enable a PCI-X workaround.
12651 tp
->dma_rwctrl
|= DMA_RWCTRL_ASSERT_ALL_BE
;
12654 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
12657 /* Unneeded, already done by tg3_get_invariants. */
12658 tg3_switch_clocks(tp
);
12662 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
12663 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
12666 /* It is best to perform DMA test with maximum write burst size
12667 * to expose the 5700/5701 write DMA bug.
12669 saved_dma_rwctrl
= tp
->dma_rwctrl
;
12670 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
12671 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
12676 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++)
12679 /* Send the buffer to the chip. */
12680 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 1);
12682 printk(KERN_ERR
"tg3_test_dma() Write the buffer failed %d\n", ret
);
12687 /* validate data reached card RAM correctly. */
12688 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
12690 tg3_read_mem(tp
, 0x2100 + (i
*4), &val
);
12691 if (le32_to_cpu(val
) != p
[i
]) {
12692 printk(KERN_ERR
" tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val
, i
);
12693 /* ret = -ENODEV here? */
12698 /* Now read it back. */
12699 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 0);
12701 printk(KERN_ERR
"tg3_test_dma() Read the buffer failed %d\n", ret
);
12707 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
12711 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
12712 DMA_RWCTRL_WRITE_BNDRY_16
) {
12713 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
12714 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
12715 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
12718 printk(KERN_ERR
"tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p
[i
], i
);
12724 if (i
== (TEST_BUFFER_SIZE
/ sizeof(u32
))) {
12730 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
12731 DMA_RWCTRL_WRITE_BNDRY_16
) {
12732 static struct pci_device_id dma_wait_state_chipsets
[] = {
12733 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
,
12734 PCI_DEVICE_ID_APPLE_UNI_N_PCI15
) },
12738 /* DMA test passed without adjusting DMA boundary,
12739 * now look for chipsets that are known to expose the
12740 * DMA bug without failing the test.
12742 if (pci_dev_present(dma_wait_state_chipsets
)) {
12743 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
12744 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
12747 /* Safe to use the calculated DMA boundary. */
12748 tp
->dma_rwctrl
= saved_dma_rwctrl
;
12750 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
12754 pci_free_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, buf
, buf_dma
);
12759 static void __devinit
tg3_init_link_config(struct tg3
*tp
)
12761 tp
->link_config
.advertising
=
12762 (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
12763 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
12764 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
|
12765 ADVERTISED_Autoneg
| ADVERTISED_MII
);
12766 tp
->link_config
.speed
= SPEED_INVALID
;
12767 tp
->link_config
.duplex
= DUPLEX_INVALID
;
12768 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
12769 tp
->link_config
.active_speed
= SPEED_INVALID
;
12770 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
12771 tp
->link_config
.phy_is_low_power
= 0;
12772 tp
->link_config
.orig_speed
= SPEED_INVALID
;
12773 tp
->link_config
.orig_duplex
= DUPLEX_INVALID
;
12774 tp
->link_config
.orig_autoneg
= AUTONEG_INVALID
;
12777 static void __devinit
tg3_init_bufmgr_config(struct tg3
*tp
)
12779 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
12780 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
12781 DEFAULT_MB_RDMA_LOW_WATER_5705
;
12782 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
12783 DEFAULT_MB_MACRX_LOW_WATER_5705
;
12784 tp
->bufmgr_config
.mbuf_high_water
=
12785 DEFAULT_MB_HIGH_WATER_5705
;
12786 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12787 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
12788 DEFAULT_MB_MACRX_LOW_WATER_5906
;
12789 tp
->bufmgr_config
.mbuf_high_water
=
12790 DEFAULT_MB_HIGH_WATER_5906
;
12793 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
12794 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780
;
12795 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
12796 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780
;
12797 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
12798 DEFAULT_MB_HIGH_WATER_JUMBO_5780
;
12800 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
12801 DEFAULT_MB_RDMA_LOW_WATER
;
12802 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
12803 DEFAULT_MB_MACRX_LOW_WATER
;
12804 tp
->bufmgr_config
.mbuf_high_water
=
12805 DEFAULT_MB_HIGH_WATER
;
12807 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
12808 DEFAULT_MB_RDMA_LOW_WATER_JUMBO
;
12809 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
12810 DEFAULT_MB_MACRX_LOW_WATER_JUMBO
;
12811 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
12812 DEFAULT_MB_HIGH_WATER_JUMBO
;
12815 tp
->bufmgr_config
.dma_low_water
= DEFAULT_DMA_LOW_WATER
;
12816 tp
->bufmgr_config
.dma_high_water
= DEFAULT_DMA_HIGH_WATER
;
12819 static char * __devinit
tg3_phy_string(struct tg3
*tp
)
12821 switch (tp
->phy_id
& PHY_ID_MASK
) {
12822 case PHY_ID_BCM5400
: return "5400";
12823 case PHY_ID_BCM5401
: return "5401";
12824 case PHY_ID_BCM5411
: return "5411";
12825 case PHY_ID_BCM5701
: return "5701";
12826 case PHY_ID_BCM5703
: return "5703";
12827 case PHY_ID_BCM5704
: return "5704";
12828 case PHY_ID_BCM5705
: return "5705";
12829 case PHY_ID_BCM5750
: return "5750";
12830 case PHY_ID_BCM5752
: return "5752";
12831 case PHY_ID_BCM5714
: return "5714";
12832 case PHY_ID_BCM5780
: return "5780";
12833 case PHY_ID_BCM5755
: return "5755";
12834 case PHY_ID_BCM5787
: return "5787";
12835 case PHY_ID_BCM5784
: return "5784";
12836 case PHY_ID_BCM5756
: return "5722/5756";
12837 case PHY_ID_BCM5906
: return "5906";
12838 case PHY_ID_BCM5761
: return "5761";
12839 case PHY_ID_BCM8002
: return "8002/serdes";
12840 case 0: return "serdes";
12841 default: return "unknown";
12845 static char * __devinit
tg3_bus_string(struct tg3
*tp
, char *str
)
12847 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
12848 strcpy(str
, "PCI Express");
12850 } else if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
12851 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
) & 0x1f;
12853 strcpy(str
, "PCIX:");
12855 if ((clock_ctrl
== 7) ||
12856 ((tr32(GRC_MISC_CFG
) & GRC_MISC_CFG_BOARD_ID_MASK
) ==
12857 GRC_MISC_CFG_BOARD_ID_5704CIOBE
))
12858 strcat(str
, "133MHz");
12859 else if (clock_ctrl
== 0)
12860 strcat(str
, "33MHz");
12861 else if (clock_ctrl
== 2)
12862 strcat(str
, "50MHz");
12863 else if (clock_ctrl
== 4)
12864 strcat(str
, "66MHz");
12865 else if (clock_ctrl
== 6)
12866 strcat(str
, "100MHz");
12868 strcpy(str
, "PCI:");
12869 if (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
)
12870 strcat(str
, "66MHz");
12872 strcat(str
, "33MHz");
12874 if (tp
->tg3_flags
& TG3_FLAG_PCI_32BIT
)
12875 strcat(str
, ":32-bit");
12877 strcat(str
, ":64-bit");
12881 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*tp
)
12883 struct pci_dev
*peer
;
12884 unsigned int func
, devnr
= tp
->pdev
->devfn
& ~7;
12886 for (func
= 0; func
< 8; func
++) {
12887 peer
= pci_get_slot(tp
->pdev
->bus
, devnr
| func
);
12888 if (peer
&& peer
!= tp
->pdev
)
12892 /* 5704 can be configured in single-port mode, set peer to
12893 * tp->pdev in that case.
12901 * We don't need to keep the refcount elevated; there's no way
12902 * to remove one half of this device without removing the other
12909 static void __devinit
tg3_init_coal(struct tg3
*tp
)
12911 struct ethtool_coalesce
*ec
= &tp
->coal
;
12913 memset(ec
, 0, sizeof(*ec
));
12914 ec
->cmd
= ETHTOOL_GCOALESCE
;
12915 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS
;
12916 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS
;
12917 ec
->rx_max_coalesced_frames
= LOW_RXMAX_FRAMES
;
12918 ec
->tx_max_coalesced_frames
= LOW_TXMAX_FRAMES
;
12919 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT
;
12920 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT
;
12921 ec
->rx_max_coalesced_frames_irq
= DEFAULT_RXCOAL_MAXF_INT
;
12922 ec
->tx_max_coalesced_frames_irq
= DEFAULT_TXCOAL_MAXF_INT
;
12923 ec
->stats_block_coalesce_usecs
= DEFAULT_STAT_COAL_TICKS
;
12925 if (tp
->coalesce_mode
& (HOSTCC_MODE_CLRTICK_RXBD
|
12926 HOSTCC_MODE_CLRTICK_TXBD
)) {
12927 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS_CLRTCKS
;
12928 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT_CLRTCKS
;
12929 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS_CLRTCKS
;
12930 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT_CLRTCKS
;
12933 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
12934 ec
->rx_coalesce_usecs_irq
= 0;
12935 ec
->tx_coalesce_usecs_irq
= 0;
12936 ec
->stats_block_coalesce_usecs
= 0;
12940 static const struct net_device_ops tg3_netdev_ops
= {
12941 .ndo_open
= tg3_open
,
12942 .ndo_stop
= tg3_close
,
12943 .ndo_start_xmit
= tg3_start_xmit
,
12944 .ndo_get_stats
= tg3_get_stats
,
12945 .ndo_validate_addr
= eth_validate_addr
,
12946 .ndo_set_multicast_list
= tg3_set_rx_mode
,
12947 .ndo_set_mac_address
= tg3_set_mac_addr
,
12948 .ndo_do_ioctl
= tg3_ioctl
,
12949 .ndo_tx_timeout
= tg3_tx_timeout
,
12950 .ndo_change_mtu
= tg3_change_mtu
,
12951 #if TG3_VLAN_TAG_USED
12952 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
12954 #ifdef CONFIG_NET_POLL_CONTROLLER
12955 .ndo_poll_controller
= tg3_poll_controller
,
12959 static const struct net_device_ops tg3_netdev_ops_dma_bug
= {
12960 .ndo_open
= tg3_open
,
12961 .ndo_stop
= tg3_close
,
12962 .ndo_start_xmit
= tg3_start_xmit_dma_bug
,
12963 .ndo_get_stats
= tg3_get_stats
,
12964 .ndo_validate_addr
= eth_validate_addr
,
12965 .ndo_set_multicast_list
= tg3_set_rx_mode
,
12966 .ndo_set_mac_address
= tg3_set_mac_addr
,
12967 .ndo_do_ioctl
= tg3_ioctl
,
12968 .ndo_tx_timeout
= tg3_tx_timeout
,
12969 .ndo_change_mtu
= tg3_change_mtu
,
12970 #if TG3_VLAN_TAG_USED
12971 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
12973 #ifdef CONFIG_NET_POLL_CONTROLLER
12974 .ndo_poll_controller
= tg3_poll_controller
,
12978 static int __devinit
tg3_init_one(struct pci_dev
*pdev
,
12979 const struct pci_device_id
*ent
)
12981 static int tg3_version_printed
= 0;
12982 struct net_device
*dev
;
12986 u64 dma_mask
, persist_dma_mask
;
12988 if (tg3_version_printed
++ == 0)
12989 printk(KERN_INFO
"%s", version
);
12991 err
= pci_enable_device(pdev
);
12993 printk(KERN_ERR PFX
"Cannot enable PCI device, "
12998 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
13000 printk(KERN_ERR PFX
"Cannot obtain PCI resources, "
13002 goto err_out_disable_pdev
;
13005 pci_set_master(pdev
);
13007 /* Find power-management capability. */
13008 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
13010 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
13013 goto err_out_free_res
;
13016 dev
= alloc_etherdev(sizeof(*tp
));
13018 printk(KERN_ERR PFX
"Etherdev alloc failed, aborting.\n");
13020 goto err_out_free_res
;
13023 SET_NETDEV_DEV(dev
, &pdev
->dev
);
13025 #if TG3_VLAN_TAG_USED
13026 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
13029 tp
= netdev_priv(dev
);
13032 tp
->pm_cap
= pm_cap
;
13033 tp
->rx_mode
= TG3_DEF_RX_MODE
;
13034 tp
->tx_mode
= TG3_DEF_TX_MODE
;
13037 tp
->msg_enable
= tg3_debug
;
13039 tp
->msg_enable
= TG3_DEF_MSG_ENABLE
;
13041 /* The word/byte swap controls here control register access byte
13042 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13045 tp
->misc_host_ctrl
=
13046 MISC_HOST_CTRL_MASK_PCI_INT
|
13047 MISC_HOST_CTRL_WORD_SWAP
|
13048 MISC_HOST_CTRL_INDIR_ACCESS
|
13049 MISC_HOST_CTRL_PCISTATE_RW
;
13051 /* The NONFRM (non-frame) byte/word swap controls take effect
13052 * on descriptor entries, anything which isn't packet data.
13054 * The StrongARM chips on the board (one for tx, one for rx)
13055 * are running in big-endian mode.
13057 tp
->grc_mode
= (GRC_MODE_WSWAP_DATA
| GRC_MODE_BSWAP_DATA
|
13058 GRC_MODE_WSWAP_NONFRM_DATA
);
13059 #ifdef __BIG_ENDIAN
13060 tp
->grc_mode
|= GRC_MODE_BSWAP_NONFRM_DATA
;
13062 spin_lock_init(&tp
->lock
);
13063 spin_lock_init(&tp
->indirect_lock
);
13064 INIT_WORK(&tp
->reset_task
, tg3_reset_task
);
13066 tp
->regs
= pci_ioremap_bar(pdev
, BAR_0
);
13068 printk(KERN_ERR PFX
"Cannot map device registers, "
13071 goto err_out_free_dev
;
13074 tg3_init_link_config(tp
);
13076 tp
->rx_pending
= TG3_DEF_RX_RING_PENDING
;
13077 tp
->rx_jumbo_pending
= TG3_DEF_RX_JUMBO_RING_PENDING
;
13078 tp
->tx_pending
= TG3_DEF_TX_RING_PENDING
;
13080 netif_napi_add(dev
, &tp
->napi
, tg3_poll
, 64);
13081 dev
->ethtool_ops
= &tg3_ethtool_ops
;
13082 dev
->watchdog_timeo
= TG3_TX_TIMEOUT
;
13083 dev
->irq
= pdev
->irq
;
13085 err
= tg3_get_invariants(tp
);
13087 printk(KERN_ERR PFX
"Problem fetching invariants of chip, "
13089 goto err_out_iounmap
;
13092 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13093 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13094 dev
->netdev_ops
= &tg3_netdev_ops
;
13096 dev
->netdev_ops
= &tg3_netdev_ops_dma_bug
;
13099 /* The EPB bridge inside 5714, 5715, and 5780 and any
13100 * device behind the EPB cannot support DMA addresses > 40-bit.
13101 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13102 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13103 * do DMA address check in tg3_start_xmit().
13105 if (tp
->tg3_flags2
& TG3_FLG2_IS_5788
)
13106 persist_dma_mask
= dma_mask
= DMA_32BIT_MASK
;
13107 else if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) {
13108 persist_dma_mask
= dma_mask
= DMA_40BIT_MASK
;
13109 #ifdef CONFIG_HIGHMEM
13110 dma_mask
= DMA_64BIT_MASK
;
13113 persist_dma_mask
= dma_mask
= DMA_64BIT_MASK
;
13115 /* Configure DMA attributes. */
13116 if (dma_mask
> DMA_32BIT_MASK
) {
13117 err
= pci_set_dma_mask(pdev
, dma_mask
);
13119 dev
->features
|= NETIF_F_HIGHDMA
;
13120 err
= pci_set_consistent_dma_mask(pdev
,
13123 printk(KERN_ERR PFX
"Unable to obtain 64 bit "
13124 "DMA for consistent allocations\n");
13125 goto err_out_iounmap
;
13129 if (err
|| dma_mask
== DMA_32BIT_MASK
) {
13130 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
13132 printk(KERN_ERR PFX
"No usable DMA configuration, "
13134 goto err_out_iounmap
;
13138 tg3_init_bufmgr_config(tp
);
13140 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
)
13141 tp
->fw_needed
= FIRMWARE_TG3
;
13143 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
13144 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
13146 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13147 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
13148 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
||
13149 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
13150 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
13151 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
13153 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
| TG3_FLG2_TSO_BUG
;
13154 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)
13155 tp
->fw_needed
= FIRMWARE_TG3TSO5
;
13157 tp
->fw_needed
= FIRMWARE_TG3TSO
;
13160 /* TSO is on by default on chips that support hardware TSO.
13161 * Firmware TSO on older chips gives lower performance, so it
13162 * is off by default, but can be enabled using ethtool.
13164 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
13165 if (dev
->features
& NETIF_F_IP_CSUM
)
13166 dev
->features
|= NETIF_F_TSO
;
13167 if ((dev
->features
& NETIF_F_IPV6_CSUM
) &&
13168 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
))
13169 dev
->features
|= NETIF_F_TSO6
;
13170 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13171 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
13172 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
13173 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13174 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
13175 dev
->features
|= NETIF_F_TSO_ECN
;
13179 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
&&
13180 !(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
13181 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
)) {
13182 tp
->tg3_flags2
|= TG3_FLG2_MAX_RXPEND_64
;
13183 tp
->rx_pending
= 63;
13186 err
= tg3_get_device_address(tp
);
13188 printk(KERN_ERR PFX
"Could not obtain valid ethernet address, "
13193 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
13194 tp
->aperegs
= pci_ioremap_bar(pdev
, BAR_2
);
13195 if (!tp
->aperegs
) {
13196 printk(KERN_ERR PFX
"Cannot map APE registers, "
13202 tg3_ape_lock_init(tp
);
13206 * Reset chip in case UNDI or EFI driver did not shutdown
13207 * DMA self test will enable WDMAC and we'll see (spurious)
13208 * pending DMA on the PCI bus at that point.
13210 if ((tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
) ||
13211 (tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
13212 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
13213 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
13216 err
= tg3_test_dma(tp
);
13218 printk(KERN_ERR PFX
"DMA engine test failed, aborting.\n");
13219 goto err_out_apeunmap
;
13222 /* flow control autonegotiation is default behavior */
13223 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
13224 tp
->link_config
.flowctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
13228 pci_set_drvdata(pdev
, dev
);
13230 err
= register_netdev(dev
);
13232 printk(KERN_ERR PFX
"Cannot register net device, "
13234 goto err_out_apeunmap
;
13237 printk(KERN_INFO
"%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13239 tp
->board_part_number
,
13240 tp
->pci_chip_rev_id
,
13241 tg3_bus_string(tp
, str
),
13244 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
)
13246 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13248 tp
->mdio_bus
->phy_map
[PHY_ADDR
]->drv
->name
,
13249 dev_name(&tp
->mdio_bus
->phy_map
[PHY_ADDR
]->dev
));
13252 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13253 tp
->dev
->name
, tg3_phy_string(tp
),
13254 ((tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) ? "10/100Base-TX" :
13255 ((tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) ? "1000Base-SX" :
13256 "10/100/1000Base-T")),
13257 (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
) == 0);
13259 printk(KERN_INFO
"%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13261 (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0,
13262 (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) != 0,
13263 (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) != 0,
13264 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0,
13265 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) != 0);
13266 printk(KERN_INFO
"%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13267 dev
->name
, tp
->dma_rwctrl
,
13268 (pdev
->dma_mask
== DMA_32BIT_MASK
) ? 32 :
13269 (((u64
) pdev
->dma_mask
== DMA_40BIT_MASK
) ? 40 : 64));
13275 iounmap(tp
->aperegs
);
13276 tp
->aperegs
= NULL
;
13281 release_firmware(tp
->fw
);
13293 pci_release_regions(pdev
);
13295 err_out_disable_pdev
:
13296 pci_disable_device(pdev
);
13297 pci_set_drvdata(pdev
, NULL
);
13301 static void __devexit
tg3_remove_one(struct pci_dev
*pdev
)
13303 struct net_device
*dev
= pci_get_drvdata(pdev
);
13306 struct tg3
*tp
= netdev_priv(dev
);
13309 release_firmware(tp
->fw
);
13311 flush_scheduled_work();
13313 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
13318 unregister_netdev(dev
);
13320 iounmap(tp
->aperegs
);
13321 tp
->aperegs
= NULL
;
13328 pci_release_regions(pdev
);
13329 pci_disable_device(pdev
);
13330 pci_set_drvdata(pdev
, NULL
);
13334 static int tg3_suspend(struct pci_dev
*pdev
, pm_message_t state
)
13336 struct net_device
*dev
= pci_get_drvdata(pdev
);
13337 struct tg3
*tp
= netdev_priv(dev
);
13338 pci_power_t target_state
;
13341 /* PCI register 4 needs to be saved whether netif_running() or not.
13342 * MSI address and data need to be saved if using MSI and
13345 pci_save_state(pdev
);
13347 if (!netif_running(dev
))
13350 flush_scheduled_work();
13352 tg3_netif_stop(tp
);
13354 del_timer_sync(&tp
->timer
);
13356 tg3_full_lock(tp
, 1);
13357 tg3_disable_ints(tp
);
13358 tg3_full_unlock(tp
);
13360 netif_device_detach(dev
);
13362 tg3_full_lock(tp
, 0);
13363 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
13364 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
13365 tg3_full_unlock(tp
);
13367 target_state
= pdev
->pm_cap
? pci_target_state(pdev
) : PCI_D3hot
;
13369 err
= tg3_set_power_state(tp
, target_state
);
13373 tg3_full_lock(tp
, 0);
13375 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
13376 err2
= tg3_restart_hw(tp
, 1);
13380 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
13381 add_timer(&tp
->timer
);
13383 netif_device_attach(dev
);
13384 tg3_netif_start(tp
);
13387 tg3_full_unlock(tp
);
13396 static int tg3_resume(struct pci_dev
*pdev
)
13398 struct net_device
*dev
= pci_get_drvdata(pdev
);
13399 struct tg3
*tp
= netdev_priv(dev
);
13402 pci_restore_state(tp
->pdev
);
13404 if (!netif_running(dev
))
13407 err
= tg3_set_power_state(tp
, PCI_D0
);
13411 netif_device_attach(dev
);
13413 tg3_full_lock(tp
, 0);
13415 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
13416 err
= tg3_restart_hw(tp
, 1);
13420 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
13421 add_timer(&tp
->timer
);
13423 tg3_netif_start(tp
);
13426 tg3_full_unlock(tp
);
13434 static struct pci_driver tg3_driver
= {
13435 .name
= DRV_MODULE_NAME
,
13436 .id_table
= tg3_pci_tbl
,
13437 .probe
= tg3_init_one
,
13438 .remove
= __devexit_p(tg3_remove_one
),
13439 .suspend
= tg3_suspend
,
13440 .resume
= tg3_resume
13443 static int __init
tg3_init(void)
13445 return pci_register_driver(&tg3_driver
);
13448 static void __exit
tg3_cleanup(void)
13450 pci_unregister_driver(&tg3_driver
);
13453 module_init(tg3_init
);
13454 module_exit(tg3_cleanup
);