2 * linux/arch/alpha/kernel/sys_eb64p.c
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1996 Jay A Estabrook
6 * Copyright (C) 1998, 1999 Richard Henderson
8 * Code supporting the EB64+ and EB66.
11 #include <linux/kernel.h>
12 #include <linux/types.h>
14 #include <linux/sched.h>
15 #include <linux/pci.h>
16 #include <linux/init.h>
17 #include <linux/bitops.h>
19 #include <asm/ptrace.h>
20 #include <asm/system.h>
23 #include <asm/mmu_context.h>
25 #include <asm/pgtable.h>
26 #include <asm/core_apecs.h>
27 #include <asm/core_lca.h>
28 #include <asm/hwrpb.h>
29 #include <asm/tlbflush.h>
34 #include "machvec_impl.h"
37 /* Note mask bit is true for DISABLED irqs. */
38 static unsigned int cached_irq_mask
= -1;
41 eb64p_update_irq_hw(unsigned int irq
, unsigned long mask
)
43 outb(mask
>> (irq
>= 24 ? 24 : 16), (irq
>= 24 ? 0x27 : 0x26));
47 eb64p_enable_irq(struct irq_data
*d
)
49 eb64p_update_irq_hw(d
->irq
, cached_irq_mask
&= ~(1 << d
->irq
));
53 eb64p_disable_irq(struct irq_data
*d
)
55 eb64p_update_irq_hw(d
->irq
, cached_irq_mask
|= 1 << d
->irq
);
58 static struct irq_chip eb64p_irq_type
= {
60 .irq_unmask
= eb64p_enable_irq
,
61 .irq_mask
= eb64p_disable_irq
,
62 .irq_mask_ack
= eb64p_disable_irq
,
66 eb64p_device_interrupt(unsigned long vector
)
71 /* Read the interrupt summary registers */
72 pld
= inb(0x26) | (inb(0x27) << 8);
75 * Now, for every possible bit set, work through
76 * them and call the appropriate interrupt handler.
80 pld
&= pld
- 1; /* clear least bit set */
83 isa_device_interrupt(vector
);
95 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_CABRIOLET)
97 * CABRIO SRM may not set variation correctly, so here we test
98 * the high word of the interrupt summary register for the RAZ
99 * bits, and hope that a true EB64+ would read all ones...
101 if (inw(0x806) != 0xffff) {
102 extern struct alpha_machine_vector cabriolet_mv
;
104 printk("Detected Cabriolet: correcting HWRPB.\n");
106 hwrpb
->sys_variation
|= 2L << 10;
107 hwrpb_update_checksum(hwrpb
);
109 alpha_mv
= cabriolet_mv
;
120 for (i
= 16; i
< 32; ++i
) {
121 set_irq_chip_and_handler(i
, &eb64p_irq_type
, handle_level_irq
);
122 irq_set_status_flags(i
, IRQ_LEVEL
);
125 common_init_isa_dma();
126 setup_irq(16+5, &isa_cascade_irqaction
);
130 * PCI Fixup configuration.
132 * There are two 8 bit external summary registers as follows:
136 * 0 Interrupt Line A from slot 0
137 * 1 Interrupt Line A from slot 1
138 * 2 Interrupt Line B from slot 0
139 * 3 Interrupt Line B from slot 1
140 * 4 Interrupt Line C from slot 0
141 * 5 Interrupt line from the two ISA PICs
147 * 0 Interrupt Line C from slot 1
148 * 1 Interrupt Line D from slot 0
149 * 2 Interrupt Line D from slot 1
156 * The device to slot mapping looks like:
159 * 5 NCR SCSI controller
160 * 6 PCI on board slot 0
161 * 7 PCI on board slot 1
162 * 8 Intel SIO PCI-ISA bridge chip
163 * 9 Tulip - DECchip 21040 Ethernet controller
166 * This two layered interrupt approach means that we allocate IRQ 16 and
167 * above for PCI interrupts. The IRQ relates to which bit the interrupt
168 * comes in on. This makes interrupt processing much easier.
172 eb64p_map_irq(struct pci_dev
*dev
, u8 slot
, u8 pin
)
174 static char irq_tab
[5][5] __initdata
= {
175 /*INT INTA INTB INTC INTD */
176 {16+7, 16+7, 16+7, 16+7, 16+7}, /* IdSel 5, slot ?, ?? */
177 {16+0, 16+0, 16+2, 16+4, 16+9}, /* IdSel 6, slot ?, ?? */
178 {16+1, 16+1, 16+3, 16+8, 16+10}, /* IdSel 7, slot ?, ?? */
179 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
180 {16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 9, TULIP */
182 const long min_idsel
= 5, max_idsel
= 9, irqs_per_slot
= 5;
183 return COMMON_TABLE_LOOKUP
;
191 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB64P)
192 struct alpha_machine_vector eb64p_mv __initmv
= {
193 .vector_name
= "EB64+",
197 .machine_check
= apecs_machine_check
,
198 .max_isa_dma_address
= ALPHA_MAX_ISA_DMA_ADDRESS
,
199 .min_io_address
= DEFAULT_IO_BASE
,
200 .min_mem_address
= APECS_AND_LCA_DEFAULT_MEM_BASE
,
203 .device_interrupt
= eb64p_device_interrupt
,
205 .init_arch
= apecs_init_arch
,
206 .init_irq
= eb64p_init_irq
,
207 .init_rtc
= common_init_rtc
,
208 .init_pci
= common_init_pci
,
210 .pci_map_irq
= eb64p_map_irq
,
211 .pci_swizzle
= common_swizzle
,
216 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB66)
217 struct alpha_machine_vector eb66_mv __initmv
= {
218 .vector_name
= "EB66",
222 .machine_check
= lca_machine_check
,
223 .max_isa_dma_address
= ALPHA_MAX_ISA_DMA_ADDRESS
,
224 .min_io_address
= DEFAULT_IO_BASE
,
225 .min_mem_address
= APECS_AND_LCA_DEFAULT_MEM_BASE
,
228 .device_interrupt
= eb64p_device_interrupt
,
230 .init_arch
= lca_init_arch
,
231 .init_irq
= eb64p_init_irq
,
232 .init_rtc
= common_init_rtc
,
233 .init_pci
= common_init_pci
,
234 .pci_map_irq
= eb64p_map_irq
,
235 .pci_swizzle
= common_swizzle
,