2 * linux/arch/alpha/kernel/core_mcpcia.c
4 * Based on code written by David A Rusling (david.rusling@reo.mts.dec.com).
6 * Code common to all MCbus-PCI Adaptor core logic chipsets
9 #define __EXTERN_INLINE inline
11 #include <asm/core_mcpcia.h>
12 #undef __EXTERN_INLINE
14 #include <linux/types.h>
15 #include <linux/pci.h>
16 #include <linux/sched.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
20 #include <asm/ptrace.h>
26 * NOTE: Herein lie back-to-back mb instructions. They are magic.
27 * One plausible explanation is that the i/o controller does not properly
28 * handle the system transaction. Another involves timing. Ho hum.
32 * BIOS32-style PCI interface:
38 # define DBG_CFG(args) printk args
40 # define DBG_CFG(args)
44 * Given a bus, device, and function number, compute resulting
45 * configuration space address and setup the MCPCIA_HAXR2 register
46 * accordingly. It is therefore not safe to have concurrent
47 * invocations to configuration space access routines, but there
48 * really shouldn't be any need for this.
52 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
53 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
54 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
55 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
56 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
58 * 31:11 Device select bit.
59 * 10:8 Function number
64 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
65 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
66 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
67 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
68 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
71 * 23:16 bus number (8 bits = 128 possible buses)
72 * 15:11 Device number (5 bits)
73 * 10:8 function number
77 * The function number selects which function of a multi-function device
78 * (e.g., SCSI and Ethernet).
80 * The register selects a DWORD (32 bit) register offset. Hence it
81 * doesn't get shifted by 2 bits as we want to "drop" the bottom two
86 conf_read(unsigned long addr
, unsigned char type1
,
87 struct pci_controller
*hose
)
90 unsigned long mid
= MCPCIA_HOSE2MID(hose
->index
);
91 unsigned int stat0
, value
, temp
, cpu
;
93 cpu
= smp_processor_id();
95 local_irq_save(flags
);
97 DBG_CFG(("conf_read(addr=0x%lx, type1=%d, hose=%d)\n",
100 /* Reset status register to avoid losing errors. */
101 stat0
= *(vuip
)MCPCIA_CAP_ERR(mid
);
102 *(vuip
)MCPCIA_CAP_ERR(mid
) = stat0
;
104 temp
= *(vuip
)MCPCIA_CAP_ERR(mid
);
105 DBG_CFG(("conf_read: MCPCIA_CAP_ERR(%d) was 0x%x\n", mid
, stat0
));
109 mcheck_expected(cpu
) = 1;
110 mcheck_taken(cpu
) = 0;
111 mcheck_extra(cpu
) = mid
;
114 /* Access configuration space. */
115 value
= *((vuip
)addr
);
119 if (mcheck_taken(cpu
)) {
120 mcheck_taken(cpu
) = 0;
124 mcheck_expected(cpu
) = 0;
127 DBG_CFG(("conf_read(): finished\n"));
129 local_irq_restore(flags
);
134 conf_write(unsigned long addr
, unsigned int value
, unsigned char type1
,
135 struct pci_controller
*hose
)
138 unsigned long mid
= MCPCIA_HOSE2MID(hose
->index
);
139 unsigned int stat0
, temp
, cpu
;
141 cpu
= smp_processor_id();
143 local_irq_save(flags
); /* avoid getting hit by machine check */
145 /* Reset status register to avoid losing errors. */
146 stat0
= *(vuip
)MCPCIA_CAP_ERR(mid
);
147 *(vuip
)MCPCIA_CAP_ERR(mid
) = stat0
; mb();
148 temp
= *(vuip
)MCPCIA_CAP_ERR(mid
);
149 DBG_CFG(("conf_write: MCPCIA CAP_ERR(%d) was 0x%x\n", mid
, stat0
));
152 mcheck_expected(cpu
) = 1;
153 mcheck_extra(cpu
) = mid
;
156 /* Access configuration space. */
157 *((vuip
)addr
) = value
;
160 temp
= *(vuip
)MCPCIA_CAP_ERR(mid
); /* read to force the write */
161 mcheck_expected(cpu
) = 0;
164 DBG_CFG(("conf_write(): finished\n"));
165 local_irq_restore(flags
);
169 mk_conf_addr(struct pci_bus
*pbus
, unsigned int devfn
, int where
,
170 struct pci_controller
*hose
, unsigned long *pci_addr
,
171 unsigned char *type1
)
173 u8 bus
= pbus
->number
;
176 DBG_CFG(("mk_conf_addr(bus=%d,devfn=0x%x,hose=%d,where=0x%x,"
177 " pci_addr=0x%p, type1=0x%p)\n",
178 bus
, devfn
, hose
->index
, where
, pci_addr
, type1
));
180 /* Type 1 configuration cycle for *ALL* busses. */
183 if (!pbus
->parent
) /* No parent means peer PCI bus. */
185 addr
= (bus
<< 16) | (devfn
<< 8) | (where
);
186 addr
<<= 5; /* swizzle for SPARSE */
187 addr
|= hose
->config_space_base
;
190 DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr
));
195 mcpcia_read_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
196 int size
, u32
*value
)
198 struct pci_controller
*hose
= bus
->sysdata
;
199 unsigned long addr
, w
;
202 if (mk_conf_addr(bus
, devfn
, where
, hose
, &addr
, &type1
))
203 return PCIBIOS_DEVICE_NOT_FOUND
;
205 addr
|= (size
- 1) * 8;
206 w
= conf_read(addr
, type1
, hose
);
209 *value
= __kernel_extbl(w
, where
& 3);
212 *value
= __kernel_extwl(w
, where
& 3);
218 return PCIBIOS_SUCCESSFUL
;
222 mcpcia_write_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
225 struct pci_controller
*hose
= bus
->sysdata
;
229 if (mk_conf_addr(bus
, devfn
, where
, hose
, &addr
, &type1
))
230 return PCIBIOS_DEVICE_NOT_FOUND
;
232 addr
|= (size
- 1) * 8;
233 value
= __kernel_insql(value
, where
& 3);
234 conf_write(addr
, value
, type1
, hose
);
235 return PCIBIOS_SUCCESSFUL
;
238 struct pci_ops mcpcia_pci_ops
=
240 .read
= mcpcia_read_config
,
241 .write
= mcpcia_write_config
,
245 mcpcia_pci_tbi(struct pci_controller
*hose
, dma_addr_t start
, dma_addr_t end
)
248 *(vuip
)MCPCIA_SG_TBIA(MCPCIA_HOSE2MID(hose
->index
)) = 0;
253 mcpcia_probe_hose(int h
)
255 int cpu
= smp_processor_id();
256 int mid
= MCPCIA_HOSE2MID(h
);
257 unsigned int pci_rev
;
259 /* Gotta be REAL careful. If hose is absent, we get an mcheck. */
266 mcheck_expected(cpu
) = 2; /* indicates probing */
267 mcheck_taken(cpu
) = 0;
268 mcheck_extra(cpu
) = mid
;
271 /* Access the bus revision word. */
272 pci_rev
= *(vuip
)MCPCIA_REV(mid
);
276 if (mcheck_taken(cpu
)) {
277 mcheck_taken(cpu
) = 0;
278 pci_rev
= 0xffffffff;
281 mcheck_expected(cpu
) = 0;
284 return (pci_rev
>> 16) == PCI_CLASS_BRIDGE_HOST
;
288 mcpcia_new_hose(int h
)
290 struct pci_controller
*hose
;
291 struct resource
*io
, *mem
, *hae_mem
;
292 int mid
= MCPCIA_HOSE2MID(h
);
294 hose
= alloc_pci_controller();
297 io
= alloc_resource();
298 mem
= alloc_resource();
299 hae_mem
= alloc_resource();
302 hose
->mem_space
= hae_mem
;
303 hose
->sparse_mem_base
= MCPCIA_SPARSE(mid
) - IDENT_ADDR
;
304 hose
->dense_mem_base
= MCPCIA_DENSE(mid
) - IDENT_ADDR
;
305 hose
->sparse_io_base
= MCPCIA_IO(mid
) - IDENT_ADDR
;
306 hose
->dense_io_base
= 0;
307 hose
->config_space_base
= MCPCIA_CONF(mid
);
310 io
->start
= MCPCIA_IO(mid
) - MCPCIA_IO_BIAS
;
311 io
->end
= io
->start
+ 0xffff;
312 io
->name
= pci_io_names
[h
];
313 io
->flags
= IORESOURCE_IO
;
315 mem
->start
= MCPCIA_DENSE(mid
) - MCPCIA_MEM_BIAS
;
316 mem
->end
= mem
->start
+ 0xffffffff;
317 mem
->name
= pci_mem_names
[h
];
318 mem
->flags
= IORESOURCE_MEM
;
320 hae_mem
->start
= mem
->start
;
321 hae_mem
->end
= mem
->start
+ MCPCIA_MEM_MASK
;
322 hae_mem
->name
= pci_hae0_name
;
323 hae_mem
->flags
= IORESOURCE_MEM
;
325 if (request_resource(&ioport_resource
, io
) < 0)
326 printk(KERN_ERR
"Failed to request IO on hose %d\n", h
);
327 if (request_resource(&iomem_resource
, mem
) < 0)
328 printk(KERN_ERR
"Failed to request MEM on hose %d\n", h
);
329 if (request_resource(mem
, hae_mem
) < 0)
330 printk(KERN_ERR
"Failed to request HAE_MEM on hose %d\n", h
);
334 mcpcia_pci_clr_err(int mid
)
336 *(vuip
)MCPCIA_CAP_ERR(mid
);
337 *(vuip
)MCPCIA_CAP_ERR(mid
) = 0xffffffff; /* Clear them all. */
339 *(vuip
)MCPCIA_CAP_ERR(mid
); /* Re-read for force write. */
343 mcpcia_startup_hose(struct pci_controller
*hose
)
345 int mid
= MCPCIA_HOSE2MID(hose
->index
);
348 mcpcia_pci_clr_err(mid
);
351 * Set up error reporting.
353 tmp
= *(vuip
)MCPCIA_CAP_ERR(mid
);
354 tmp
|= 0x0006; /* master/target abort */
355 *(vuip
)MCPCIA_CAP_ERR(mid
) = tmp
;
357 tmp
= *(vuip
)MCPCIA_CAP_ERR(mid
);
360 * Set up the PCI->physical memory translation windows.
362 * Window 0 is scatter-gather 8MB at 8MB (for isa)
363 * Window 1 is scatter-gather (up to) 1GB at 1GB (for pci)
364 * Window 2 is direct access 2GB at 2GB
366 hose
->sg_isa
= iommu_arena_new(hose
, 0x00800000, 0x00800000, 0);
367 hose
->sg_pci
= iommu_arena_new(hose
, 0x40000000,
368 size_for_memory(0x40000000), 0);
370 __direct_map_base
= 0x80000000;
371 __direct_map_size
= 0x80000000;
373 *(vuip
)MCPCIA_W0_BASE(mid
) = hose
->sg_isa
->dma_base
| 3;
374 *(vuip
)MCPCIA_W0_MASK(mid
) = (hose
->sg_isa
->size
- 1) & 0xfff00000;
375 *(vuip
)MCPCIA_T0_BASE(mid
) = virt_to_phys(hose
->sg_isa
->ptes
) >> 8;
377 *(vuip
)MCPCIA_W1_BASE(mid
) = hose
->sg_pci
->dma_base
| 3;
378 *(vuip
)MCPCIA_W1_MASK(mid
) = (hose
->sg_pci
->size
- 1) & 0xfff00000;
379 *(vuip
)MCPCIA_T1_BASE(mid
) = virt_to_phys(hose
->sg_pci
->ptes
) >> 8;
381 *(vuip
)MCPCIA_W2_BASE(mid
) = __direct_map_base
| 1;
382 *(vuip
)MCPCIA_W2_MASK(mid
) = (__direct_map_size
- 1) & 0xfff00000;
383 *(vuip
)MCPCIA_T2_BASE(mid
) = 0;
385 *(vuip
)MCPCIA_W3_BASE(mid
) = 0x0;
387 mcpcia_pci_tbi(hose
, 0, -1);
389 *(vuip
)MCPCIA_HBASE(mid
) = 0x0;
392 *(vuip
)MCPCIA_HAE_MEM(mid
) = 0U;
394 *(vuip
)MCPCIA_HAE_MEM(mid
); /* read it back. */
395 *(vuip
)MCPCIA_HAE_IO(mid
) = 0;
397 *(vuip
)MCPCIA_HAE_IO(mid
); /* read it back. */
401 mcpcia_init_arch(void)
403 /* With multiple PCI busses, we play with I/O as physical addrs. */
404 ioport_resource
.end
= ~0UL;
406 /* Allocate hose 0. That's the one that all the ISA junk hangs
407 off of, from which we'll be registering stuff here in a bit.
408 Other hose detection is done in mcpcia_init_hoses, which is
409 called from init_IRQ. */
414 /* This is called from init_IRQ, since we cannot take interrupts
415 before then. Which means we cannot do this in init_arch. */
418 mcpcia_init_hoses(void)
420 struct pci_controller
*hose
;
424 /* First, find how many hoses we have. */
426 for (h
= 0; h
< MCPCIA_MAX_HOSES
; ++h
) {
427 if (mcpcia_probe_hose(h
)) {
434 printk("mcpcia_init_hoses: found %d hoses\n", hose_count
);
436 /* Now do init for each hose. */
437 for (hose
= hose_head
; hose
; hose
= hose
->next
)
438 mcpcia_startup_hose(hose
);
442 mcpcia_print_uncorrectable(struct el_MCPCIA_uncorrected_frame_mcheck
*logout
)
444 struct el_common_EV5_uncorrectable_mcheck
*frame
;
447 frame
= &logout
->procdata
;
449 /* Print PAL fields */
450 for (i
= 0; i
< 24; i
+= 2) {
451 printk(" paltmp[%d-%d] = %16lx %16lx\n",
452 i
, i
+1, frame
->paltemp
[i
], frame
->paltemp
[i
+1]);
454 for (i
= 0; i
< 8; i
+= 2) {
455 printk(" shadow[%d-%d] = %16lx %16lx\n",
456 i
, i
+1, frame
->shadow
[i
],
459 printk(" Addr of excepting instruction = %16lx\n",
461 printk(" Summary of arithmetic traps = %16lx\n",
463 printk(" Exception mask = %16lx\n",
465 printk(" Base address for PALcode = %16lx\n",
467 printk(" Interrupt Status Reg = %16lx\n",
469 printk(" CURRENT SETUP OF EV5 IBOX = %16lx\n",
471 printk(" I-CACHE Reg %s parity error = %16lx\n",
472 (frame
->ic_perr_stat
& 0x800L
) ?
474 frame
->ic_perr_stat
);
475 printk(" D-CACHE error Reg = %16lx\n",
476 frame
->dc_perr_stat
);
477 if (frame
->dc_perr_stat
& 0x2) {
478 switch (frame
->dc_perr_stat
& 0x03c) {
480 printk(" Data error in bank 1\n");
483 printk(" Data error in bank 0\n");
486 printk(" Tag error in bank 1\n");
489 printk(" Tag error in bank 0\n");
493 printk(" Effective VA = %16lx\n",
495 printk(" Reason for D-stream = %16lx\n",
497 printk(" EV5 SCache address = %16lx\n",
499 printk(" EV5 SCache TAG/Data parity = %16lx\n",
501 printk(" EV5 BC_TAG_ADDR = %16lx\n",
503 printk(" EV5 EI_ADDR: Phys addr of Xfer = %16lx\n",
505 printk(" Fill Syndrome = %16lx\n",
506 frame
->fill_syndrome
);
507 printk(" EI_STAT reg = %16lx\n",
509 printk(" LD_LOCK = %16lx\n",
514 mcpcia_print_system_area(unsigned long la_ptr
)
516 struct el_common
*frame
;
517 struct pci_controller
*hose
;
519 struct IOD_subpacket
{
523 unsigned int pci_rev
;
524 unsigned int cap_ctrl
;
525 unsigned int hae_mem
;
527 unsigned int int_ctl
;
528 unsigned int int_reg
;
529 unsigned int int_mask0
;
530 unsigned int int_mask1
;
531 unsigned int mc_err0
;
532 unsigned int mc_err1
;
533 unsigned int cap_err
;
535 unsigned int pci_err1
;
536 unsigned int mdpa_stat
;
537 unsigned int mdpa_syn
;
538 unsigned int mdpb_stat
;
539 unsigned int mdpb_syn
;
545 frame
= (struct el_common
*)la_ptr
;
546 iodpp
= (struct IOD_subpacket
*) (la_ptr
+ frame
->sys_offset
);
548 for (hose
= hose_head
; hose
; hose
= hose
->next
, iodpp
++) {
550 printk("IOD %d Register Subpacket - Bridge Base Address %16lx\n",
551 hose
->index
, iodpp
->base
);
552 printk(" WHOAMI = %8x\n", iodpp
->whoami
);
553 printk(" PCI_REV = %8x\n", iodpp
->pci_rev
);
554 printk(" CAP_CTRL = %8x\n", iodpp
->cap_ctrl
);
555 printk(" HAE_MEM = %8x\n", iodpp
->hae_mem
);
556 printk(" HAE_IO = %8x\n", iodpp
->hae_io
);
557 printk(" INT_CTL = %8x\n", iodpp
->int_ctl
);
558 printk(" INT_REG = %8x\n", iodpp
->int_reg
);
559 printk(" INT_MASK0 = %8x\n", iodpp
->int_mask0
);
560 printk(" INT_MASK1 = %8x\n", iodpp
->int_mask1
);
561 printk(" MC_ERR0 = %8x\n", iodpp
->mc_err0
);
562 printk(" MC_ERR1 = %8x\n", iodpp
->mc_err1
);
563 printk(" CAP_ERR = %8x\n", iodpp
->cap_err
);
564 printk(" PCI_ERR1 = %8x\n", iodpp
->pci_err1
);
565 printk(" MDPA_STAT = %8x\n", iodpp
->mdpa_stat
);
566 printk(" MDPA_SYN = %8x\n", iodpp
->mdpa_syn
);
567 printk(" MDPB_STAT = %8x\n", iodpp
->mdpb_stat
);
568 printk(" MDPB_SYN = %8x\n", iodpp
->mdpb_syn
);
573 mcpcia_machine_check(unsigned long vector
, unsigned long la_ptr
)
575 struct el_common
*mchk_header
;
576 struct el_MCPCIA_uncorrected_frame_mcheck
*mchk_logout
;
577 unsigned int cpu
= smp_processor_id();
580 mchk_header
= (struct el_common
*)la_ptr
;
581 mchk_logout
= (struct el_MCPCIA_uncorrected_frame_mcheck
*)la_ptr
;
582 expected
= mcheck_expected(cpu
);
591 /* FIXME: how do we figure out which hose the
593 struct pci_controller
*hose
;
594 for (hose
= hose_head
; hose
; hose
= hose
->next
)
595 mcpcia_pci_clr_err(MCPCIA_HOSE2MID(hose
->index
));
599 mcpcia_pci_clr_err(mcheck_extra(cpu
));
602 /* Otherwise, we're being called from mcpcia_probe_hose
603 and there's no hose clear an error from. */
610 process_mcheck_info(vector
, la_ptr
, "MCPCIA", expected
!= 0);
611 if (!expected
&& vector
!= 0x620 && vector
!= 0x630) {
612 mcpcia_print_uncorrectable(mchk_logout
);
613 mcpcia_print_system_area(la_ptr
);