drivers/net/ps3_gelic_net.h

   1 /*
   2  *  PS3 Platfom gelic network driver.
   3  *
   4  * Copyright (C) 2007 Sony Computer Entertainment Inc.
   5  * Copyright 2006, 2007 Sony Corporation.
   6  *
   7  * This file is based on: spider_net.h
   8  *
   9  * (C) Copyright IBM Corp. 2005
  10  *
  11  * Authors : Utz Bacher <utz.bacher@de.ibm.com>
  12  *           Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2, or (at your option)
  17  * any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  27  */
  28 #ifndef _GELIC_NET_H
  29 #define _GELIC_NET_H
  30
  31 /* descriptors */
  32 #define GELIC_NET_RX_DESCRIPTORS        128 /* num of descriptors */
  33 #define GELIC_NET_TX_DESCRIPTORS        128 /* num of descriptors */
  34
  35 #define GELIC_NET_MAX_MTU               VLAN_ETH_FRAME_LEN
  36 #define GELIC_NET_MIN_MTU               VLAN_ETH_ZLEN
  37 #define GELIC_NET_RXBUF_ALIGN           128
  38 #define GELIC_CARD_RX_CSUM_DEFAULT      1 /* hw chksum */
  39 #define GELIC_NET_WATCHDOG_TIMEOUT      5*HZ
  40 #define GELIC_NET_NAPI_WEIGHT           (GELIC_NET_RX_DESCRIPTORS)
  41 #define GELIC_NET_BROADCAST_ADDR        0xffffffffffffL
  42
  43 #define GELIC_NET_MC_COUNT_MAX          32 /* multicast address list */
  44
  45 /* virtual interrupt status register bits */
  46         /* INT1 */
  47 #define GELIC_CARD_TX_RAM_FULL_ERR           0x0000000000000001L
  48 #define GELIC_CARD_RX_RAM_FULL_ERR           0x0000000000000002L
  49 #define GELIC_CARD_TX_SHORT_FRAME_ERR        0x0000000000000004L
  50 #define GELIC_CARD_TX_INVALID_DESCR_ERR      0x0000000000000008L
  51 #define GELIC_CARD_RX_FIFO_FULL_ERR          0x0000000000002000L
  52 #define GELIC_CARD_RX_DESCR_CHAIN_END        0x0000000000004000L
  53 #define GELIC_CARD_RX_INVALID_DESCR_ERR      0x0000000000008000L
  54 #define GELIC_CARD_TX_RESPONCE_ERR           0x0000000000010000L
  55 #define GELIC_CARD_RX_RESPONCE_ERR           0x0000000000100000L
  56 #define GELIC_CARD_TX_PROTECTION_ERR         0x0000000000400000L
  57 #define GELIC_CARD_RX_PROTECTION_ERR         0x0000000004000000L
  58 #define GELIC_CARD_TX_TCP_UDP_CHECKSUM_ERR   0x0000000008000000L
  59 #define GELIC_CARD_PORT_STATUS_CHANGED       0x0000000020000000L
  60 #define GELIC_CARD_WLAN_EVENT_RECEIVED       0x0000000040000000L
  61 #define GELIC_CARD_WLAN_COMMAND_COMPLETED    0x0000000080000000L
  62         /* INT 0 */
  63 #define GELIC_CARD_TX_FLAGGED_DESCR          0x0004000000000000L
  64 #define GELIC_CARD_RX_FLAGGED_DESCR          0x0040000000000000L
  65 #define GELIC_CARD_TX_TRANSFER_END           0x0080000000000000L
  66 #define GELIC_CARD_TX_DESCR_CHAIN_END        0x0100000000000000L
  67 #define GELIC_CARD_NUMBER_OF_RX_FRAME        0x1000000000000000L
  68 #define GELIC_CARD_ONE_TIME_COUNT_TIMER      0x4000000000000000L
  69 #define GELIC_CARD_FREE_RUN_COUNT_TIMER      0x8000000000000000L
  70
  71 /* initial interrupt mask */
  72 #define GELIC_CARD_TXINT        GELIC_CARD_TX_DESCR_CHAIN_END
  73
  74 #define GELIC_CARD_RXINT        (GELIC_CARD_RX_DESCR_CHAIN_END | \
  75                                  GELIC_CARD_NUMBER_OF_RX_FRAME)
  76
  77  /* RX descriptor data_status bits */
  78 enum gelic_descr_rx_status {
  79         GELIC_DESCR_RXDMADU     = 0x80000000, /* destination MAC addr unknown */
  80         GELIC_DESCR_RXLSTFBF    = 0x40000000, /* last frame buffer            */
  81         GELIC_DESCR_RXIPCHK     = 0x20000000, /* IP checksum performed        */
  82         GELIC_DESCR_RXTCPCHK    = 0x10000000, /* TCP/UDP checksup performed   */
  83         GELIC_DESCR_RXWTPKT     = 0x00C00000, /*
  84                                                * wakeup trigger packet
  85                                                * 01: Magic Packet (TM)
  86                                                * 10: ARP packet
  87                                                * 11: Multicast MAC addr
  88                                                */
  89         GELIC_DESCR_RXVLNPKT    = 0x00200000, /* VLAN packet */
  90         /* bit 20..16 reserved */
  91         GELIC_DESCR_RXRRECNUM   = 0x0000ff00, /* reception receipt number */
  92         /* bit 7..0 reserved */
  93 };
  94
  95 #define GELIC_DESCR_DATA_STATUS_CHK_MASK        \
  96         (GELIC_DESCR_RXIPCHK | GELIC_DESCR_RXTCPCHK)
  97
  98  /* TX descriptor data_status bits */
  99 enum gelic_descr_tx_status {
 100         GELIC_DESCR_TX_TAIL     = 0x00000001, /* gelic treated this
 101                                                * descriptor was end of
 102                                                * a tx frame
 103                                                */
 104 };
 105
 106 /* RX descriptor data error bits */
 107 enum gelic_descr_rx_error {
 108         /* bit 31 reserved */
 109         GELIC_DESCR_RXALNERR    = 0x40000000, /* alignement error 10/100M */
 110         GELIC_DESCR_RXOVERERR   = 0x20000000, /* oversize error */
 111         GELIC_DESCR_RXRNTERR    = 0x10000000, /* Runt error */
 112         GELIC_DESCR_RXIPCHKERR  = 0x08000000, /* IP checksum  error */
 113         GELIC_DESCR_RXTCPCHKERR = 0x04000000, /* TCP/UDP checksum  error */
 114         GELIC_DESCR_RXDRPPKT    = 0x00100000, /* drop packet */
 115         GELIC_DESCR_RXIPFMTERR  = 0x00080000, /* IP packet format error */
 116         /* bit 18 reserved */
 117         GELIC_DESCR_RXDATAERR   = 0x00020000, /* IP packet format error */
 118         GELIC_DESCR_RXCALERR    = 0x00010000, /* cariier extension length
 119                                               * error */
 120         GELIC_DESCR_RXCREXERR   = 0x00008000, /* carrier extension error */
 121         GELIC_DESCR_RXMLTCST    = 0x00004000, /* multicast address frame */
 122         /* bit 13..0 reserved */
 123 };
 124 #define GELIC_DESCR_DATA_ERROR_CHK_MASK         \
 125         (GELIC_DESCR_RXIPCHKERR | GELIC_DESCR_RXTCPCHKERR)
 126
 127 /* DMA command and status (RX and TX)*/
 128 enum gelic_descr_dma_status {
 129         GELIC_DESCR_DMA_COMPLETE            = 0x00000000, /* used in tx */
 130         GELIC_DESCR_DMA_BUFFER_FULL         = 0x00000000, /* used in rx */
 131         GELIC_DESCR_DMA_RESPONSE_ERROR      = 0x10000000, /* used in rx, tx */
 132         GELIC_DESCR_DMA_PROTECTION_ERROR    = 0x20000000, /* used in rx, tx */
 133         GELIC_DESCR_DMA_FRAME_END           = 0x40000000, /* used in rx */
 134         GELIC_DESCR_DMA_FORCE_END           = 0x50000000, /* used in rx, tx */
 135         GELIC_DESCR_DMA_CARDOWNED           = 0xa0000000, /* used in rx, tx */
 136         GELIC_DESCR_DMA_NOT_IN_USE          = 0xb0000000, /* any other value */
 137 };
 138
 139 #define GELIC_DESCR_DMA_STAT_MASK       (0xf0000000)
 140
 141 /* tx descriptor command and status */
 142 enum gelic_descr_tx_dma_status {
 143         /* [19] */
 144         GELIC_DESCR_TX_DMA_IKE          = 0x00080000, /* IPSEC off */
 145         /* [18] */
 146         GELIC_DESCR_TX_DMA_FRAME_TAIL   = 0x00040000, /* last descriptor of
 147                                                        * the packet
 148                                                        */
 149         /* [17..16] */
 150         GELIC_DESCR_TX_DMA_TCP_CHKSUM   = 0x00020000, /* TCP packet */
 151         GELIC_DESCR_TX_DMA_UDP_CHKSUM   = 0x00030000, /* UDP packet */
 152         GELIC_DESCR_TX_DMA_NO_CHKSUM    = 0x00000000, /* no checksum */
 153
 154         /* [1] */
 155         GELIC_DESCR_TX_DMA_CHAIN_END    = 0x00000002, /* DMA terminated
 156                                                        * due to chain end
 157                                                        */
 158 };
 159
 160 #define GELIC_DESCR_DMA_CMD_NO_CHKSUM   \
 161         (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
 162         GELIC_DESCR_TX_DMA_NO_CHKSUM)
 163
 164 #define GELIC_DESCR_DMA_CMD_TCP_CHKSUM  \
 165         (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
 166         GELIC_DESCR_TX_DMA_TCP_CHKSUM)
 167
 168 #define GELIC_DESCR_DMA_CMD_UDP_CHKSUM  \
 169         (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
 170         GELIC_DESCR_TX_DMA_UDP_CHKSUM)
 171
 172 enum gelic_descr_rx_dma_status {
 173         /* [ 1 ] */
 174         GELIC_DESCR_RX_DMA_CHAIN_END    = 0x00000002, /* DMA terminated
 175                                                        * due to chain end
 176                                                        */
 177 };
 178
 179 /* for lv1_net_control */
 180 enum gelic_lv1_net_control_code {
 181         GELIC_LV1_GET_MAC_ADDRESS       = 1,
 182         GELIC_LV1_GET_ETH_PORT_STATUS   = 2,
 183         GELIC_LV1_SET_NEGOTIATION_MODE  = 3,
 184         GELIC_LV1_GET_VLAN_ID           = 4,
 185         GELIC_LV1_SET_WOL               = 5,
 186         GELIC_LV1_GET_CHANNEL           = 6,
 187         GELIC_LV1_POST_WLAN_CMD         = 9,
 188         GELIC_LV1_GET_WLAN_CMD_RESULT   = 10,
 189         GELIC_LV1_GET_WLAN_EVENT        = 11,
 190 };
 191
 192 /* for GELIC_LV1_SET_WOL */
 193 enum gelic_lv1_wol_command {
 194         GELIC_LV1_WOL_MAGIC_PACKET      = 1,
 195         GELIC_LV1_WOL_ADD_MATCH_ADDR    = 6,
 196         GELIC_LV1_WOL_DELETE_MATCH_ADDR = 7,
 197 };
 198
 199 /* for GELIC_LV1_WOL_MAGIC_PACKET */
 200 enum gelic_lv1_wol_mp_arg {
 201         GELIC_LV1_WOL_MP_DISABLE        = 0,
 202         GELIC_LV1_WOL_MP_ENABLE         = 1,
 203 };
 204
 205 /* for GELIC_LV1_WOL_{ADD,DELETE}_MATCH_ADDR */
 206 enum gelic_lv1_wol_match_arg {
 207         GELIC_LV1_WOL_MATCH_INDIVIDUAL  = 0,
 208         GELIC_LV1_WOL_MATCH_ALL         = 1,
 209 };
 210
 211 /* status returened from GET_ETH_PORT_STATUS */
 212 enum gelic_lv1_ether_port_status {
 213         GELIC_LV1_ETHER_LINK_UP         = 0x0000000000000001L,
 214         GELIC_LV1_ETHER_FULL_DUPLEX     = 0x0000000000000002L,
 215         GELIC_LV1_ETHER_AUTO_NEG        = 0x0000000000000004L,
 216
 217         GELIC_LV1_ETHER_SPEED_10        = 0x0000000000000010L,
 218         GELIC_LV1_ETHER_SPEED_100       = 0x0000000000000020L,
 219         GELIC_LV1_ETHER_SPEED_1000      = 0x0000000000000040L,
 220         GELIC_LV1_ETHER_SPEED_MASK      = 0x0000000000000070L,
 221 };
 222
 223 enum gelic_lv1_vlan_index {
 224         /* for outgoing packets */
 225         GELIC_LV1_VLAN_TX_ETHERNET_0    = 0x0000000000000002L,
 226         GELIC_LV1_VLAN_TX_WIRELESS      = 0x0000000000000003L,
 227
 228         /* for incoming packets */
 229         GELIC_LV1_VLAN_RX_ETHERNET_0    = 0x0000000000000012L,
 230         GELIC_LV1_VLAN_RX_WIRELESS      = 0x0000000000000013L,
 231 };
 232
 233 enum gelic_lv1_phy {
 234         GELIC_LV1_PHY_ETHERNET_0        = 0x0000000000000002L,
 235 };
 236
 237 /* size of hardware part of gelic descriptor */
 238 #define GELIC_DESCR_SIZE        (32)
 239
 240 enum gelic_port_type {
 241         GELIC_PORT_ETHERNET_0   = 0,
 242         GELIC_PORT_WIRELESS     = 1,
 243         GELIC_PORT_MAX
 244 };
 245
 246 struct gelic_descr {
 247         /* as defined by the hardware */
 248         __be32 buf_addr;
 249         __be32 buf_size;
 250         __be32 next_descr_addr;
 251         __be32 dmac_cmd_status;
 252         __be32 result_size;
 253         __be32 valid_size;      /* all zeroes for tx */
 254         __be32 data_status;
 255         __be32 data_error;      /* all zeroes for tx */
 256
 257         /* used in the driver */
 258         struct sk_buff *skb;
 259         dma_addr_t bus_addr;
 260         struct gelic_descr *next;
 261         struct gelic_descr *prev;
 262 } __attribute__((aligned(32)));
 263
 264 struct gelic_descr_chain {
 265         /* we walk from tail to head */
 266         struct gelic_descr *head;
 267         struct gelic_descr *tail;
 268 };
 269
 270 struct gelic_vlan_id {
 271         u16 tx;
 272         u16 rx;
 273 };
 274
 275 struct gelic_card {
 276         struct napi_struct napi;
 277         struct net_device *netdev[GELIC_PORT_MAX];
 278         /*
 279          * hypervisor requires irq_status should be
 280          * 8 bytes aligned, but u64 member is
 281          * always disposed in that manner
 282          */
 283         u64 irq_status;
 284         u64 irq_mask;
 285
 286         struct ps3_system_bus_device *dev;
 287         struct gelic_vlan_id vlan[GELIC_PORT_MAX];
 288         int vlan_required;
 289
 290         struct gelic_descr_chain tx_chain;
 291         struct gelic_descr_chain rx_chain;
 292         int rx_dma_restart_required;
 293         /*
 294          * tx_lock guards tx descriptor list and
 295          * tx_dma_progress.
 296          */
 297         spinlock_t tx_lock;
 298         int tx_dma_progress;
 299
 300         struct work_struct tx_timeout_task;
 301         atomic_t tx_timeout_task_counter;
 302         wait_queue_head_t waitq;
 303
 304         /* only first user should up the card */
 305         struct mutex updown_lock;
 306         atomic_t users;
 307
 308         u64 ether_port_status;
 309         int link_mode;
 310
 311         /* original address returned by kzalloc */
 312         void *unalign;
 313
 314         /*
 315          * each netdevice has copy of irq
 316          */
 317         unsigned int irq;
 318         struct gelic_descr *tx_top, *rx_top;
 319         struct gelic_descr descr[0]; /* must be the last */
 320 };
 321
 322 struct gelic_port {
 323         struct gelic_card *card;
 324         struct net_device *netdev;
 325         enum gelic_port_type type;
 326         long priv[0]; /* long for alignment */
 327 };
 328
 329 static inline struct gelic_card *port_to_card(struct gelic_port *p)
 330 {
 331         return p->card;
 332 }
 333 static inline struct net_device *port_to_netdev(struct gelic_port *p)
 334 {
 335         return p->netdev;
 336 }
 337 static inline struct gelic_card *netdev_card(struct net_device *d)
 338 {
 339         return ((struct gelic_port *)netdev_priv(d))->card;
 340 }
 341 static inline struct gelic_port *netdev_port(struct net_device *d)
 342 {
 343         return (struct gelic_port *)netdev_priv(d);
 344 }
 345 static inline struct device *ctodev(struct gelic_card *card)
 346 {
 347         return &card->dev->core;
 348 }
 349 static inline u64 bus_id(struct gelic_card *card)
 350 {
 351         return card->dev->bus_id;
 352 }
 353 static inline u64 dev_id(struct gelic_card *card)
 354 {
 355         return card->dev->dev_id;
 356 }
 357
 358 static inline void *port_priv(struct gelic_port *port)
 359 {
 360         return port->priv;
 361 }
 362
 363 extern int gelic_card_set_irq_mask(struct gelic_card *card, u64 mask);
 364 /* shared netdev ops */
 365 extern void gelic_card_up(struct gelic_card *card);
 366 extern void gelic_card_down(struct gelic_card *card);
 367 extern int gelic_net_open(struct net_device *netdev);
 368 extern int gelic_net_stop(struct net_device *netdev);
 369 extern int gelic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
 370 extern void gelic_net_set_multi(struct net_device *netdev);
 371 extern void gelic_net_tx_timeout(struct net_device *netdev);
 372 extern int gelic_net_change_mtu(struct net_device *netdev, int new_mtu);
 373 extern int gelic_net_setup_netdev(struct net_device *netdev,
 374                                   struct gelic_card *card);
 375
 376 /* shared ethtool ops */
 377 extern void gelic_net_get_drvinfo(struct net_device *netdev,
 378                                   struct ethtool_drvinfo *info);
 379 extern void gelic_net_poll_controller(struct net_device *netdev);
 380
 381 #endif /* _GELIC_NET_H */