2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
32 #include <linux/dmar.h>
34 #include <asm/atomic.h>
37 #include <asm/mpspec.h>
39 #include <asm/arch_hooks.h>
41 #include <asm/pgalloc.h>
42 #include <asm/i8253.h>
45 #include <asm/proto.h>
46 #include <asm/timex.h>
48 #include <asm/i8259.h>
50 #include <mach_apic.h>
51 #include <mach_apicdef.h>
57 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
58 # error SPURIOUS_APIC_VECTOR definition error
63 * Knob to control our willingness to enable the local APIC.
67 static int force_enable_local_apic
;
69 * APIC command line parameters
71 static int __init
parse_lapic(char *arg
)
73 force_enable_local_apic
= 1;
76 early_param("lapic", parse_lapic
);
77 /* Local APIC was disabled by the BIOS and enabled by the kernel */
78 static int enabled_via_apicbase
;
83 static int apic_calibrate_pmtmr __initdata
;
84 static __init
int setup_apicpmtimer(char *s
)
86 apic_calibrate_pmtmr
= 1;
90 __setup("apicpmtimer", setup_apicpmtimer
);
99 /* x2apic enabled before OS handover */
100 int x2apic_preenabled
;
102 static __init
int setup_nox2apic(char *str
)
105 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
108 early_param("nox2apic", setup_nox2apic
);
111 unsigned long mp_lapic_addr
;
113 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
114 static int disable_apic_timer __cpuinitdata
;
115 /* Local APIC timer works in C2 */
116 int local_apic_timer_c2_ok
;
117 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
119 int first_system_vector
= 0xfe;
121 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
124 * Debug level, exported for io_apic.c
126 unsigned int apic_verbosity
;
130 /* Have we found an MP table */
131 int smp_found_config
;
133 static struct resource lapic_resource
= {
134 .name
= "Local APIC",
135 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
138 static unsigned int calibration_result
;
140 static int lapic_next_event(unsigned long delta
,
141 struct clock_event_device
*evt
);
142 static void lapic_timer_setup(enum clock_event_mode mode
,
143 struct clock_event_device
*evt
);
144 static void lapic_timer_broadcast(cpumask_t mask
);
145 static void apic_pm_activate(void);
148 * The local apic timer can be used for any function which is CPU local.
150 static struct clock_event_device lapic_clockevent
= {
152 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
153 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
155 .set_mode
= lapic_timer_setup
,
156 .set_next_event
= lapic_next_event
,
157 .broadcast
= lapic_timer_broadcast
,
161 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
163 static unsigned long apic_phys
;
166 * Get the LAPIC version
168 static inline int lapic_get_version(void)
170 return GET_APIC_VERSION(apic_read(APIC_LVR
));
174 * Check, if the APIC is integrated or a separate chip
176 static inline int lapic_is_integrated(void)
181 return APIC_INTEGRATED(lapic_get_version());
186 * Check, whether this is a modern or a first generation APIC
188 static int modern_apic(void)
190 /* AMD systems use old APIC versions, so check the CPU */
191 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
192 boot_cpu_data
.x86
>= 0xf)
194 return lapic_get_version() >= 0x14;
198 * Paravirt kernels also might be using these below ops. So we still
199 * use generic apic_read()/apic_write(), which might be pointing to different
200 * ops in PARAVIRT case.
202 void xapic_wait_icr_idle(void)
204 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
208 u32
safe_xapic_wait_icr_idle(void)
215 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
219 } while (timeout
++ < 1000);
224 void xapic_icr_write(u32 low
, u32 id
)
226 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
227 apic_write(APIC_ICR
, low
);
230 u64
xapic_icr_read(void)
234 icr2
= apic_read(APIC_ICR2
);
235 icr1
= apic_read(APIC_ICR
);
237 return icr1
| ((u64
)icr2
<< 32);
240 static struct apic_ops xapic_ops
= {
241 .read
= native_apic_mem_read
,
242 .write
= native_apic_mem_write
,
243 .icr_read
= xapic_icr_read
,
244 .icr_write
= xapic_icr_write
,
245 .wait_icr_idle
= xapic_wait_icr_idle
,
246 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
249 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
250 EXPORT_SYMBOL_GPL(apic_ops
);
253 static void x2apic_wait_icr_idle(void)
255 /* no need to wait for icr idle in x2apic */
259 static u32
safe_x2apic_wait_icr_idle(void)
261 /* no need to wait for icr idle in x2apic */
265 void x2apic_icr_write(u32 low
, u32 id
)
267 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
270 u64
x2apic_icr_read(void)
274 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
278 static struct apic_ops x2apic_ops
= {
279 .read
= native_apic_msr_read
,
280 .write
= native_apic_msr_write
,
281 .icr_read
= x2apic_icr_read
,
282 .icr_write
= x2apic_icr_write
,
283 .wait_icr_idle
= x2apic_wait_icr_idle
,
284 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
289 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
291 void __cpuinit
enable_NMI_through_LVT0(void)
295 /* unmask and set to NMI */
298 /* Level triggered for 82489DX (32bit mode) */
299 if (!lapic_is_integrated())
300 v
|= APIC_LVT_LEVEL_TRIGGER
;
302 apic_write(APIC_LVT0
, v
);
307 * get_physical_broadcast - Get number of physical broadcast IDs
309 int get_physical_broadcast(void)
311 return modern_apic() ? 0xff : 0xf;
316 * lapic_get_maxlvt - get the maximum number of local vector table entries
318 int lapic_get_maxlvt(void)
322 v
= apic_read(APIC_LVR
);
324 * - we always have APIC integrated on 64bit mode
325 * - 82489DXs do not report # of LVT entries
327 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
335 #define APIC_DIVISOR 16
338 * This function sets up the local APIC timer, with a timeout of
339 * 'clocks' APIC bus clock. During calibration we actually call
340 * this function twice on the boot CPU, once with a bogus timeout
341 * value, second time for real. The other (noncalibrating) CPUs
342 * call this function only once, with the real, calibrated value.
344 * We do reads before writes even if unnecessary, to get around the
345 * P5 APIC double write bug.
347 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
349 unsigned int lvtt_value
, tmp_value
;
351 lvtt_value
= LOCAL_TIMER_VECTOR
;
353 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
354 if (!lapic_is_integrated())
355 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
358 lvtt_value
|= APIC_LVT_MASKED
;
360 apic_write(APIC_LVTT
, lvtt_value
);
365 tmp_value
= apic_read(APIC_TDCR
);
366 apic_write(APIC_TDCR
,
367 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
371 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
375 * Setup extended LVT, AMD specific (K8, family 10h)
377 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
378 * MCE interrupts are supported. Thus MCE offset must be set to 0.
380 * If mask=1, the LVT entry does not generate interrupts while mask=0
381 * enables the vector. See also the BKDGs.
384 #define APIC_EILVT_LVTOFF_MCE 0
385 #define APIC_EILVT_LVTOFF_IBS 1
387 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
389 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
390 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
395 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
397 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
398 return APIC_EILVT_LVTOFF_MCE
;
401 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
403 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
404 return APIC_EILVT_LVTOFF_IBS
;
406 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
409 * Program the next event, relative to now
411 static int lapic_next_event(unsigned long delta
,
412 struct clock_event_device
*evt
)
414 apic_write(APIC_TMICT
, delta
);
419 * Setup the lapic timer in periodic or oneshot mode
421 static void lapic_timer_setup(enum clock_event_mode mode
,
422 struct clock_event_device
*evt
)
427 /* Lapic used as dummy for broadcast ? */
428 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
431 local_irq_save(flags
);
434 case CLOCK_EVT_MODE_PERIODIC
:
435 case CLOCK_EVT_MODE_ONESHOT
:
436 __setup_APIC_LVTT(calibration_result
,
437 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
439 case CLOCK_EVT_MODE_UNUSED
:
440 case CLOCK_EVT_MODE_SHUTDOWN
:
441 v
= apic_read(APIC_LVTT
);
442 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
443 apic_write(APIC_LVTT
, v
);
445 case CLOCK_EVT_MODE_RESUME
:
446 /* Nothing to do here */
450 local_irq_restore(flags
);
454 * Local APIC timer broadcast function
456 static void lapic_timer_broadcast(cpumask_t mask
)
459 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
464 * Setup the local APIC timer for this CPU. Copy the initilized values
465 * of the boot CPU and register the clock event in the framework.
467 static void __cpuinit
setup_APIC_timer(void)
469 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
471 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
472 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
474 clockevents_register_device(levt
);
478 * In this functions we calibrate APIC bus clocks to the external timer.
480 * We want to do the calibration only once since we want to have local timer
481 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
484 * This was previously done by reading the PIT/HPET and waiting for a wrap
485 * around to find out, that a tick has elapsed. I have a box, where the PIT
486 * readout is broken, so it never gets out of the wait loop again. This was
487 * also reported by others.
489 * Monitoring the jiffies value is inaccurate and the clockevents
490 * infrastructure allows us to do a simple substitution of the interrupt
493 * The calibration routine also uses the pm_timer when possible, as the PIT
494 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
495 * back to normal later in the boot process).
498 #define LAPIC_CAL_LOOPS (HZ/10)
500 static __initdata
int lapic_cal_loops
= -1;
501 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
502 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
503 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
504 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
507 * Temporary interrupt handler.
509 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
511 unsigned long long tsc
= 0;
512 long tapic
= apic_read(APIC_TMCCT
);
513 unsigned long pm
= acpi_pm_read_early();
518 switch (lapic_cal_loops
++) {
520 lapic_cal_t1
= tapic
;
521 lapic_cal_tsc1
= tsc
;
523 lapic_cal_j1
= jiffies
;
526 case LAPIC_CAL_LOOPS
:
527 lapic_cal_t2
= tapic
;
528 lapic_cal_tsc2
= tsc
;
529 if (pm
< lapic_cal_pm1
)
530 pm
+= ACPI_PM_OVRRUN
;
532 lapic_cal_j2
= jiffies
;
537 static int __init
calibrate_by_pmtimer(long deltapm
, long *delta
)
539 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
540 const long pm_thresh
= pm_100ms
/ 100;
544 #ifndef CONFIG_X86_PM_TIMER
548 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
550 /* Check, if the PM timer is available */
554 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
556 if (deltapm
> (pm_100ms
- pm_thresh
) &&
557 deltapm
< (pm_100ms
+ pm_thresh
)) {
558 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
560 res
= (((u64
)deltapm
) * mult
) >> 22;
561 do_div(res
, 1000000);
562 pr_warning("APIC calibration not consistent "
563 "with PM Timer: %ldms instead of 100ms\n",
565 /* Correct the lapic counter value */
566 res
= (((u64
)(*delta
)) * pm_100ms
);
567 do_div(res
, deltapm
);
568 pr_info("APIC delta adjusted to PM-Timer: "
569 "%lu (%ld)\n", (unsigned long)res
, *delta
);
576 static int __init
calibrate_APIC_clock(void)
578 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
579 void (*real_handler
)(struct clock_event_device
*dev
);
580 unsigned long deltaj
;
582 int pm_referenced
= 0;
586 /* Replace the global interrupt handler */
587 real_handler
= global_clock_event
->event_handler
;
588 global_clock_event
->event_handler
= lapic_cal_handler
;
591 * Setup the APIC counter to maximum. There is no way the lapic
592 * can underflow in the 100ms detection time frame
594 __setup_APIC_LVTT(0xffffffff, 0, 0);
596 /* Let the interrupts run */
599 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
604 /* Restore the real event handler */
605 global_clock_event
->event_handler
= real_handler
;
607 /* Build delta t1-t2 as apic timer counts down */
608 delta
= lapic_cal_t1
- lapic_cal_t2
;
609 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
611 /* we trust the PM based calibration if possible */
612 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
615 /* Calculate the scaled math multiplication factor */
616 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
617 lapic_clockevent
.shift
);
618 lapic_clockevent
.max_delta_ns
=
619 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
620 lapic_clockevent
.min_delta_ns
=
621 clockevent_delta2ns(0xF, &lapic_clockevent
);
623 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
625 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
626 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
627 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
631 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
632 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
634 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
635 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
638 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
640 calibration_result
/ (1000000 / HZ
),
641 calibration_result
% (1000000 / HZ
));
644 * Do a sanity check on the APIC calibration result
646 if (calibration_result
< (1000000 / HZ
)) {
648 pr_warning("APIC frequency too slow, disabling apic timer\n");
652 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
655 * PM timer calibration failed or not turned on
656 * so lets try APIC timer based calibration
658 if (!pm_referenced
) {
659 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
662 * Setup the apic timer manually
664 levt
->event_handler
= lapic_cal_handler
;
665 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
666 lapic_cal_loops
= -1;
668 /* Let the interrupts run */
671 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
674 /* Stop the lapic timer */
675 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
678 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
679 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
681 /* Check, if the jiffies result is consistent */
682 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
683 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
685 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
689 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
690 pr_warning("APIC timer disabled due to verification failure.\n");
698 * Setup the boot APIC
700 * Calibrate and verify the result.
702 void __init
setup_boot_APIC_clock(void)
705 * The local apic timer can be disabled via the kernel
706 * commandline or from the CPU detection code. Register the lapic
707 * timer as a dummy clock event source on SMP systems, so the
708 * broadcast mechanism is used. On UP systems simply ignore it.
710 if (disable_apic_timer
) {
711 pr_info("Disabling APIC timer\n");
712 /* No broadcast on UP ! */
713 if (num_possible_cpus() > 1) {
714 lapic_clockevent
.mult
= 1;
720 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
721 "calibrating APIC timer ...\n");
723 if (calibrate_APIC_clock()) {
724 /* No broadcast on UP ! */
725 if (num_possible_cpus() > 1)
731 * If nmi_watchdog is set to IO_APIC, we need the
732 * PIT/HPET going. Otherwise register lapic as a dummy
735 if (nmi_watchdog
!= NMI_IO_APIC
)
736 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
738 pr_warning("APIC timer registered as dummy,"
739 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
741 /* Setup the lapic or request the broadcast */
745 void __cpuinit
setup_secondary_APIC_clock(void)
751 * The guts of the apic timer interrupt
753 static void local_apic_timer_interrupt(void)
755 int cpu
= smp_processor_id();
756 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
759 * Normally we should not be here till LAPIC has been initialized but
760 * in some cases like kdump, its possible that there is a pending LAPIC
761 * timer interrupt from previous kernel's context and is delivered in
762 * new kernel the moment interrupts are enabled.
764 * Interrupts are enabled early and LAPIC is setup much later, hence
765 * its possible that when we get here evt->event_handler is NULL.
766 * Check for event_handler being NULL and discard the interrupt as
769 if (!evt
->event_handler
) {
770 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
772 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
777 * the NMI deadlock-detector uses this.
780 add_pda(apic_timer_irqs
, 1);
782 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
785 evt
->event_handler(evt
);
789 * Local APIC timer interrupt. This is the most natural way for doing
790 * local interrupts, but local timer interrupts can be emulated by
791 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
793 * [ if a single-CPU system runs an SMP kernel then we call the local
794 * interrupt as well. Thus we cannot inline the local irq ... ]
796 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
798 struct pt_regs
*old_regs
= set_irq_regs(regs
);
801 * NOTE! We'd better ACK the irq immediately,
802 * because timer handling can be slow.
806 * update_process_times() expects us to have done irq_enter().
807 * Besides, if we don't timer interrupts ignore the global
808 * interrupt lock, which is the WrongThing (tm) to do.
814 local_apic_timer_interrupt();
817 set_irq_regs(old_regs
);
820 int setup_profiling_timer(unsigned int multiplier
)
826 * Local APIC start and shutdown
830 * clear_local_APIC - shutdown the local APIC
832 * This is called, when a CPU is disabled and before rebooting, so the state of
833 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
834 * leftovers during boot.
836 void clear_local_APIC(void)
841 /* APIC hasn't been mapped yet */
845 maxlvt
= lapic_get_maxlvt();
847 * Masking an LVT entry can trigger a local APIC error
848 * if the vector is zero. Mask LVTERR first to prevent this.
851 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
852 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
855 * Careful: we have to set masks only first to deassert
856 * any level-triggered sources.
858 v
= apic_read(APIC_LVTT
);
859 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
860 v
= apic_read(APIC_LVT0
);
861 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
862 v
= apic_read(APIC_LVT1
);
863 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
865 v
= apic_read(APIC_LVTPC
);
866 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
869 /* lets not touch this if we didn't frob it */
870 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
872 v
= apic_read(APIC_LVTTHMR
);
873 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
877 * Clean APIC state for other OSs:
879 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
880 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
881 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
883 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
885 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
887 /* Integrated APIC (!82489DX) ? */
888 if (lapic_is_integrated()) {
890 /* Clear ESR due to Pentium errata 3AP and 11AP */
891 apic_write(APIC_ESR
, 0);
897 * disable_local_APIC - clear and disable the local APIC
899 void disable_local_APIC(void)
906 * Disable APIC (implies clearing of registers
909 value
= apic_read(APIC_SPIV
);
910 value
&= ~APIC_SPIV_APIC_ENABLED
;
911 apic_write(APIC_SPIV
, value
);
915 * When LAPIC was disabled by the BIOS and enabled by the kernel,
916 * restore the disabled state.
918 if (enabled_via_apicbase
) {
921 rdmsr(MSR_IA32_APICBASE
, l
, h
);
922 l
&= ~MSR_IA32_APICBASE_ENABLE
;
923 wrmsr(MSR_IA32_APICBASE
, l
, h
);
929 * If Linux enabled the LAPIC against the BIOS default disable it down before
930 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
931 * not power-off. Additionally clear all LVT entries before disable_local_APIC
932 * for the case where Linux didn't enable the LAPIC.
934 void lapic_shutdown(void)
941 local_irq_save(flags
);
944 if (!enabled_via_apicbase
)
948 disable_local_APIC();
951 local_irq_restore(flags
);
955 * This is to verify that we're looking at a real local APIC.
956 * Check these against your board if the CPUs aren't getting
957 * started for no apparent reason.
959 int __init
verify_local_APIC(void)
961 unsigned int reg0
, reg1
;
964 * The version register is read-only in a real APIC.
966 reg0
= apic_read(APIC_LVR
);
967 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
968 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
969 reg1
= apic_read(APIC_LVR
);
970 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
973 * The two version reads above should print the same
974 * numbers. If the second one is different, then we
975 * poke at a non-APIC.
981 * Check if the version looks reasonably.
983 reg1
= GET_APIC_VERSION(reg0
);
984 if (reg1
== 0x00 || reg1
== 0xff)
986 reg1
= lapic_get_maxlvt();
987 if (reg1
< 0x02 || reg1
== 0xff)
991 * The ID register is read/write in a real APIC.
993 reg0
= apic_read(APIC_ID
);
994 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
995 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
996 reg1
= apic_read(APIC_ID
);
997 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
998 apic_write(APIC_ID
, reg0
);
999 if (reg1
!= (reg0
^ APIC_ID_MASK
))
1003 * The next two are just to see if we have sane values.
1004 * They're only really relevant if we're in Virtual Wire
1005 * compatibility mode, but most boxes are anymore.
1007 reg0
= apic_read(APIC_LVT0
);
1008 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1009 reg1
= apic_read(APIC_LVT1
);
1010 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1016 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1018 void __init
sync_Arb_IDs(void)
1021 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1024 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1030 apic_wait_icr_idle();
1032 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1033 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1034 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1038 * An initial setup of the virtual wire mode.
1040 void __init
init_bsp_APIC(void)
1045 * Don't do the setup now if we have a SMP BIOS as the
1046 * through-I/O-APIC virtual wire mode might be active.
1048 if (smp_found_config
|| !cpu_has_apic
)
1052 * Do not trust the local APIC being empty at bootup.
1059 value
= apic_read(APIC_SPIV
);
1060 value
&= ~APIC_VECTOR_MASK
;
1061 value
|= APIC_SPIV_APIC_ENABLED
;
1063 #ifdef CONFIG_X86_32
1064 /* This bit is reserved on P4/Xeon and should be cleared */
1065 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1066 (boot_cpu_data
.x86
== 15))
1067 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1070 value
|= APIC_SPIV_FOCUS_DISABLED
;
1071 value
|= SPURIOUS_APIC_VECTOR
;
1072 apic_write(APIC_SPIV
, value
);
1075 * Set up the virtual wire mode.
1077 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1078 value
= APIC_DM_NMI
;
1079 if (!lapic_is_integrated()) /* 82489DX */
1080 value
|= APIC_LVT_LEVEL_TRIGGER
;
1081 apic_write(APIC_LVT1
, value
);
1084 static void __cpuinit
lapic_setup_esr(void)
1086 unsigned int oldvalue
, value
, maxlvt
;
1088 if (!lapic_is_integrated()) {
1089 pr_info("No ESR for 82489DX.\n");
1095 * Something untraceable is creating bad interrupts on
1096 * secondary quads ... for the moment, just leave the
1097 * ESR disabled - we can't do anything useful with the
1098 * errors anyway - mbligh
1100 pr_info("Leaving ESR disabled.\n");
1104 maxlvt
= lapic_get_maxlvt();
1105 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1106 apic_write(APIC_ESR
, 0);
1107 oldvalue
= apic_read(APIC_ESR
);
1109 /* enables sending errors */
1110 value
= ERROR_APIC_VECTOR
;
1111 apic_write(APIC_LVTERR
, value
);
1114 * spec says clear errors after enabling vector.
1117 apic_write(APIC_ESR
, 0);
1118 value
= apic_read(APIC_ESR
);
1119 if (value
!= oldvalue
)
1120 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1121 "vector: 0x%08x after: 0x%08x\n",
1127 * setup_local_APIC - setup the local APIC
1129 void __cpuinit
setup_local_APIC(void)
1134 #ifdef CONFIG_X86_32
1135 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1136 if (lapic_is_integrated() && esr_disable
) {
1137 apic_write(APIC_ESR
, 0);
1138 apic_write(APIC_ESR
, 0);
1139 apic_write(APIC_ESR
, 0);
1140 apic_write(APIC_ESR
, 0);
1147 * Double-check whether this APIC is really registered.
1148 * This is meaningless in clustered apic mode, so we skip it.
1150 if (!apic_id_registered())
1154 * Intel recommends to set DFR, LDR and TPR before enabling
1155 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1156 * document number 292116). So here it goes...
1161 * Set Task Priority to 'accept all'. We never change this
1164 value
= apic_read(APIC_TASKPRI
);
1165 value
&= ~APIC_TPRI_MASK
;
1166 apic_write(APIC_TASKPRI
, value
);
1169 * After a crash, we no longer service the interrupts and a pending
1170 * interrupt from previous kernel might still have ISR bit set.
1172 * Most probably by now CPU has serviced that pending interrupt and
1173 * it might not have done the ack_APIC_irq() because it thought,
1174 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1175 * does not clear the ISR bit and cpu thinks it has already serivced
1176 * the interrupt. Hence a vector might get locked. It was noticed
1177 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1179 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1180 value
= apic_read(APIC_ISR
+ i
*0x10);
1181 for (j
= 31; j
>= 0; j
--) {
1188 * Now that we are all set up, enable the APIC
1190 value
= apic_read(APIC_SPIV
);
1191 value
&= ~APIC_VECTOR_MASK
;
1195 value
|= APIC_SPIV_APIC_ENABLED
;
1197 #ifdef CONFIG_X86_32
1199 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1200 * certain networking cards. If high frequency interrupts are
1201 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1202 * entry is masked/unmasked at a high rate as well then sooner or
1203 * later IOAPIC line gets 'stuck', no more interrupts are received
1204 * from the device. If focus CPU is disabled then the hang goes
1207 * [ This bug can be reproduced easily with a level-triggered
1208 * PCI Ne2000 networking cards and PII/PIII processors, dual
1212 * Actually disabling the focus CPU check just makes the hang less
1213 * frequent as it makes the interrupt distributon model be more
1214 * like LRU than MRU (the short-term load is more even across CPUs).
1215 * See also the comment in end_level_ioapic_irq(). --macro
1219 * - enable focus processor (bit==0)
1220 * - 64bit mode always use processor focus
1221 * so no need to set it
1223 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1227 * Set spurious IRQ vector
1229 value
|= SPURIOUS_APIC_VECTOR
;
1230 apic_write(APIC_SPIV
, value
);
1233 * Set up LVT0, LVT1:
1235 * set up through-local-APIC on the BP's LINT0. This is not
1236 * strictly necessary in pure symmetric-IO mode, but sometimes
1237 * we delegate interrupts to the 8259A.
1240 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1242 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1243 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1244 value
= APIC_DM_EXTINT
;
1245 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1246 smp_processor_id());
1248 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1249 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1250 smp_processor_id());
1252 apic_write(APIC_LVT0
, value
);
1255 * only the BP should see the LINT1 NMI signal, obviously.
1257 if (!smp_processor_id())
1258 value
= APIC_DM_NMI
;
1260 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1261 if (!lapic_is_integrated()) /* 82489DX */
1262 value
|= APIC_LVT_LEVEL_TRIGGER
;
1263 apic_write(APIC_LVT1
, value
);
1268 void __cpuinit
end_local_APIC_setup(void)
1272 #ifdef CONFIG_X86_32
1275 /* Disable the local apic timer */
1276 value
= apic_read(APIC_LVTT
);
1277 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1278 apic_write(APIC_LVTT
, value
);
1282 setup_apic_nmi_watchdog(NULL
);
1287 void check_x2apic(void)
1291 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1293 if (msr
& X2APIC_ENABLE
) {
1294 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1295 x2apic_preenabled
= x2apic
= 1;
1296 apic_ops
= &x2apic_ops
;
1300 void enable_x2apic(void)
1304 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1305 if (!(msr
& X2APIC_ENABLE
)) {
1306 pr_info("Enabling x2apic\n");
1307 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1311 void enable_IR_x2apic(void)
1313 #ifdef CONFIG_INTR_REMAP
1315 unsigned long flags
;
1317 if (!cpu_has_x2apic
)
1320 if (!x2apic_preenabled
&& disable_x2apic
) {
1321 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1322 "because of nox2apic\n");
1326 if (x2apic_preenabled
&& disable_x2apic
)
1327 panic("Bios already enabled x2apic, can't enforce nox2apic");
1329 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1330 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1331 "because of skipping io-apic setup\n");
1335 ret
= dmar_table_init();
1337 pr_info("dmar_table_init() failed with %d:\n", ret
);
1339 if (x2apic_preenabled
)
1340 panic("x2apic enabled by bios. But IR enabling failed");
1342 pr_info("Not enabling x2apic,Intr-remapping\n");
1346 local_irq_save(flags
);
1349 ret
= save_mask_IO_APIC_setup();
1351 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1355 ret
= enable_intr_remapping(1);
1357 if (ret
&& x2apic_preenabled
) {
1358 local_irq_restore(flags
);
1359 panic("x2apic enabled by bios. But IR enabling failed");
1367 apic_ops
= &x2apic_ops
;
1374 * IR enabling failed
1376 restore_IO_APIC_setup();
1378 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1382 local_irq_restore(flags
);
1385 if (!x2apic_preenabled
)
1386 pr_info("Enabled x2apic and interrupt-remapping\n");
1388 pr_info("Enabled Interrupt-remapping\n");
1390 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1392 if (!cpu_has_x2apic
)
1395 if (x2apic_preenabled
)
1396 panic("x2apic enabled prior OS handover,"
1397 " enable CONFIG_INTR_REMAP");
1399 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1405 #endif /* HAVE_X2APIC */
1407 #ifdef CONFIG_X86_64
1409 * Detect and enable local APICs on non-SMP boards.
1410 * Original code written by Keir Fraser.
1411 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1412 * not correctly set up (usually the APIC timer won't work etc.)
1414 static int __init
detect_init_APIC(void)
1416 if (!cpu_has_apic
) {
1417 pr_info("No local APIC present\n");
1421 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1422 boot_cpu_physical_apicid
= 0;
1427 * Detect and initialize APIC
1429 static int __init
detect_init_APIC(void)
1433 /* Disabled by kernel option? */
1437 switch (boot_cpu_data
.x86_vendor
) {
1438 case X86_VENDOR_AMD
:
1439 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1440 (boot_cpu_data
.x86
== 15))
1443 case X86_VENDOR_INTEL
:
1444 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1445 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1452 if (!cpu_has_apic
) {
1454 * Over-ride BIOS and try to enable the local APIC only if
1455 * "lapic" specified.
1457 if (!force_enable_local_apic
) {
1458 pr_info("Local APIC disabled by BIOS -- "
1459 "you can enable it with \"lapic\"\n");
1463 * Some BIOSes disable the local APIC in the APIC_BASE
1464 * MSR. This can only be done in software for Intel P6 or later
1465 * and AMD K7 (Model > 1) or later.
1467 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1468 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1469 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1470 l
&= ~MSR_IA32_APICBASE_BASE
;
1471 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1472 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1473 enabled_via_apicbase
= 1;
1477 * The APIC feature bit should now be enabled
1480 features
= cpuid_edx(1);
1481 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1482 pr_warning("Could not enable APIC!\n");
1485 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1486 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1488 /* The BIOS may have set up the APIC at some other address */
1489 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1490 if (l
& MSR_IA32_APICBASE_ENABLE
)
1491 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1493 pr_info("Found and enabled local APIC!\n");
1500 pr_info("No local APIC present or hardware disabled\n");
1505 #ifdef CONFIG_X86_64
1506 void __init
early_init_lapic_mapping(void)
1508 unsigned long phys_addr
;
1511 * If no local APIC can be found then go out
1512 * : it means there is no mpatable and MADT
1514 if (!smp_found_config
)
1517 phys_addr
= mp_lapic_addr
;
1519 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1520 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1521 APIC_BASE
, phys_addr
);
1524 * Fetch the APIC ID of the BSP in case we have a
1525 * default configuration (or the MP table is broken).
1527 boot_cpu_physical_apicid
= read_apic_id();
1532 * init_apic_mappings - initialize APIC mappings
1534 void __init
init_apic_mappings(void)
1538 boot_cpu_physical_apicid
= read_apic_id();
1544 * If no local APIC can be found then set up a fake all
1545 * zeroes page to simulate the local APIC and another
1546 * one for the IO-APIC.
1548 if (!smp_found_config
&& detect_init_APIC()) {
1549 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1550 apic_phys
= __pa(apic_phys
);
1552 apic_phys
= mp_lapic_addr
;
1554 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1555 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1556 APIC_BASE
, apic_phys
);
1559 * Fetch the APIC ID of the BSP in case we have a
1560 * default configuration (or the MP table is broken).
1562 if (boot_cpu_physical_apicid
== -1U)
1563 boot_cpu_physical_apicid
= read_apic_id();
1567 * This initializes the IO-APIC and APIC hardware if this is
1570 int apic_version
[MAX_APICS
];
1572 int __init
APIC_init_uniprocessor(void)
1574 #ifdef CONFIG_X86_64
1576 pr_info("Apic disabled\n");
1579 if (!cpu_has_apic
) {
1581 pr_info("Apic disabled by BIOS\n");
1585 if (!smp_found_config
&& !cpu_has_apic
)
1589 * Complain if the BIOS pretends there is one.
1591 if (!cpu_has_apic
&&
1592 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1593 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1594 boot_cpu_physical_apicid
);
1595 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1603 #ifdef CONFIG_X86_64
1604 setup_apic_routing();
1607 verify_local_APIC();
1610 #ifdef CONFIG_X86_64
1611 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1614 * Hack: In case of kdump, after a crash, kernel might be booting
1615 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1616 * might be zero if read from MP tables. Get it from LAPIC.
1618 # ifdef CONFIG_CRASH_DUMP
1619 boot_cpu_physical_apicid
= read_apic_id();
1622 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1625 #ifdef CONFIG_X86_64
1627 * Now enable IO-APICs, actually call clear_IO_APIC
1628 * We need clear_IO_APIC before enabling vector on BP
1630 if (!skip_ioapic_setup
&& nr_ioapics
)
1634 #ifdef CONFIG_X86_IO_APIC
1635 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1637 localise_nmi_watchdog();
1638 end_local_APIC_setup();
1640 #ifdef CONFIG_X86_IO_APIC
1641 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1643 # ifdef CONFIG_X86_64
1649 #ifdef CONFIG_X86_64
1650 setup_boot_APIC_clock();
1651 check_nmi_watchdog();
1660 * Local APIC interrupts
1664 * This interrupt should _never_ happen with our APIC/SMP architecture
1666 void smp_spurious_interrupt(struct pt_regs
*regs
)
1670 #ifdef CONFIG_X86_64
1675 * Check if this really is a spurious interrupt and ACK it
1676 * if it is a vectored one. Just in case...
1677 * Spurious interrupts should not be ACKed.
1679 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1680 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1683 #ifdef CONFIG_X86_64
1684 add_pda(irq_spurious_count
, 1);
1686 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1687 pr_info("spurious APIC interrupt on CPU#%d, "
1688 "should never happen.\n", smp_processor_id());
1689 __get_cpu_var(irq_stat
).irq_spurious_count
++;
1695 * This interrupt should never happen with our APIC/SMP architecture
1697 void smp_error_interrupt(struct pt_regs
*regs
)
1701 #ifdef CONFIG_X86_64
1705 /* First tickle the hardware, only then report what went on. -- REW */
1706 v
= apic_read(APIC_ESR
);
1707 apic_write(APIC_ESR
, 0);
1708 v1
= apic_read(APIC_ESR
);
1710 atomic_inc(&irq_err_count
);
1713 * Here is what the APIC error bits mean:
1715 * 1: Receive CS error
1716 * 2: Send accept error
1717 * 3: Receive accept error
1719 * 5: Send illegal vector
1720 * 6: Received illegal vector
1721 * 7: Illegal register address
1723 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1724 smp_processor_id(), v
, v1
);
1729 * connect_bsp_APIC - attach the APIC to the interrupt system
1731 void __init
connect_bsp_APIC(void)
1733 #ifdef CONFIG_X86_32
1736 * Do not trust the local APIC being empty at bootup.
1740 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1741 * local APIC to INT and NMI lines.
1743 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1744 "enabling APIC mode.\n");
1753 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1754 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1756 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1759 void disconnect_bsp_APIC(int virt_wire_setup
)
1763 #ifdef CONFIG_X86_32
1766 * Put the board back into PIC mode (has an effect only on
1767 * certain older boards). Note that APIC interrupts, including
1768 * IPIs, won't work beyond this point! The only exception are
1771 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1772 "entering PIC mode.\n");
1779 /* Go back to Virtual Wire compatibility mode */
1781 /* For the spurious interrupt use vector F, and enable it */
1782 value
= apic_read(APIC_SPIV
);
1783 value
&= ~APIC_VECTOR_MASK
;
1784 value
|= APIC_SPIV_APIC_ENABLED
;
1786 apic_write(APIC_SPIV
, value
);
1788 if (!virt_wire_setup
) {
1790 * For LVT0 make it edge triggered, active high,
1791 * external and enabled
1793 value
= apic_read(APIC_LVT0
);
1794 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1795 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1796 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1797 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1798 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1799 apic_write(APIC_LVT0
, value
);
1802 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1806 * For LVT1 make it edge triggered, active high,
1809 value
= apic_read(APIC_LVT1
);
1810 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1811 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1812 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1813 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1814 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1815 apic_write(APIC_LVT1
, value
);
1818 void __cpuinit
generic_processor_info(int apicid
, int version
)
1826 if (version
== 0x0) {
1827 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1828 "fixing up to 0x10. (tell your hw vendor)\n",
1832 apic_version
[apicid
] = version
;
1834 if (num_processors
>= NR_CPUS
) {
1835 pr_warning("WARNING: NR_CPUS limit of %i reached."
1836 " Processor ignored.\n", NR_CPUS
);
1841 cpus_complement(tmp_map
, cpu_present_map
);
1842 cpu
= first_cpu(tmp_map
);
1844 physid_set(apicid
, phys_cpu_present_map
);
1845 if (apicid
== boot_cpu_physical_apicid
) {
1847 * x86_bios_cpu_apicid is required to have processors listed
1848 * in same order as logical cpu numbers. Hence the first
1849 * entry is BSP, and so on.
1853 if (apicid
> max_physical_apicid
)
1854 max_physical_apicid
= apicid
;
1856 #ifdef CONFIG_X86_32
1858 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1859 * but we need to work other dependencies like SMP_SUSPEND etc
1860 * before this can be done without some confusion.
1861 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1862 * - Ashok Raj <ashok.raj@intel.com>
1864 if (max_physical_apicid
>= 8) {
1865 switch (boot_cpu_data
.x86_vendor
) {
1866 case X86_VENDOR_INTEL
:
1867 if (!APIC_XAPIC(version
)) {
1871 /* If P4 and above fall through */
1872 case X86_VENDOR_AMD
:
1878 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1879 /* are we being called early in kernel startup? */
1880 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1881 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1882 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1884 cpu_to_apicid
[cpu
] = apicid
;
1885 bios_cpu_apicid
[cpu
] = apicid
;
1887 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1888 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1892 cpu_set(cpu
, cpu_possible_map
);
1893 cpu_set(cpu
, cpu_present_map
);
1896 #ifdef CONFIG_X86_64
1897 int hard_smp_processor_id(void)
1899 return read_apic_id();
1910 * 'active' is true if the local APIC was enabled by us and
1911 * not the BIOS; this signifies that we are also responsible
1912 * for disabling it before entering apm/acpi suspend
1915 /* r/w apic fields */
1916 unsigned int apic_id
;
1917 unsigned int apic_taskpri
;
1918 unsigned int apic_ldr
;
1919 unsigned int apic_dfr
;
1920 unsigned int apic_spiv
;
1921 unsigned int apic_lvtt
;
1922 unsigned int apic_lvtpc
;
1923 unsigned int apic_lvt0
;
1924 unsigned int apic_lvt1
;
1925 unsigned int apic_lvterr
;
1926 unsigned int apic_tmict
;
1927 unsigned int apic_tdcr
;
1928 unsigned int apic_thmr
;
1931 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1933 unsigned long flags
;
1936 if (!apic_pm_state
.active
)
1939 maxlvt
= lapic_get_maxlvt();
1941 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1942 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1943 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1944 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1945 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1946 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1948 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1949 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1950 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1951 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1952 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1953 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1954 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1956 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1959 local_irq_save(flags
);
1960 disable_local_APIC();
1961 local_irq_restore(flags
);
1965 static int lapic_resume(struct sys_device
*dev
)
1968 unsigned long flags
;
1971 if (!apic_pm_state
.active
)
1974 maxlvt
= lapic_get_maxlvt();
1976 local_irq_save(flags
);
1985 * Make sure the APICBASE points to the right address
1987 * FIXME! This will be wrong if we ever support suspend on
1988 * SMP! We'll need to do this as part of the CPU restore!
1990 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1991 l
&= ~MSR_IA32_APICBASE_BASE
;
1992 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1993 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1996 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1997 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1998 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1999 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2000 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2001 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2002 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2003 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2004 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2006 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2009 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2010 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2011 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2012 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2013 apic_write(APIC_ESR
, 0);
2014 apic_read(APIC_ESR
);
2015 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2016 apic_write(APIC_ESR
, 0);
2017 apic_read(APIC_ESR
);
2019 local_irq_restore(flags
);
2025 * This device has no shutdown method - fully functioning local APICs
2026 * are needed on every CPU up until machine_halt/restart/poweroff.
2029 static struct sysdev_class lapic_sysclass
= {
2031 .resume
= lapic_resume
,
2032 .suspend
= lapic_suspend
,
2035 static struct sys_device device_lapic
= {
2037 .cls
= &lapic_sysclass
,
2040 static void __cpuinit
apic_pm_activate(void)
2042 apic_pm_state
.active
= 1;
2045 static int __init
init_lapic_sysfs(void)
2051 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2053 error
= sysdev_class_register(&lapic_sysclass
);
2055 error
= sysdev_register(&device_lapic
);
2058 device_initcall(init_lapic_sysfs
);
2060 #else /* CONFIG_PM */
2062 static void apic_pm_activate(void) { }
2064 #endif /* CONFIG_PM */
2066 #ifdef CONFIG_X86_64
2068 * apic_is_clustered_box() -- Check if we can expect good TSC
2070 * Thus far, the major user of this is IBM's Summit2 series:
2072 * Clustered boxes may have unsynced TSC problems if they are
2073 * multi-chassis. Use available data to take a good guess.
2074 * If in doubt, go HPET.
2076 __cpuinit
int apic_is_clustered_box(void)
2078 int i
, clusters
, zeros
;
2080 u16
*bios_cpu_apicid
;
2081 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2084 * there is not this kind of box with AMD CPU yet.
2085 * Some AMD box with quadcore cpu and 8 sockets apicid
2086 * will be [4, 0x23] or [8, 0x27] could be thought to
2087 * vsmp box still need checking...
2089 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2092 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2093 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2095 for (i
= 0; i
< NR_CPUS
; i
++) {
2096 /* are we being called early in kernel startup? */
2097 if (bios_cpu_apicid
) {
2098 id
= bios_cpu_apicid
[i
];
2100 else if (i
< nr_cpu_ids
) {
2102 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2109 if (id
!= BAD_APICID
)
2110 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2113 /* Problem: Partially populated chassis may not have CPUs in some of
2114 * the APIC clusters they have been allocated. Only present CPUs have
2115 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2116 * Since clusters are allocated sequentially, count zeros only if
2117 * they are bounded by ones.
2121 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2122 if (test_bit(i
, clustermap
)) {
2123 clusters
+= 1 + zeros
;
2129 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2130 * not guaranteed to be synced between boards
2132 if (is_vsmp_box() && clusters
> 1)
2136 * If clusters > 2, then should be multi-chassis.
2137 * May have to revisit this when multi-core + hyperthreaded CPUs come
2138 * out, but AFAIK this will work even for them.
2140 return (clusters
> 2);
2145 * APIC command line parameters
2147 static int __init
setup_disableapic(char *arg
)
2150 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2153 early_param("disableapic", setup_disableapic
);
2155 /* same as disableapic, for compatibility */
2156 static int __init
setup_nolapic(char *arg
)
2158 return setup_disableapic(arg
);
2160 early_param("nolapic", setup_nolapic
);
2162 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2164 local_apic_timer_c2_ok
= 1;
2167 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2169 static int __init
parse_disable_apic_timer(char *arg
)
2171 disable_apic_timer
= 1;
2174 early_param("noapictimer", parse_disable_apic_timer
);
2176 static int __init
parse_nolapic_timer(char *arg
)
2178 disable_apic_timer
= 1;
2181 early_param("nolapic_timer", parse_nolapic_timer
);
2183 static int __init
apic_set_verbosity(char *arg
)
2186 #ifdef CONFIG_X86_64
2187 skip_ioapic_setup
= 0;
2193 if (strcmp("debug", arg
) == 0)
2194 apic_verbosity
= APIC_DEBUG
;
2195 else if (strcmp("verbose", arg
) == 0)
2196 apic_verbosity
= APIC_VERBOSE
;
2198 pr_warning("APIC Verbosity level %s not recognised"
2199 " use apic=verbose or apic=debug\n", arg
);
2205 early_param("apic", apic_set_verbosity
);
2207 static int __init
lapic_insert_resource(void)
2212 /* Put local APIC into the resource map. */
2213 lapic_resource
.start
= apic_phys
;
2214 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2215 insert_resource(&iomem_resource
, &lapic_resource
);
2221 * need call insert after e820_reserve_resources()
2222 * that is using request_resource
2224 late_initcall(lapic_insert_resource
);