arch/x86/oprofile/nmi_int.c

   1 /**
   2  * @file nmi_int.c
   3  *
   4  * @remark Copyright 2002-2008 OProfile authors
   5  * @remark Read the file COPYING
   6  *
   7  * @author John Levon <levon@movementarian.org>
   8  * @author Robert Richter <robert.richter@amd.com>
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/notifier.h>
  13 #include <linux/smp.h>
  14 #include <linux/oprofile.h>
  15 #include <linux/sysdev.h>
  16 #include <linux/slab.h>
  17 #include <linux/moduleparam.h>
  18 #include <linux/kdebug.h>
  19 #include <linux/cpu.h>
  20 #include <asm/nmi.h>
  21 #include <asm/msr.h>
  22 #include <asm/apic.h>
  23
  24 #include "op_counter.h"
  25 #include "op_x86_model.h"
  26
  27 static struct op_x86_model_spec const *model;
  28 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
  29 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
  30
  31 static int nmi_start(void);
  32 static void nmi_stop(void);
  33 static void nmi_cpu_start(void *dummy);
  34 static void nmi_cpu_stop(void *dummy);
  35
  36 /* 0 == registered but off, 1 == registered and on */
  37 static int nmi_enabled = 0;
  38
  39 #ifdef CONFIG_SMP
  40 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
  41                                  void *data)
  42 {
  43         int cpu = (unsigned long)data;
  44         switch (action) {
  45         case CPU_DOWN_FAILED:
  46         case CPU_ONLINE:
  47                 smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
  48                 break;
  49         case CPU_DOWN_PREPARE:
  50                 smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
  51                 break;
  52         }
  53         return NOTIFY_DONE;
  54 }
  55
  56 static struct notifier_block oprofile_cpu_nb = {
  57         .notifier_call = oprofile_cpu_notifier
  58 };
  59 #endif
  60
  61 #ifdef CONFIG_PM
  62
  63 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
  64 {
  65         /* Only one CPU left, just stop that one */
  66         if (nmi_enabled == 1)
  67                 nmi_cpu_stop(NULL);
  68         return 0;
  69 }
  70
  71 static int nmi_resume(struct sys_device *dev)
  72 {
  73         if (nmi_enabled == 1)
  74                 nmi_cpu_start(NULL);
  75         return 0;
  76 }
  77
  78 static struct sysdev_class oprofile_sysclass = {
  79         .name           = "oprofile",
  80         .resume         = nmi_resume,
  81         .suspend        = nmi_suspend,
  82 };
  83
  84 static struct sys_device device_oprofile = {
  85         .id     = 0,
  86         .cls    = &oprofile_sysclass,
  87 };
  88
  89 static int __init init_sysfs(void)
  90 {
  91         int error;
  92
  93         error = sysdev_class_register(&oprofile_sysclass);
  94         if (!error)
  95                 error = sysdev_register(&device_oprofile);
  96         return error;
  97 }
  98
  99 static void exit_sysfs(void)
 100 {
 101         sysdev_unregister(&device_oprofile);
 102         sysdev_class_unregister(&oprofile_sysclass);
 103 }
 104
 105 #else
 106 #define init_sysfs() do { } while (0)
 107 #define exit_sysfs() do { } while (0)
 108 #endif /* CONFIG_PM */
 109
 110 static int profile_exceptions_notify(struct notifier_block *self,
 111                                      unsigned long val, void *data)
 112 {
 113         struct die_args *args = (struct die_args *)data;
 114         int ret = NOTIFY_DONE;
 115         int cpu = smp_processor_id();
 116
 117         switch (val) {
 118         case DIE_NMI:
 119                 if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))
 120                         ret = NOTIFY_STOP;
 121                 break;
 122         default:
 123                 break;
 124         }
 125         return ret;
 126 }
 127
 128 static void nmi_cpu_save_registers(struct op_msrs *msrs)
 129 {
 130         unsigned int const nr_ctrs = model->num_counters;
 131         unsigned int const nr_ctrls = model->num_controls;
 132         struct op_msr *counters = msrs->counters;
 133         struct op_msr *controls = msrs->controls;
 134         unsigned int i;
 135
 136         for (i = 0; i < nr_ctrs; ++i) {
 137                 if (counters[i].addr) {
 138                         rdmsr(counters[i].addr,
 139                                 counters[i].saved.low,
 140                                 counters[i].saved.high);
 141                 }
 142         }
 143
 144         for (i = 0; i < nr_ctrls; ++i) {
 145                 if (controls[i].addr) {
 146                         rdmsr(controls[i].addr,
 147                                 controls[i].saved.low,
 148                                 controls[i].saved.high);
 149                 }
 150         }
 151 }
 152
 153 static void nmi_save_registers(void *dummy)
 154 {
 155         int cpu = smp_processor_id();
 156         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 157         nmi_cpu_save_registers(msrs);
 158 }
 159
 160 static void free_msrs(void)
 161 {
 162         int i;
 163         for_each_possible_cpu(i) {
 164                 kfree(per_cpu(cpu_msrs, i).counters);
 165                 per_cpu(cpu_msrs, i).counters = NULL;
 166                 kfree(per_cpu(cpu_msrs, i).controls);
 167                 per_cpu(cpu_msrs, i).controls = NULL;
 168         }
 169 }
 170
 171 static int allocate_msrs(void)
 172 {
 173         int success = 1;
 174         size_t controls_size = sizeof(struct op_msr) * model->num_controls;
 175         size_t counters_size = sizeof(struct op_msr) * model->num_counters;
 176
 177         int i;
 178         for_each_possible_cpu(i) {
 179                 per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
 180                                                                 GFP_KERNEL);
 181                 if (!per_cpu(cpu_msrs, i).counters) {
 182                         success = 0;
 183                         break;
 184                 }
 185                 per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
 186                                                                 GFP_KERNEL);
 187                 if (!per_cpu(cpu_msrs, i).controls) {
 188                         success = 0;
 189                         break;
 190                 }
 191         }
 192
 193         if (!success)
 194                 free_msrs();
 195
 196         return success;
 197 }
 198
 199 static void nmi_cpu_setup(void *dummy)
 200 {
 201         int cpu = smp_processor_id();
 202         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 203         spin_lock(&oprofilefs_lock);
 204         model->setup_ctrs(msrs);
 205         spin_unlock(&oprofilefs_lock);
 206         per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
 207         apic_write(APIC_LVTPC, APIC_DM_NMI);
 208 }
 209
 210 static struct notifier_block profile_exceptions_nb = {
 211         .notifier_call = profile_exceptions_notify,
 212         .next = NULL,
 213         .priority = 0
 214 };
 215
 216 static int nmi_setup(void)
 217 {
 218         int err = 0;
 219         int cpu;
 220
 221         if (!allocate_msrs())
 222                 return -ENOMEM;
 223
 224         err = register_die_notifier(&profile_exceptions_nb);
 225         if (err) {
 226                 free_msrs();
 227                 return err;
 228         }
 229
 230         /* We need to serialize save and setup for HT because the subset
 231          * of msrs are distinct for save and setup operations
 232          */
 233
 234         /* Assume saved/restored counters are the same on all CPUs */
 235         model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
 236         for_each_possible_cpu(cpu) {
 237                 if (cpu != 0) {
 238                         memcpy(per_cpu(cpu_msrs, cpu).counters,
 239                                 per_cpu(cpu_msrs, 0).counters,
 240                                 sizeof(struct op_msr) * model->num_counters);
 241
 242                         memcpy(per_cpu(cpu_msrs, cpu).controls,
 243                                 per_cpu(cpu_msrs, 0).controls,
 244                                 sizeof(struct op_msr) * model->num_controls);
 245                 }
 246
 247         }
 248         on_each_cpu(nmi_save_registers, NULL, 1);
 249         on_each_cpu(nmi_cpu_setup, NULL, 1);
 250         nmi_enabled = 1;
 251         return 0;
 252 }
 253
 254 static void nmi_restore_registers(struct op_msrs *msrs)
 255 {
 256         unsigned int const nr_ctrs = model->num_counters;
 257         unsigned int const nr_ctrls = model->num_controls;
 258         struct op_msr *counters = msrs->counters;
 259         struct op_msr *controls = msrs->controls;
 260         unsigned int i;
 261
 262         for (i = 0; i < nr_ctrls; ++i) {
 263                 if (controls[i].addr) {
 264                         wrmsr(controls[i].addr,
 265                                 controls[i].saved.low,
 266                                 controls[i].saved.high);
 267                 }
 268         }
 269
 270         for (i = 0; i < nr_ctrs; ++i) {
 271                 if (counters[i].addr) {
 272                         wrmsr(counters[i].addr,
 273                                 counters[i].saved.low,
 274                                 counters[i].saved.high);
 275                 }
 276         }
 277 }
 278
 279 static void nmi_cpu_shutdown(void *dummy)
 280 {
 281         unsigned int v;
 282         int cpu = smp_processor_id();
 283         struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
 284
 285         /* restoring APIC_LVTPC can trigger an apic error because the delivery
 286          * mode and vector nr combination can be illegal. That's by design: on
 287          * power on apic lvt contain a zero vector nr which are legal only for
 288          * NMI delivery mode. So inhibit apic err before restoring lvtpc
 289          */
 290         v = apic_read(APIC_LVTERR);
 291         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
 292         apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
 293         apic_write(APIC_LVTERR, v);
 294         nmi_restore_registers(msrs);
 295 }
 296
 297 static void nmi_shutdown(void)
 298 {
 299         struct op_msrs *msrs;
 300
 301         nmi_enabled = 0;
 302         on_each_cpu(nmi_cpu_shutdown, NULL, 1);
 303         unregister_die_notifier(&profile_exceptions_nb);
 304         msrs = &get_cpu_var(cpu_msrs);
 305         model->shutdown(msrs);
 306         free_msrs();
 307         put_cpu_var(cpu_msrs);
 308 }
 309
 310 static void nmi_cpu_start(void *dummy)
 311 {
 312         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 313         model->start(msrs);
 314 }
 315
 316 static int nmi_start(void)
 317 {
 318         on_each_cpu(nmi_cpu_start, NULL, 1);
 319         return 0;
 320 }
 321
 322 static void nmi_cpu_stop(void *dummy)
 323 {
 324         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 325         model->stop(msrs);
 326 }
 327
 328 static void nmi_stop(void)
 329 {
 330         on_each_cpu(nmi_cpu_stop, NULL, 1);
 331 }
 332
 333 struct op_counter_config counter_config[OP_MAX_COUNTER];
 334
 335 static int nmi_create_files(struct super_block *sb, struct dentry *root)
 336 {
 337         unsigned int i;
 338
 339         for (i = 0; i < model->num_counters; ++i) {
 340                 struct dentry *dir;
 341                 char buf[4];
 342
 343                 /* quick little hack to _not_ expose a counter if it is not
 344                  * available for use.  This should protect userspace app.
 345                  * NOTE:  assumes 1:1 mapping here (that counters are organized
 346                  *        sequentially in their struct assignment).
 347                  */
 348                 if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
 349                         continue;
 350
 351                 snprintf(buf,  sizeof(buf), "%d", i);
 352                 dir = oprofilefs_mkdir(sb, root, buf);
 353                 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
 354                 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
 355                 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
 356                 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
 357                 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
 358                 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
 359         }
 360
 361         return 0;
 362 }
 363
 364 static int p4force;
 365 module_param(p4force, int, 0);
 366
 367 static int __init p4_init(char **cpu_type)
 368 {
 369         __u8 cpu_model = boot_cpu_data.x86_model;
 370
 371         if (!p4force && (cpu_model > 6 || cpu_model == 5))
 372                 return 0;
 373
 374 #ifndef CONFIG_SMP
 375         *cpu_type = "i386/p4";
 376         model = &op_p4_spec;
 377         return 1;
 378 #else
 379         switch (smp_num_siblings) {
 380         case 1:
 381                 *cpu_type = "i386/p4";
 382                 model = &op_p4_spec;
 383                 return 1;
 384
 385         case 2:
 386                 *cpu_type = "i386/p4-ht";
 387                 model = &op_p4_ht2_spec;
 388                 return 1;
 389         }
 390 #endif
 391
 392         printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
 393         printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
 394         return 0;
 395 }
 396
 397 static int __init ppro_init(char **cpu_type)
 398 {
 399         __u8 cpu_model = boot_cpu_data.x86_model;
 400
 401         switch (cpu_model) {
 402         case 0 ... 2:
 403                 *cpu_type = "i386/ppro";
 404                 break;
 405         case 3 ... 5:
 406                 *cpu_type = "i386/pii";
 407                 break;
 408         case 6 ... 8:
 409                 *cpu_type = "i386/piii";
 410                 break;
 411         case 9:
 412                 *cpu_type = "i386/p6_mobile";
 413                 break;
 414         case 10 ... 13:
 415                 *cpu_type = "i386/p6";
 416                 break;
 417         case 14:
 418                 *cpu_type = "i386/core";
 419                 break;
 420         case 15: case 23:
 421                 *cpu_type = "i386/core_2";
 422                 break;
 423         default:
 424                 /* Unknown */
 425                 return 0;
 426         }
 427
 428         model = &op_ppro_spec;
 429         return 1;
 430 }
 431
 432 static int __init arch_perfmon_init(char **cpu_type)
 433 {
 434         if (!cpu_has_arch_perfmon)
 435                 return 0;
 436         *cpu_type = "i386/arch_perfmon";
 437         model = &op_arch_perfmon_spec;
 438         arch_perfmon_setup_counters();
 439         return 1;
 440 }
 441
 442 /* in order to get sysfs right */
 443 static int using_nmi;
 444
 445 int __init op_nmi_init(struct oprofile_operations *ops)
 446 {
 447         __u8 vendor = boot_cpu_data.x86_vendor;
 448         __u8 family = boot_cpu_data.x86;
 449         char *cpu_type = NULL;
 450         int ret = 0;
 451
 452         if (!cpu_has_apic)
 453                 return -ENODEV;
 454
 455         switch (vendor) {
 456         case X86_VENDOR_AMD:
 457                 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
 458
 459                 switch (family) {
 460                 default:
 461                         return -ENODEV;
 462                 case 6:
 463                         model = &op_amd_spec;
 464                         cpu_type = "i386/athlon";
 465                         break;
 466                 case 0xf:
 467                         model = &op_amd_spec;
 468                         /* Actually it could be i386/hammer too, but give
 469                          user space an consistent name. */
 470                         cpu_type = "x86-64/hammer";
 471                         break;
 472                 case 0x10:
 473                         model = &op_amd_spec;
 474                         cpu_type = "x86-64/family10";
 475                         break;
 476                 case 0x11:
 477                         model = &op_amd_spec;
 478                         cpu_type = "x86-64/family11h";
 479                         break;
 480                 }
 481                 break;
 482
 483         case X86_VENDOR_INTEL:
 484                 switch (family) {
 485                         /* Pentium IV */
 486                 case 0xf:
 487                         p4_init(&cpu_type);
 488                         break;
 489
 490                         /* A P6-class processor */
 491                 case 6:
 492                         ppro_init(&cpu_type);
 493                         break;
 494
 495                 default:
 496                         break;
 497                 }
 498
 499                 if (!cpu_type && !arch_perfmon_init(&cpu_type))
 500                         return -ENODEV;
 501                 break;
 502
 503         default:
 504                 return -ENODEV;
 505         }
 506
 507 #ifdef CONFIG_SMP
 508         register_cpu_notifier(&oprofile_cpu_nb);
 509 #endif
 510         /* default values, can be overwritten by model */
 511         ops->create_files = nmi_create_files;
 512         ops->setup = nmi_setup;
 513         ops->shutdown = nmi_shutdown;
 514         ops->start = nmi_start;
 515         ops->stop = nmi_stop;
 516         ops->cpu_type = cpu_type;
 517
 518         if (model->init)
 519                 ret = model->init(ops);
 520         if (ret)
 521                 return ret;
 522
 523         init_sysfs();
 524         using_nmi = 1;
 525         printk(KERN_INFO "oprofile: using NMI interrupt.\n");
 526         return 0;
 527 }
 528
 529 void op_nmi_exit(void)
 530 {
 531         if (using_nmi) {
 532                 exit_sysfs();
 533 #ifdef CONFIG_SMP
 534                 unregister_cpu_notifier(&oprofile_cpu_nb);
 535 #endif
 536         }
 537         if (model->exit)
 538                 model->exit();
 539 }