drivers/usb/otg/msm72k_otg.c

   1 /* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15  * 02110-1301, USA.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/clk.h>
  23 #include <linux/slab.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/err.h>
  26 #include <linux/delay.h>
  27 #include <linux/io.h>
  28 #include <linux/ioport.h>
  29 #include <linux/uaccess.h>
  30 #include <linux/debugfs.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/pm_runtime.h>
  33
  34 #include <linux/usb.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/usb/ulpi.h>
  37 #include <linux/usb/gadget.h>
  38 #include <linux/usb/hcd.h>
  39 #include <linux/usb/msm_hsusb.h>
  40 #include <linux/usb/msm_hsusb_hw.h>
  41
  42 #include <mach/clk.h>
  43
  44 #define MSM_USB_BASE    (motg->regs)
  45 #define DRIVER_NAME     "msm_otg"
  46
  47 #define ULPI_IO_TIMEOUT_USEC    (10 * 1000)
  48 static int ulpi_read(struct otg_transceiver *otg, u32 reg)
  49 {
  50         struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
  51         int cnt = 0;
  52
  53         /* initiate read operation */
  54         writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
  55                USB_ULPI_VIEWPORT);
  56
  57         /* wait for completion */
  58         while (cnt < ULPI_IO_TIMEOUT_USEC) {
  59                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
  60                         break;
  61                 udelay(1);
  62                 cnt++;
  63         }
  64
  65         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
  66                 dev_err(otg->dev, "ulpi_read: timeout %08x\n",
  67                         readl(USB_ULPI_VIEWPORT));
  68                 return -ETIMEDOUT;
  69         }
  70         return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
  71 }
  72
  73 static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
  74 {
  75         struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
  76         int cnt = 0;
  77
  78         /* initiate write operation */
  79         writel(ULPI_RUN | ULPI_WRITE |
  80                ULPI_ADDR(reg) | ULPI_DATA(val),
  81                USB_ULPI_VIEWPORT);
  82
  83         /* wait for completion */
  84         while (cnt < ULPI_IO_TIMEOUT_USEC) {
  85                 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
  86                         break;
  87                 udelay(1);
  88                 cnt++;
  89         }
  90
  91         if (cnt >= ULPI_IO_TIMEOUT_USEC) {
  92                 dev_err(otg->dev, "ulpi_write: timeout\n");
  93                 return -ETIMEDOUT;
  94         }
  95         return 0;
  96 }
  97
  98 static struct otg_io_access_ops msm_otg_io_ops = {
  99         .read = ulpi_read,
 100         .write = ulpi_write,
 101 };
 102
 103 static void ulpi_init(struct msm_otg *motg)
 104 {
 105         struct msm_otg_platform_data *pdata = motg->pdata;
 106         int *seq = pdata->phy_init_seq;
 107
 108         if (!seq)
 109                 return;
 110
 111         while (seq[0] >= 0) {
 112                 dev_vdbg(motg->otg.dev, "ulpi: write 0x%02x to 0x%02x\n",
 113                                 seq[0], seq[1]);
 114                 ulpi_write(&motg->otg, seq[0], seq[1]);
 115                 seq += 2;
 116         }
 117 }
 118
 119 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
 120 {
 121         int ret;
 122
 123         if (assert) {
 124                 ret = clk_reset(motg->clk, CLK_RESET_ASSERT);
 125                 if (ret)
 126                         dev_err(motg->otg.dev, "usb hs_clk assert failed\n");
 127         } else {
 128                 ret = clk_reset(motg->clk, CLK_RESET_DEASSERT);
 129                 if (ret)
 130                         dev_err(motg->otg.dev, "usb hs_clk deassert failed\n");
 131         }
 132         return ret;
 133 }
 134
 135 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
 136 {
 137         int ret;
 138
 139         ret = clk_reset(motg->phy_reset_clk, CLK_RESET_ASSERT);
 140         if (ret) {
 141                 dev_err(motg->otg.dev, "usb phy clk assert failed\n");
 142                 return ret;
 143         }
 144         usleep_range(10000, 12000);
 145         ret = clk_reset(motg->phy_reset_clk, CLK_RESET_DEASSERT);
 146         if (ret)
 147                 dev_err(motg->otg.dev, "usb phy clk deassert failed\n");
 148         return ret;
 149 }
 150
 151 static int msm_otg_phy_reset(struct msm_otg *motg)
 152 {
 153         u32 val;
 154         int ret;
 155         int retries;
 156
 157         ret = msm_otg_link_clk_reset(motg, 1);
 158         if (ret)
 159                 return ret;
 160         ret = msm_otg_phy_clk_reset(motg);
 161         if (ret)
 162                 return ret;
 163         ret = msm_otg_link_clk_reset(motg, 0);
 164         if (ret)
 165                 return ret;
 166
 167         val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
 168         writel(val | PORTSC_PTS_ULPI, USB_PORTSC);
 169
 170         for (retries = 3; retries > 0; retries--) {
 171                 ret = ulpi_write(&motg->otg, ULPI_FUNC_CTRL_SUSPENDM,
 172                                 ULPI_CLR(ULPI_FUNC_CTRL));
 173                 if (!ret)
 174                         break;
 175                 ret = msm_otg_phy_clk_reset(motg);
 176                 if (ret)
 177                         return ret;
 178         }
 179         if (!retries)
 180                 return -ETIMEDOUT;
 181
 182         /* This reset calibrates the phy, if the above write succeeded */
 183         ret = msm_otg_phy_clk_reset(motg);
 184         if (ret)
 185                 return ret;
 186
 187         for (retries = 3; retries > 0; retries--) {
 188                 ret = ulpi_read(&motg->otg, ULPI_DEBUG);
 189                 if (ret != -ETIMEDOUT)
 190                         break;
 191                 ret = msm_otg_phy_clk_reset(motg);
 192                 if (ret)
 193                         return ret;
 194         }
 195         if (!retries)
 196                 return -ETIMEDOUT;
 197
 198         dev_info(motg->otg.dev, "phy_reset: success\n");
 199         return 0;
 200 }
 201
 202 #define LINK_RESET_TIMEOUT_USEC         (250 * 1000)
 203 static int msm_otg_reset(struct otg_transceiver *otg)
 204 {
 205         struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
 206         struct msm_otg_platform_data *pdata = motg->pdata;
 207         int cnt = 0;
 208         int ret;
 209         u32 val = 0;
 210         u32 ulpi_val = 0;
 211
 212         ret = msm_otg_phy_reset(motg);
 213         if (ret) {
 214                 dev_err(otg->dev, "phy_reset failed\n");
 215                 return ret;
 216         }
 217
 218         ulpi_init(motg);
 219
 220         writel(USBCMD_RESET, USB_USBCMD);
 221         while (cnt < LINK_RESET_TIMEOUT_USEC) {
 222                 if (!(readl(USB_USBCMD) & USBCMD_RESET))
 223                         break;
 224                 udelay(1);
 225                 cnt++;
 226         }
 227         if (cnt >= LINK_RESET_TIMEOUT_USEC)
 228                 return -ETIMEDOUT;
 229
 230         /* select ULPI phy */
 231         writel(0x80000000, USB_PORTSC);
 232
 233         msleep(100);
 234
 235         writel(0x0, USB_AHBBURST);
 236         writel(0x00, USB_AHBMODE);
 237
 238         if (pdata->otg_control == OTG_PHY_CONTROL) {
 239                 val = readl(USB_OTGSC);
 240                 if (pdata->mode == USB_OTG) {
 241                         ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
 242                         val |= OTGSC_IDIE | OTGSC_BSVIE;
 243                 } else if (pdata->mode == USB_PERIPHERAL) {
 244                         ulpi_val = ULPI_INT_SESS_VALID;
 245                         val |= OTGSC_BSVIE;
 246                 }
 247                 writel(val, USB_OTGSC);
 248                 ulpi_write(otg, ulpi_val, ULPI_USB_INT_EN_RISE);
 249                 ulpi_write(otg, ulpi_val, ULPI_USB_INT_EN_FALL);
 250         }
 251
 252         return 0;
 253 }
 254
 255 #define PHY_SUSPEND_TIMEOUT_USEC        (500 * 1000)
 256 static int msm_otg_suspend(struct msm_otg *motg)
 257 {
 258         struct otg_transceiver *otg = &motg->otg;
 259         struct usb_bus *bus = otg->host;
 260         struct msm_otg_platform_data *pdata = motg->pdata;
 261         int cnt = 0;
 262
 263         if (atomic_read(&motg->in_lpm))
 264                 return 0;
 265
 266         disable_irq(motg->irq);
 267         /*
 268          * Interrupt Latch Register auto-clear feature is not present
 269          * in all PHY versions. Latch register is clear on read type.
 270          * Clear latch register to avoid spurious wakeup from
 271          * low power mode (LPM).
 272          */
 273         ulpi_read(otg, 0x14);
 274
 275         /*
 276          * PHY comparators are disabled when PHY enters into low power
 277          * mode (LPM). Keep PHY comparators ON in LPM only when we expect
 278          * VBUS/Id notifications from USB PHY. Otherwise turn off USB
 279          * PHY comparators. This save significant amount of power.
 280          */
 281         if (pdata->otg_control == OTG_PHY_CONTROL)
 282                 ulpi_write(otg, 0x01, 0x30);
 283
 284         /*
 285          * PLL is not turned off when PHY enters into low power mode (LPM).
 286          * Disable PLL for maximum power savings.
 287          */
 288         ulpi_write(otg, 0x08, 0x09);
 289
 290         /*
 291          * PHY may take some time or even fail to enter into low power
 292          * mode (LPM). Hence poll for 500 msec and reset the PHY and link
 293          * in failure case.
 294          */
 295         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
 296         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
 297                 if (readl(USB_PORTSC) & PORTSC_PHCD)
 298                         break;
 299                 udelay(1);
 300                 cnt++;
 301         }
 302
 303         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
 304                 dev_err(otg->dev, "Unable to suspend PHY\n");
 305                 msm_otg_reset(otg);
 306                 enable_irq(motg->irq);
 307                 return -ETIMEDOUT;
 308         }
 309
 310         /*
 311          * PHY has capability to generate interrupt asynchronously in low
 312          * power mode (LPM). This interrupt is level triggered. So USB IRQ
 313          * line must be disabled till async interrupt enable bit is cleared
 314          * in USBCMD register. Assert STP (ULPI interface STOP signal) to
 315          * block data communication from PHY.
 316          */
 317         writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
 318
 319         clk_disable(motg->pclk);
 320         clk_disable(motg->clk);
 321         if (motg->core_clk)
 322                 clk_disable(motg->core_clk);
 323
 324         if (device_may_wakeup(otg->dev))
 325                 enable_irq_wake(motg->irq);
 326         if (bus)
 327                 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
 328
 329         atomic_set(&motg->in_lpm, 1);
 330         enable_irq(motg->irq);
 331
 332         dev_info(otg->dev, "USB in low power mode\n");
 333
 334         return 0;
 335 }
 336
 337 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
 338 static int msm_otg_resume(struct msm_otg *motg)
 339 {
 340         struct otg_transceiver *otg = &motg->otg;
 341         struct usb_bus *bus = otg->host;
 342         int cnt = 0;
 343         unsigned temp;
 344
 345         if (!atomic_read(&motg->in_lpm))
 346                 return 0;
 347
 348         clk_enable(motg->pclk);
 349         clk_enable(motg->clk);
 350         if (motg->core_clk)
 351                 clk_enable(motg->core_clk);
 352
 353         temp = readl(USB_USBCMD);
 354         temp &= ~ASYNC_INTR_CTRL;
 355         temp &= ~ULPI_STP_CTRL;
 356         writel(temp, USB_USBCMD);
 357
 358         /*
 359          * PHY comes out of low power mode (LPM) in case of wakeup
 360          * from asynchronous interrupt.
 361          */
 362         if (!(readl(USB_PORTSC) & PORTSC_PHCD))
 363                 goto skip_phy_resume;
 364
 365         writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
 366         while (cnt < PHY_RESUME_TIMEOUT_USEC) {
 367                 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
 368                         break;
 369                 udelay(1);
 370                 cnt++;
 371         }
 372
 373         if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
 374                 /*
 375                  * This is a fatal error. Reset the link and
 376                  * PHY. USB state can not be restored. Re-insertion
 377                  * of USB cable is the only way to get USB working.
 378                  */
 379                 dev_err(otg->dev, "Unable to resume USB."
 380                                 "Re-plugin the cable\n");
 381                 msm_otg_reset(otg);
 382         }
 383
 384 skip_phy_resume:
 385         if (device_may_wakeup(otg->dev))
 386                 disable_irq_wake(motg->irq);
 387         if (bus)
 388                 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
 389
 390         if (motg->async_int) {
 391                 motg->async_int = 0;
 392                 pm_runtime_put(otg->dev);
 393                 enable_irq(motg->irq);
 394         }
 395
 396         atomic_set(&motg->in_lpm, 0);
 397
 398         dev_info(otg->dev, "USB exited from low power mode\n");
 399
 400         return 0;
 401 }
 402
 403 static void msm_otg_start_host(struct otg_transceiver *otg, int on)
 404 {
 405         struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
 406         struct msm_otg_platform_data *pdata = motg->pdata;
 407         struct usb_hcd *hcd;
 408
 409         if (!otg->host)
 410                 return;
 411
 412         hcd = bus_to_hcd(otg->host);
 413
 414         if (on) {
 415                 dev_dbg(otg->dev, "host on\n");
 416
 417                 if (pdata->vbus_power)
 418                         pdata->vbus_power(1);
 419                 /*
 420                  * Some boards have a switch cotrolled by gpio
 421                  * to enable/disable internal HUB. Enable internal
 422                  * HUB before kicking the host.
 423                  */
 424                 if (pdata->setup_gpio)
 425                         pdata->setup_gpio(OTG_STATE_A_HOST);
 426 #ifdef CONFIG_USB
 427                 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 428 #endif
 429         } else {
 430                 dev_dbg(otg->dev, "host off\n");
 431
 432 #ifdef CONFIG_USB
 433                 usb_remove_hcd(hcd);
 434 #endif
 435                 if (pdata->setup_gpio)
 436                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
 437                 if (pdata->vbus_power)
 438                         pdata->vbus_power(0);
 439         }
 440 }
 441
 442 static int msm_otg_set_host(struct otg_transceiver *otg, struct usb_bus *host)
 443 {
 444         struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
 445         struct usb_hcd *hcd;
 446
 447         /*
 448          * Fail host registration if this board can support
 449          * only peripheral configuration.
 450          */
 451         if (motg->pdata->mode == USB_PERIPHERAL) {
 452                 dev_info(otg->dev, "Host mode is not supported\n");
 453                 return -ENODEV;
 454         }
 455
 456         if (!host) {
 457                 if (otg->state == OTG_STATE_A_HOST) {
 458                         pm_runtime_get_sync(otg->dev);
 459                         msm_otg_start_host(otg, 0);
 460                         otg->host = NULL;
 461                         otg->state = OTG_STATE_UNDEFINED;
 462                         schedule_work(&motg->sm_work);
 463                 } else {
 464                         otg->host = NULL;
 465                 }
 466
 467                 return 0;
 468         }
 469
 470         hcd = bus_to_hcd(host);
 471         hcd->power_budget = motg->pdata->power_budget;
 472
 473         otg->host = host;
 474         dev_dbg(otg->dev, "host driver registered w/ tranceiver\n");
 475
 476         /*
 477          * Kick the state machine work, if peripheral is not supported
 478          * or peripheral is already registered with us.
 479          */
 480         if (motg->pdata->mode == USB_HOST || otg->gadget) {
 481                 pm_runtime_get_sync(otg->dev);
 482                 schedule_work(&motg->sm_work);
 483         }
 484
 485         return 0;
 486 }
 487
 488 static void msm_otg_start_peripheral(struct otg_transceiver *otg, int on)
 489 {
 490         struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
 491         struct msm_otg_platform_data *pdata = motg->pdata;
 492
 493         if (!otg->gadget)
 494                 return;
 495
 496         if (on) {
 497                 dev_dbg(otg->dev, "gadget on\n");
 498                 /*
 499                  * Some boards have a switch cotrolled by gpio
 500                  * to enable/disable internal HUB. Disable internal
 501                  * HUB before kicking the gadget.
 502                  */
 503                 if (pdata->setup_gpio)
 504                         pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
 505                 usb_gadget_vbus_connect(otg->gadget);
 506         } else {
 507                 dev_dbg(otg->dev, "gadget off\n");
 508                 usb_gadget_vbus_disconnect(otg->gadget);
 509                 if (pdata->setup_gpio)
 510                         pdata->setup_gpio(OTG_STATE_UNDEFINED);
 511         }
 512
 513 }
 514
 515 static int msm_otg_set_peripheral(struct otg_transceiver *otg,
 516                         struct usb_gadget *gadget)
 517 {
 518         struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
 519
 520         /*
 521          * Fail peripheral registration if this board can support
 522          * only host configuration.
 523          */
 524         if (motg->pdata->mode == USB_HOST) {
 525                 dev_info(otg->dev, "Peripheral mode is not supported\n");
 526                 return -ENODEV;
 527         }
 528
 529         if (!gadget) {
 530                 if (otg->state == OTG_STATE_B_PERIPHERAL) {
 531                         pm_runtime_get_sync(otg->dev);
 532                         msm_otg_start_peripheral(otg, 0);
 533                         otg->gadget = NULL;
 534                         otg->state = OTG_STATE_UNDEFINED;
 535                         schedule_work(&motg->sm_work);
 536                 } else {
 537                         otg->gadget = NULL;
 538                 }
 539
 540                 return 0;
 541         }
 542         otg->gadget = gadget;
 543         dev_dbg(otg->dev, "peripheral driver registered w/ tranceiver\n");
 544
 545         /*
 546          * Kick the state machine work, if host is not supported
 547          * or host is already registered with us.
 548          */
 549         if (motg->pdata->mode == USB_PERIPHERAL || otg->host) {
 550                 pm_runtime_get_sync(otg->dev);
 551                 schedule_work(&motg->sm_work);
 552         }
 553
 554         return 0;
 555 }
 556
 557 /*
 558  * We support OTG, Peripheral only and Host only configurations. In case
 559  * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
 560  * via Id pin status or user request (debugfs). Id/BSV interrupts are not
 561  * enabled when switch is controlled by user and default mode is supplied
 562  * by board file, which can be changed by userspace later.
 563  */
 564 static void msm_otg_init_sm(struct msm_otg *motg)
 565 {
 566         struct msm_otg_platform_data *pdata = motg->pdata;
 567         u32 otgsc = readl(USB_OTGSC);
 568
 569         switch (pdata->mode) {
 570         case USB_OTG:
 571                 if (pdata->otg_control == OTG_PHY_CONTROL) {
 572                         if (otgsc & OTGSC_ID)
 573                                 set_bit(ID, &motg->inputs);
 574                         else
 575                                 clear_bit(ID, &motg->inputs);
 576
 577                         if (otgsc & OTGSC_BSV)
 578                                 set_bit(B_SESS_VLD, &motg->inputs);
 579                         else
 580                                 clear_bit(B_SESS_VLD, &motg->inputs);
 581                 } else if (pdata->otg_control == OTG_USER_CONTROL) {
 582                         if (pdata->default_mode == USB_HOST) {
 583                                 clear_bit(ID, &motg->inputs);
 584                         } else if (pdata->default_mode == USB_PERIPHERAL) {
 585                                 set_bit(ID, &motg->inputs);
 586                                 set_bit(B_SESS_VLD, &motg->inputs);
 587                         } else {
 588                                 set_bit(ID, &motg->inputs);
 589                                 clear_bit(B_SESS_VLD, &motg->inputs);
 590                         }
 591                 }
 592                 break;
 593         case USB_HOST:
 594                 clear_bit(ID, &motg->inputs);
 595                 break;
 596         case USB_PERIPHERAL:
 597                 set_bit(ID, &motg->inputs);
 598                 if (otgsc & OTGSC_BSV)
 599                         set_bit(B_SESS_VLD, &motg->inputs);
 600                 else
 601                         clear_bit(B_SESS_VLD, &motg->inputs);
 602                 break;
 603         default:
 604                 break;
 605         }
 606 }
 607
 608 static void msm_otg_sm_work(struct work_struct *w)
 609 {
 610         struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
 611         struct otg_transceiver *otg = &motg->otg;
 612
 613         switch (otg->state) {
 614         case OTG_STATE_UNDEFINED:
 615                 dev_dbg(otg->dev, "OTG_STATE_UNDEFINED state\n");
 616                 msm_otg_reset(otg);
 617                 msm_otg_init_sm(motg);
 618                 otg->state = OTG_STATE_B_IDLE;
 619                 /* FALL THROUGH */
 620         case OTG_STATE_B_IDLE:
 621                 dev_dbg(otg->dev, "OTG_STATE_B_IDLE state\n");
 622                 if (!test_bit(ID, &motg->inputs) && otg->host) {
 623                         /* disable BSV bit */
 624                         writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
 625                         msm_otg_start_host(otg, 1);
 626                         otg->state = OTG_STATE_A_HOST;
 627                 } else if (test_bit(B_SESS_VLD, &motg->inputs) && otg->gadget) {
 628                         msm_otg_start_peripheral(otg, 1);
 629                         otg->state = OTG_STATE_B_PERIPHERAL;
 630                 }
 631                 pm_runtime_put_sync(otg->dev);
 632                 break;
 633         case OTG_STATE_B_PERIPHERAL:
 634                 dev_dbg(otg->dev, "OTG_STATE_B_PERIPHERAL state\n");
 635                 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
 636                                 !test_bit(ID, &motg->inputs)) {
 637                         msm_otg_start_peripheral(otg, 0);
 638                         otg->state = OTG_STATE_B_IDLE;
 639                         msm_otg_reset(otg);
 640                         schedule_work(w);
 641                 }
 642                 break;
 643         case OTG_STATE_A_HOST:
 644                 dev_dbg(otg->dev, "OTG_STATE_A_HOST state\n");
 645                 if (test_bit(ID, &motg->inputs)) {
 646                         msm_otg_start_host(otg, 0);
 647                         otg->state = OTG_STATE_B_IDLE;
 648                         msm_otg_reset(otg);
 649                         schedule_work(w);
 650                 }
 651                 break;
 652         default:
 653                 break;
 654         }
 655 }
 656
 657 static irqreturn_t msm_otg_irq(int irq, void *data)
 658 {
 659         struct msm_otg *motg = data;
 660         struct otg_transceiver *otg = &motg->otg;
 661         u32 otgsc = 0;
 662
 663         if (atomic_read(&motg->in_lpm)) {
 664                 disable_irq_nosync(irq);
 665                 motg->async_int = 1;
 666                 pm_runtime_get(otg->dev);
 667                 return IRQ_HANDLED;
 668         }
 669
 670         otgsc = readl(USB_OTGSC);
 671         if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
 672                 return IRQ_NONE;
 673
 674         if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
 675                 if (otgsc & OTGSC_ID)
 676                         set_bit(ID, &motg->inputs);
 677                 else
 678                         clear_bit(ID, &motg->inputs);
 679                 dev_dbg(otg->dev, "ID set/clear\n");
 680                 pm_runtime_get_noresume(otg->dev);
 681         } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
 682                 if (otgsc & OTGSC_BSV)
 683                         set_bit(B_SESS_VLD, &motg->inputs);
 684                 else
 685                         clear_bit(B_SESS_VLD, &motg->inputs);
 686                 dev_dbg(otg->dev, "BSV set/clear\n");
 687                 pm_runtime_get_noresume(otg->dev);
 688         }
 689
 690         writel(otgsc, USB_OTGSC);
 691         schedule_work(&motg->sm_work);
 692         return IRQ_HANDLED;
 693 }
 694
 695 static int msm_otg_mode_show(struct seq_file *s, void *unused)
 696 {
 697         struct msm_otg *motg = s->private;
 698         struct otg_transceiver *otg = &motg->otg;
 699
 700         switch (otg->state) {
 701         case OTG_STATE_A_HOST:
 702                 seq_printf(s, "host\n");
 703                 break;
 704         case OTG_STATE_B_PERIPHERAL:
 705                 seq_printf(s, "peripheral\n");
 706                 break;
 707         default:
 708                 seq_printf(s, "none\n");
 709                 break;
 710         }
 711
 712         return 0;
 713 }
 714
 715 static int msm_otg_mode_open(struct inode *inode, struct file *file)
 716 {
 717         return single_open(file, msm_otg_mode_show, inode->i_private);
 718 }
 719
 720 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
 721                                 size_t count, loff_t *ppos)
 722 {
 723         struct msm_otg *motg = file->private_data;
 724         char buf[16];
 725         struct otg_transceiver *otg = &motg->otg;
 726         int status = count;
 727         enum usb_mode_type req_mode;
 728
 729         memset(buf, 0x00, sizeof(buf));
 730
 731         if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
 732                 status = -EFAULT;
 733                 goto out;
 734         }
 735
 736         if (!strncmp(buf, "host", 4)) {
 737                 req_mode = USB_HOST;
 738         } else if (!strncmp(buf, "peripheral", 10)) {
 739                 req_mode = USB_PERIPHERAL;
 740         } else if (!strncmp(buf, "none", 4)) {
 741                 req_mode = USB_NONE;
 742         } else {
 743                 status = -EINVAL;
 744                 goto out;
 745         }
 746
 747         switch (req_mode) {
 748         case USB_NONE:
 749                 switch (otg->state) {
 750                 case OTG_STATE_A_HOST:
 751                 case OTG_STATE_B_PERIPHERAL:
 752                         set_bit(ID, &motg->inputs);
 753                         clear_bit(B_SESS_VLD, &motg->inputs);
 754                         break;
 755                 default:
 756                         goto out;
 757                 }
 758                 break;
 759         case USB_PERIPHERAL:
 760                 switch (otg->state) {
 761                 case OTG_STATE_B_IDLE:
 762                 case OTG_STATE_A_HOST:
 763                         set_bit(ID, &motg->inputs);
 764                         set_bit(B_SESS_VLD, &motg->inputs);
 765                         break;
 766                 default:
 767                         goto out;
 768                 }
 769                 break;
 770         case USB_HOST:
 771                 switch (otg->state) {
 772                 case OTG_STATE_B_IDLE:
 773                 case OTG_STATE_B_PERIPHERAL:
 774                         clear_bit(ID, &motg->inputs);
 775                         break;
 776                 default:
 777                         goto out;
 778                 }
 779                 break;
 780         default:
 781                 goto out;
 782         }
 783
 784         pm_runtime_get_sync(otg->dev);
 785         schedule_work(&motg->sm_work);
 786 out:
 787         return status;
 788 }
 789
 790 const struct file_operations msm_otg_mode_fops = {
 791         .open = msm_otg_mode_open,
 792         .read = seq_read,
 793         .write = msm_otg_mode_write,
 794         .llseek = seq_lseek,
 795         .release = single_release,
 796 };
 797
 798 static struct dentry *msm_otg_dbg_root;
 799 static struct dentry *msm_otg_dbg_mode;
 800
 801 static int msm_otg_debugfs_init(struct msm_otg *motg)
 802 {
 803         msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
 804
 805         if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
 806                 return -ENODEV;
 807
 808         msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
 809                                 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
 810         if (!msm_otg_dbg_mode) {
 811                 debugfs_remove(msm_otg_dbg_root);
 812                 msm_otg_dbg_root = NULL;
 813                 return -ENODEV;
 814         }
 815
 816         return 0;
 817 }
 818
 819 static void msm_otg_debugfs_cleanup(void)
 820 {
 821         debugfs_remove(msm_otg_dbg_mode);
 822         debugfs_remove(msm_otg_dbg_root);
 823 }
 824
 825 static int __init msm_otg_probe(struct platform_device *pdev)
 826 {
 827         int ret = 0;
 828         struct resource *res;
 829         struct msm_otg *motg;
 830         struct otg_transceiver *otg;
 831
 832         dev_info(&pdev->dev, "msm_otg probe\n");
 833         if (!pdev->dev.platform_data) {
 834                 dev_err(&pdev->dev, "No platform data given. Bailing out\n");
 835                 return -ENODEV;
 836         }
 837
 838         motg = kzalloc(sizeof(struct msm_otg), GFP_KERNEL);
 839         if (!motg) {
 840                 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
 841                 return -ENOMEM;
 842         }
 843
 844         motg->pdata = pdev->dev.platform_data;
 845         otg = &motg->otg;
 846         otg->dev = &pdev->dev;
 847
 848         motg->phy_reset_clk = clk_get(&pdev->dev, "usb_phy_clk");
 849         if (IS_ERR(motg->phy_reset_clk)) {
 850                 dev_err(&pdev->dev, "failed to get usb_phy_clk\n");
 851                 ret = PTR_ERR(motg->phy_reset_clk);
 852                 goto free_motg;
 853         }
 854
 855         motg->clk = clk_get(&pdev->dev, "usb_hs_clk");
 856         if (IS_ERR(motg->clk)) {
 857                 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
 858                 ret = PTR_ERR(motg->clk);
 859                 goto put_phy_reset_clk;
 860         }
 861
 862         motg->pclk = clk_get(&pdev->dev, "usb_hs_pclk");
 863         if (IS_ERR(motg->pclk)) {
 864                 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
 865                 ret = PTR_ERR(motg->pclk);
 866                 goto put_clk;
 867         }
 868
 869         /*
 870          * USB core clock is not present on all MSM chips. This
 871          * clock is introduced to remove the dependency on AXI
 872          * bus frequency.
 873          */
 874         motg->core_clk = clk_get(&pdev->dev, "usb_hs_core_clk");
 875         if (IS_ERR(motg->core_clk))
 876                 motg->core_clk = NULL;
 877
 878         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 879         if (!res) {
 880                 dev_err(&pdev->dev, "failed to get platform resource mem\n");
 881                 ret = -ENODEV;
 882                 goto put_core_clk;
 883         }
 884
 885         motg->regs = ioremap(res->start, resource_size(res));
 886         if (!motg->regs) {
 887                 dev_err(&pdev->dev, "ioremap failed\n");
 888                 ret = -ENOMEM;
 889                 goto put_core_clk;
 890         }
 891         dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
 892
 893         motg->irq = platform_get_irq(pdev, 0);
 894         if (!motg->irq) {
 895                 dev_err(&pdev->dev, "platform_get_irq failed\n");
 896                 ret = -ENODEV;
 897                 goto free_regs;
 898         }
 899
 900         clk_enable(motg->clk);
 901         clk_enable(motg->pclk);
 902         if (motg->core_clk)
 903                 clk_enable(motg->core_clk);
 904
 905         writel(0, USB_USBINTR);
 906         writel(0, USB_OTGSC);
 907
 908         INIT_WORK(&motg->sm_work, msm_otg_sm_work);
 909         ret = request_irq(motg->irq, msm_otg_irq, IRQF_SHARED,
 910                                         "msm_otg", motg);
 911         if (ret) {
 912                 dev_err(&pdev->dev, "request irq failed\n");
 913                 goto disable_clks;
 914         }
 915
 916         otg->init = msm_otg_reset;
 917         otg->set_host = msm_otg_set_host;
 918         otg->set_peripheral = msm_otg_set_peripheral;
 919
 920         otg->io_ops = &msm_otg_io_ops;
 921
 922         ret = otg_set_transceiver(&motg->otg);
 923         if (ret) {
 924                 dev_err(&pdev->dev, "otg_set_transceiver failed\n");
 925                 goto free_irq;
 926         }
 927
 928         platform_set_drvdata(pdev, motg);
 929         device_init_wakeup(&pdev->dev, 1);
 930
 931         if (motg->pdata->mode == USB_OTG &&
 932                         motg->pdata->otg_control == OTG_USER_CONTROL) {
 933                 ret = msm_otg_debugfs_init(motg);
 934                 if (ret)
 935                         dev_dbg(&pdev->dev, "mode debugfs file is"
 936                                         "not available\n");
 937         }
 938
 939         pm_runtime_set_active(&pdev->dev);
 940         pm_runtime_enable(&pdev->dev);
 941
 942         return 0;
 943 free_irq:
 944         free_irq(motg->irq, motg);
 945 disable_clks:
 946         clk_disable(motg->pclk);
 947         clk_disable(motg->clk);
 948 free_regs:
 949         iounmap(motg->regs);
 950 put_core_clk:
 951         if (motg->core_clk)
 952                 clk_put(motg->core_clk);
 953         clk_put(motg->pclk);
 954 put_clk:
 955         clk_put(motg->clk);
 956 put_phy_reset_clk:
 957         clk_put(motg->phy_reset_clk);
 958 free_motg:
 959         kfree(motg);
 960         return ret;
 961 }
 962
 963 static int __devexit msm_otg_remove(struct platform_device *pdev)
 964 {
 965         struct msm_otg *motg = platform_get_drvdata(pdev);
 966         struct otg_transceiver *otg = &motg->otg;
 967         int cnt = 0;
 968
 969         if (otg->host || otg->gadget)
 970                 return -EBUSY;
 971
 972         msm_otg_debugfs_cleanup();
 973         cancel_work_sync(&motg->sm_work);
 974
 975         msm_otg_resume(motg);
 976
 977         device_init_wakeup(&pdev->dev, 0);
 978         pm_runtime_disable(&pdev->dev);
 979
 980         otg_set_transceiver(NULL);
 981         free_irq(motg->irq, motg);
 982
 983         /*
 984          * Put PHY in low power mode.
 985          */
 986         ulpi_read(otg, 0x14);
 987         ulpi_write(otg, 0x08, 0x09);
 988
 989         writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
 990         while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
 991                 if (readl(USB_PORTSC) & PORTSC_PHCD)
 992                         break;
 993                 udelay(1);
 994                 cnt++;
 995         }
 996         if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
 997                 dev_err(otg->dev, "Unable to suspend PHY\n");
 998
 999         clk_disable(motg->pclk);
1000         clk_disable(motg->clk);
1001         if (motg->core_clk)
1002                 clk_disable(motg->core_clk);
1003
1004         iounmap(motg->regs);
1005         pm_runtime_set_suspended(&pdev->dev);
1006
1007         clk_put(motg->phy_reset_clk);
1008         clk_put(motg->pclk);
1009         clk_put(motg->clk);
1010         if (motg->core_clk)
1011                 clk_put(motg->core_clk);
1012
1013         kfree(motg);
1014
1015         return 0;
1016 }
1017
1018 #ifdef CONFIG_PM_RUNTIME
1019 static int msm_otg_runtime_idle(struct device *dev)
1020 {
1021         struct msm_otg *motg = dev_get_drvdata(dev);
1022         struct otg_transceiver *otg = &motg->otg;
1023
1024         dev_dbg(dev, "OTG runtime idle\n");
1025
1026         /*
1027          * It is observed some times that a spurious interrupt
1028          * comes when PHY is put into LPM immediately after PHY reset.
1029          * This 1 sec delay also prevents entering into LPM immediately
1030          * after asynchronous interrupt.
1031          */
1032         if (otg->state != OTG_STATE_UNDEFINED)
1033                 pm_schedule_suspend(dev, 1000);
1034
1035         return -EAGAIN;
1036 }
1037
1038 static int msm_otg_runtime_suspend(struct device *dev)
1039 {
1040         struct msm_otg *motg = dev_get_drvdata(dev);
1041
1042         dev_dbg(dev, "OTG runtime suspend\n");
1043         return msm_otg_suspend(motg);
1044 }
1045
1046 static int msm_otg_runtime_resume(struct device *dev)
1047 {
1048         struct msm_otg *motg = dev_get_drvdata(dev);
1049
1050         dev_dbg(dev, "OTG runtime resume\n");
1051         return msm_otg_resume(motg);
1052 }
1053 #else
1054 #define msm_otg_runtime_idle    NULL
1055 #define msm_otg_runtime_suspend NULL
1056 #define msm_otg_runtime_resume  NULL
1057 #endif
1058
1059 #ifdef CONFIG_PM
1060 static int msm_otg_pm_suspend(struct device *dev)
1061 {
1062         struct msm_otg *motg = dev_get_drvdata(dev);
1063
1064         dev_dbg(dev, "OTG PM suspend\n");
1065         return msm_otg_suspend(motg);
1066 }
1067
1068 static int msm_otg_pm_resume(struct device *dev)
1069 {
1070         struct msm_otg *motg = dev_get_drvdata(dev);
1071         int ret;
1072
1073         dev_dbg(dev, "OTG PM resume\n");
1074
1075         ret = msm_otg_resume(motg);
1076         if (ret)
1077                 return ret;
1078
1079         /*
1080          * Runtime PM Documentation recommends bringing the
1081          * device to full powered state upon resume.
1082          */
1083         pm_runtime_disable(dev);
1084         pm_runtime_set_active(dev);
1085         pm_runtime_enable(dev);
1086
1087         return 0;
1088 }
1089 #else
1090 #define msm_otg_pm_suspend      NULL
1091 #define msm_otg_pm_resume       NULL
1092 #endif
1093
1094 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
1095         .runtime_suspend = msm_otg_runtime_suspend,
1096         .runtime_resume  = msm_otg_runtime_resume,
1097         .runtime_idle    = msm_otg_runtime_idle,
1098         .suspend         = msm_otg_pm_suspend,
1099         .resume          = msm_otg_pm_resume,
1100 };
1101
1102 static struct platform_driver msm_otg_driver = {
1103         .remove = __devexit_p(msm_otg_remove),
1104         .driver = {
1105                 .name = DRIVER_NAME,
1106                 .owner = THIS_MODULE,
1107                 .pm = &msm_otg_dev_pm_ops,
1108         },
1109 };
1110
1111 static int __init msm_otg_init(void)
1112 {
1113         return platform_driver_probe(&msm_otg_driver, msm_otg_probe);
1114 }
1115
1116 static void __exit msm_otg_exit(void)
1117 {
1118         platform_driver_unregister(&msm_otg_driver);
1119 }
1120
1121 module_init(msm_otg_init);
1122 module_exit(msm_otg_exit);
1123
1124 MODULE_LICENSE("GPL v2");
1125 MODULE_DESCRIPTION("MSM USB transceiver driver");