drivers/mfd/mc13783-core.c

   1 /*
   2  * Copyright 2009 Pengutronix
   3  * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
   4  *
   5  * loosely based on an earlier driver that has
   6  * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it under
   9  * the terms of the GNU General Public License version 2 as published by the
  10  * Free Software Foundation.
  11  */
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/mutex.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/spi/spi.h>
  18 #include <linux/mfd/core.h>
  19 #include <linux/mfd/mc13783.h>
  20
  21 struct mc13783 {
  22         struct spi_device *spidev;
  23         struct mutex lock;
  24         int irq;
  25         int flags;
  26
  27         irq_handler_t irqhandler[MC13783_NUM_IRQ];
  28         void *irqdata[MC13783_NUM_IRQ];
  29
  30         /* XXX these should go as platformdata to the regulator subdevice */
  31         struct mc13783_regulator_init_data *regulators;
  32         int num_regulators;
  33 };
  34
  35 #define MC13783_REG_REVISION                     7
  36 #define MC13783_REG_ADC_0                       43
  37 #define MC13783_REG_ADC_1                       44
  38 #define MC13783_REG_ADC_2                       45
  39
  40 #define MC13783_IRQSTAT0        0
  41 #define MC13783_IRQSTAT0_ADCDONEI       (1 << 0)
  42 #define MC13783_IRQSTAT0_ADCBISDONEI    (1 << 1)
  43 #define MC13783_IRQSTAT0_TSI            (1 << 2)
  44 #define MC13783_IRQSTAT0_WHIGHI         (1 << 3)
  45 #define MC13783_IRQSTAT0_WLOWI          (1 << 4)
  46 #define MC13783_IRQSTAT0_CHGDETI        (1 << 6)
  47 #define MC13783_IRQSTAT0_CHGOVI         (1 << 7)
  48 #define MC13783_IRQSTAT0_CHGREVI        (1 << 8)
  49 #define MC13783_IRQSTAT0_CHGSHORTI      (1 << 9)
  50 #define MC13783_IRQSTAT0_CCCVI          (1 << 10)
  51 #define MC13783_IRQSTAT0_CHGCURRI       (1 << 11)
  52 #define MC13783_IRQSTAT0_BPONI          (1 << 12)
  53 #define MC13783_IRQSTAT0_LOBATLI        (1 << 13)
  54 #define MC13783_IRQSTAT0_LOBATHI        (1 << 14)
  55 #define MC13783_IRQSTAT0_UDPI           (1 << 15)
  56 #define MC13783_IRQSTAT0_USBI           (1 << 16)
  57 #define MC13783_IRQSTAT0_IDI            (1 << 19)
  58 #define MC13783_IRQSTAT0_SE1I           (1 << 21)
  59 #define MC13783_IRQSTAT0_CKDETI         (1 << 22)
  60 #define MC13783_IRQSTAT0_UDMI           (1 << 23)
  61
  62 #define MC13783_IRQMASK0        1
  63 #define MC13783_IRQMASK0_ADCDONEM       MC13783_IRQSTAT0_ADCDONEI
  64 #define MC13783_IRQMASK0_ADCBISDONEM    MC13783_IRQSTAT0_ADCBISDONEI
  65 #define MC13783_IRQMASK0_TSM            MC13783_IRQSTAT0_TSI
  66 #define MC13783_IRQMASK0_WHIGHM         MC13783_IRQSTAT0_WHIGHI
  67 #define MC13783_IRQMASK0_WLOWM          MC13783_IRQSTAT0_WLOWI
  68 #define MC13783_IRQMASK0_CHGDETM        MC13783_IRQSTAT0_CHGDETI
  69 #define MC13783_IRQMASK0_CHGOVM         MC13783_IRQSTAT0_CHGOVI
  70 #define MC13783_IRQMASK0_CHGREVM        MC13783_IRQSTAT0_CHGREVI
  71 #define MC13783_IRQMASK0_CHGSHORTM      MC13783_IRQSTAT0_CHGSHORTI
  72 #define MC13783_IRQMASK0_CCCVM          MC13783_IRQSTAT0_CCCVI
  73 #define MC13783_IRQMASK0_CHGCURRM       MC13783_IRQSTAT0_CHGCURRI
  74 #define MC13783_IRQMASK0_BPONM          MC13783_IRQSTAT0_BPONI
  75 #define MC13783_IRQMASK0_LOBATLM        MC13783_IRQSTAT0_LOBATLI
  76 #define MC13783_IRQMASK0_LOBATHM        MC13783_IRQSTAT0_LOBATHI
  77 #define MC13783_IRQMASK0_UDPM           MC13783_IRQSTAT0_UDPI
  78 #define MC13783_IRQMASK0_USBM           MC13783_IRQSTAT0_USBI
  79 #define MC13783_IRQMASK0_IDM            MC13783_IRQSTAT0_IDI
  80 #define MC13783_IRQMASK0_SE1M           MC13783_IRQSTAT0_SE1I
  81 #define MC13783_IRQMASK0_CKDETM         MC13783_IRQSTAT0_CKDETI
  82 #define MC13783_IRQMASK0_UDMM           MC13783_IRQSTAT0_UDMI
  83
  84 #define MC13783_IRQSTAT1        3
  85 #define MC13783_IRQSTAT1_1HZI           (1 << 0)
  86 #define MC13783_IRQSTAT1_TODAI          (1 << 1)
  87 #define MC13783_IRQSTAT1_ONOFD1I        (1 << 3)
  88 #define MC13783_IRQSTAT1_ONOFD2I        (1 << 4)
  89 #define MC13783_IRQSTAT1_ONOFD3I        (1 << 5)
  90 #define MC13783_IRQSTAT1_SYSRSTI        (1 << 6)
  91 #define MC13783_IRQSTAT1_RTCRSTI        (1 << 7)
  92 #define MC13783_IRQSTAT1_PCI            (1 << 8)
  93 #define MC13783_IRQSTAT1_WARMI          (1 << 9)
  94 #define MC13783_IRQSTAT1_MEMHLDI        (1 << 10)
  95 #define MC13783_IRQSTAT1_PWRRDYI        (1 << 11)
  96 #define MC13783_IRQSTAT1_THWARNLI       (1 << 12)
  97 #define MC13783_IRQSTAT1_THWARNHI       (1 << 13)
  98 #define MC13783_IRQSTAT1_CLKI           (1 << 14)
  99 #define MC13783_IRQSTAT1_SEMAFI         (1 << 15)
 100 #define MC13783_IRQSTAT1_MC2BI          (1 << 17)
 101 #define MC13783_IRQSTAT1_HSDETI         (1 << 18)
 102 #define MC13783_IRQSTAT1_HSLI           (1 << 19)
 103 #define MC13783_IRQSTAT1_ALSPTHI        (1 << 20)
 104 #define MC13783_IRQSTAT1_AHSSHORTI      (1 << 21)
 105
 106 #define MC13783_IRQMASK1        4
 107 #define MC13783_IRQMASK1_1HZM           MC13783_IRQSTAT1_1HZI
 108 #define MC13783_IRQMASK1_TODAM          MC13783_IRQSTAT1_TODAI
 109 #define MC13783_IRQMASK1_ONOFD1M        MC13783_IRQSTAT1_ONOFD1I
 110 #define MC13783_IRQMASK1_ONOFD2M        MC13783_IRQSTAT1_ONOFD2I
 111 #define MC13783_IRQMASK1_ONOFD3M        MC13783_IRQSTAT1_ONOFD3I
 112 #define MC13783_IRQMASK1_SYSRSTM        MC13783_IRQSTAT1_SYSRSTI
 113 #define MC13783_IRQMASK1_RTCRSTM        MC13783_IRQSTAT1_RTCRSTI
 114 #define MC13783_IRQMASK1_PCM            MC13783_IRQSTAT1_PCI
 115 #define MC13783_IRQMASK1_WARMM          MC13783_IRQSTAT1_WARMI
 116 #define MC13783_IRQMASK1_MEMHLDM        MC13783_IRQSTAT1_MEMHLDI
 117 #define MC13783_IRQMASK1_PWRRDYM        MC13783_IRQSTAT1_PWRRDYI
 118 #define MC13783_IRQMASK1_THWARNLM       MC13783_IRQSTAT1_THWARNLI
 119 #define MC13783_IRQMASK1_THWARNHM       MC13783_IRQSTAT1_THWARNHI
 120 #define MC13783_IRQMASK1_CLKM           MC13783_IRQSTAT1_CLKI
 121 #define MC13783_IRQMASK1_SEMAFM         MC13783_IRQSTAT1_SEMAFI
 122 #define MC13783_IRQMASK1_MC2BM          MC13783_IRQSTAT1_MC2BI
 123 #define MC13783_IRQMASK1_HSDETM         MC13783_IRQSTAT1_HSDETI
 124 #define MC13783_IRQMASK1_HSLM           MC13783_IRQSTAT1_HSLI
 125 #define MC13783_IRQMASK1_ALSPTHM        MC13783_IRQSTAT1_ALSPTHI
 126 #define MC13783_IRQMASK1_AHSSHORTM      MC13783_IRQSTAT1_AHSSHORTI
 127
 128 #define MC13783_ADC1            44
 129 #define MC13783_ADC1_ADEN               (1 << 0)
 130 #define MC13783_ADC1_RAND               (1 << 1)
 131 #define MC13783_ADC1_ADSEL              (1 << 3)
 132 #define MC13783_ADC1_ASC                (1 << 20)
 133 #define MC13783_ADC1_ADTRIGIGN          (1 << 21)
 134
 135 #define MC13783_NUMREGS 0x3f
 136
 137 void mc13783_lock(struct mc13783 *mc13783)
 138 {
 139         if (!mutex_trylock(&mc13783->lock)) {
 140                 dev_dbg(&mc13783->spidev->dev, "wait for %s from %pf\n",
 141                                 __func__, __builtin_return_address(0));
 142
 143                 mutex_lock(&mc13783->lock);
 144         }
 145         dev_dbg(&mc13783->spidev->dev, "%s from %pf\n",
 146                         __func__, __builtin_return_address(0));
 147 }
 148 EXPORT_SYMBOL(mc13783_lock);
 149
 150 void mc13783_unlock(struct mc13783 *mc13783)
 151 {
 152         dev_dbg(&mc13783->spidev->dev, "%s from %pf\n",
 153                         __func__, __builtin_return_address(0));
 154         mutex_unlock(&mc13783->lock);
 155 }
 156 EXPORT_SYMBOL(mc13783_unlock);
 157
 158 #define MC13783_REGOFFSET_SHIFT 25
 159 int mc13783_reg_read(struct mc13783 *mc13783, unsigned int offset, u32 *val)
 160 {
 161         struct spi_transfer t;
 162         struct spi_message m;
 163         int ret;
 164
 165         BUG_ON(!mutex_is_locked(&mc13783->lock));
 166
 167         if (offset > MC13783_NUMREGS)
 168                 return -EINVAL;
 169
 170         *val = offset << MC13783_REGOFFSET_SHIFT;
 171
 172         memset(&t, 0, sizeof(t));
 173
 174         t.tx_buf = val;
 175         t.rx_buf = val;
 176         t.len = sizeof(u32);
 177
 178         spi_message_init(&m);
 179         spi_message_add_tail(&t, &m);
 180
 181         ret = spi_sync(mc13783->spidev, &m);
 182
 183         /* error in message.status implies error return from spi_sync */
 184         BUG_ON(!ret && m.status);
 185
 186         if (ret)
 187                 return ret;
 188
 189         *val &= 0xffffff;
 190
 191         dev_vdbg(&mc13783->spidev->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
 192
 193         return 0;
 194 }
 195 EXPORT_SYMBOL(mc13783_reg_read);
 196
 197 int mc13783_reg_write(struct mc13783 *mc13783, unsigned int offset, u32 val)
 198 {
 199         u32 buf;
 200         struct spi_transfer t;
 201         struct spi_message m;
 202         int ret;
 203
 204         BUG_ON(!mutex_is_locked(&mc13783->lock));
 205
 206         dev_vdbg(&mc13783->spidev->dev, "[0x%02x] <- 0x%06x\n", offset, val);
 207
 208         if (offset > MC13783_NUMREGS || val > 0xffffff)
 209                 return -EINVAL;
 210
 211         buf = 1 << 31 | offset << MC13783_REGOFFSET_SHIFT | val;
 212
 213         memset(&t, 0, sizeof(t));
 214
 215         t.tx_buf = &buf;
 216         t.rx_buf = &buf;
 217         t.len = sizeof(u32);
 218
 219         spi_message_init(&m);
 220         spi_message_add_tail(&t, &m);
 221
 222         ret = spi_sync(mc13783->spidev, &m);
 223
 224         BUG_ON(!ret && m.status);
 225
 226         if (ret)
 227                 return ret;
 228
 229         return 0;
 230 }
 231 EXPORT_SYMBOL(mc13783_reg_write);
 232
 233 int mc13783_reg_rmw(struct mc13783 *mc13783, unsigned int offset,
 234                 u32 mask, u32 val)
 235 {
 236         int ret;
 237         u32 valread;
 238
 239         BUG_ON(val & ~mask);
 240
 241         ret = mc13783_reg_read(mc13783, offset, &valread);
 242         if (ret)
 243                 return ret;
 244
 245         valread = (valread & ~mask) | val;
 246
 247         return mc13783_reg_write(mc13783, offset, valread);
 248 }
 249 EXPORT_SYMBOL(mc13783_reg_rmw);
 250
 251 int mc13783_get_flags(struct mc13783 *mc13783)
 252 {
 253         return mc13783->flags;
 254 }
 255 EXPORT_SYMBOL(mc13783_get_flags);
 256
 257 int mc13783_irq_mask(struct mc13783 *mc13783, int irq)
 258 {
 259         int ret;
 260         unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
 261         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 262         u32 mask;
 263
 264         if (irq < 0 || irq >= MC13783_NUM_IRQ)
 265                 return -EINVAL;
 266
 267         ret = mc13783_reg_read(mc13783, offmask, &mask);
 268         if (ret)
 269                 return ret;
 270
 271         if (mask & irqbit)
 272                 /* already masked */
 273                 return 0;
 274
 275         return mc13783_reg_write(mc13783, offmask, mask | irqbit);
 276 }
 277 EXPORT_SYMBOL(mc13783_irq_mask);
 278
 279 int mc13783_irq_unmask(struct mc13783 *mc13783, int irq)
 280 {
 281         int ret;
 282         unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
 283         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 284         u32 mask;
 285
 286         if (irq < 0 || irq >= MC13783_NUM_IRQ)
 287                 return -EINVAL;
 288
 289         ret = mc13783_reg_read(mc13783, offmask, &mask);
 290         if (ret)
 291                 return ret;
 292
 293         if (!(mask & irqbit))
 294                 /* already unmasked */
 295                 return 0;
 296
 297         return mc13783_reg_write(mc13783, offmask, mask & ~irqbit);
 298 }
 299 EXPORT_SYMBOL(mc13783_irq_unmask);
 300
 301 int mc13783_irq_status(struct mc13783 *mc13783, int irq,
 302                 int *enabled, int *pending)
 303 {
 304         int ret;
 305         unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
 306         unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1;
 307         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 308
 309         if (irq < 0 || irq >= MC13783_NUM_IRQ)
 310                 return -EINVAL;
 311
 312         if (enabled) {
 313                 u32 mask;
 314
 315                 ret = mc13783_reg_read(mc13783, offmask, &mask);
 316                 if (ret)
 317                         return ret;
 318
 319                 *enabled = mask & irqbit;
 320         }
 321
 322         if (pending) {
 323                 u32 stat;
 324
 325                 ret = mc13783_reg_read(mc13783, offstat, &stat);
 326                 if (ret)
 327                         return ret;
 328
 329                 *pending = stat & irqbit;
 330         }
 331
 332         return 0;
 333 }
 334 EXPORT_SYMBOL(mc13783_irq_status);
 335
 336 int mc13783_irq_ack(struct mc13783 *mc13783, int irq)
 337 {
 338         unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1;
 339         unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
 340
 341         BUG_ON(irq < 0 || irq >= MC13783_NUM_IRQ);
 342
 343         return mc13783_reg_write(mc13783, offstat, val);
 344 }
 345 EXPORT_SYMBOL(mc13783_irq_ack);
 346
 347 int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
 348                 irq_handler_t handler, const char *name, void *dev)
 349 {
 350         BUG_ON(!mutex_is_locked(&mc13783->lock));
 351         BUG_ON(!handler);
 352
 353         if (irq < 0 || irq >= MC13783_NUM_IRQ)
 354                 return -EINVAL;
 355
 356         if (mc13783->irqhandler[irq])
 357                 return -EBUSY;
 358
 359         mc13783->irqhandler[irq] = handler;
 360         mc13783->irqdata[irq] = dev;
 361
 362         return 0;
 363 }
 364 EXPORT_SYMBOL(mc13783_irq_request_nounmask);
 365
 366 int mc13783_irq_request(struct mc13783 *mc13783, int irq,
 367                 irq_handler_t handler, const char *name, void *dev)
 368 {
 369         int ret;
 370
 371         ret = mc13783_irq_request_nounmask(mc13783, irq, handler, name, dev);
 372         if (ret)
 373                 return ret;
 374
 375         ret = mc13783_irq_unmask(mc13783, irq);
 376         if (ret) {
 377                 mc13783->irqhandler[irq] = NULL;
 378                 mc13783->irqdata[irq] = NULL;
 379                 return ret;
 380         }
 381
 382         return 0;
 383 }
 384 EXPORT_SYMBOL(mc13783_irq_request);
 385
 386 int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev)
 387 {
 388         int ret;
 389         BUG_ON(!mutex_is_locked(&mc13783->lock));
 390
 391         if (irq < 0 || irq >= MC13783_NUM_IRQ || !mc13783->irqhandler[irq] ||
 392                         mc13783->irqdata[irq] != dev)
 393                 return -EINVAL;
 394
 395         ret = mc13783_irq_mask(mc13783, irq);
 396         if (ret)
 397                 return ret;
 398
 399         mc13783->irqhandler[irq] = NULL;
 400         mc13783->irqdata[irq] = NULL;
 401
 402         return 0;
 403 }
 404 EXPORT_SYMBOL(mc13783_irq_free);
 405
 406 static inline irqreturn_t mc13783_irqhandler(struct mc13783 *mc13783, int irq)
 407 {
 408         return mc13783->irqhandler[irq](irq, mc13783->irqdata[irq]);
 409 }
 410
 411 /*
 412  * returns: number of handled irqs or negative error
 413  * locking: holds mc13783->lock
 414  */
 415 static int mc13783_irq_handle(struct mc13783 *mc13783,
 416                 unsigned int offstat, unsigned int offmask, int baseirq)
 417 {
 418         u32 stat, mask;
 419         int ret = mc13783_reg_read(mc13783, offstat, &stat);
 420         int num_handled = 0;
 421
 422         if (ret)
 423                 return ret;
 424
 425         ret = mc13783_reg_read(mc13783, offmask, &mask);
 426         if (ret)
 427                 return ret;
 428
 429         while (stat & ~mask) {
 430                 int irq = __ffs(stat & ~mask);
 431
 432                 stat &= ~(1 << irq);
 433
 434                 if (likely(mc13783->irqhandler[baseirq + irq])) {
 435                         irqreturn_t handled;
 436
 437                         handled = mc13783_irqhandler(mc13783, baseirq + irq);
 438                         if (handled == IRQ_HANDLED)
 439                                 num_handled++;
 440                 } else {
 441                         dev_err(&mc13783->spidev->dev,
 442                                         "BUG: irq %u but no handler\n",
 443                                         baseirq + irq);
 444
 445                         mask |= 1 << irq;
 446
 447                         ret = mc13783_reg_write(mc13783, offmask, mask);
 448                 }
 449         }
 450
 451         return num_handled;
 452 }
 453
 454 static irqreturn_t mc13783_irq_thread(int irq, void *data)
 455 {
 456         struct mc13783 *mc13783 = data;
 457         irqreturn_t ret;
 458         int handled = 0;
 459
 460         mc13783_lock(mc13783);
 461
 462         ret = mc13783_irq_handle(mc13783, MC13783_IRQSTAT0,
 463                         MC13783_IRQMASK0, MC13783_IRQ_ADCDONE);
 464         if (ret > 0)
 465                 handled = 1;
 466
 467         ret = mc13783_irq_handle(mc13783, MC13783_IRQSTAT1,
 468                         MC13783_IRQMASK1, MC13783_IRQ_1HZ);
 469         if (ret > 0)
 470                 handled = 1;
 471
 472         mc13783_unlock(mc13783);
 473
 474         return IRQ_RETVAL(handled);
 475 }
 476
 477 #define MC13783_ADC1_CHAN0_SHIFT        5
 478 #define MC13783_ADC1_CHAN1_SHIFT        8
 479
 480 struct mc13783_adcdone_data {
 481         struct mc13783 *mc13783;
 482         struct completion done;
 483 };
 484
 485 static irqreturn_t mc13783_handler_adcdone(int irq, void *data)
 486 {
 487         struct mc13783_adcdone_data *adcdone_data = data;
 488
 489         mc13783_irq_ack(adcdone_data->mc13783, irq);
 490
 491         complete_all(&adcdone_data->done);
 492
 493         return IRQ_HANDLED;
 494 }
 495
 496 #define MC13783_ADC_WORKING (1 << 16)
 497
 498 int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
 499                 unsigned int channel, unsigned int *sample)
 500 {
 501         u32 adc0, adc1, old_adc0;
 502         int i, ret;
 503         struct mc13783_adcdone_data adcdone_data = {
 504                 .mc13783 = mc13783,
 505         };
 506         init_completion(&adcdone_data.done);
 507
 508         dev_dbg(&mc13783->spidev->dev, "%s\n", __func__);
 509
 510         mc13783_lock(mc13783);
 511
 512         if (mc13783->flags & MC13783_ADC_WORKING) {
 513                 ret = -EBUSY;
 514                 goto out;
 515         }
 516
 517         mc13783->flags |= MC13783_ADC_WORKING;
 518
 519         mc13783_reg_read(mc13783, MC13783_ADC0, &old_adc0);
 520
 521         adc0 = MC13783_ADC0_ADINC1 | MC13783_ADC0_ADINC2;
 522         adc1 = MC13783_ADC1_ADEN | MC13783_ADC1_ADTRIGIGN | MC13783_ADC1_ASC;
 523
 524         if (channel > 7)
 525                 adc1 |= MC13783_ADC1_ADSEL;
 526
 527         switch (mode) {
 528         case MC13783_ADC_MODE_TS:
 529                 adc0 |= MC13783_ADC0_ADREFEN | MC13783_ADC0_TSMOD0 |
 530                         MC13783_ADC0_TSMOD1;
 531                 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
 532                 break;
 533
 534         case MC13783_ADC_MODE_SINGLE_CHAN:
 535                 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
 536                 adc1 |= (channel & 0x7) << MC13783_ADC1_CHAN0_SHIFT;
 537                 adc1 |= MC13783_ADC1_RAND;
 538                 break;
 539
 540         case MC13783_ADC_MODE_MULT_CHAN:
 541                 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
 542                 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
 543                 break;
 544
 545         default:
 546                 mc13783_unlock(mc13783);
 547                 return -EINVAL;
 548         }
 549
 550         dev_dbg(&mc13783->spidev->dev, "%s: request irq\n", __func__);
 551         mc13783_irq_request(mc13783, MC13783_IRQ_ADCDONE,
 552                         mc13783_handler_adcdone, __func__, &adcdone_data);
 553         mc13783_irq_ack(mc13783, MC13783_IRQ_ADCDONE);
 554
 555         mc13783_reg_write(mc13783, MC13783_REG_ADC_0, adc0);
 556         mc13783_reg_write(mc13783, MC13783_REG_ADC_1, adc1);
 557
 558         mc13783_unlock(mc13783);
 559
 560         ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
 561
 562         if (!ret)
 563                 ret = -ETIMEDOUT;
 564
 565         mc13783_lock(mc13783);
 566
 567         mc13783_irq_free(mc13783, MC13783_IRQ_ADCDONE, &adcdone_data);
 568
 569         if (ret > 0)
 570                 for (i = 0; i < 4; ++i) {
 571                         ret = mc13783_reg_read(mc13783,
 572                                         MC13783_REG_ADC_2, &sample[i]);
 573                         if (ret)
 574                                 break;
 575                 }
 576
 577         if (mode == MC13783_ADC_MODE_TS)
 578                 /* restore TSMOD */
 579                 mc13783_reg_write(mc13783, MC13783_REG_ADC_0, old_adc0);
 580
 581         mc13783->flags &= ~MC13783_ADC_WORKING;
 582 out:
 583         mc13783_unlock(mc13783);
 584
 585         return ret;
 586 }
 587 EXPORT_SYMBOL_GPL(mc13783_adc_do_conversion);
 588
 589 static int mc13783_add_subdevice_pdata(struct mc13783 *mc13783,
 590                 const char *name, void *pdata, size_t pdata_size)
 591 {
 592         struct mfd_cell cell = {
 593                 .name = name,
 594                 .platform_data = pdata,
 595                 .data_size = pdata_size,
 596         };
 597
 598         return mfd_add_devices(&mc13783->spidev->dev, -1, &cell, 1, NULL, 0);
 599 }
 600
 601 static int mc13783_add_subdevice(struct mc13783 *mc13783, const char *name)
 602 {
 603         return mc13783_add_subdevice_pdata(mc13783, name, NULL, 0);
 604 }
 605
 606 static int mc13783_check_revision(struct mc13783 *mc13783)
 607 {
 608         u32 rev_id, rev1, rev2, finid, icid;
 609
 610         mc13783_reg_read(mc13783, MC13783_REG_REVISION, &rev_id);
 611
 612         rev1 = (rev_id & 0x018) >> 3;
 613         rev2 = (rev_id & 0x007);
 614         icid = (rev_id & 0x01C0) >> 6;
 615         finid = (rev_id & 0x01E00) >> 9;
 616
 617         /* Ver 0.2 is actually 3.2a.  Report as 3.2 */
 618         if ((rev1 == 0) && (rev2 == 2))
 619                 rev1 = 3;
 620
 621         if (rev1 == 0 || icid != 2) {
 622                 dev_err(&mc13783->spidev->dev, "No MC13783 detected.\n");
 623                 return -ENODEV;
 624         }
 625
 626         dev_info(&mc13783->spidev->dev,
 627                         "MC13783 Rev %d.%d FinVer %x detected\n",
 628                         rev1, rev2, finid);
 629
 630         return 0;
 631 }
 632
 633 static int mc13783_probe(struct spi_device *spi)
 634 {
 635         struct mc13783 *mc13783;
 636         struct mc13783_platform_data *pdata = dev_get_platdata(&spi->dev);
 637         int ret;
 638
 639         mc13783 = kzalloc(sizeof(*mc13783), GFP_KERNEL);
 640         if (!mc13783)
 641                 return -ENOMEM;
 642
 643         dev_set_drvdata(&spi->dev, mc13783);
 644         spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
 645         spi->bits_per_word = 32;
 646         spi_setup(spi);
 647
 648         mc13783->spidev = spi;
 649
 650         mutex_init(&mc13783->lock);
 651         mc13783_lock(mc13783);
 652
 653         ret = mc13783_check_revision(mc13783);
 654         if (ret)
 655                 goto err_revision;
 656
 657         /* mask all irqs */
 658         ret = mc13783_reg_write(mc13783, MC13783_IRQMASK0, 0x00ffffff);
 659         if (ret)
 660                 goto err_mask;
 661
 662         ret = mc13783_reg_write(mc13783, MC13783_IRQMASK1, 0x00ffffff);
 663         if (ret)
 664                 goto err_mask;
 665
 666         ret = request_threaded_irq(spi->irq, NULL, mc13783_irq_thread,
 667                         IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13783", mc13783);
 668
 669         if (ret) {
 670 err_mask:
 671 err_revision:
 672                 mutex_unlock(&mc13783->lock);
 673                 dev_set_drvdata(&spi->dev, NULL);
 674                 kfree(mc13783);
 675                 return ret;
 676         }
 677
 678         /* This should go away (BEGIN) */
 679         if (pdata) {
 680                 mc13783->flags = pdata->flags;
 681                 mc13783->regulators = pdata->regulators;
 682                 mc13783->num_regulators = pdata->num_regulators;
 683         }
 684         /* This should go away (END) */
 685
 686         mc13783_unlock(mc13783);
 687
 688         if (pdata->flags & MC13783_USE_ADC)
 689                 mc13783_add_subdevice(mc13783, "mc13783-adc");
 690
 691         if (pdata->flags & MC13783_USE_CODEC)
 692                 mc13783_add_subdevice(mc13783, "mc13783-codec");
 693
 694         if (pdata->flags & MC13783_USE_REGULATOR) {
 695                 struct mc13783_regulator_platform_data regulator_pdata = {
 696                         .num_regulators = pdata->num_regulators,
 697                         .regulators = pdata->regulators,
 698                 };
 699
 700                 mc13783_add_subdevice_pdata(mc13783, "mc13783-regulator",
 701                                 &regulator_pdata, sizeof(regulator_pdata));
 702         }
 703
 704         if (pdata->flags & MC13783_USE_RTC)
 705                 mc13783_add_subdevice(mc13783, "mc13783-rtc");
 706
 707         if (pdata->flags & MC13783_USE_TOUCHSCREEN)
 708                 mc13783_add_subdevice(mc13783, "mc13783-ts");
 709
 710         if (pdata->flags & MC13783_USE_LED)
 711                 mc13783_add_subdevice_pdata(mc13783, "mc13783-led",
 712                                         pdata->leds, sizeof(*pdata->leds));
 713
 714         return 0;
 715 }
 716
 717 static int __devexit mc13783_remove(struct spi_device *spi)
 718 {
 719         struct mc13783 *mc13783 = dev_get_drvdata(&spi->dev);
 720
 721         free_irq(mc13783->spidev->irq, mc13783);
 722
 723         mfd_remove_devices(&spi->dev);
 724
 725         return 0;
 726 }
 727
 728 static struct spi_driver mc13783_driver = {
 729         .driver = {
 730                 .name = "mc13783",
 731                 .bus = &spi_bus_type,
 732                 .owner = THIS_MODULE,
 733         },
 734         .probe = mc13783_probe,
 735         .remove = __devexit_p(mc13783_remove),
 736 };
 737
 738 static int __init mc13783_init(void)
 739 {
 740         return spi_register_driver(&mc13783_driver);
 741 }
 742 subsys_initcall(mc13783_init);
 743
 744 static void __exit mc13783_exit(void)
 745 {
 746         spi_unregister_driver(&mc13783_driver);
 747 }
 748 module_exit(mc13783_exit);
 749
 750 MODULE_DESCRIPTION("Core driver for Freescale MC13783 PMIC");
 751 MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
 752 MODULE_LICENSE("GPL v2");