drivers/pci/msi.c

   1 /*
   2  * File:        msi.c
   3  * Purpose:     PCI Message Signaled Interrupt (MSI)
   4  *
   5  * Copyright (C) 2003-2004 Intel
   6  * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
   7  */
   8
   9 #include <linux/err.h>
  10 #include <linux/mm.h>
  11 #include <linux/irq.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/init.h>
  14 #include <linux/ioport.h>
  15 #include <linux/smp_lock.h>
  16 #include <linux/pci.h>
  17 #include <linux/proc_fs.h>
  18 #include <linux/msi.h>
  19
  20 #include <asm/errno.h>
  21 #include <asm/io.h>
  22 #include <asm/smp.h>
  23
  24 #include "pci.h"
  25 #include "msi.h"
  26
  27 static DEFINE_SPINLOCK(msi_lock);
  28 static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL };
  29 static struct kmem_cache* msi_cachep;
  30
  31 static int pci_msi_enable = 1;
  32
  33 static int msi_cache_init(void)
  34 {
  35         msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc),
  36                                         0, SLAB_HWCACHE_ALIGN, NULL, NULL);
  37         if (!msi_cachep)
  38                 return -ENOMEM;
  39
  40         return 0;
  41 }
  42
  43 static void msi_set_mask_bit(unsigned int irq, int flag)
  44 {
  45         struct msi_desc *entry;
  46
  47         entry = msi_desc[irq];
  48         BUG_ON(!entry || !entry->dev);
  49         switch (entry->msi_attrib.type) {
  50         case PCI_CAP_ID_MSI:
  51                 if (entry->msi_attrib.maskbit) {
  52                         int             pos;
  53                         u32             mask_bits;
  54
  55                         pos = (long)entry->mask_base;
  56                         pci_read_config_dword(entry->dev, pos, &mask_bits);
  57                         mask_bits &= ~(1);
  58                         mask_bits |= flag;
  59                         pci_write_config_dword(entry->dev, pos, mask_bits);
  60                 }
  61                 break;
  62         case PCI_CAP_ID_MSIX:
  63         {
  64                 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
  65                         PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
  66                 writel(flag, entry->mask_base + offset);
  67                 break;
  68         }
  69         default:
  70                 BUG();
  71                 break;
  72         }
  73 }
  74
  75 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
  76 {
  77         struct msi_desc *entry = get_irq_data(irq);
  78         switch(entry->msi_attrib.type) {
  79         case PCI_CAP_ID_MSI:
  80         {
  81                 struct pci_dev *dev = entry->dev;
  82                 int pos = entry->msi_attrib.pos;
  83                 u16 data;
  84
  85                 pci_read_config_dword(dev, msi_lower_address_reg(pos),
  86                                         &msg->address_lo);
  87                 if (entry->msi_attrib.is_64) {
  88                         pci_read_config_dword(dev, msi_upper_address_reg(pos),
  89                                                 &msg->address_hi);
  90                         pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
  91                 } else {
  92                         msg->address_hi = 0;
  93                         pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
  94                 }
  95                 msg->data = data;
  96                 break;
  97         }
  98         case PCI_CAP_ID_MSIX:
  99         {
 100                 void __iomem *base;
 101                 base = entry->mask_base +
 102                         entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 103
 104                 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
 105                 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
 106                 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET);
 107                 break;
 108         }
 109         default:
 110                 BUG();
 111         }
 112 }
 113
 114 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
 115 {
 116         struct msi_desc *entry = get_irq_data(irq);
 117         switch (entry->msi_attrib.type) {
 118         case PCI_CAP_ID_MSI:
 119         {
 120                 struct pci_dev *dev = entry->dev;
 121                 int pos = entry->msi_attrib.pos;
 122
 123                 pci_write_config_dword(dev, msi_lower_address_reg(pos),
 124                                         msg->address_lo);
 125                 if (entry->msi_attrib.is_64) {
 126                         pci_write_config_dword(dev, msi_upper_address_reg(pos),
 127                                                 msg->address_hi);
 128                         pci_write_config_word(dev, msi_data_reg(pos, 1),
 129                                                 msg->data);
 130                 } else {
 131                         pci_write_config_word(dev, msi_data_reg(pos, 0),
 132                                                 msg->data);
 133                 }
 134                 break;
 135         }
 136         case PCI_CAP_ID_MSIX:
 137         {
 138                 void __iomem *base;
 139                 base = entry->mask_base +
 140                         entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 141
 142                 writel(msg->address_lo,
 143                         base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
 144                 writel(msg->address_hi,
 145                         base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
 146                 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET);
 147                 break;
 148         }
 149         default:
 150                 BUG();
 151         }
 152 }
 153
 154 void mask_msi_irq(unsigned int irq)
 155 {
 156         msi_set_mask_bit(irq, 1);
 157 }
 158
 159 void unmask_msi_irq(unsigned int irq)
 160 {
 161         msi_set_mask_bit(irq, 0);
 162 }
 163
 164 static int msi_free_irq(struct pci_dev* dev, int irq);
 165 static int msi_init(void)
 166 {
 167         static int status = -ENOMEM;
 168
 169         if (!status)
 170                 return status;
 171
 172         if (pci_msi_quirk) {
 173                 pci_msi_enable = 0;
 174                 printk(KERN_WARNING "PCI: MSI quirk detected. MSI disabled.\n");
 175                 status = -EINVAL;
 176                 return status;
 177         }
 178
 179         status = msi_cache_init();
 180         if (status < 0) {
 181                 pci_msi_enable = 0;
 182                 printk(KERN_WARNING "PCI: MSI cache init failed\n");
 183                 return status;
 184         }
 185
 186         return status;
 187 }
 188
 189 static struct msi_desc* alloc_msi_entry(void)
 190 {
 191         struct msi_desc *entry;
 192
 193         entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL);
 194         if (!entry)
 195                 return NULL;
 196
 197         entry->link.tail = entry->link.head = 0;        /* single message */
 198         entry->dev = NULL;
 199
 200         return entry;
 201 }
 202
 203 static void attach_msi_entry(struct msi_desc *entry, int irq)
 204 {
 205         unsigned long flags;
 206
 207         spin_lock_irqsave(&msi_lock, flags);
 208         msi_desc[irq] = entry;
 209         spin_unlock_irqrestore(&msi_lock, flags);
 210 }
 211
 212 static int create_msi_irq(void)
 213 {
 214         struct msi_desc *entry;
 215         int irq;
 216
 217         entry = alloc_msi_entry();
 218         if (!entry)
 219                 return -ENOMEM;
 220
 221         irq = create_irq();
 222         if (irq < 0) {
 223                 kmem_cache_free(msi_cachep, entry);
 224                 return -EBUSY;
 225         }
 226
 227         set_irq_data(irq, entry);
 228
 229         return irq;
 230 }
 231
 232 static void destroy_msi_irq(unsigned int irq)
 233 {
 234         struct msi_desc *entry;
 235
 236         entry = get_irq_data(irq);
 237         set_irq_chip(irq, NULL);
 238         set_irq_data(irq, NULL);
 239         destroy_irq(irq);
 240         kmem_cache_free(msi_cachep, entry);
 241 }
 242
 243 static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
 244 {
 245         u16 control;
 246
 247         pci_read_config_word(dev, msi_control_reg(pos), &control);
 248         if (type == PCI_CAP_ID_MSI) {
 249                 /* Set enabled bits to single MSI & enable MSI_enable bit */
 250                 msi_enable(control, 1);
 251                 pci_write_config_word(dev, msi_control_reg(pos), control);
 252                 dev->msi_enabled = 1;
 253         } else {
 254                 msix_enable(control);
 255                 pci_write_config_word(dev, msi_control_reg(pos), control);
 256                 dev->msix_enabled = 1;
 257         }
 258
 259         pci_intx(dev, 0);  /* disable intx */
 260 }
 261
 262 void disable_msi_mode(struct pci_dev *dev, int pos, int type)
 263 {
 264         u16 control;
 265
 266         pci_read_config_word(dev, msi_control_reg(pos), &control);
 267         if (type == PCI_CAP_ID_MSI) {
 268                 /* Set enabled bits to single MSI & enable MSI_enable bit */
 269                 msi_disable(control);
 270                 pci_write_config_word(dev, msi_control_reg(pos), control);
 271                 dev->msi_enabled = 0;
 272         } else {
 273                 msix_disable(control);
 274                 pci_write_config_word(dev, msi_control_reg(pos), control);
 275                 dev->msix_enabled = 0;
 276         }
 277
 278         pci_intx(dev, 1);  /* enable intx */
 279 }
 280
 281 static int msi_lookup_irq(struct pci_dev *dev, int type)
 282 {
 283         int irq;
 284         unsigned long flags;
 285
 286         spin_lock_irqsave(&msi_lock, flags);
 287         for (irq = 0; irq < NR_IRQS; irq++) {
 288                 if (!msi_desc[irq] || msi_desc[irq]->dev != dev ||
 289                         msi_desc[irq]->msi_attrib.type != type ||
 290                         msi_desc[irq]->msi_attrib.default_irq != dev->irq)
 291                         continue;
 292                 spin_unlock_irqrestore(&msi_lock, flags);
 293                 /* This pre-assigned MSI irq for this device
 294                    already exits. Override dev->irq with this irq */
 295                 dev->irq = irq;
 296                 return 0;
 297         }
 298         spin_unlock_irqrestore(&msi_lock, flags);
 299
 300         return -EACCES;
 301 }
 302
 303 void pci_scan_msi_device(struct pci_dev *dev)
 304 {
 305         if (!dev)
 306                 return;
 307 }
 308
 309 #ifdef CONFIG_PM
 310 int pci_save_msi_state(struct pci_dev *dev)
 311 {
 312         int pos, i = 0;
 313         u16 control;
 314         struct pci_cap_saved_state *save_state;
 315         u32 *cap;
 316
 317         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 318         if (pos <= 0 || dev->no_msi)
 319                 return 0;
 320
 321         pci_read_config_word(dev, msi_control_reg(pos), &control);
 322         if (!(control & PCI_MSI_FLAGS_ENABLE))
 323                 return 0;
 324
 325         save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5,
 326                 GFP_KERNEL);
 327         if (!save_state) {
 328                 printk(KERN_ERR "Out of memory in pci_save_msi_state\n");
 329                 return -ENOMEM;
 330         }
 331         cap = &save_state->data[0];
 332
 333         pci_read_config_dword(dev, pos, &cap[i++]);
 334         control = cap[0] >> 16;
 335         pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]);
 336         if (control & PCI_MSI_FLAGS_64BIT) {
 337                 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]);
 338                 pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]);
 339         } else
 340                 pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]);
 341         if (control & PCI_MSI_FLAGS_MASKBIT)
 342                 pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]);
 343         save_state->cap_nr = PCI_CAP_ID_MSI;
 344         pci_add_saved_cap(dev, save_state);
 345         return 0;
 346 }
 347
 348 void pci_restore_msi_state(struct pci_dev *dev)
 349 {
 350         int i = 0, pos;
 351         u16 control;
 352         struct pci_cap_saved_state *save_state;
 353         u32 *cap;
 354
 355         save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI);
 356         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 357         if (!save_state || pos <= 0)
 358                 return;
 359         cap = &save_state->data[0];
 360
 361         control = cap[i++] >> 16;
 362         pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]);
 363         if (control & PCI_MSI_FLAGS_64BIT) {
 364                 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]);
 365                 pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]);
 366         } else
 367                 pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]);
 368         if (control & PCI_MSI_FLAGS_MASKBIT)
 369                 pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]);
 370         pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
 371         enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
 372         pci_remove_saved_cap(save_state);
 373         kfree(save_state);
 374 }
 375
 376 int pci_save_msix_state(struct pci_dev *dev)
 377 {
 378         int pos;
 379         int temp;
 380         int irq, head, tail = 0;
 381         u16 control;
 382         struct pci_cap_saved_state *save_state;
 383
 384         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 385         if (pos <= 0 || dev->no_msi)
 386                 return 0;
 387
 388         /* save the capability */
 389         pci_read_config_word(dev, msi_control_reg(pos), &control);
 390         if (!(control & PCI_MSIX_FLAGS_ENABLE))
 391                 return 0;
 392         save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16),
 393                 GFP_KERNEL);
 394         if (!save_state) {
 395                 printk(KERN_ERR "Out of memory in pci_save_msix_state\n");
 396                 return -ENOMEM;
 397         }
 398         *((u16 *)&save_state->data[0]) = control;
 399
 400         /* save the table */
 401         temp = dev->irq;
 402         if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
 403                 kfree(save_state);
 404                 return -EINVAL;
 405         }
 406
 407         irq = head = dev->irq;
 408         while (head != tail) {
 409                 struct msi_desc *entry;
 410
 411                 entry = msi_desc[irq];
 412                 read_msi_msg(irq, &entry->msg_save);
 413
 414                 tail = msi_desc[irq]->link.tail;
 415                 irq = tail;
 416         }
 417         dev->irq = temp;
 418
 419         save_state->cap_nr = PCI_CAP_ID_MSIX;
 420         pci_add_saved_cap(dev, save_state);
 421         return 0;
 422 }
 423
 424 void pci_restore_msix_state(struct pci_dev *dev)
 425 {
 426         u16 save;
 427         int pos;
 428         int irq, head, tail = 0;
 429         struct msi_desc *entry;
 430         int temp;
 431         struct pci_cap_saved_state *save_state;
 432
 433         save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX);
 434         if (!save_state)
 435                 return;
 436         save = *((u16 *)&save_state->data[0]);
 437         pci_remove_saved_cap(save_state);
 438         kfree(save_state);
 439
 440         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 441         if (pos <= 0)
 442                 return;
 443
 444         /* route the table */
 445         temp = dev->irq;
 446         if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX))
 447                 return;
 448         irq = head = dev->irq;
 449         while (head != tail) {
 450                 entry = msi_desc[irq];
 451                 write_msi_msg(irq, &entry->msg_save);
 452
 453                 tail = msi_desc[irq]->link.tail;
 454                 irq = tail;
 455         }
 456         dev->irq = temp;
 457
 458         pci_write_config_word(dev, msi_control_reg(pos), save);
 459         enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
 460 }
 461 #endif
 462
 463 /**
 464  * msi_capability_init - configure device's MSI capability structure
 465  * @dev: pointer to the pci_dev data structure of MSI device function
 466  *
 467  * Setup the MSI capability structure of device function with a single
 468  * MSI irq, regardless of device function is capable of handling
 469  * multiple messages. A return of zero indicates the successful setup
 470  * of an entry zero with the new MSI irq or non-zero for otherwise.
 471  **/
 472 static int msi_capability_init(struct pci_dev *dev)
 473 {
 474         int status;
 475         struct msi_desc *entry;
 476         int pos, irq;
 477         u16 control;
 478
 479         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 480         pci_read_config_word(dev, msi_control_reg(pos), &control);
 481         /* MSI Entry Initialization */
 482         irq = create_msi_irq();
 483         if (irq < 0)
 484                 return irq;
 485
 486         entry = get_irq_data(irq);
 487         entry->link.head = irq;
 488         entry->link.tail = irq;
 489         entry->msi_attrib.type = PCI_CAP_ID_MSI;
 490         entry->msi_attrib.is_64 = is_64bit_address(control);
 491         entry->msi_attrib.entry_nr = 0;
 492         entry->msi_attrib.maskbit = is_mask_bit_support(control);
 493         entry->msi_attrib.default_irq = dev->irq;       /* Save IOAPIC IRQ */
 494         entry->msi_attrib.pos = pos;
 495         if (is_mask_bit_support(control)) {
 496                 entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos,
 497                                 is_64bit_address(control));
 498         }
 499         entry->dev = dev;
 500         if (entry->msi_attrib.maskbit) {
 501                 unsigned int maskbits, temp;
 502                 /* All MSIs are unmasked by default, Mask them all */
 503                 pci_read_config_dword(dev,
 504                         msi_mask_bits_reg(pos, is_64bit_address(control)),
 505                         &maskbits);
 506                 temp = (1 << multi_msi_capable(control));
 507                 temp = ((temp - 1) & ~temp);
 508                 maskbits |= temp;
 509                 pci_write_config_dword(dev,
 510                         msi_mask_bits_reg(pos, is_64bit_address(control)),
 511                         maskbits);
 512         }
 513         /* Configure MSI capability structure */
 514         status = arch_setup_msi_irq(irq, dev);
 515         if (status < 0) {
 516                 destroy_msi_irq(irq);
 517                 return status;
 518         }
 519
 520         attach_msi_entry(entry, irq);
 521         /* Set MSI enabled bits  */
 522         enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
 523
 524         dev->irq = irq;
 525         return 0;
 526 }
 527
 528 /**
 529  * msix_capability_init - configure device's MSI-X capability
 530  * @dev: pointer to the pci_dev data structure of MSI-X device function
 531  * @entries: pointer to an array of struct msix_entry entries
 532  * @nvec: number of @entries
 533  *
 534  * Setup the MSI-X capability structure of device function with a
 535  * single MSI-X irq. A return of zero indicates the successful setup of
 536  * requested MSI-X entries with allocated irqs or non-zero for otherwise.
 537  **/
 538 static int msix_capability_init(struct pci_dev *dev,
 539                                 struct msix_entry *entries, int nvec)
 540 {
 541         struct msi_desc *head = NULL, *tail = NULL, *entry = NULL;
 542         int status;
 543         int irq, pos, i, j, nr_entries, temp = 0;
 544         unsigned long phys_addr;
 545         u32 table_offset;
 546         u16 control;
 547         u8 bir;
 548         void __iomem *base;
 549
 550         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 551         /* Request & Map MSI-X table region */
 552         pci_read_config_word(dev, msi_control_reg(pos), &control);
 553         nr_entries = multi_msix_capable(control);
 554
 555         pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
 556         bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
 557         table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
 558         phys_addr = pci_resource_start (dev, bir) + table_offset;
 559         base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
 560         if (base == NULL)
 561                 return -ENOMEM;
 562
 563         /* MSI-X Table Initialization */
 564         for (i = 0; i < nvec; i++) {
 565                 irq = create_msi_irq();
 566                 if (irq < 0)
 567                         break;
 568
 569                 entry = get_irq_data(irq);
 570                 j = entries[i].entry;
 571                 entries[i].vector = irq;
 572                 entry->msi_attrib.type = PCI_CAP_ID_MSIX;
 573                 entry->msi_attrib.is_64 = 1;
 574                 entry->msi_attrib.entry_nr = j;
 575                 entry->msi_attrib.maskbit = 1;
 576                 entry->msi_attrib.default_irq = dev->irq;
 577                 entry->msi_attrib.pos = pos;
 578                 entry->dev = dev;
 579                 entry->mask_base = base;
 580                 if (!head) {
 581                         entry->link.head = irq;
 582                         entry->link.tail = irq;
 583                         head = entry;
 584                 } else {
 585                         entry->link.head = temp;
 586                         entry->link.tail = tail->link.tail;
 587                         tail->link.tail = irq;
 588                         head->link.head = irq;
 589                 }
 590                 temp = irq;
 591                 tail = entry;
 592                 /* Configure MSI-X capability structure */
 593                 status = arch_setup_msi_irq(irq, dev);
 594                 if (status < 0) {
 595                         destroy_msi_irq(irq);
 596                         break;
 597                 }
 598
 599                 attach_msi_entry(entry, irq);
 600         }
 601         if (i != nvec) {
 602                 int avail = i - 1;
 603                 i--;
 604                 for (; i >= 0; i--) {
 605                         irq = (entries + i)->vector;
 606                         msi_free_irq(dev, irq);
 607                         (entries + i)->vector = 0;
 608                 }
 609                 /* If we had some success report the number of irqs
 610                  * we succeeded in setting up.
 611                  */
 612                 if (avail <= 0)
 613                         avail = -EBUSY;
 614                 return avail;
 615         }
 616         /* Set MSI-X enabled bits */
 617         enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
 618
 619         return 0;
 620 }
 621
 622 /**
 623  * pci_msi_supported - check whether MSI may be enabled on device
 624  * @dev: pointer to the pci_dev data structure of MSI device function
 625  *
 626  * Look at global flags, the device itself, and its parent busses
 627  * to return 0 if MSI are supported for the device.
 628  **/
 629 static
 630 int pci_msi_supported(struct pci_dev * dev)
 631 {
 632         struct pci_bus *bus;
 633
 634         /* MSI must be globally enabled and supported by the device */
 635         if (!pci_msi_enable || !dev || dev->no_msi)
 636                 return -EINVAL;
 637
 638         /* Any bridge which does NOT route MSI transactions from it's
 639          * secondary bus to it's primary bus must set NO_MSI flag on
 640          * the secondary pci_bus.
 641          * We expect only arch-specific PCI host bus controller driver
 642          * or quirks for specific PCI bridges to be setting NO_MSI.
 643          */
 644         for (bus = dev->bus; bus; bus = bus->parent)
 645                 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
 646                         return -EINVAL;
 647
 648         return 0;
 649 }
 650
 651 /**
 652  * pci_enable_msi - configure device's MSI capability structure
 653  * @dev: pointer to the pci_dev data structure of MSI device function
 654  *
 655  * Setup the MSI capability structure of device function with
 656  * a single MSI irq upon its software driver call to request for
 657  * MSI mode enabled on its hardware device function. A return of zero
 658  * indicates the successful setup of an entry zero with the new MSI
 659  * irq or non-zero for otherwise.
 660  **/
 661 int pci_enable_msi(struct pci_dev* dev)
 662 {
 663         int pos, temp, status;
 664
 665         if (pci_msi_supported(dev) < 0)
 666                 return -EINVAL;
 667
 668         temp = dev->irq;
 669
 670         status = msi_init();
 671         if (status < 0)
 672                 return status;
 673
 674         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 675         if (!pos)
 676                 return -EINVAL;
 677
 678         WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSI));
 679
 680         /* Check whether driver already requested for MSI-X irqs */
 681         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 682         if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
 683                         printk(KERN_INFO "PCI: %s: Can't enable MSI.  "
 684                                "Device already has MSI-X irq assigned\n",
 685                                pci_name(dev));
 686                         dev->irq = temp;
 687                         return -EINVAL;
 688         }
 689         status = msi_capability_init(dev);
 690         return status;
 691 }
 692
 693 void pci_disable_msi(struct pci_dev* dev)
 694 {
 695         struct msi_desc *entry;
 696         int pos, default_irq;
 697         u16 control;
 698         unsigned long flags;
 699
 700         if (!pci_msi_enable)
 701                 return;
 702         if (!dev)
 703                 return;
 704
 705         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 706         if (!pos)
 707                 return;
 708
 709         pci_read_config_word(dev, msi_control_reg(pos), &control);
 710         if (!(control & PCI_MSI_FLAGS_ENABLE))
 711                 return;
 712
 713         disable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
 714
 715         spin_lock_irqsave(&msi_lock, flags);
 716         entry = msi_desc[dev->irq];
 717         if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) {
 718                 spin_unlock_irqrestore(&msi_lock, flags);
 719                 return;
 720         }
 721         if (irq_has_action(dev->irq)) {
 722                 spin_unlock_irqrestore(&msi_lock, flags);
 723                 printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without "
 724                        "free_irq() on MSI irq %d\n",
 725                        pci_name(dev), dev->irq);
 726                 BUG_ON(irq_has_action(dev->irq));
 727         } else {
 728                 default_irq = entry->msi_attrib.default_irq;
 729                 spin_unlock_irqrestore(&msi_lock, flags);
 730                 msi_free_irq(dev, dev->irq);
 731
 732                 /* Restore dev->irq to its default pin-assertion irq */
 733                 dev->irq = default_irq;
 734         }
 735 }
 736
 737 static int msi_free_irq(struct pci_dev* dev, int irq)
 738 {
 739         struct msi_desc *entry;
 740         int head, entry_nr, type;
 741         void __iomem *base;
 742         unsigned long flags;
 743
 744         arch_teardown_msi_irq(irq);
 745
 746         spin_lock_irqsave(&msi_lock, flags);
 747         entry = msi_desc[irq];
 748         if (!entry || entry->dev != dev) {
 749                 spin_unlock_irqrestore(&msi_lock, flags);
 750                 return -EINVAL;
 751         }
 752         type = entry->msi_attrib.type;
 753         entry_nr = entry->msi_attrib.entry_nr;
 754         head = entry->link.head;
 755         base = entry->mask_base;
 756         msi_desc[entry->link.head]->link.tail = entry->link.tail;
 757         msi_desc[entry->link.tail]->link.head = entry->link.head;
 758         entry->dev = NULL;
 759         msi_desc[irq] = NULL;
 760         spin_unlock_irqrestore(&msi_lock, flags);
 761
 762         destroy_msi_irq(irq);
 763
 764         if (type == PCI_CAP_ID_MSIX) {
 765                 writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE +
 766                         PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
 767
 768                 if (head == irq)
 769                         iounmap(base);
 770         }
 771
 772         return 0;
 773 }
 774
 775 /**
 776  * pci_enable_msix - configure device's MSI-X capability structure
 777  * @dev: pointer to the pci_dev data structure of MSI-X device function
 778  * @entries: pointer to an array of MSI-X entries
 779  * @nvec: number of MSI-X irqs requested for allocation by device driver
 780  *
 781  * Setup the MSI-X capability structure of device function with the number
 782  * of requested irqs upon its software driver call to request for
 783  * MSI-X mode enabled on its hardware device function. A return of zero
 784  * indicates the successful configuration of MSI-X capability structure
 785  * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
 786  * Or a return of > 0 indicates that driver request is exceeding the number
 787  * of irqs available. Driver should use the returned value to re-send
 788  * its request.
 789  **/
 790 int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
 791 {
 792         int status, pos, nr_entries;
 793         int i, j, temp;
 794         u16 control;
 795
 796         if (!entries || pci_msi_supported(dev) < 0)
 797                 return -EINVAL;
 798
 799         status = msi_init();
 800         if (status < 0)
 801                 return status;
 802
 803         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 804         if (!pos)
 805                 return -EINVAL;
 806
 807         pci_read_config_word(dev, msi_control_reg(pos), &control);
 808         nr_entries = multi_msix_capable(control);
 809         if (nvec > nr_entries)
 810                 return -EINVAL;
 811
 812         /* Check for any invalid entries */
 813         for (i = 0; i < nvec; i++) {
 814                 if (entries[i].entry >= nr_entries)
 815                         return -EINVAL;         /* invalid entry */
 816                 for (j = i + 1; j < nvec; j++) {
 817                         if (entries[i].entry == entries[j].entry)
 818                                 return -EINVAL; /* duplicate entry */
 819                 }
 820         }
 821         temp = dev->irq;
 822         WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSIX));
 823
 824         /* Check whether driver already requested for MSI irq */
 825         if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 &&
 826                 !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) {
 827                 printk(KERN_INFO "PCI: %s: Can't enable MSI-X.  "
 828                        "Device already has an MSI irq assigned\n",
 829                        pci_name(dev));
 830                 dev->irq = temp;
 831                 return -EINVAL;
 832         }
 833         status = msix_capability_init(dev, entries, nvec);
 834         return status;
 835 }
 836
 837 void pci_disable_msix(struct pci_dev* dev)
 838 {
 839         int pos, temp;
 840         u16 control;
 841
 842         if (!pci_msi_enable)
 843                 return;
 844         if (!dev)
 845                 return;
 846
 847         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 848         if (!pos)
 849                 return;
 850
 851         pci_read_config_word(dev, msi_control_reg(pos), &control);
 852         if (!(control & PCI_MSIX_FLAGS_ENABLE))
 853                 return;
 854
 855         disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
 856
 857         temp = dev->irq;
 858         if (!msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
 859                 int irq, head, tail = 0, warning = 0;
 860                 unsigned long flags;
 861
 862                 irq = head = dev->irq;
 863                 dev->irq = temp;                        /* Restore pin IRQ */
 864                 while (head != tail) {
 865                         spin_lock_irqsave(&msi_lock, flags);
 866                         tail = msi_desc[irq]->link.tail;
 867                         spin_unlock_irqrestore(&msi_lock, flags);
 868                         if (irq_has_action(irq))
 869                                 warning = 1;
 870                         else if (irq != head)   /* Release MSI-X irq */
 871                                 msi_free_irq(dev, irq);
 872                         irq = tail;
 873                 }
 874                 msi_free_irq(dev, irq);
 875                 if (warning) {
 876                         printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without "
 877                                "free_irq() on all MSI-X irqs\n",
 878                                pci_name(dev));
 879                         BUG_ON(warning > 0);
 880                 }
 881         }
 882 }
 883
 884 /**
 885  * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
 886  * @dev: pointer to the pci_dev data structure of MSI(X) device function
 887  *
 888  * Being called during hotplug remove, from which the device function
 889  * is hot-removed. All previous assigned MSI/MSI-X irqs, if
 890  * allocated for this device function, are reclaimed to unused state,
 891  * which may be used later on.
 892  **/
 893 void msi_remove_pci_irq_vectors(struct pci_dev* dev)
 894 {
 895         int pos, temp;
 896         unsigned long flags;
 897
 898         if (!pci_msi_enable || !dev)
 899                 return;
 900
 901         temp = dev->irq;                /* Save IOAPIC IRQ */
 902         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 903         if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) {
 904                 if (irq_has_action(dev->irq)) {
 905                         printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
 906                                "called without free_irq() on MSI irq %d\n",
 907                                pci_name(dev), dev->irq);
 908                         BUG_ON(irq_has_action(dev->irq));
 909                 } else /* Release MSI irq assigned to this device */
 910                         msi_free_irq(dev, dev->irq);
 911                 dev->irq = temp;                /* Restore IOAPIC IRQ */
 912         }
 913         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 914         if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
 915                 int irq, head, tail = 0, warning = 0;
 916                 void __iomem *base = NULL;
 917
 918                 irq = head = dev->irq;
 919                 while (head != tail) {
 920                         spin_lock_irqsave(&msi_lock, flags);
 921                         tail = msi_desc[irq]->link.tail;
 922                         base = msi_desc[irq]->mask_base;
 923                         spin_unlock_irqrestore(&msi_lock, flags);
 924                         if (irq_has_action(irq))
 925                                 warning = 1;
 926                         else if (irq != head) /* Release MSI-X irq */
 927                                 msi_free_irq(dev, irq);
 928                         irq = tail;
 929                 }
 930                 msi_free_irq(dev, irq);
 931                 if (warning) {
 932                         iounmap(base);
 933                         printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
 934                                "called without free_irq() on all MSI-X irqs\n",
 935                                pci_name(dev));
 936                         BUG_ON(warning > 0);
 937                 }
 938                 dev->irq = temp;                /* Restore IOAPIC IRQ */
 939         }
 940 }
 941
 942 void pci_no_msi(void)
 943 {
 944         pci_msi_enable = 0;
 945 }
 946
 947 EXPORT_SYMBOL(pci_enable_msi);
 948 EXPORT_SYMBOL(pci_disable_msi);
 949 EXPORT_SYMBOL(pci_enable_msix);
 950 EXPORT_SYMBOL(pci_disable_msix);