2 * Support for the interrupt controllers found on Power Macintosh,
3 * currently Apple's "Grand Central" interrupt controller in all
4 * it's incarnations. OpenPIC support used on newer machines is
7 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
8 * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
18 #include <linux/stddef.h>
19 #include <linux/init.h>
20 #include <linux/sched.h>
21 #include <linux/signal.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 #include <linux/sysdev.h>
25 #include <linux/adb.h>
26 #include <linux/pmu.h>
27 #include <linux/module.h>
29 #include <asm/sections.h>
33 #include <asm/pci-bridge.h>
35 #include <asm/pmac_feature.h>
49 /* Workaround flags for 32bit powermac machines */
50 unsigned int of_irq_workarounds
;
51 struct device_node
*of_irq_dflt_pic
;
53 /* Default addresses */
54 static volatile struct pmac_irq_hw __iomem
*pmac_irq_hw
[4];
56 #define GC_LEVEL_MASK 0x3ff00000
57 #define OHARE_LEVEL_MASK 0x1ff00000
58 #define HEATHROW_LEVEL_MASK 0x1ff00000
61 static int max_real_irqs
;
62 static u32 level_mask
[4];
64 static DEFINE_RAW_SPINLOCK(pmac_pic_lock
);
66 #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
67 static unsigned long ppc_lost_interrupts
[NR_MASK_WORDS
];
68 static unsigned long ppc_cached_irq_mask
[NR_MASK_WORDS
];
69 static int pmac_irq_cascade
= -1;
70 static struct irq_host
*pmac_pic_host
;
72 static void __pmac_retrigger(unsigned int irq_nr
)
74 if (irq_nr
>= max_real_irqs
&& pmac_irq_cascade
> 0) {
75 __set_bit(irq_nr
, ppc_lost_interrupts
);
76 irq_nr
= pmac_irq_cascade
;
79 if (!__test_and_set_bit(irq_nr
, ppc_lost_interrupts
)) {
80 atomic_inc(&ppc_n_lost_interrupts
);
85 static void pmac_mask_and_ack_irq(unsigned int virq
)
87 unsigned int src
= irq_map
[virq
].hwirq
;
88 unsigned long bit
= 1UL << (src
& 0x1f);
92 raw_spin_lock_irqsave(&pmac_pic_lock
, flags
);
93 __clear_bit(src
, ppc_cached_irq_mask
);
94 if (__test_and_clear_bit(src
, ppc_lost_interrupts
))
95 atomic_dec(&ppc_n_lost_interrupts
);
96 out_le32(&pmac_irq_hw
[i
]->enable
, ppc_cached_irq_mask
[i
]);
97 out_le32(&pmac_irq_hw
[i
]->ack
, bit
);
99 /* make sure ack gets to controller before we enable
102 } while((in_le32(&pmac_irq_hw
[i
]->enable
) & bit
)
103 != (ppc_cached_irq_mask
[i
] & bit
));
104 raw_spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
107 static void pmac_ack_irq(unsigned int virq
)
109 unsigned int src
= irq_map
[virq
].hwirq
;
110 unsigned long bit
= 1UL << (src
& 0x1f);
114 raw_spin_lock_irqsave(&pmac_pic_lock
, flags
);
115 if (__test_and_clear_bit(src
, ppc_lost_interrupts
))
116 atomic_dec(&ppc_n_lost_interrupts
);
117 out_le32(&pmac_irq_hw
[i
]->ack
, bit
);
118 (void)in_le32(&pmac_irq_hw
[i
]->ack
);
119 raw_spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
122 static void __pmac_set_irq_mask(unsigned int irq_nr
, int nokicklost
)
124 unsigned long bit
= 1UL << (irq_nr
& 0x1f);
127 if ((unsigned)irq_nr
>= max_irqs
)
130 /* enable unmasked interrupts */
131 out_le32(&pmac_irq_hw
[i
]->enable
, ppc_cached_irq_mask
[i
]);
134 /* make sure mask gets to controller before we
137 } while((in_le32(&pmac_irq_hw
[i
]->enable
) & bit
)
138 != (ppc_cached_irq_mask
[i
] & bit
));
141 * Unfortunately, setting the bit in the enable register
142 * when the device interrupt is already on *doesn't* set
143 * the bit in the flag register or request another interrupt.
145 if (bit
& ppc_cached_irq_mask
[i
] & in_le32(&pmac_irq_hw
[i
]->level
))
146 __pmac_retrigger(irq_nr
);
149 /* When an irq gets requested for the first client, if it's an
150 * edge interrupt, we clear any previous one on the controller
152 static unsigned int pmac_startup_irq(unsigned int virq
)
155 unsigned int src
= irq_map
[virq
].hwirq
;
156 unsigned long bit
= 1UL << (src
& 0x1f);
159 raw_spin_lock_irqsave(&pmac_pic_lock
, flags
);
160 if ((irq_to_desc(virq
)->status
& IRQ_LEVEL
) == 0)
161 out_le32(&pmac_irq_hw
[i
]->ack
, bit
);
162 __set_bit(src
, ppc_cached_irq_mask
);
163 __pmac_set_irq_mask(src
, 0);
164 raw_spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
169 static void pmac_mask_irq(unsigned int virq
)
172 unsigned int src
= irq_map
[virq
].hwirq
;
174 raw_spin_lock_irqsave(&pmac_pic_lock
, flags
);
175 __clear_bit(src
, ppc_cached_irq_mask
);
176 __pmac_set_irq_mask(src
, 1);
177 raw_spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
180 static void pmac_unmask_irq(unsigned int virq
)
183 unsigned int src
= irq_map
[virq
].hwirq
;
185 raw_spin_lock_irqsave(&pmac_pic_lock
, flags
);
186 __set_bit(src
, ppc_cached_irq_mask
);
187 __pmac_set_irq_mask(src
, 0);
188 raw_spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
191 static int pmac_retrigger(unsigned int virq
)
195 raw_spin_lock_irqsave(&pmac_pic_lock
, flags
);
196 __pmac_retrigger(irq_map
[virq
].hwirq
);
197 raw_spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
201 static struct irq_chip pmac_pic
= {
203 .startup
= pmac_startup_irq
,
204 .mask
= pmac_mask_irq
,
206 .mask_ack
= pmac_mask_and_ack_irq
,
207 .unmask
= pmac_unmask_irq
,
208 .retrigger
= pmac_retrigger
,
211 static irqreturn_t
gatwick_action(int cpl
, void *dev_id
)
217 raw_spin_lock_irqsave(&pmac_pic_lock
, flags
);
218 for (irq
= max_irqs
; (irq
-= 32) >= max_real_irqs
; ) {
220 bits
= in_le32(&pmac_irq_hw
[i
]->event
) | ppc_lost_interrupts
[i
];
221 /* We must read level interrupts from the level register */
222 bits
|= (in_le32(&pmac_irq_hw
[i
]->level
) & level_mask
[i
]);
223 bits
&= ppc_cached_irq_mask
[i
];
226 irq
+= __ilog2(bits
);
227 raw_spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
228 generic_handle_irq(irq
);
229 raw_spin_lock_irqsave(&pmac_pic_lock
, flags
);
232 raw_spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
236 static unsigned int pmac_pic_get_irq(void)
239 unsigned long bits
= 0;
243 void psurge_smp_message_recv(void);
245 /* IPI's are a hack on the powersurge -- Cort */
246 if ( smp_processor_id() != 0 ) {
247 psurge_smp_message_recv();
248 return NO_IRQ_IGNORE
; /* ignore, already handled */
250 #endif /* CONFIG_SMP */
251 raw_spin_lock_irqsave(&pmac_pic_lock
, flags
);
252 for (irq
= max_real_irqs
; (irq
-= 32) >= 0; ) {
254 bits
= in_le32(&pmac_irq_hw
[i
]->event
) | ppc_lost_interrupts
[i
];
255 /* We must read level interrupts from the level register */
256 bits
|= (in_le32(&pmac_irq_hw
[i
]->level
) & level_mask
[i
]);
257 bits
&= ppc_cached_irq_mask
[i
];
260 irq
+= __ilog2(bits
);
263 raw_spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
264 if (unlikely(irq
< 0))
266 return irq_linear_revmap(pmac_pic_host
, irq
);
270 static struct irqaction xmon_action
= {
277 static struct irqaction gatwick_cascade_action
= {
278 .handler
= gatwick_action
,
279 .flags
= IRQF_DISABLED
,
283 static int pmac_pic_host_match(struct irq_host
*h
, struct device_node
*node
)
285 /* We match all, we don't always have a node anyway */
289 static int pmac_pic_host_map(struct irq_host
*h
, unsigned int virq
,
292 struct irq_desc
*desc
= irq_to_desc(virq
);
298 /* Mark level interrupts, set delayed disable for edge ones and set
301 level
= !!(level_mask
[hw
>> 5] & (1UL << (hw
& 0x1f)));
303 desc
->status
|= IRQ_LEVEL
;
304 set_irq_chip_and_handler(virq
, &pmac_pic
, level
?
305 handle_level_irq
: handle_edge_irq
);
309 static int pmac_pic_host_xlate(struct irq_host
*h
, struct device_node
*ct
,
310 const u32
*intspec
, unsigned int intsize
,
311 irq_hw_number_t
*out_hwirq
,
312 unsigned int *out_flags
)
315 *out_flags
= IRQ_TYPE_NONE
;
316 *out_hwirq
= *intspec
;
320 static struct irq_host_ops pmac_pic_host_ops
= {
321 .match
= pmac_pic_host_match
,
322 .map
= pmac_pic_host_map
,
323 .xlate
= pmac_pic_host_xlate
,
326 static void __init
pmac_pic_probe_oldstyle(void)
329 struct device_node
*master
= NULL
;
330 struct device_node
*slave
= NULL
;
334 /* Set our get_irq function */
335 ppc_md
.get_irq
= pmac_pic_get_irq
;
338 * Find the interrupt controller type & node
341 if ((master
= of_find_node_by_name(NULL
, "gc")) != NULL
) {
342 max_irqs
= max_real_irqs
= 32;
343 level_mask
[0] = GC_LEVEL_MASK
;
344 } else if ((master
= of_find_node_by_name(NULL
, "ohare")) != NULL
) {
345 max_irqs
= max_real_irqs
= 32;
346 level_mask
[0] = OHARE_LEVEL_MASK
;
348 /* We might have a second cascaded ohare */
349 slave
= of_find_node_by_name(NULL
, "pci106b,7");
352 level_mask
[1] = OHARE_LEVEL_MASK
;
354 } else if ((master
= of_find_node_by_name(NULL
, "mac-io")) != NULL
) {
355 max_irqs
= max_real_irqs
= 64;
356 level_mask
[0] = HEATHROW_LEVEL_MASK
;
359 /* We might have a second cascaded heathrow */
360 slave
= of_find_node_by_name(master
, "mac-io");
362 /* Check ordering of master & slave */
363 if (of_device_is_compatible(master
, "gatwick")) {
364 struct device_node
*tmp
;
365 BUG_ON(slave
== NULL
);
371 /* We found a slave */
374 level_mask
[2] = HEATHROW_LEVEL_MASK
;
378 BUG_ON(master
== NULL
);
381 * Allocate an irq host
383 pmac_pic_host
= irq_alloc_host(master
, IRQ_HOST_MAP_LINEAR
, max_irqs
,
386 BUG_ON(pmac_pic_host
== NULL
);
387 irq_set_default_host(pmac_pic_host
);
389 /* Get addresses of first controller if we have a node for it */
390 BUG_ON(of_address_to_resource(master
, 0, &r
));
392 /* Map interrupts of primary controller */
393 addr
= (u8 __iomem
*) ioremap(r
.start
, 0x40);
395 pmac_irq_hw
[i
++] = (volatile struct pmac_irq_hw __iomem
*)
397 if (max_real_irqs
> 32)
398 pmac_irq_hw
[i
++] = (volatile struct pmac_irq_hw __iomem
*)
402 printk(KERN_INFO
"irq: Found primary Apple PIC %s for %d irqs\n",
403 master
->full_name
, max_real_irqs
);
405 /* Map interrupts of cascaded controller */
406 if (slave
&& !of_address_to_resource(slave
, 0, &r
)) {
407 addr
= (u8 __iomem
*)ioremap(r
.start
, 0x40);
408 pmac_irq_hw
[i
++] = (volatile struct pmac_irq_hw __iomem
*)
412 (volatile struct pmac_irq_hw __iomem
*)
414 pmac_irq_cascade
= irq_of_parse_and_map(slave
, 0);
416 printk(KERN_INFO
"irq: Found slave Apple PIC %s for %d irqs"
417 " cascade: %d\n", slave
->full_name
,
418 max_irqs
- max_real_irqs
, pmac_irq_cascade
);
422 /* Disable all interrupts in all controllers */
423 for (i
= 0; i
* 32 < max_irqs
; ++i
)
424 out_le32(&pmac_irq_hw
[i
]->enable
, 0);
426 /* Hookup cascade irq */
427 if (slave
&& pmac_irq_cascade
!= NO_IRQ
)
428 setup_irq(pmac_irq_cascade
, &gatwick_cascade_action
);
430 printk(KERN_INFO
"irq: System has %d possible interrupts\n", max_irqs
);
432 setup_irq(irq_create_mapping(NULL
, 20), &xmon_action
);
436 int of_irq_map_oldworld(struct device_node
*device
, int index
,
437 struct of_irq
*out_irq
)
439 const u32
*ints
= NULL
;
443 * Old machines just have a list of interrupt numbers
444 * and no interrupt-controller nodes. We also have dodgy
445 * cases where the APPL,interrupts property is completely
446 * missing behind pci-pci bridges and we have to get it
447 * from the parent (the bridge itself, as apple just wired
448 * everything together on these)
451 ints
= of_get_property(device
, "AAPL,interrupts", &intlen
);
454 device
= device
->parent
;
455 if (device
&& strcmp(device
->type
, "pci") != 0)
460 intlen
/= sizeof(u32
);
465 out_irq
->controller
= NULL
;
466 out_irq
->specifier
[0] = ints
[index
];
471 #endif /* CONFIG_PPC32 */
473 static void pmac_u3_cascade(unsigned int irq
, struct irq_desc
*desc
)
475 struct mpic
*mpic
= desc
->handler_data
;
477 unsigned int cascade_irq
= mpic_get_one_irq(mpic
);
478 if (cascade_irq
!= NO_IRQ
)
479 generic_handle_irq(cascade_irq
);
480 desc
->chip
->eoi(irq
);
483 static void __init
pmac_pic_setup_mpic_nmi(struct mpic
*mpic
)
485 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
486 struct device_node
* pswitch
;
489 pswitch
= of_find_node_by_name(NULL
, "programmer-switch");
491 nmi_irq
= irq_of_parse_and_map(pswitch
, 0);
492 if (nmi_irq
!= NO_IRQ
) {
493 mpic_irq_set_priority(nmi_irq
, 9);
494 setup_irq(nmi_irq
, &xmon_action
);
496 of_node_put(pswitch
);
498 #endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
501 static struct mpic
* __init
pmac_setup_one_mpic(struct device_node
*np
,
504 const char *name
= master
? " MPIC 1 " : " MPIC 2 ";
507 unsigned int flags
= master
? MPIC_PRIMARY
: 0;
510 rc
= of_address_to_resource(np
, 0, &r
);
514 pmac_call_feature(PMAC_FTR_ENABLE_MPIC
, np
, 0, 0);
516 flags
|= MPIC_WANTS_RESET
;
517 if (of_get_property(np
, "big-endian", NULL
))
518 flags
|= MPIC_BIG_ENDIAN
;
520 /* Primary Big Endian means HT interrupts. This is quite dodgy
521 * but works until I find a better way
523 if (master
&& (flags
& MPIC_BIG_ENDIAN
))
524 flags
|= MPIC_U3_HT_IRQS
;
526 mpic
= mpic_alloc(np
, r
.start
, flags
, 0, 0, name
);
535 static int __init
pmac_pic_probe_mpic(void)
537 struct mpic
*mpic1
, *mpic2
;
538 struct device_node
*np
, *master
= NULL
, *slave
= NULL
;
539 unsigned int cascade
;
541 /* We can have up to 2 MPICs cascaded */
542 for (np
= NULL
; (np
= of_find_node_by_type(np
, "open-pic"))
544 if (master
== NULL
&&
545 of_get_property(np
, "interrupts", NULL
) == NULL
)
546 master
= of_node_get(np
);
547 else if (slave
== NULL
)
548 slave
= of_node_get(np
);
553 /* Check for bogus setups */
554 if (master
== NULL
&& slave
!= NULL
) {
559 /* Not found, default to good old pmac pic */
563 /* Set master handler */
564 ppc_md
.get_irq
= mpic_get_irq
;
567 mpic1
= pmac_setup_one_mpic(master
, 1);
568 BUG_ON(mpic1
== NULL
);
570 /* Install NMI if any */
571 pmac_pic_setup_mpic_nmi(mpic1
);
575 /* No slave, let's go out */
579 /* Get/Map slave interrupt */
580 cascade
= irq_of_parse_and_map(slave
, 0);
581 if (cascade
== NO_IRQ
) {
582 printk(KERN_ERR
"Failed to map cascade IRQ\n");
586 mpic2
= pmac_setup_one_mpic(slave
, 0);
588 printk(KERN_ERR
"Failed to setup slave MPIC\n");
592 set_irq_data(cascade
, mpic2
);
593 set_irq_chained_handler(cascade
, pmac_u3_cascade
);
600 void __init
pmac_pic_init(void)
602 /* We configure the OF parsing based on our oldworld vs. newworld
603 * platform type and wether we were booted by BootX.
607 of_irq_workarounds
|= OF_IMAP_OLDWORLD_MAC
;
608 if (of_get_property(of_chosen
, "linux,bootx", NULL
) != NULL
)
609 of_irq_workarounds
|= OF_IMAP_NO_PHANDLE
;
611 /* If we don't have phandles on a newworld, then try to locate a
612 * default interrupt controller (happens when booting with BootX).
613 * We do a first match here, hopefully, that only ever happens on
614 * machines with one controller.
616 if (pmac_newworld
&& (of_irq_workarounds
& OF_IMAP_NO_PHANDLE
)) {
617 struct device_node
*np
;
619 for_each_node_with_property(np
, "interrupt-controller") {
620 /* Skip /chosen/interrupt-controller */
621 if (strcmp(np
->name
, "chosen") == 0)
623 /* It seems like at least one person wants
624 * to use BootX on a machine with an AppleKiwi
625 * controller which happens to pretend to be an
626 * interrupt controller too. */
627 if (strcmp(np
->name
, "AppleKiwi") == 0)
629 /* I think we found one ! */
630 of_irq_dflt_pic
= np
;
634 #endif /* CONFIG_PPC32 */
636 /* We first try to detect Apple's new Core99 chipset, since mac-io
637 * is quite different on those machines and contains an IBM MPIC2.
639 if (pmac_pic_probe_mpic() == 0)
643 pmac_pic_probe_oldstyle();
647 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
649 * These procedures are used in implementing sleep on the powerbooks.
650 * sleep_save_intrs() saves the states of all interrupt enables
651 * and disables all interrupts except for the nominated one.
652 * sleep_restore_intrs() restores the states of all interrupt enables.
654 unsigned long sleep_save_mask
[2];
656 /* This used to be passed by the PMU driver but that link got
657 * broken with the new driver model. We use this tweak for now...
658 * We really want to do things differently though...
660 static int pmacpic_find_viaint(void)
664 #ifdef CONFIG_ADB_PMU
665 struct device_node
*np
;
667 if (pmu_get_model() != PMU_OHARE_BASED
)
669 np
= of_find_node_by_name(NULL
, "via-pmu");
672 viaint
= irq_of_parse_and_map(np
, 0);
675 #endif /* CONFIG_ADB_PMU */
679 static int pmacpic_suspend(struct sys_device
*sysdev
, pm_message_t state
)
681 int viaint
= pmacpic_find_viaint();
683 sleep_save_mask
[0] = ppc_cached_irq_mask
[0];
684 sleep_save_mask
[1] = ppc_cached_irq_mask
[1];
685 ppc_cached_irq_mask
[0] = 0;
686 ppc_cached_irq_mask
[1] = 0;
688 set_bit(viaint
, ppc_cached_irq_mask
);
689 out_le32(&pmac_irq_hw
[0]->enable
, ppc_cached_irq_mask
[0]);
690 if (max_real_irqs
> 32)
691 out_le32(&pmac_irq_hw
[1]->enable
, ppc_cached_irq_mask
[1]);
692 (void)in_le32(&pmac_irq_hw
[0]->event
);
693 /* make sure mask gets to controller before we return to caller */
695 (void)in_le32(&pmac_irq_hw
[0]->enable
);
700 static int pmacpic_resume(struct sys_device
*sysdev
)
704 out_le32(&pmac_irq_hw
[0]->enable
, 0);
705 if (max_real_irqs
> 32)
706 out_le32(&pmac_irq_hw
[1]->enable
, 0);
708 for (i
= 0; i
< max_real_irqs
; ++i
)
709 if (test_bit(i
, sleep_save_mask
))
715 #endif /* CONFIG_PM && CONFIG_PPC32 */
717 static struct sysdev_class pmacpic_sysclass
= {
721 static struct sys_device device_pmacpic
= {
723 .cls
= &pmacpic_sysclass
,
726 static struct sysdev_driver driver_pmacpic
= {
727 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
728 .suspend
= &pmacpic_suspend
,
729 .resume
= &pmacpic_resume
,
730 #endif /* CONFIG_PM && CONFIG_PPC32 */
733 static int __init
init_pmacpic_sysfs(void)
739 printk(KERN_DEBUG
"Registering pmac pic with sysfs...\n");
740 sysdev_class_register(&pmacpic_sysclass
);
741 sysdev_register(&device_pmacpic
);
742 sysdev_driver_register(&pmacpic_sysclass
, &driver_pmacpic
);
745 machine_subsys_initcall(powermac
, init_pmacpic_sysfs
);