arch/arm/mach-omap1/serial.c

   1 /*
   2  * linux/arch/arm/mach-omap1/serial.c
   3  *
   4  * OMAP1 serial support.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/irq.h>
  15 #include <linux/delay.h>
  16 #include <linux/serial.h>
  17 #include <linux/tty.h>
  18 #include <linux/serial_8250.h>
  19 #include <linux/serial_reg.h>
  20 #include <linux/clk.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/mach-types.h>
  24
  25 #include <plat/board.h>
  26 #include <plat/mux.h>
  27 #include <mach/gpio.h>
  28 #include <plat/fpga.h>
  29
  30 #include "pm.h"
  31
  32 static struct clk * uart1_ck;
  33 static struct clk * uart2_ck;
  34 static struct clk * uart3_ck;
  35
  36 static inline unsigned int omap_serial_in(struct plat_serial8250_port *up,
  37                                           int offset)
  38 {
  39         offset <<= up->regshift;
  40         return (unsigned int)__raw_readb(up->membase + offset);
  41 }
  42
  43 static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset,
  44                                     int value)
  45 {
  46         offset <<= p->regshift;
  47         __raw_writeb(value, p->membase + offset);
  48 }
  49
  50 /*
  51  * Internal UARTs need to be initialized for the 8250 autoconfig to work
  52  * properly. Note that the TX watermark initialization may not be needed
  53  * once the 8250.c watermark handling code is merged.
  54  */
  55 static void __init omap_serial_reset(struct plat_serial8250_port *p)
  56 {
  57         omap_serial_outp(p, UART_OMAP_MDR1,
  58                         UART_OMAP_MDR1_DISABLE);        /* disable UART */
  59         omap_serial_outp(p, UART_OMAP_SCR, 0x08);       /* TX watermark */
  60         omap_serial_outp(p, UART_OMAP_MDR1,
  61                         UART_OMAP_MDR1_16X_MODE);       /* enable UART */
  62
  63         if (!cpu_is_omap15xx()) {
  64                 omap_serial_outp(p, UART_OMAP_SYSC, 0x01);
  65                 while (!(omap_serial_in(p, UART_OMAP_SYSC) & 0x01));
  66         }
  67 }
  68
  69 static struct plat_serial8250_port serial_platform_data[] = {
  70         {
  71                 .mapbase        = OMAP1_UART1_BASE,
  72                 .irq            = INT_UART1,
  73                 .flags          = UPF_BOOT_AUTOCONF,
  74                 .iotype         = UPIO_MEM,
  75                 .regshift       = 2,
  76                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
  77         },
  78         {
  79                 .mapbase        = OMAP1_UART2_BASE,
  80                 .irq            = INT_UART2,
  81                 .flags          = UPF_BOOT_AUTOCONF,
  82                 .iotype         = UPIO_MEM,
  83                 .regshift       = 2,
  84                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
  85         },
  86         {
  87                 .mapbase        = OMAP1_UART3_BASE,
  88                 .irq            = INT_UART3,
  89                 .flags          = UPF_BOOT_AUTOCONF,
  90                 .iotype         = UPIO_MEM,
  91                 .regshift       = 2,
  92                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
  93         },
  94         { },
  95 };
  96
  97 static struct platform_device serial_device = {
  98         .name                   = "serial8250",
  99         .id                     = PLAT8250_DEV_PLATFORM,
 100         .dev                    = {
 101                 .platform_data  = serial_platform_data,
 102         },
 103 };
 104
 105 /*
 106  * Note that on Innovator-1510 UART2 pins conflict with USB2.
 107  * By default UART2 does not work on Innovator-1510 if you have
 108  * USB OHCI enabled. To use UART2, you must disable USB2 first.
 109  */
 110 void __init omap_serial_init(void)
 111 {
 112         int i;
 113
 114         if (cpu_is_omap7xx()) {
 115                 serial_platform_data[0].regshift = 0;
 116                 serial_platform_data[1].regshift = 0;
 117                 serial_platform_data[0].irq = INT_7XX_UART_MODEM_1;
 118                 serial_platform_data[1].irq = INT_7XX_UART_MODEM_IRDA_2;
 119         }
 120
 121         if (cpu_is_omap15xx()) {
 122                 serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16;
 123                 serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16;
 124                 serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;
 125         }
 126
 127         for (i = 0; i < ARRAY_SIZE(serial_platform_data) - 1; i++) {
 128
 129                 /* Don't look at UARTs higher than 2 for omap7xx */
 130                 if (cpu_is_omap7xx() && i > 1) {
 131                         serial_platform_data[i].membase = NULL;
 132                         serial_platform_data[i].mapbase = 0;
 133                         continue;
 134                 }
 135
 136                 /* Static mapping, never released */
 137                 serial_platform_data[i].membase =
 138                         ioremap(serial_platform_data[i].mapbase, SZ_2K);
 139                 if (!serial_platform_data[i].membase) {
 140                         printk(KERN_ERR "Could not ioremap uart%i\n", i);
 141                         continue;
 142                 }
 143                 switch (i) {
 144                 case 0:
 145                         uart1_ck = clk_get(NULL, "uart1_ck");
 146                         if (IS_ERR(uart1_ck))
 147                                 printk("Could not get uart1_ck\n");
 148                         else {
 149                                 clk_enable(uart1_ck);
 150                                 if (cpu_is_omap15xx())
 151                                         clk_set_rate(uart1_ck, 12000000);
 152                         }
 153                         break;
 154                 case 1:
 155                         uart2_ck = clk_get(NULL, "uart2_ck");
 156                         if (IS_ERR(uart2_ck))
 157                                 printk("Could not get uart2_ck\n");
 158                         else {
 159                                 clk_enable(uart2_ck);
 160                                 if (cpu_is_omap15xx())
 161                                         clk_set_rate(uart2_ck, 12000000);
 162                                 else
 163                                         clk_set_rate(uart2_ck, 48000000);
 164                         }
 165                         break;
 166                 case 2:
 167                         uart3_ck = clk_get(NULL, "uart3_ck");
 168                         if (IS_ERR(uart3_ck))
 169                                 printk("Could not get uart3_ck\n");
 170                         else {
 171                                 clk_enable(uart3_ck);
 172                                 if (cpu_is_omap15xx())
 173                                         clk_set_rate(uart3_ck, 12000000);
 174                         }
 175                         break;
 176                 }
 177                 omap_serial_reset(&serial_platform_data[i]);
 178         }
 179 }
 180
 181 #ifdef CONFIG_OMAP_SERIAL_WAKE
 182
 183 static irqreturn_t omap_serial_wake_interrupt(int irq, void *dev_id)
 184 {
 185         /* Need to do something with serial port right after wake-up? */
 186         return IRQ_HANDLED;
 187 }
 188
 189 /*
 190  * Reroutes serial RX lines to GPIO lines for the duration of
 191  * sleep to allow waking up the device from serial port even
 192  * in deep sleep.
 193  */
 194 void omap_serial_wake_trigger(int enable)
 195 {
 196         if (!cpu_is_omap16xx())
 197                 return;
 198
 199         if (uart1_ck != NULL) {
 200                 if (enable)
 201                         omap_cfg_reg(V14_16XX_GPIO37);
 202                 else
 203                         omap_cfg_reg(V14_16XX_UART1_RX);
 204         }
 205         if (uart2_ck != NULL) {
 206                 if (enable)
 207                         omap_cfg_reg(R9_16XX_GPIO18);
 208                 else
 209                         omap_cfg_reg(R9_16XX_UART2_RX);
 210         }
 211         if (uart3_ck != NULL) {
 212                 if (enable)
 213                         omap_cfg_reg(L14_16XX_GPIO49);
 214                 else
 215                         omap_cfg_reg(L14_16XX_UART3_RX);
 216         }
 217 }
 218
 219 static void __init omap_serial_set_port_wakeup(int gpio_nr)
 220 {
 221         int ret;
 222
 223         ret = gpio_request(gpio_nr, "UART wake");
 224         if (ret < 0) {
 225                 printk(KERN_ERR "Could not request UART wake GPIO: %i\n",
 226                        gpio_nr);
 227                 return;
 228         }
 229         gpio_direction_input(gpio_nr);
 230         ret = request_irq(gpio_to_irq(gpio_nr), &omap_serial_wake_interrupt,
 231                           IRQF_TRIGGER_RISING, "serial wakeup", NULL);
 232         if (ret) {
 233                 gpio_free(gpio_nr);
 234                 printk(KERN_ERR "No interrupt for UART wake GPIO: %i\n",
 235                        gpio_nr);
 236                 return;
 237         }
 238         enable_irq_wake(gpio_to_irq(gpio_nr));
 239 }
 240
 241 static int __init omap_serial_wakeup_init(void)
 242 {
 243         if (!cpu_is_omap16xx())
 244                 return 0;
 245
 246         if (uart1_ck != NULL)
 247                 omap_serial_set_port_wakeup(37);
 248         if (uart2_ck != NULL)
 249                 omap_serial_set_port_wakeup(18);
 250         if (uart3_ck != NULL)
 251                 omap_serial_set_port_wakeup(49);
 252
 253         return 0;
 254 }
 255 late_initcall(omap_serial_wakeup_init);
 256
 257 #endif  /* CONFIG_OMAP_SERIAL_WAKE */
 258
 259 static int __init omap_init(void)
 260 {
 261         if (!cpu_class_is_omap1())
 262                 return -ENODEV;
 263
 264         return platform_device_register(&serial_device);
 265 }
 266 arch_initcall(omap_init);