?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
crypto: updates to enable omap aes
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / mach-omap2 / devices.c
blob072893a7d1362901130ea9be2d25323649875970
1 /*
2 * linux/arch/arm/mach-omap2/devices.c
3 *
4 * OMAP2 platform device setup/initialization
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/io.h>
17 #include <linux/clk.h>
18
19 #include <mach/hardware.h>
20 #include <mach/irqs.h>
21 #include <asm/mach-types.h>
22 #include <asm/mach/map.h>
23 #include <asm/pmu.h>
24
25 #include <plat/control.h>
26 #include <plat/tc.h>
27 #include <plat/board.h>
28 #include <plat/mux.h>
29 #include <mach/gpio.h>
30 #include <plat/mmc.h>
31 #include <plat/dma.h>
32
33 #include "mux.h"
34
35 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
36
37 static struct resource cam_resources[] = {
38 {
39 .start = OMAP24XX_CAMERA_BASE,
40 .end = OMAP24XX_CAMERA_BASE + 0xfff,
41 .flags = IORESOURCE_MEM,
42 },
43 {
44 .start = INT_24XX_CAM_IRQ,
45 .flags = IORESOURCE_IRQ,
46 }
47 };
48
49 static struct platform_device omap_cam_device = {
50 .name = "omap24xxcam",
51 .id = -1,
52 .num_resources = ARRAY_SIZE(cam_resources),
53 .resource = cam_resources,
54 };
55
56 static inline void omap_init_camera(void)
57 {
58 platform_device_register(&omap_cam_device);
59 }
60
61 #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
62
63 static struct resource omap3isp_resources[] = {
64 {
65 .start = OMAP3430_ISP_BASE,
66 .end = OMAP3430_ISP_END,
67 .flags = IORESOURCE_MEM,
68 },
69 {
70 .start = OMAP3430_ISP_CBUFF_BASE,
71 .end = OMAP3430_ISP_CBUFF_END,
72 .flags = IORESOURCE_MEM,
73 },
74 {
75 .start = OMAP3430_ISP_CCP2_BASE,
76 .end = OMAP3430_ISP_CCP2_END,
77 .flags = IORESOURCE_MEM,
78 },
79 {
80 .start = OMAP3430_ISP_CCDC_BASE,
81 .end = OMAP3430_ISP_CCDC_END,
82 .flags = IORESOURCE_MEM,
83 },
84 {
85 .start = OMAP3430_ISP_HIST_BASE,
86 .end = OMAP3430_ISP_HIST_END,
87 .flags = IORESOURCE_MEM,
88 },
89 {
90 .start = OMAP3430_ISP_H3A_BASE,
91 .end = OMAP3430_ISP_H3A_END,
92 .flags = IORESOURCE_MEM,
93 },
94 {
95 .start = OMAP3430_ISP_PREV_BASE,
96 .end = OMAP3430_ISP_PREV_END,
97 .flags = IORESOURCE_MEM,
98 },
99 {
100 .start = OMAP3430_ISP_RESZ_BASE,
101 .end = OMAP3430_ISP_RESZ_END,
102 .flags = IORESOURCE_MEM,
103 },
104 {
105 .start = OMAP3430_ISP_SBL_BASE,
106 .end = OMAP3430_ISP_SBL_END,
107 .flags = IORESOURCE_MEM,
108 },
109 {
110 .start = OMAP3430_ISP_CSI2A_BASE,
111 .end = OMAP3430_ISP_CSI2A_END,
112 .flags = IORESOURCE_MEM,
113 },
114 {
115 .start = OMAP3430_ISP_CSI2PHY_BASE,
116 .end = OMAP3430_ISP_CSI2PHY_END,
117 .flags = IORESOURCE_MEM,
118 },
119 {
120 .start = INT_34XX_CAM_IRQ,
121 .flags = IORESOURCE_IRQ,
122 }
123 };
124
125 static struct platform_device omap3isp_device = {
126 .name = "omap3isp",
127 .id = -1,
128 .num_resources = ARRAY_SIZE(omap3isp_resources),
129 .resource = omap3isp_resources,
130 };
131
132 static inline void omap_init_camera(void)
133 {
134 platform_device_register(&omap3isp_device);
135 }
136 #else
137 static inline void omap_init_camera(void)
138 {
139 }
140 #endif
141
142 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
143
144 #define MBOX_REG_SIZE 0x120
145
146 #ifdef CONFIG_ARCH_OMAP2
147 static struct resource omap2_mbox_resources[] = {
148 {
149 .start = OMAP24XX_MAILBOX_BASE,
150 .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
151 .flags = IORESOURCE_MEM,
152 },
153 {
154 .start = INT_24XX_MAIL_U0_MPU,
155 .flags = IORESOURCE_IRQ,
156 },
157 {
158 .start = INT_24XX_MAIL_U3_MPU,
159 .flags = IORESOURCE_IRQ,
160 },
161 };
162 static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
163 #else
164 #define omap2_mbox_resources NULL
165 #define omap2_mbox_resources_sz 0
166 #endif
167
168 #ifdef CONFIG_ARCH_OMAP3
169 static struct resource omap3_mbox_resources[] = {
170 {
171 .start = OMAP34XX_MAILBOX_BASE,
172 .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
173 .flags = IORESOURCE_MEM,
174 },
175 {
176 .start = INT_24XX_MAIL_U0_MPU,
177 .flags = IORESOURCE_IRQ,
178 },
179 };
180 static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
181 #else
182 #define omap3_mbox_resources NULL
183 #define omap3_mbox_resources_sz 0
184 #endif
185
186 #ifdef CONFIG_ARCH_OMAP4
187
188 #define OMAP4_MBOX_REG_SIZE 0x130
189 static struct resource omap4_mbox_resources[] = {
190 {
191 .start = OMAP44XX_MAILBOX_BASE,
192 .end = OMAP44XX_MAILBOX_BASE +
193 OMAP4_MBOX_REG_SIZE - 1,
194 .flags = IORESOURCE_MEM,
195 },
196 {
197 .start = OMAP44XX_IRQ_MAIL_U0,
198 .flags = IORESOURCE_IRQ,
199 },
200 };
201 static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
202 #else
203 #define omap4_mbox_resources NULL
204 #define omap4_mbox_resources_sz 0
205 #endif
206
207 static struct platform_device mbox_device = {
208 .name = "omap2-mailbox",
209 .id = -1,
210 };
211
212 static inline void omap_init_mbox(void)
213 {
214 if (cpu_is_omap24xx()) {
215 mbox_device.resource = omap2_mbox_resources;
216 mbox_device.num_resources = omap2_mbox_resources_sz;
217 } else if (cpu_is_omap34xx()) {
218 mbox_device.resource = omap3_mbox_resources;
219 mbox_device.num_resources = omap3_mbox_resources_sz;
220 } else if (cpu_is_omap44xx()) {
221 mbox_device.resource = omap4_mbox_resources;
222 mbox_device.num_resources = omap4_mbox_resources_sz;
223 } else {
224 pr_err("%s: platform not supported\n", __func__);
225 return;
226 }
227 platform_device_register(&mbox_device);
228 }
229 #else
230 static inline void omap_init_mbox(void) { }
231 #endif /* CONFIG_OMAP_MBOX_FWK */
232
233 #if defined(CONFIG_OMAP_STI)
234
235 #if defined(CONFIG_ARCH_OMAP2)
236
237 #define OMAP2_STI_BASE 0x48068000
238 #define OMAP2_STI_CHANNEL_BASE 0x54000000
239 #define OMAP2_STI_IRQ 4
240
241 static struct resource sti_resources[] = {
242 {
243 .start = OMAP2_STI_BASE,
244 .end = OMAP2_STI_BASE + 0x7ff,
245 .flags = IORESOURCE_MEM,
246 },
247 {
248 .start = OMAP2_STI_CHANNEL_BASE,
249 .end = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1,
250 .flags = IORESOURCE_MEM,
251 },
252 {
253 .start = OMAP2_STI_IRQ,
254 .flags = IORESOURCE_IRQ,
255 }
256 };
257 #elif defined(CONFIG_ARCH_OMAP3)
258
259 #define OMAP3_SDTI_BASE 0x54500000
260 #define OMAP3_SDTI_CHANNEL_BASE 0x54600000
261
262 static struct resource sti_resources[] = {
263 {
264 .start = OMAP3_SDTI_BASE,
265 .end = OMAP3_SDTI_BASE + 0xFFF,
266 .flags = IORESOURCE_MEM,
267 },
268 {
269 .start = OMAP3_SDTI_CHANNEL_BASE,
270 .end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
271 .flags = IORESOURCE_MEM,
272 }
273 };
274
275 #endif
276
277 static struct platform_device sti_device = {
278 .name = "sti",
279 .id = -1,
280 .num_resources = ARRAY_SIZE(sti_resources),
281 .resource = sti_resources,
282 };
283
284 static inline void omap_init_sti(void)
285 {
286 platform_device_register(&sti_device);
287 }
288 #else
289 static inline void omap_init_sti(void) {}
290 #endif
291
292 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
293
294 #include <plat/mcspi.h>
295
296 #define OMAP2_MCSPI1_BASE 0x48098000
297 #define OMAP2_MCSPI2_BASE 0x4809a000
298 #define OMAP2_MCSPI3_BASE 0x480b8000
299 #define OMAP2_MCSPI4_BASE 0x480ba000
300
301 #define OMAP4_MCSPI1_BASE 0x48098100
302 #define OMAP4_MCSPI2_BASE 0x4809a100
303 #define OMAP4_MCSPI3_BASE 0x480b8100
304 #define OMAP4_MCSPI4_BASE 0x480ba100
305
306 static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
307 .num_cs = 4,
308 };
309
310 static struct resource omap2_mcspi1_resources[] = {
311 {
312 .start = OMAP2_MCSPI1_BASE,
313 .end = OMAP2_MCSPI1_BASE + 0xff,
314 .flags = IORESOURCE_MEM,
315 },
316 };
317
318 static struct platform_device omap2_mcspi1 = {
319 .name = "omap2_mcspi",
320 .id = 1,
321 .num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
322 .resource = omap2_mcspi1_resources,
323 .dev = {
324 .platform_data = &omap2_mcspi1_config,
325 },
326 };
327
328 static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
329 .num_cs = 2,
330 };
331
332 static struct resource omap2_mcspi2_resources[] = {
333 {
334 .start = OMAP2_MCSPI2_BASE,
335 .end = OMAP2_MCSPI2_BASE + 0xff,
336 .flags = IORESOURCE_MEM,
337 },
338 };
339
340 static struct platform_device omap2_mcspi2 = {
341 .name = "omap2_mcspi",
342 .id = 2,
343 .num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
344 .resource = omap2_mcspi2_resources,
345 .dev = {
346 .platform_data = &omap2_mcspi2_config,
347 },
348 };
349
350 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
351 defined(CONFIG_ARCH_OMAP4)
352 static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
353 .num_cs = 2,
354 };
355
356 static struct resource omap2_mcspi3_resources[] = {
357 {
358 .start = OMAP2_MCSPI3_BASE,
359 .end = OMAP2_MCSPI3_BASE + 0xff,
360 .flags = IORESOURCE_MEM,
361 },
362 };
363
364 static struct platform_device omap2_mcspi3 = {
365 .name = "omap2_mcspi",
366 .id = 3,
367 .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
368 .resource = omap2_mcspi3_resources,
369 .dev = {
370 .platform_data = &omap2_mcspi3_config,
371 },
372 };
373 #endif
374
375 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
376 static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
377 .num_cs = 1,
378 };
379
380 static struct resource omap2_mcspi4_resources[] = {
381 {
382 .start = OMAP2_MCSPI4_BASE,
383 .end = OMAP2_MCSPI4_BASE + 0xff,
384 .flags = IORESOURCE_MEM,
385 },
386 };
387
388 static struct platform_device omap2_mcspi4 = {
389 .name = "omap2_mcspi",
390 .id = 4,
391 .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
392 .resource = omap2_mcspi4_resources,
393 .dev = {
394 .platform_data = &omap2_mcspi4_config,
395 },
396 };
397 #endif
398
399 #ifdef CONFIG_ARCH_OMAP4
400 static inline void omap4_mcspi_fixup(void)
401 {
402 omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
403 omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff;
404 omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
405 omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff;
406 omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
407 omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff;
408 omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
409 omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff;
410 }
411 #else
412 static inline void omap4_mcspi_fixup(void)
413 {
414 }
415 #endif
416
417 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
418 defined(CONFIG_ARCH_OMAP4)
419 static inline void omap2_mcspi3_init(void)
420 {
421 platform_device_register(&omap2_mcspi3);
422 }
423 #else
424 static inline void omap2_mcspi3_init(void)
425 {
426 }
427 #endif
428
429 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
430 static inline void omap2_mcspi4_init(void)
431 {
432 platform_device_register(&omap2_mcspi4);
433 }
434 #else
435 static inline void omap2_mcspi4_init(void)
436 {
437 }
438 #endif
439
440 static void omap_init_mcspi(void)
441 {
442 if (cpu_is_omap44xx())
443 omap4_mcspi_fixup();
444
445 platform_device_register(&omap2_mcspi1);
446 platform_device_register(&omap2_mcspi2);
447
448 if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
449 omap2_mcspi3_init();
450
451 if (cpu_is_omap343x() || cpu_is_omap44xx())
452 omap2_mcspi4_init();
453 }
454
455 #else
456 static inline void omap_init_mcspi(void) {}
457 #endif
458
459 static struct resource omap2_pmu_resource = {
460 .start = 3,
461 .end = 3,
462 .flags = IORESOURCE_IRQ,
463 };
464
465 static struct resource omap3_pmu_resource = {
466 .start = INT_34XX_BENCH_MPU_EMUL,
467 .end = INT_34XX_BENCH_MPU_EMUL,
468 .flags = IORESOURCE_IRQ,
469 };
470
471 static struct platform_device omap_pmu_device = {
472 .name = "arm-pmu",
473 .id = ARM_PMU_DEVICE_CPU,
474 .num_resources = 1,
475 };
476
477 static void omap_init_pmu(void)
478 {
479 if (cpu_is_omap24xx())
480 omap_pmu_device.resource = &omap2_pmu_resource;
481 else if (cpu_is_omap34xx())
482 omap_pmu_device.resource = &omap3_pmu_resource;
483 else
484 return;
485
486 platform_device_register(&omap_pmu_device);
487 }
488
489
490 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
491
492 #ifdef CONFIG_ARCH_OMAP2
493 static struct resource omap2_sham_resources[] = {
494 {
495 .start = OMAP24XX_SEC_SHA1MD5_BASE,
496 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
497 .flags = IORESOURCE_MEM,
498 },
499 {
500 .start = INT_24XX_SHA1MD5,
501 .flags = IORESOURCE_IRQ,
502 }
503 };
504 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
505 #else
506 #define omap2_sham_resources NULL
507 #define omap2_sham_resources_sz 0
508 #endif
509
510 #ifdef CONFIG_ARCH_OMAP3
511 static struct resource omap3_sham_resources[] = {
512 {
513 .start = OMAP34XX_SEC_SHA1MD5_BASE,
514 .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
515 .flags = IORESOURCE_MEM,
516 },
517 {
518 .start = INT_34XX_SHA1MD52_IRQ,
519 .flags = IORESOURCE_IRQ,
520 },
521 {
522 .start = OMAP34XX_DMA_SHA1MD5_RX,
523 .flags = IORESOURCE_DMA,
524 }
525 };
526 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
527 #else
528 #define omap3_sham_resources NULL
529 #define omap3_sham_resources_sz 0
530 #endif
531
532 static struct platform_device sham_device = {
533 .name = "omap-sham",
534 .id = -1,
535 };
536
537 static void omap_init_sham(void)
538 {
539 if (cpu_is_omap24xx()) {
540 sham_device.resource = omap2_sham_resources;
541 sham_device.num_resources = omap2_sham_resources_sz;
542 } else if (cpu_is_omap34xx()) {
543 sham_device.resource = omap3_sham_resources;
544 sham_device.num_resources = omap3_sham_resources_sz;
545 } else {
546 pr_err("%s: platform not supported\n", __func__);
547 return;
548 }
549 platform_device_register(&sham_device);
550 }
551 #else
552 static inline void omap_init_sham(void) { }
553 #endif
554
555 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
556
557 #ifdef CONFIG_ARCH_OMAP24XX
558 static struct resource omap2_aes_resources[] = {
559 {
560 .start = OMAP24XX_SEC_AES_BASE,
561 .end = OMAP24XX_SEC_AES_BASE + 0x4C,
562 .flags = IORESOURCE_MEM,
563 },
564 {
565 .start = OMAP24XX_DMA_AES_TX,
566 .flags = IORESOURCE_DMA,
567 },
568 {
569 .start = OMAP24XX_DMA_AES_RX,
570 .flags = IORESOURCE_DMA,
571 }
572 };
573 static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
574 #else
575 #define omap2_aes_resources NULL
576 #define omap2_aes_resources_sz 0
577 #endif
578
579 #ifdef CONFIG_ARCH_OMAP34XX
580 static struct resource omap3_aes_resources[] = {
581 {
582 .start = OMAP34XX_SEC_AES_BASE,
583 .end = OMAP34XX_SEC_AES_BASE + 0x4C,
584 .flags = IORESOURCE_MEM,
585 },
586 {
587 .start = OMAP34XX_DMA_AES2_TX,
588 .flags = IORESOURCE_DMA,
589 },
590 {
591 .start = OMAP34XX_DMA_AES2_RX,
592 .flags = IORESOURCE_DMA,
593 }
594 };
595 static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
596 #else
597 #define omap3_aes_resources NULL
598 #define omap3_aes_resources_sz 0
599 #endif
600
601 static struct platform_device aes_device = {
602 .name = "omap-aes",
603 .id = -1,
604 };
605
606 static void omap_init_aes(void)
607 {
608 if (cpu_is_omap24xx()) {
609 aes_device.resource = omap2_aes_resources;
610 aes_device.num_resources = omap2_aes_resources_sz;
611 } else if (cpu_is_omap34xx()) {
612 aes_device.resource = omap3_aes_resources;
613 aes_device.num_resources = omap3_aes_resources_sz;
614 } else {
615 pr_err("%s: platform not supported\n", __func__);
616 return;
617 }
618 platform_device_register(&aes_device);
619 }
620
621 #else
622 static inline void omap_init_aes(void) { }
623 #endif
624
625 /*-------------------------------------------------------------------------*/
626
627 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
628
629 #define MMCHS_SYSCONFIG 0x0010
630 #define MMCHS_SYSCONFIG_SWRESET (1 << 1)
631 #define MMCHS_SYSSTATUS 0x0014
632 #define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
633
634 static struct platform_device dummy_pdev = {
635 .dev = {
636 .bus = &platform_bus_type,
637 },
638 };
639
640 /**
641 * omap_hsmmc_reset() - Full reset of each HS-MMC controller
642 *
643 * Ensure that each MMC controller is fully reset. Controllers
644 * left in an unknown state (by bootloader) may prevent retention
645 * or OFF-mode. This is especially important in cases where the
646 * MMC driver is not enabled, _or_ built as a module.
647 *
648 * In order for reset to work, interface, functional and debounce
649 * clocks must be enabled. The debounce clock comes from func_32k_clk
650 * and is not under SW control, so we only enable i- and f-clocks.
651 **/
652 static void __init omap_hsmmc_reset(void)
653 {
654 u32 i, nr_controllers;
655
656 if (cpu_is_omap242x())
657 return;
658
659 nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
660 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
661
662 for (i = 0; i < nr_controllers; i++) {
663 u32 v, base = 0;
664 struct clk *iclk, *fclk;
665 struct device *dev = &dummy_pdev.dev;
666
667 switch (i) {
668 case 0:
669 base = OMAP2_MMC1_BASE;
670 break;
671 case 1:
672 base = OMAP2_MMC2_BASE;
673 break;
674 case 2:
675 base = OMAP3_MMC3_BASE;
676 break;
677 case 3:
678 if (!cpu_is_omap44xx())
679 return;
680 base = OMAP4_MMC4_BASE;
681 break;
682 case 4:
683 if (!cpu_is_omap44xx())
684 return;
685 base = OMAP4_MMC5_BASE;
686 break;
687 }
688
689 if (cpu_is_omap44xx())
690 base += OMAP4_MMC_REG_OFFSET;
691
692 dummy_pdev.id = i;
693 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
694 iclk = clk_get(dev, "ick");
695 if (iclk && clk_enable(iclk))
696 iclk = NULL;
697
698 fclk = clk_get(dev, "fck");
699 if (fclk && clk_enable(fclk))
700 fclk = NULL;
701
702 if (!iclk || !fclk) {
703 printk(KERN_WARNING
704 "%s: Unable to enable clocks for MMC%d, "
705 "cannot reset.\n", __func__, i);
706 break;
707 }
708
709 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
710 v = omap_readl(base + MMCHS_SYSSTATUS);
711 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
712 MMCHS_SYSSTATUS_RESETDONE))
713 cpu_relax();
714
715 if (fclk) {
716 clk_disable(fclk);
717 clk_put(fclk);
718 }
719 if (iclk) {
720 clk_disable(iclk);
721 clk_put(iclk);
722 }
723 }
724 }
725 #else
726 static inline void omap_hsmmc_reset(void) {}
727 #endif
728
729 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
730 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
731
732 static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
733 int controller_nr)
734 {
735 if ((mmc_controller->slots[0].switch_pin > 0) && \
736 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
737 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
738 OMAP_PIN_INPUT_PULLUP);
739 if ((mmc_controller->slots[0].gpio_wp > 0) && \
740 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
741 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
742 OMAP_PIN_INPUT_PULLUP);
743
744 if (cpu_is_omap2420() && controller_nr == 0) {
745 omap_cfg_reg(H18_24XX_MMC_CMD);
746 omap_cfg_reg(H15_24XX_MMC_CLKI);
747 omap_cfg_reg(G19_24XX_MMC_CLKO);
748 omap_cfg_reg(F20_24XX_MMC_DAT0);
749 omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
750 omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
751 if (mmc_controller->slots[0].wires == 4) {
752 omap_cfg_reg(H14_24XX_MMC_DAT1);
753 omap_cfg_reg(E19_24XX_MMC_DAT2);
754 omap_cfg_reg(D19_24XX_MMC_DAT3);
755 omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
756 omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
757 omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
758 }
759
760 /*
761 * Use internal loop-back in MMC/SDIO Module Input Clock
762 * selection
763 */
764 if (mmc_controller->slots[0].internal_clock) {
765 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
766 v |= (1 << 24);
767 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
768 }
769 }
770
771 if (cpu_is_omap34xx()) {
772 if (controller_nr == 0) {
773 omap_mux_init_signal("sdmmc1_clk",
774 OMAP_PIN_INPUT_PULLUP);
775 omap_mux_init_signal("sdmmc1_cmd",
776 OMAP_PIN_INPUT_PULLUP);
777 omap_mux_init_signal("sdmmc1_dat0",
778 OMAP_PIN_INPUT_PULLUP);
779 if (mmc_controller->slots[0].wires == 4 ||
780 mmc_controller->slots[0].wires == 8) {
781 omap_mux_init_signal("sdmmc1_dat1",
782 OMAP_PIN_INPUT_PULLUP);
783 omap_mux_init_signal("sdmmc1_dat2",
784 OMAP_PIN_INPUT_PULLUP);
785 omap_mux_init_signal("sdmmc1_dat3",
786 OMAP_PIN_INPUT_PULLUP);
787 }
788 if (mmc_controller->slots[0].wires == 8) {
789 omap_mux_init_signal("sdmmc1_dat4",
790 OMAP_PIN_INPUT_PULLUP);
791 omap_mux_init_signal("sdmmc1_dat5",
792 OMAP_PIN_INPUT_PULLUP);
793 omap_mux_init_signal("sdmmc1_dat6",
794 OMAP_PIN_INPUT_PULLUP);
795 omap_mux_init_signal("sdmmc1_dat7",
796 OMAP_PIN_INPUT_PULLUP);
797 }
798 }
799 if (controller_nr == 1) {
800 /* MMC2 */
801 omap_mux_init_signal("sdmmc2_clk",
802 OMAP_PIN_INPUT_PULLUP);
803 omap_mux_init_signal("sdmmc2_cmd",
804 OMAP_PIN_INPUT_PULLUP);
805 omap_mux_init_signal("sdmmc2_dat0",
806 OMAP_PIN_INPUT_PULLUP);
807
808 /*
809 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
810 * in the board-*.c files
811 */
812 if (mmc_controller->slots[0].wires == 4 ||
813 mmc_controller->slots[0].wires == 8) {
814 omap_mux_init_signal("sdmmc2_dat1",
815 OMAP_PIN_INPUT_PULLUP);
816 omap_mux_init_signal("sdmmc2_dat2",
817 OMAP_PIN_INPUT_PULLUP);
818 omap_mux_init_signal("sdmmc2_dat3",
819 OMAP_PIN_INPUT_PULLUP);
820 }
821 if (mmc_controller->slots[0].wires == 8) {
822 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
823 OMAP_PIN_INPUT_PULLUP);
824 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
825 OMAP_PIN_INPUT_PULLUP);
826 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
827 OMAP_PIN_INPUT_PULLUP);
828 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
829 OMAP_PIN_INPUT_PULLUP);
830 }
831 }
832
833 /*
834 * For MMC3 the pins need to be muxed in the board-*.c files
835 */
836 }
837 }
838
839 void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
840 int nr_controllers)
841 {
842 int i;
843 char *name;
844
845 for (i = 0; i < nr_controllers; i++) {
846 unsigned long base, size;
847 unsigned int irq = 0;
848
849 if (!mmc_data[i])
850 continue;
851
852 omap2_mmc_mux(mmc_data[i], i);
853
854 switch (i) {
855 case 0:
856 base = OMAP2_MMC1_BASE;
857 irq = INT_24XX_MMC_IRQ;
858 break;
859 case 1:
860 base = OMAP2_MMC2_BASE;
861 irq = INT_24XX_MMC2_IRQ;
862 break;
863 case 2:
864 if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
865 return;
866 base = OMAP3_MMC3_BASE;
867 irq = INT_34XX_MMC3_IRQ;
868 break;
869 case 3:
870 if (!cpu_is_omap44xx())
871 return;
872 base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
873 irq = OMAP44XX_IRQ_MMC4;
874 break;
875 case 4:
876 if (!cpu_is_omap44xx())
877 return;
878 base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
879 irq = OMAP44XX_IRQ_MMC5;
880 break;
881 default:
882 continue;
883 }
884
885 if (cpu_is_omap2420()) {
886 size = OMAP2420_MMC_SIZE;
887 name = "mmci-omap";
888 } else if (cpu_is_omap44xx()) {
889 if (i < 3) {
890 base += OMAP4_MMC_REG_OFFSET;
891 irq += OMAP44XX_IRQ_GIC_START;
892 }
893 size = OMAP4_HSMMC_SIZE;
894 name = "mmci-omap-hs";
895 } else {
896 size = OMAP3_HSMMC_SIZE;
897 name = "mmci-omap-hs";
898 }
899 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
900 };
901 }
902
903 #endif
904
905 /*-------------------------------------------------------------------------*/
906
907 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
908 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
909 #define OMAP_HDQ_BASE 0x480B2000
910 #endif
911 static struct resource omap_hdq_resources[] = {
912 {
913 .start = OMAP_HDQ_BASE,
914 .end = OMAP_HDQ_BASE + 0x1C,
915 .flags = IORESOURCE_MEM,
916 },
917 {
918 .start = INT_24XX_HDQ_IRQ,
919 .flags = IORESOURCE_IRQ,
920 },
921 };
922 static struct platform_device omap_hdq_dev = {
923 .name = "omap_hdq",
924 .id = 0,
925 .dev = {
926 .platform_data = NULL,
927 },
928 .num_resources = ARRAY_SIZE(omap_hdq_resources),
929 .resource = omap_hdq_resources,
930 };
931 static inline void omap_hdq_init(void)
932 {
933 (void) platform_device_register(&omap_hdq_dev);
934 }
935 #else
936 static inline void omap_hdq_init(void) {}
937 #endif
938
939 /*---------------------------------------------------------------------------*/
940
941 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
942 defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
943 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
944 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
945 };
946 #else
947 static struct resource omap_vout_resource[2] = {
948 };
949 #endif
950
951 static struct platform_device omap_vout_device = {
952 .name = "omap_vout",
953 .num_resources = ARRAY_SIZE(omap_vout_resource),
954 .resource = &omap_vout_resource[0],
955 .id = -1,
956 };
957 static void omap_init_vout(void)
958 {
959 if (platform_device_register(&omap_vout_device) < 0)
960 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
961 }
962 #else
963 static inline void omap_init_vout(void) {}
964 #endif
965
966 /*-------------------------------------------------------------------------*/
967
968 static int __init omap2_init_devices(void)
969 {
970 /* please keep these calls, and their implementations above,
971 * in alphabetical order so they're easier to sort through.
972 */
973 omap_hsmmc_reset();
974 omap_init_camera();
975 omap_init_mbox();
976 omap_init_mcspi();
977 omap_init_pmu();
978 omap_hdq_init();
979 omap_init_sti();
980 omap_init_sham();
981 omap_init_aes();
982 omap_init_vout();
983
984 return 0;
985 }
986 arch_initcall(omap2_init_devices);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree