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ALSA: hda - Add quirk for Dell Vostro 1220
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / tg3.c
blobecc41cffb470d3d16b97e5fe61768f57c4822d65
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
44
45 #include <net/checksum.h>
46 #include <net/ip.h>
47
48 #include <asm/system.h>
49 #include <asm/io.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
52
53 #ifdef CONFIG_SPARC
54 #include <asm/idprom.h>
55 #include <asm/prom.h>
56 #endif
57
58 #define BAR_0 0
59 #define BAR_2 2
60
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
63 #else
64 #define TG3_VLAN_TAG_USED 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME "tg3"
70 #define DRV_MODULE_VERSION "3.108"
71 #define DRV_MODULE_RELDATE "February 17, 2010"
72
73 #define TG3_DEF_MAC_MODE 0
74 #define TG3_DEF_RX_MODE 0
75 #define TG3_DEF_TX_MODE 0
76 #define TG3_DEF_MSG_ENABLE \
77 (NETIF_MSG_DRV | \
78 NETIF_MSG_PROBE | \
79 NETIF_MSG_LINK | \
80 NETIF_MSG_TIMER | \
81 NETIF_MSG_IFDOWN | \
82 NETIF_MSG_IFUP | \
83 NETIF_MSG_RX_ERR | \
84 NETIF_MSG_TX_ERR)
85
86 /* length of time before we decide the hardware is borked,
87 * and dev->tx_timeout() should be called to fix the problem
88 */
89 #define TG3_TX_TIMEOUT (5 * HZ)
90
91 /* hardware minimum and maximum for a single frame's data payload */
92 #define TG3_MIN_MTU 60
93 #define TG3_MAX_MTU(tp) \
94 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
95
96 /* These numbers seem to be hard coded in the NIC firmware somehow.
97 * You can't change the ring sizes, but you can change where you place
98 * them in the NIC onboard memory.
99 */
100 #define TG3_RX_RING_SIZE 512
101 #define TG3_DEF_RX_RING_PENDING 200
102 #define TG3_RX_JUMBO_RING_SIZE 256
103 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
104 #define TG3_RSS_INDIR_TBL_SIZE 128
105
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
114 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
115
116 #define TG3_TX_RING_SIZE 512
117 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
118
119 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120 TG3_RX_RING_SIZE)
121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
122 TG3_RX_JUMBO_RING_SIZE)
123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
124 TG3_RX_RCB_RING_SIZE(tp))
125 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
126 TG3_TX_RING_SIZE)
127 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128
129 #define TG3_DMA_BYTE_ENAB 64
130
131 #define TG3_RX_STD_DMA_SZ 1536
132 #define TG3_RX_JMB_DMA_SZ 9046
133
134 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
135
136 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
137 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
138
139 #define TG3_RX_STD_BUFF_RING_SIZE \
140 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
141
142 #define TG3_RX_JMB_BUFF_RING_SIZE \
143 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
144
145 /* minimum number of free TX descriptors required to wake up TX process */
146 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
147
148 #define TG3_RAW_IP_ALIGN 2
149
150 /* number of ETHTOOL_GSTATS u64's */
151 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
152
153 #define TG3_NUM_TEST 6
154
155 #define FIRMWARE_TG3 "tigon/tg3.bin"
156 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
157 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
158
159 static char version[] __devinitdata =
160 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
161
162 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
163 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
164 MODULE_LICENSE("GPL");
165 MODULE_VERSION(DRV_MODULE_VERSION);
166 MODULE_FIRMWARE(FIRMWARE_TG3);
167 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
168 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
169
170 #define TG3_RSS_MIN_NUM_MSIX_VECS 2
171
172 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
173 module_param(tg3_debug, int, 0);
174 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
175
176 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
252 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
253 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
254 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
255 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
256 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
257 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
258 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
259 {}
260 };
261
262 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
263
264 static const struct {
265 const char string[ETH_GSTRING_LEN];
266 } ethtool_stats_keys[TG3_NUM_STATS] = {
267 { "rx_octets" },
268 { "rx_fragments" },
269 { "rx_ucast_packets" },
270 { "rx_mcast_packets" },
271 { "rx_bcast_packets" },
272 { "rx_fcs_errors" },
273 { "rx_align_errors" },
274 { "rx_xon_pause_rcvd" },
275 { "rx_xoff_pause_rcvd" },
276 { "rx_mac_ctrl_rcvd" },
277 { "rx_xoff_entered" },
278 { "rx_frame_too_long_errors" },
279 { "rx_jabbers" },
280 { "rx_undersize_packets" },
281 { "rx_in_length_errors" },
282 { "rx_out_length_errors" },
283 { "rx_64_or_less_octet_packets" },
284 { "rx_65_to_127_octet_packets" },
285 { "rx_128_to_255_octet_packets" },
286 { "rx_256_to_511_octet_packets" },
287 { "rx_512_to_1023_octet_packets" },
288 { "rx_1024_to_1522_octet_packets" },
289 { "rx_1523_to_2047_octet_packets" },
290 { "rx_2048_to_4095_octet_packets" },
291 { "rx_4096_to_8191_octet_packets" },
292 { "rx_8192_to_9022_octet_packets" },
293
294 { "tx_octets" },
295 { "tx_collisions" },
296
297 { "tx_xon_sent" },
298 { "tx_xoff_sent" },
299 { "tx_flow_control" },
300 { "tx_mac_errors" },
301 { "tx_single_collisions" },
302 { "tx_mult_collisions" },
303 { "tx_deferred" },
304 { "tx_excessive_collisions" },
305 { "tx_late_collisions" },
306 { "tx_collide_2times" },
307 { "tx_collide_3times" },
308 { "tx_collide_4times" },
309 { "tx_collide_5times" },
310 { "tx_collide_6times" },
311 { "tx_collide_7times" },
312 { "tx_collide_8times" },
313 { "tx_collide_9times" },
314 { "tx_collide_10times" },
315 { "tx_collide_11times" },
316 { "tx_collide_12times" },
317 { "tx_collide_13times" },
318 { "tx_collide_14times" },
319 { "tx_collide_15times" },
320 { "tx_ucast_packets" },
321 { "tx_mcast_packets" },
322 { "tx_bcast_packets" },
323 { "tx_carrier_sense_errors" },
324 { "tx_discards" },
325 { "tx_errors" },
326
327 { "dma_writeq_full" },
328 { "dma_write_prioq_full" },
329 { "rxbds_empty" },
330 { "rx_discards" },
331 { "rx_errors" },
332 { "rx_threshold_hit" },
333
334 { "dma_readq_full" },
335 { "dma_read_prioq_full" },
336 { "tx_comp_queue_full" },
337
338 { "ring_set_send_prod_index" },
339 { "ring_status_update" },
340 { "nic_irqs" },
341 { "nic_avoided_irqs" },
342 { "nic_tx_threshold_hit" }
343 };
344
345 static const struct {
346 const char string[ETH_GSTRING_LEN];
347 } ethtool_test_keys[TG3_NUM_TEST] = {
348 { "nvram test (online) " },
349 { "link test (online) " },
350 { "register test (offline)" },
351 { "memory test (offline)" },
352 { "loopback test (offline)" },
353 { "interrupt test (offline)" },
354 };
355
356 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
357 {
358 writel(val, tp->regs + off);
359 }
360
361 static u32 tg3_read32(struct tg3 *tp, u32 off)
362 {
363 return (readl(tp->regs + off));
364 }
365
366 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
367 {
368 writel(val, tp->aperegs + off);
369 }
370
371 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
372 {
373 return (readl(tp->aperegs + off));
374 }
375
376 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
377 {
378 unsigned long flags;
379
380 spin_lock_irqsave(&tp->indirect_lock, flags);
381 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
382 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
383 spin_unlock_irqrestore(&tp->indirect_lock, flags);
384 }
385
386 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
387 {
388 writel(val, tp->regs + off);
389 readl(tp->regs + off);
390 }
391
392 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
393 {
394 unsigned long flags;
395 u32 val;
396
397 spin_lock_irqsave(&tp->indirect_lock, flags);
398 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
399 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
400 spin_unlock_irqrestore(&tp->indirect_lock, flags);
401 return val;
402 }
403
404 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
405 {
406 unsigned long flags;
407
408 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
409 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
410 TG3_64BIT_REG_LOW, val);
411 return;
412 }
413 if (off == TG3_RX_STD_PROD_IDX_REG) {
414 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
415 TG3_64BIT_REG_LOW, val);
416 return;
417 }
418
419 spin_lock_irqsave(&tp->indirect_lock, flags);
420 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
421 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
422 spin_unlock_irqrestore(&tp->indirect_lock, flags);
423
424 /* In indirect mode when disabling interrupts, we also need
425 * to clear the interrupt bit in the GRC local ctrl register.
426 */
427 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
428 (val == 0x1)) {
429 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
430 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
431 }
432 }
433
434 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
435 {
436 unsigned long flags;
437 u32 val;
438
439 spin_lock_irqsave(&tp->indirect_lock, flags);
440 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
441 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
442 spin_unlock_irqrestore(&tp->indirect_lock, flags);
443 return val;
444 }
445
446 /* usec_wait specifies the wait time in usec when writing to certain registers
447 * where it is unsafe to read back the register without some delay.
448 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
449 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
450 */
451 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
452 {
453 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
454 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
455 /* Non-posted methods */
456 tp->write32(tp, off, val);
457 else {
458 /* Posted method */
459 tg3_write32(tp, off, val);
460 if (usec_wait)
461 udelay(usec_wait);
462 tp->read32(tp, off);
463 }
464 /* Wait again after the read for the posted method to guarantee that
465 * the wait time is met.
466 */
467 if (usec_wait)
468 udelay(usec_wait);
469 }
470
471 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
472 {
473 tp->write32_mbox(tp, off, val);
474 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
475 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
476 tp->read32_mbox(tp, off);
477 }
478
479 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
480 {
481 void __iomem *mbox = tp->regs + off;
482 writel(val, mbox);
483 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
484 writel(val, mbox);
485 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
486 readl(mbox);
487 }
488
489 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
490 {
491 return (readl(tp->regs + off + GRCMBOX_BASE));
492 }
493
494 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
495 {
496 writel(val, tp->regs + off + GRCMBOX_BASE);
497 }
498
499 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
500 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
501 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
502 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
503 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
504
505 #define tw32(reg,val) tp->write32(tp, reg, val)
506 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
507 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
508 #define tr32(reg) tp->read32(tp, reg)
509
510 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
511 {
512 unsigned long flags;
513
514 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
515 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
516 return;
517
518 spin_lock_irqsave(&tp->indirect_lock, flags);
519 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
520 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
521 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
522
523 /* Always leave this as zero. */
524 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
525 } else {
526 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
527 tw32_f(TG3PCI_MEM_WIN_DATA, val);
528
529 /* Always leave this as zero. */
530 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
531 }
532 spin_unlock_irqrestore(&tp->indirect_lock, flags);
533 }
534
535 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
536 {
537 unsigned long flags;
538
539 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
540 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
541 *val = 0;
542 return;
543 }
544
545 spin_lock_irqsave(&tp->indirect_lock, flags);
546 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
547 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
548 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
549
550 /* Always leave this as zero. */
551 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
552 } else {
553 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
554 *val = tr32(TG3PCI_MEM_WIN_DATA);
555
556 /* Always leave this as zero. */
557 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
558 }
559 spin_unlock_irqrestore(&tp->indirect_lock, flags);
560 }
561
562 static void tg3_ape_lock_init(struct tg3 *tp)
563 {
564 int i;
565
566 /* Make sure the driver hasn't any stale locks. */
567 for (i = 0; i < 8; i++)
568 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
569 APE_LOCK_GRANT_DRIVER);
570 }
571
572 static int tg3_ape_lock(struct tg3 *tp, int locknum)
573 {
574 int i, off;
575 int ret = 0;
576 u32 status;
577
578 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
579 return 0;
580
581 switch (locknum) {
582 case TG3_APE_LOCK_GRC:
583 case TG3_APE_LOCK_MEM:
584 break;
585 default:
586 return -EINVAL;
587 }
588
589 off = 4 * locknum;
590
591 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
592
593 /* Wait for up to 1 millisecond to acquire lock. */
594 for (i = 0; i < 100; i++) {
595 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
596 if (status == APE_LOCK_GRANT_DRIVER)
597 break;
598 udelay(10);
599 }
600
601 if (status != APE_LOCK_GRANT_DRIVER) {
602 /* Revoke the lock request. */
603 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
604 APE_LOCK_GRANT_DRIVER);
605
606 ret = -EBUSY;
607 }
608
609 return ret;
610 }
611
612 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
613 {
614 int off;
615
616 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
617 return;
618
619 switch (locknum) {
620 case TG3_APE_LOCK_GRC:
621 case TG3_APE_LOCK_MEM:
622 break;
623 default:
624 return;
625 }
626
627 off = 4 * locknum;
628 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
629 }
630
631 static void tg3_disable_ints(struct tg3 *tp)
632 {
633 int i;
634
635 tw32(TG3PCI_MISC_HOST_CTRL,
636 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
637 for (i = 0; i < tp->irq_max; i++)
638 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
639 }
640
641 static void tg3_enable_ints(struct tg3 *tp)
642 {
643 int i;
644
645 tp->irq_sync = 0;
646 wmb();
647
648 tw32(TG3PCI_MISC_HOST_CTRL,
649 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
650
651 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
652 for (i = 0; i < tp->irq_cnt; i++) {
653 struct tg3_napi *tnapi = &tp->napi[i];
654 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
655 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
656 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
657
658 tp->coal_now |= tnapi->coal_now;
659 }
660
661 /* Force an initial interrupt */
662 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
663 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
664 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
665 else
666 tw32(HOSTCC_MODE, tp->coal_now);
667
668 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
669 }
670
671 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
672 {
673 struct tg3 *tp = tnapi->tp;
674 struct tg3_hw_status *sblk = tnapi->hw_status;
675 unsigned int work_exists = 0;
676
677 /* check for phy events */
678 if (!(tp->tg3_flags &
679 (TG3_FLAG_USE_LINKCHG_REG |
680 TG3_FLAG_POLL_SERDES))) {
681 if (sblk->status & SD_STATUS_LINK_CHG)
682 work_exists = 1;
683 }
684 /* check for RX/TX work to do */
685 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
686 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
687 work_exists = 1;
688
689 return work_exists;
690 }
691
692 /* tg3_int_reenable
693 * similar to tg3_enable_ints, but it accurately determines whether there
694 * is new work pending and can return without flushing the PIO write
695 * which reenables interrupts
696 */
697 static void tg3_int_reenable(struct tg3_napi *tnapi)
698 {
699 struct tg3 *tp = tnapi->tp;
700
701 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
702 mmiowb();
703
704 /* When doing tagged status, this work check is unnecessary.
705 * The last_tag we write above tells the chip which piece of
706 * work we've completed.
707 */
708 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
709 tg3_has_work(tnapi))
710 tw32(HOSTCC_MODE, tp->coalesce_mode |
711 HOSTCC_MODE_ENABLE | tnapi->coal_now);
712 }
713
714 static void tg3_napi_disable(struct tg3 *tp)
715 {
716 int i;
717
718 for (i = tp->irq_cnt - 1; i >= 0; i--)
719 napi_disable(&tp->napi[i].napi);
720 }
721
722 static void tg3_napi_enable(struct tg3 *tp)
723 {
724 int i;
725
726 for (i = 0; i < tp->irq_cnt; i++)
727 napi_enable(&tp->napi[i].napi);
728 }
729
730 static inline void tg3_netif_stop(struct tg3 *tp)
731 {
732 tp->dev->trans_start = jiffies; /* prevent tx timeout */
733 tg3_napi_disable(tp);
734 netif_tx_disable(tp->dev);
735 }
736
737 static inline void tg3_netif_start(struct tg3 *tp)
738 {
739 /* NOTE: unconditional netif_tx_wake_all_queues is only
740 * appropriate so long as all callers are assured to
741 * have free tx slots (such as after tg3_init_hw)
742 */
743 netif_tx_wake_all_queues(tp->dev);
744
745 tg3_napi_enable(tp);
746 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
747 tg3_enable_ints(tp);
748 }
749
750 static void tg3_switch_clocks(struct tg3 *tp)
751 {
752 u32 clock_ctrl;
753 u32 orig_clock_ctrl;
754
755 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
756 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
757 return;
758
759 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
760
761 orig_clock_ctrl = clock_ctrl;
762 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
763 CLOCK_CTRL_CLKRUN_OENABLE |
764 0x1f);
765 tp->pci_clock_ctrl = clock_ctrl;
766
767 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
768 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
769 tw32_wait_f(TG3PCI_CLOCK_CTRL,
770 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
771 }
772 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
773 tw32_wait_f(TG3PCI_CLOCK_CTRL,
774 clock_ctrl |
775 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
776 40);
777 tw32_wait_f(TG3PCI_CLOCK_CTRL,
778 clock_ctrl | (CLOCK_CTRL_ALTCLK),
779 40);
780 }
781 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
782 }
783
784 #define PHY_BUSY_LOOPS 5000
785
786 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
787 {
788 u32 frame_val;
789 unsigned int loops;
790 int ret;
791
792 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
793 tw32_f(MAC_MI_MODE,
794 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
795 udelay(80);
796 }
797
798 *val = 0x0;
799
800 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
801 MI_COM_PHY_ADDR_MASK);
802 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
803 MI_COM_REG_ADDR_MASK);
804 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
805
806 tw32_f(MAC_MI_COM, frame_val);
807
808 loops = PHY_BUSY_LOOPS;
809 while (loops != 0) {
810 udelay(10);
811 frame_val = tr32(MAC_MI_COM);
812
813 if ((frame_val & MI_COM_BUSY) == 0) {
814 udelay(5);
815 frame_val = tr32(MAC_MI_COM);
816 break;
817 }
818 loops -= 1;
819 }
820
821 ret = -EBUSY;
822 if (loops != 0) {
823 *val = frame_val & MI_COM_DATA_MASK;
824 ret = 0;
825 }
826
827 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
828 tw32_f(MAC_MI_MODE, tp->mi_mode);
829 udelay(80);
830 }
831
832 return ret;
833 }
834
835 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
836 {
837 u32 frame_val;
838 unsigned int loops;
839 int ret;
840
841 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
842 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
843 return 0;
844
845 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
846 tw32_f(MAC_MI_MODE,
847 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
848 udelay(80);
849 }
850
851 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
852 MI_COM_PHY_ADDR_MASK);
853 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
854 MI_COM_REG_ADDR_MASK);
855 frame_val |= (val & MI_COM_DATA_MASK);
856 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
857
858 tw32_f(MAC_MI_COM, frame_val);
859
860 loops = PHY_BUSY_LOOPS;
861 while (loops != 0) {
862 udelay(10);
863 frame_val = tr32(MAC_MI_COM);
864 if ((frame_val & MI_COM_BUSY) == 0) {
865 udelay(5);
866 frame_val = tr32(MAC_MI_COM);
867 break;
868 }
869 loops -= 1;
870 }
871
872 ret = -EBUSY;
873 if (loops != 0)
874 ret = 0;
875
876 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
877 tw32_f(MAC_MI_MODE, tp->mi_mode);
878 udelay(80);
879 }
880
881 return ret;
882 }
883
884 static int tg3_bmcr_reset(struct tg3 *tp)
885 {
886 u32 phy_control;
887 int limit, err;
888
889 /* OK, reset it, and poll the BMCR_RESET bit until it
890 * clears or we time out.
891 */
892 phy_control = BMCR_RESET;
893 err = tg3_writephy(tp, MII_BMCR, phy_control);
894 if (err != 0)
895 return -EBUSY;
896
897 limit = 5000;
898 while (limit--) {
899 err = tg3_readphy(tp, MII_BMCR, &phy_control);
900 if (err != 0)
901 return -EBUSY;
902
903 if ((phy_control & BMCR_RESET) == 0) {
904 udelay(40);
905 break;
906 }
907 udelay(10);
908 }
909 if (limit < 0)
910 return -EBUSY;
911
912 return 0;
913 }
914
915 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
916 {
917 struct tg3 *tp = bp->priv;
918 u32 val;
919
920 spin_lock_bh(&tp->lock);
921
922 if (tg3_readphy(tp, reg, &val))
923 val = -EIO;
924
925 spin_unlock_bh(&tp->lock);
926
927 return val;
928 }
929
930 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
931 {
932 struct tg3 *tp = bp->priv;
933 u32 ret = 0;
934
935 spin_lock_bh(&tp->lock);
936
937 if (tg3_writephy(tp, reg, val))
938 ret = -EIO;
939
940 spin_unlock_bh(&tp->lock);
941
942 return ret;
943 }
944
945 static int tg3_mdio_reset(struct mii_bus *bp)
946 {
947 return 0;
948 }
949
950 static void tg3_mdio_config_5785(struct tg3 *tp)
951 {
952 u32 val;
953 struct phy_device *phydev;
954
955 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
956 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
957 case PHY_ID_BCM50610:
958 case PHY_ID_BCM50610M:
959 val = MAC_PHYCFG2_50610_LED_MODES;
960 break;
961 case PHY_ID_BCMAC131:
962 val = MAC_PHYCFG2_AC131_LED_MODES;
963 break;
964 case PHY_ID_RTL8211C:
965 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
966 break;
967 case PHY_ID_RTL8201E:
968 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
969 break;
970 default:
971 return;
972 }
973
974 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
975 tw32(MAC_PHYCFG2, val);
976
977 val = tr32(MAC_PHYCFG1);
978 val &= ~(MAC_PHYCFG1_RGMII_INT |
979 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
980 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
981 tw32(MAC_PHYCFG1, val);
982
983 return;
984 }
985
986 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
987 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
988 MAC_PHYCFG2_FMODE_MASK_MASK |
989 MAC_PHYCFG2_GMODE_MASK_MASK |
990 MAC_PHYCFG2_ACT_MASK_MASK |
991 MAC_PHYCFG2_QUAL_MASK_MASK |
992 MAC_PHYCFG2_INBAND_ENABLE;
993
994 tw32(MAC_PHYCFG2, val);
995
996 val = tr32(MAC_PHYCFG1);
997 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
998 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
999 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1000 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1001 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1002 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1003 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1004 }
1005 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1006 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1007 tw32(MAC_PHYCFG1, val);
1008
1009 val = tr32(MAC_EXT_RGMII_MODE);
1010 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1011 MAC_RGMII_MODE_RX_QUALITY |
1012 MAC_RGMII_MODE_RX_ACTIVITY |
1013 MAC_RGMII_MODE_RX_ENG_DET |
1014 MAC_RGMII_MODE_TX_ENABLE |
1015 MAC_RGMII_MODE_TX_LOWPWR |
1016 MAC_RGMII_MODE_TX_RESET);
1017 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1018 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1019 val |= MAC_RGMII_MODE_RX_INT_B |
1020 MAC_RGMII_MODE_RX_QUALITY |
1021 MAC_RGMII_MODE_RX_ACTIVITY |
1022 MAC_RGMII_MODE_RX_ENG_DET;
1023 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1024 val |= MAC_RGMII_MODE_TX_ENABLE |
1025 MAC_RGMII_MODE_TX_LOWPWR |
1026 MAC_RGMII_MODE_TX_RESET;
1027 }
1028 tw32(MAC_EXT_RGMII_MODE, val);
1029 }
1030
1031 static void tg3_mdio_start(struct tg3 *tp)
1032 {
1033 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1034 tw32_f(MAC_MI_MODE, tp->mi_mode);
1035 udelay(80);
1036
1037 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1039 tg3_mdio_config_5785(tp);
1040 }
1041
1042 static int tg3_mdio_init(struct tg3 *tp)
1043 {
1044 int i;
1045 u32 reg;
1046 struct phy_device *phydev;
1047
1048 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1049 u32 funcnum, is_serdes;
1050
1051 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1052 if (funcnum)
1053 tp->phy_addr = 2;
1054 else
1055 tp->phy_addr = 1;
1056
1057 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1058 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1059 else
1060 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1061 TG3_CPMU_PHY_STRAP_IS_SERDES;
1062 if (is_serdes)
1063 tp->phy_addr += 7;
1064 } else
1065 tp->phy_addr = TG3_PHY_MII_ADDR;
1066
1067 tg3_mdio_start(tp);
1068
1069 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1070 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1071 return 0;
1072
1073 tp->mdio_bus = mdiobus_alloc();
1074 if (tp->mdio_bus == NULL)
1075 return -ENOMEM;
1076
1077 tp->mdio_bus->name = "tg3 mdio bus";
1078 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1079 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1080 tp->mdio_bus->priv = tp;
1081 tp->mdio_bus->parent = &tp->pdev->dev;
1082 tp->mdio_bus->read = &tg3_mdio_read;
1083 tp->mdio_bus->write = &tg3_mdio_write;
1084 tp->mdio_bus->reset = &tg3_mdio_reset;
1085 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1086 tp->mdio_bus->irq = &tp->mdio_irq[0];
1087
1088 for (i = 0; i < PHY_MAX_ADDR; i++)
1089 tp->mdio_bus->irq[i] = PHY_POLL;
1090
1091 /* The bus registration will look for all the PHYs on the mdio bus.
1092 * Unfortunately, it does not ensure the PHY is powered up before
1093 * accessing the PHY ID registers. A chip reset is the
1094 * quickest way to bring the device back to an operational state..
1095 */
1096 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1097 tg3_bmcr_reset(tp);
1098
1099 i = mdiobus_register(tp->mdio_bus);
1100 if (i) {
1101 netdev_warn(tp->dev, "mdiobus_reg failed (0x%x)\n", i);
1102 mdiobus_free(tp->mdio_bus);
1103 return i;
1104 }
1105
1106 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1107
1108 if (!phydev || !phydev->drv) {
1109 netdev_warn(tp->dev, "No PHY devices\n");
1110 mdiobus_unregister(tp->mdio_bus);
1111 mdiobus_free(tp->mdio_bus);
1112 return -ENODEV;
1113 }
1114
1115 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1116 case PHY_ID_BCM57780:
1117 phydev->interface = PHY_INTERFACE_MODE_GMII;
1118 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1119 break;
1120 case PHY_ID_BCM50610:
1121 case PHY_ID_BCM50610M:
1122 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1123 PHY_BRCM_RX_REFCLK_UNUSED |
1124 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1125 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1126 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1127 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1128 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1129 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1130 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1131 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1132 /* fallthru */
1133 case PHY_ID_RTL8211C:
1134 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1135 break;
1136 case PHY_ID_RTL8201E:
1137 case PHY_ID_BCMAC131:
1138 phydev->interface = PHY_INTERFACE_MODE_MII;
1139 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1140 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1141 break;
1142 }
1143
1144 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1145
1146 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1147 tg3_mdio_config_5785(tp);
1148
1149 return 0;
1150 }
1151
1152 static void tg3_mdio_fini(struct tg3 *tp)
1153 {
1154 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1155 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1156 mdiobus_unregister(tp->mdio_bus);
1157 mdiobus_free(tp->mdio_bus);
1158 }
1159 }
1160
1161 /* tp->lock is held. */
1162 static inline void tg3_generate_fw_event(struct tg3 *tp)
1163 {
1164 u32 val;
1165
1166 val = tr32(GRC_RX_CPU_EVENT);
1167 val |= GRC_RX_CPU_DRIVER_EVENT;
1168 tw32_f(GRC_RX_CPU_EVENT, val);
1169
1170 tp->last_event_jiffies = jiffies;
1171 }
1172
1173 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1174
1175 /* tp->lock is held. */
1176 static void tg3_wait_for_event_ack(struct tg3 *tp)
1177 {
1178 int i;
1179 unsigned int delay_cnt;
1180 long time_remain;
1181
1182 /* If enough time has passed, no wait is necessary. */
1183 time_remain = (long)(tp->last_event_jiffies + 1 +
1184 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1185 (long)jiffies;
1186 if (time_remain < 0)
1187 return;
1188
1189 /* Check if we can shorten the wait time. */
1190 delay_cnt = jiffies_to_usecs(time_remain);
1191 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1192 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1193 delay_cnt = (delay_cnt >> 3) + 1;
1194
1195 for (i = 0; i < delay_cnt; i++) {
1196 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1197 break;
1198 udelay(8);
1199 }
1200 }
1201
1202 /* tp->lock is held. */
1203 static void tg3_ump_link_report(struct tg3 *tp)
1204 {
1205 u32 reg;
1206 u32 val;
1207
1208 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1209 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1210 return;
1211
1212 tg3_wait_for_event_ack(tp);
1213
1214 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1215
1216 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1217
1218 val = 0;
1219 if (!tg3_readphy(tp, MII_BMCR, &reg))
1220 val = reg << 16;
1221 if (!tg3_readphy(tp, MII_BMSR, &reg))
1222 val |= (reg & 0xffff);
1223 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1224
1225 val = 0;
1226 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1227 val = reg << 16;
1228 if (!tg3_readphy(tp, MII_LPA, &reg))
1229 val |= (reg & 0xffff);
1230 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1231
1232 val = 0;
1233 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1234 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1235 val = reg << 16;
1236 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1237 val |= (reg & 0xffff);
1238 }
1239 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1240
1241 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1242 val = reg << 16;
1243 else
1244 val = 0;
1245 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1246
1247 tg3_generate_fw_event(tp);
1248 }
1249
1250 static void tg3_link_report(struct tg3 *tp)
1251 {
1252 if (!netif_carrier_ok(tp->dev)) {
1253 netif_info(tp, link, tp->dev, "Link is down\n");
1254 tg3_ump_link_report(tp);
1255 } else if (netif_msg_link(tp)) {
1256 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1257 (tp->link_config.active_speed == SPEED_1000 ?
1258 1000 :
1259 (tp->link_config.active_speed == SPEED_100 ?
1260 100 : 10)),
1261 (tp->link_config.active_duplex == DUPLEX_FULL ?
1262 "full" : "half"));
1263
1264 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1265 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1266 "on" : "off",
1267 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1268 "on" : "off");
1269 tg3_ump_link_report(tp);
1270 }
1271 }
1272
1273 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1274 {
1275 u16 miireg;
1276
1277 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1278 miireg = ADVERTISE_PAUSE_CAP;
1279 else if (flow_ctrl & FLOW_CTRL_TX)
1280 miireg = ADVERTISE_PAUSE_ASYM;
1281 else if (flow_ctrl & FLOW_CTRL_RX)
1282 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1283 else
1284 miireg = 0;
1285
1286 return miireg;
1287 }
1288
1289 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1290 {
1291 u16 miireg;
1292
1293 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1294 miireg = ADVERTISE_1000XPAUSE;
1295 else if (flow_ctrl & FLOW_CTRL_TX)
1296 miireg = ADVERTISE_1000XPSE_ASYM;
1297 else if (flow_ctrl & FLOW_CTRL_RX)
1298 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1299 else
1300 miireg = 0;
1301
1302 return miireg;
1303 }
1304
1305 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1306 {
1307 u8 cap = 0;
1308
1309 if (lcladv & ADVERTISE_1000XPAUSE) {
1310 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1311 if (rmtadv & LPA_1000XPAUSE)
1312 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1313 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1314 cap = FLOW_CTRL_RX;
1315 } else {
1316 if (rmtadv & LPA_1000XPAUSE)
1317 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1318 }
1319 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1320 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1321 cap = FLOW_CTRL_TX;
1322 }
1323
1324 return cap;
1325 }
1326
1327 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1328 {
1329 u8 autoneg;
1330 u8 flowctrl = 0;
1331 u32 old_rx_mode = tp->rx_mode;
1332 u32 old_tx_mode = tp->tx_mode;
1333
1334 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1335 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1336 else
1337 autoneg = tp->link_config.autoneg;
1338
1339 if (autoneg == AUTONEG_ENABLE &&
1340 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1341 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1342 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1343 else
1344 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1345 } else
1346 flowctrl = tp->link_config.flowctrl;
1347
1348 tp->link_config.active_flowctrl = flowctrl;
1349
1350 if (flowctrl & FLOW_CTRL_RX)
1351 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1352 else
1353 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1354
1355 if (old_rx_mode != tp->rx_mode)
1356 tw32_f(MAC_RX_MODE, tp->rx_mode);
1357
1358 if (flowctrl & FLOW_CTRL_TX)
1359 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1360 else
1361 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1362
1363 if (old_tx_mode != tp->tx_mode)
1364 tw32_f(MAC_TX_MODE, tp->tx_mode);
1365 }
1366
1367 static void tg3_adjust_link(struct net_device *dev)
1368 {
1369 u8 oldflowctrl, linkmesg = 0;
1370 u32 mac_mode, lcl_adv, rmt_adv;
1371 struct tg3 *tp = netdev_priv(dev);
1372 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1373
1374 spin_lock_bh(&tp->lock);
1375
1376 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1377 MAC_MODE_HALF_DUPLEX);
1378
1379 oldflowctrl = tp->link_config.active_flowctrl;
1380
1381 if (phydev->link) {
1382 lcl_adv = 0;
1383 rmt_adv = 0;
1384
1385 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1386 mac_mode |= MAC_MODE_PORT_MODE_MII;
1387 else if (phydev->speed == SPEED_1000 ||
1388 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1389 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1390 else
1391 mac_mode |= MAC_MODE_PORT_MODE_MII;
1392
1393 if (phydev->duplex == DUPLEX_HALF)
1394 mac_mode |= MAC_MODE_HALF_DUPLEX;
1395 else {
1396 lcl_adv = tg3_advert_flowctrl_1000T(
1397 tp->link_config.flowctrl);
1398
1399 if (phydev->pause)
1400 rmt_adv = LPA_PAUSE_CAP;
1401 if (phydev->asym_pause)
1402 rmt_adv |= LPA_PAUSE_ASYM;
1403 }
1404
1405 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1406 } else
1407 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1408
1409 if (mac_mode != tp->mac_mode) {
1410 tp->mac_mode = mac_mode;
1411 tw32_f(MAC_MODE, tp->mac_mode);
1412 udelay(40);
1413 }
1414
1415 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1416 if (phydev->speed == SPEED_10)
1417 tw32(MAC_MI_STAT,
1418 MAC_MI_STAT_10MBPS_MODE |
1419 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1420 else
1421 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1422 }
1423
1424 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1425 tw32(MAC_TX_LENGTHS,
1426 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1427 (6 << TX_LENGTHS_IPG_SHIFT) |
1428 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1429 else
1430 tw32(MAC_TX_LENGTHS,
1431 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1432 (6 << TX_LENGTHS_IPG_SHIFT) |
1433 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1434
1435 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1436 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1437 phydev->speed != tp->link_config.active_speed ||
1438 phydev->duplex != tp->link_config.active_duplex ||
1439 oldflowctrl != tp->link_config.active_flowctrl)
1440 linkmesg = 1;
1441
1442 tp->link_config.active_speed = phydev->speed;
1443 tp->link_config.active_duplex = phydev->duplex;
1444
1445 spin_unlock_bh(&tp->lock);
1446
1447 if (linkmesg)
1448 tg3_link_report(tp);
1449 }
1450
1451 static int tg3_phy_init(struct tg3 *tp)
1452 {
1453 struct phy_device *phydev;
1454
1455 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1456 return 0;
1457
1458 /* Bring the PHY back to a known state. */
1459 tg3_bmcr_reset(tp);
1460
1461 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1462
1463 /* Attach the MAC to the PHY. */
1464 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1465 phydev->dev_flags, phydev->interface);
1466 if (IS_ERR(phydev)) {
1467 netdev_err(tp->dev, "Could not attach to PHY\n");
1468 return PTR_ERR(phydev);
1469 }
1470
1471 /* Mask with MAC supported features. */
1472 switch (phydev->interface) {
1473 case PHY_INTERFACE_MODE_GMII:
1474 case PHY_INTERFACE_MODE_RGMII:
1475 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1476 phydev->supported &= (PHY_GBIT_FEATURES |
1477 SUPPORTED_Pause |
1478 SUPPORTED_Asym_Pause);
1479 break;
1480 }
1481 /* fallthru */
1482 case PHY_INTERFACE_MODE_MII:
1483 phydev->supported &= (PHY_BASIC_FEATURES |
1484 SUPPORTED_Pause |
1485 SUPPORTED_Asym_Pause);
1486 break;
1487 default:
1488 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1489 return -EINVAL;
1490 }
1491
1492 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1493
1494 phydev->advertising = phydev->supported;
1495
1496 return 0;
1497 }
1498
1499 static void tg3_phy_start(struct tg3 *tp)
1500 {
1501 struct phy_device *phydev;
1502
1503 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1504 return;
1505
1506 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1507
1508 if (tp->link_config.phy_is_low_power) {
1509 tp->link_config.phy_is_low_power = 0;
1510 phydev->speed = tp->link_config.orig_speed;
1511 phydev->duplex = tp->link_config.orig_duplex;
1512 phydev->autoneg = tp->link_config.orig_autoneg;
1513 phydev->advertising = tp->link_config.orig_advertising;
1514 }
1515
1516 phy_start(phydev);
1517
1518 phy_start_aneg(phydev);
1519 }
1520
1521 static void tg3_phy_stop(struct tg3 *tp)
1522 {
1523 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1524 return;
1525
1526 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1527 }
1528
1529 static void tg3_phy_fini(struct tg3 *tp)
1530 {
1531 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1532 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1533 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1534 }
1535 }
1536
1537 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1538 {
1539 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1540 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1541 }
1542
1543 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1544 {
1545 u32 phytest;
1546
1547 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1548 u32 phy;
1549
1550 tg3_writephy(tp, MII_TG3_FET_TEST,
1551 phytest | MII_TG3_FET_SHADOW_EN);
1552 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1553 if (enable)
1554 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1555 else
1556 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1557 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1558 }
1559 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1560 }
1561 }
1562
1563 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1564 {
1565 u32 reg;
1566
1567 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1568 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1569 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1570 return;
1571
1572 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1573 tg3_phy_fet_toggle_apd(tp, enable);
1574 return;
1575 }
1576
1577 reg = MII_TG3_MISC_SHDW_WREN |
1578 MII_TG3_MISC_SHDW_SCR5_SEL |
1579 MII_TG3_MISC_SHDW_SCR5_LPED |
1580 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1581 MII_TG3_MISC_SHDW_SCR5_SDTL |
1582 MII_TG3_MISC_SHDW_SCR5_C125OE;
1583 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1584 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1585
1586 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1587
1588
1589 reg = MII_TG3_MISC_SHDW_WREN |
1590 MII_TG3_MISC_SHDW_APD_SEL |
1591 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1592 if (enable)
1593 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1594
1595 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1596 }
1597
1598 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1599 {
1600 u32 phy;
1601
1602 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1603 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1604 return;
1605
1606 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1607 u32 ephy;
1608
1609 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1610 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1611
1612 tg3_writephy(tp, MII_TG3_FET_TEST,
1613 ephy | MII_TG3_FET_SHADOW_EN);
1614 if (!tg3_readphy(tp, reg, &phy)) {
1615 if (enable)
1616 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1617 else
1618 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1619 tg3_writephy(tp, reg, phy);
1620 }
1621 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1622 }
1623 } else {
1624 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1625 MII_TG3_AUXCTL_SHDWSEL_MISC;
1626 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1627 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1628 if (enable)
1629 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1630 else
1631 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1632 phy |= MII_TG3_AUXCTL_MISC_WREN;
1633 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1634 }
1635 }
1636 }
1637
1638 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1639 {
1640 u32 val;
1641
1642 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1643 return;
1644
1645 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1646 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1647 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1648 (val | (1 << 15) | (1 << 4)));
1649 }
1650
1651 static void tg3_phy_apply_otp(struct tg3 *tp)
1652 {
1653 u32 otp, phy;
1654
1655 if (!tp->phy_otp)
1656 return;
1657
1658 otp = tp->phy_otp;
1659
1660 /* Enable SM_DSP clock and tx 6dB coding. */
1661 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1662 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1663 MII_TG3_AUXCTL_ACTL_TX_6DB;
1664 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1665
1666 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1667 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1668 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1669
1670 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1671 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1672 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1673
1674 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1675 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1676 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1677
1678 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1679 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1680
1681 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1682 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1683
1684 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1685 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1686 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1687
1688 /* Turn off SM_DSP clock. */
1689 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1690 MII_TG3_AUXCTL_ACTL_TX_6DB;
1691 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1692 }
1693
1694 static int tg3_wait_macro_done(struct tg3 *tp)
1695 {
1696 int limit = 100;
1697
1698 while (limit--) {
1699 u32 tmp32;
1700
1701 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1702 if ((tmp32 & 0x1000) == 0)
1703 break;
1704 }
1705 }
1706 if (limit < 0)
1707 return -EBUSY;
1708
1709 return 0;
1710 }
1711
1712 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1713 {
1714 static const u32 test_pat[4][6] = {
1715 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1716 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1717 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1718 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1719 };
1720 int chan;
1721
1722 for (chan = 0; chan < 4; chan++) {
1723 int i;
1724
1725 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1726 (chan * 0x2000) | 0x0200);
1727 tg3_writephy(tp, 0x16, 0x0002);
1728
1729 for (i = 0; i < 6; i++)
1730 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1731 test_pat[chan][i]);
1732
1733 tg3_writephy(tp, 0x16, 0x0202);
1734 if (tg3_wait_macro_done(tp)) {
1735 *resetp = 1;
1736 return -EBUSY;
1737 }
1738
1739 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1740 (chan * 0x2000) | 0x0200);
1741 tg3_writephy(tp, 0x16, 0x0082);
1742 if (tg3_wait_macro_done(tp)) {
1743 *resetp = 1;
1744 return -EBUSY;
1745 }
1746
1747 tg3_writephy(tp, 0x16, 0x0802);
1748 if (tg3_wait_macro_done(tp)) {
1749 *resetp = 1;
1750 return -EBUSY;
1751 }
1752
1753 for (i = 0; i < 6; i += 2) {
1754 u32 low, high;
1755
1756 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1757 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1758 tg3_wait_macro_done(tp)) {
1759 *resetp = 1;
1760 return -EBUSY;
1761 }
1762 low &= 0x7fff;
1763 high &= 0x000f;
1764 if (low != test_pat[chan][i] ||
1765 high != test_pat[chan][i+1]) {
1766 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1767 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1768 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1769
1770 return -EBUSY;
1771 }
1772 }
1773 }
1774
1775 return 0;
1776 }
1777
1778 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1779 {
1780 int chan;
1781
1782 for (chan = 0; chan < 4; chan++) {
1783 int i;
1784
1785 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1786 (chan * 0x2000) | 0x0200);
1787 tg3_writephy(tp, 0x16, 0x0002);
1788 for (i = 0; i < 6; i++)
1789 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1790 tg3_writephy(tp, 0x16, 0x0202);
1791 if (tg3_wait_macro_done(tp))
1792 return -EBUSY;
1793 }
1794
1795 return 0;
1796 }
1797
1798 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1799 {
1800 u32 reg32, phy9_orig;
1801 int retries, do_phy_reset, err;
1802
1803 retries = 10;
1804 do_phy_reset = 1;
1805 do {
1806 if (do_phy_reset) {
1807 err = tg3_bmcr_reset(tp);
1808 if (err)
1809 return err;
1810 do_phy_reset = 0;
1811 }
1812
1813 /* Disable transmitter and interrupt. */
1814 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1815 continue;
1816
1817 reg32 |= 0x3000;
1818 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1819
1820 /* Set full-duplex, 1000 mbps. */
1821 tg3_writephy(tp, MII_BMCR,
1822 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1823
1824 /* Set to master mode. */
1825 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1826 continue;
1827
1828 tg3_writephy(tp, MII_TG3_CTRL,
1829 (MII_TG3_CTRL_AS_MASTER |
1830 MII_TG3_CTRL_ENABLE_AS_MASTER));
1831
1832 /* Enable SM_DSP_CLOCK and 6dB. */
1833 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1834
1835 /* Block the PHY control access. */
1836 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1837 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1838
1839 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1840 if (!err)
1841 break;
1842 } while (--retries);
1843
1844 err = tg3_phy_reset_chanpat(tp);
1845 if (err)
1846 return err;
1847
1848 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1849 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1850
1851 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1852 tg3_writephy(tp, 0x16, 0x0000);
1853
1854 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1855 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1856 /* Set Extended packet length bit for jumbo frames */
1857 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1858 }
1859 else {
1860 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1861 }
1862
1863 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1864
1865 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1866 reg32 &= ~0x3000;
1867 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1868 } else if (!err)
1869 err = -EBUSY;
1870
1871 return err;
1872 }
1873
1874 /* This will reset the tigon3 PHY if there is no valid
1875 * link unless the FORCE argument is non-zero.
1876 */
1877 static int tg3_phy_reset(struct tg3 *tp)
1878 {
1879 u32 cpmuctrl;
1880 u32 phy_status;
1881 int err;
1882
1883 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1884 u32 val;
1885
1886 val = tr32(GRC_MISC_CFG);
1887 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1888 udelay(40);
1889 }
1890 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1891 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1892 if (err != 0)
1893 return -EBUSY;
1894
1895 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1896 netif_carrier_off(tp->dev);
1897 tg3_link_report(tp);
1898 }
1899
1900 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1901 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1902 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1903 err = tg3_phy_reset_5703_4_5(tp);
1904 if (err)
1905 return err;
1906 goto out;
1907 }
1908
1909 cpmuctrl = 0;
1910 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1911 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1912 cpmuctrl = tr32(TG3_CPMU_CTRL);
1913 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1914 tw32(TG3_CPMU_CTRL,
1915 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1916 }
1917
1918 err = tg3_bmcr_reset(tp);
1919 if (err)
1920 return err;
1921
1922 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1923 u32 phy;
1924
1925 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1926 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1927
1928 tw32(TG3_CPMU_CTRL, cpmuctrl);
1929 }
1930
1931 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1932 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1933 u32 val;
1934
1935 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1936 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1937 CPMU_LSPD_1000MB_MACCLK_12_5) {
1938 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1939 udelay(40);
1940 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1941 }
1942 }
1943
1944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1945 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1946 return 0;
1947
1948 tg3_phy_apply_otp(tp);
1949
1950 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1951 tg3_phy_toggle_apd(tp, true);
1952 else
1953 tg3_phy_toggle_apd(tp, false);
1954
1955 out:
1956 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1957 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1958 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1959 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1960 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1961 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1962 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1963 }
1964 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1965 tg3_writephy(tp, 0x1c, 0x8d68);
1966 tg3_writephy(tp, 0x1c, 0x8d68);
1967 }
1968 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1969 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1970 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1971 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1972 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1973 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1974 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1975 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1976 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1977 }
1978 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1979 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1980 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1981 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1982 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1983 tg3_writephy(tp, MII_TG3_TEST1,
1984 MII_TG3_TEST1_TRIM_EN | 0x4);
1985 } else
1986 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1987 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1988 }
1989 /* Set Extended packet length bit (bit 14) on all chips that */
1990 /* support jumbo frames */
1991 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1992 /* Cannot do read-modify-write on 5401 */
1993 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1994 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1995 u32 phy_reg;
1996
1997 /* Set bit 14 with read-modify-write to preserve other bits */
1998 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1999 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2000 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2001 }
2002
2003 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2004 * jumbo frames transmission.
2005 */
2006 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2007 u32 phy_reg;
2008
2009 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2010 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2011 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2012 }
2013
2014 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2015 /* adjust output voltage */
2016 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2017 }
2018
2019 tg3_phy_toggle_automdix(tp, 1);
2020 tg3_phy_set_wirespeed(tp);
2021 return 0;
2022 }
2023
2024 static void tg3_frob_aux_power(struct tg3 *tp)
2025 {
2026 struct tg3 *tp_peer = tp;
2027
2028 /* The GPIOs do something completely different on 57765. */
2029 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2031 return;
2032
2033 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2034 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2036 struct net_device *dev_peer;
2037
2038 dev_peer = pci_get_drvdata(tp->pdev_peer);
2039 /* remove_one() may have been run on the peer. */
2040 if (!dev_peer)
2041 tp_peer = tp;
2042 else
2043 tp_peer = netdev_priv(dev_peer);
2044 }
2045
2046 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2047 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2048 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2049 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2050 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2052 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2053 (GRC_LCLCTRL_GPIO_OE0 |
2054 GRC_LCLCTRL_GPIO_OE1 |
2055 GRC_LCLCTRL_GPIO_OE2 |
2056 GRC_LCLCTRL_GPIO_OUTPUT0 |
2057 GRC_LCLCTRL_GPIO_OUTPUT1),
2058 100);
2059 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2060 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2061 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2062 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2063 GRC_LCLCTRL_GPIO_OE1 |
2064 GRC_LCLCTRL_GPIO_OE2 |
2065 GRC_LCLCTRL_GPIO_OUTPUT0 |
2066 GRC_LCLCTRL_GPIO_OUTPUT1 |
2067 tp->grc_local_ctrl;
2068 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2069
2070 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2071 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2072
2073 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2074 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2075 } else {
2076 u32 no_gpio2;
2077 u32 grc_local_ctrl = 0;
2078
2079 if (tp_peer != tp &&
2080 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2081 return;
2082
2083 /* Workaround to prevent overdrawing Amps. */
2084 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2085 ASIC_REV_5714) {
2086 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2087 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2088 grc_local_ctrl, 100);
2089 }
2090
2091 /* On 5753 and variants, GPIO2 cannot be used. */
2092 no_gpio2 = tp->nic_sram_data_cfg &
2093 NIC_SRAM_DATA_CFG_NO_GPIO2;
2094
2095 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2096 GRC_LCLCTRL_GPIO_OE1 |
2097 GRC_LCLCTRL_GPIO_OE2 |
2098 GRC_LCLCTRL_GPIO_OUTPUT1 |
2099 GRC_LCLCTRL_GPIO_OUTPUT2;
2100 if (no_gpio2) {
2101 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2102 GRC_LCLCTRL_GPIO_OUTPUT2);
2103 }
2104 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2105 grc_local_ctrl, 100);
2106
2107 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2108
2109 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2110 grc_local_ctrl, 100);
2111
2112 if (!no_gpio2) {
2113 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2114 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2115 grc_local_ctrl, 100);
2116 }
2117 }
2118 } else {
2119 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2120 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2121 if (tp_peer != tp &&
2122 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2123 return;
2124
2125 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2126 (GRC_LCLCTRL_GPIO_OE1 |
2127 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2128
2129 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2130 GRC_LCLCTRL_GPIO_OE1, 100);
2131
2132 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2133 (GRC_LCLCTRL_GPIO_OE1 |
2134 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2135 }
2136 }
2137 }
2138
2139 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2140 {
2141 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2142 return 1;
2143 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2144 if (speed != SPEED_10)
2145 return 1;
2146 } else if (speed == SPEED_10)
2147 return 1;
2148
2149 return 0;
2150 }
2151
2152 static int tg3_setup_phy(struct tg3 *, int);
2153
2154 #define RESET_KIND_SHUTDOWN 0
2155 #define RESET_KIND_INIT 1
2156 #define RESET_KIND_SUSPEND 2
2157
2158 static void tg3_write_sig_post_reset(struct tg3 *, int);
2159 static int tg3_halt_cpu(struct tg3 *, u32);
2160
2161 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2162 {
2163 u32 val;
2164
2165 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2166 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2167 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2168 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2169
2170 sg_dig_ctrl |=
2171 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2172 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2173 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2174 }
2175 return;
2176 }
2177
2178 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2179 tg3_bmcr_reset(tp);
2180 val = tr32(GRC_MISC_CFG);
2181 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2182 udelay(40);
2183 return;
2184 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2185 u32 phytest;
2186 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2187 u32 phy;
2188
2189 tg3_writephy(tp, MII_ADVERTISE, 0);
2190 tg3_writephy(tp, MII_BMCR,
2191 BMCR_ANENABLE | BMCR_ANRESTART);
2192
2193 tg3_writephy(tp, MII_TG3_FET_TEST,
2194 phytest | MII_TG3_FET_SHADOW_EN);
2195 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2196 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2197 tg3_writephy(tp,
2198 MII_TG3_FET_SHDW_AUXMODE4,
2199 phy);
2200 }
2201 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2202 }
2203 return;
2204 } else if (do_low_power) {
2205 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2206 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2207
2208 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2209 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2210 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2211 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2212 MII_TG3_AUXCTL_PCTL_VREG_11V);
2213 }
2214
2215 /* The PHY should not be powered down on some chips because
2216 * of bugs.
2217 */
2218 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2219 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2220 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2221 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2222 return;
2223
2224 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2225 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2226 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2227 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2228 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2229 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2230 }
2231
2232 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2233 }
2234
2235 /* tp->lock is held. */
2236 static int tg3_nvram_lock(struct tg3 *tp)
2237 {
2238 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2239 int i;
2240
2241 if (tp->nvram_lock_cnt == 0) {
2242 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2243 for (i = 0; i < 8000; i++) {
2244 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2245 break;
2246 udelay(20);
2247 }
2248 if (i == 8000) {
2249 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2250 return -ENODEV;
2251 }
2252 }
2253 tp->nvram_lock_cnt++;
2254 }
2255 return 0;
2256 }
2257
2258 /* tp->lock is held. */
2259 static void tg3_nvram_unlock(struct tg3 *tp)
2260 {
2261 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2262 if (tp->nvram_lock_cnt > 0)
2263 tp->nvram_lock_cnt--;
2264 if (tp->nvram_lock_cnt == 0)
2265 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2266 }
2267 }
2268
2269 /* tp->lock is held. */
2270 static void tg3_enable_nvram_access(struct tg3 *tp)
2271 {
2272 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2273 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2274 u32 nvaccess = tr32(NVRAM_ACCESS);
2275
2276 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2277 }
2278 }
2279
2280 /* tp->lock is held. */
2281 static void tg3_disable_nvram_access(struct tg3 *tp)
2282 {
2283 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2284 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2285 u32 nvaccess = tr32(NVRAM_ACCESS);
2286
2287 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2288 }
2289 }
2290
2291 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2292 u32 offset, u32 *val)
2293 {
2294 u32 tmp;
2295 int i;
2296
2297 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2298 return -EINVAL;
2299
2300 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2301 EEPROM_ADDR_DEVID_MASK |
2302 EEPROM_ADDR_READ);
2303 tw32(GRC_EEPROM_ADDR,
2304 tmp |
2305 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2306 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2307 EEPROM_ADDR_ADDR_MASK) |
2308 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2309
2310 for (i = 0; i < 1000; i++) {
2311 tmp = tr32(GRC_EEPROM_ADDR);
2312
2313 if (tmp & EEPROM_ADDR_COMPLETE)
2314 break;
2315 msleep(1);
2316 }
2317 if (!(tmp & EEPROM_ADDR_COMPLETE))
2318 return -EBUSY;
2319
2320 tmp = tr32(GRC_EEPROM_DATA);
2321
2322 /*
2323 * The data will always be opposite the native endian
2324 * format. Perform a blind byteswap to compensate.
2325 */
2326 *val = swab32(tmp);
2327
2328 return 0;
2329 }
2330
2331 #define NVRAM_CMD_TIMEOUT 10000
2332
2333 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2334 {
2335 int i;
2336
2337 tw32(NVRAM_CMD, nvram_cmd);
2338 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2339 udelay(10);
2340 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2341 udelay(10);
2342 break;
2343 }
2344 }
2345
2346 if (i == NVRAM_CMD_TIMEOUT)
2347 return -EBUSY;
2348
2349 return 0;
2350 }
2351
2352 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2353 {
2354 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2355 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2356 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2357 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2358 (tp->nvram_jedecnum == JEDEC_ATMEL))
2359
2360 addr = ((addr / tp->nvram_pagesize) <<
2361 ATMEL_AT45DB0X1B_PAGE_POS) +
2362 (addr % tp->nvram_pagesize);
2363
2364 return addr;
2365 }
2366
2367 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2368 {
2369 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2370 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2371 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2372 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2373 (tp->nvram_jedecnum == JEDEC_ATMEL))
2374
2375 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2376 tp->nvram_pagesize) +
2377 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2378
2379 return addr;
2380 }
2381
2382 /* NOTE: Data read in from NVRAM is byteswapped according to
2383 * the byteswapping settings for all other register accesses.
2384 * tg3 devices are BE devices, so on a BE machine, the data
2385 * returned will be exactly as it is seen in NVRAM. On a LE
2386 * machine, the 32-bit value will be byteswapped.
2387 */
2388 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2389 {
2390 int ret;
2391
2392 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2393 return tg3_nvram_read_using_eeprom(tp, offset, val);
2394
2395 offset = tg3_nvram_phys_addr(tp, offset);
2396
2397 if (offset > NVRAM_ADDR_MSK)
2398 return -EINVAL;
2399
2400 ret = tg3_nvram_lock(tp);
2401 if (ret)
2402 return ret;
2403
2404 tg3_enable_nvram_access(tp);
2405
2406 tw32(NVRAM_ADDR, offset);
2407 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2408 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2409
2410 if (ret == 0)
2411 *val = tr32(NVRAM_RDDATA);
2412
2413 tg3_disable_nvram_access(tp);
2414
2415 tg3_nvram_unlock(tp);
2416
2417 return ret;
2418 }
2419
2420 /* Ensures NVRAM data is in bytestream format. */
2421 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2422 {
2423 u32 v;
2424 int res = tg3_nvram_read(tp, offset, &v);
2425 if (!res)
2426 *val = cpu_to_be32(v);
2427 return res;
2428 }
2429
2430 /* tp->lock is held. */
2431 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2432 {
2433 u32 addr_high, addr_low;
2434 int i;
2435
2436 addr_high = ((tp->dev->dev_addr[0] << 8) |
2437 tp->dev->dev_addr[1]);
2438 addr_low = ((tp->dev->dev_addr[2] << 24) |
2439 (tp->dev->dev_addr[3] << 16) |
2440 (tp->dev->dev_addr[4] << 8) |
2441 (tp->dev->dev_addr[5] << 0));
2442 for (i = 0; i < 4; i++) {
2443 if (i == 1 && skip_mac_1)
2444 continue;
2445 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2446 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2447 }
2448
2449 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2450 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2451 for (i = 0; i < 12; i++) {
2452 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2453 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2454 }
2455 }
2456
2457 addr_high = (tp->dev->dev_addr[0] +
2458 tp->dev->dev_addr[1] +
2459 tp->dev->dev_addr[2] +
2460 tp->dev->dev_addr[3] +
2461 tp->dev->dev_addr[4] +
2462 tp->dev->dev_addr[5]) &
2463 TX_BACKOFF_SEED_MASK;
2464 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2465 }
2466
2467 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2468 {
2469 u32 misc_host_ctrl;
2470 bool device_should_wake, do_low_power;
2471
2472 /* Make sure register accesses (indirect or otherwise)
2473 * will function correctly.
2474 */
2475 pci_write_config_dword(tp->pdev,
2476 TG3PCI_MISC_HOST_CTRL,
2477 tp->misc_host_ctrl);
2478
2479 switch (state) {
2480 case PCI_D0:
2481 pci_enable_wake(tp->pdev, state, false);
2482 pci_set_power_state(tp->pdev, PCI_D0);
2483
2484 /* Switch out of Vaux if it is a NIC */
2485 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2486 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2487
2488 return 0;
2489
2490 case PCI_D1:
2491 case PCI_D2:
2492 case PCI_D3hot:
2493 break;
2494
2495 default:
2496 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2497 state);
2498 return -EINVAL;
2499 }
2500
2501 /* Restore the CLKREQ setting. */
2502 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2503 u16 lnkctl;
2504
2505 pci_read_config_word(tp->pdev,
2506 tp->pcie_cap + PCI_EXP_LNKCTL,
2507 &lnkctl);
2508 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2509 pci_write_config_word(tp->pdev,
2510 tp->pcie_cap + PCI_EXP_LNKCTL,
2511 lnkctl);
2512 }
2513
2514 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2515 tw32(TG3PCI_MISC_HOST_CTRL,
2516 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2517
2518 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2519 device_may_wakeup(&tp->pdev->dev) &&
2520 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2521
2522 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2523 do_low_power = false;
2524 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2525 !tp->link_config.phy_is_low_power) {
2526 struct phy_device *phydev;
2527 u32 phyid, advertising;
2528
2529 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2530
2531 tp->link_config.phy_is_low_power = 1;
2532
2533 tp->link_config.orig_speed = phydev->speed;
2534 tp->link_config.orig_duplex = phydev->duplex;
2535 tp->link_config.orig_autoneg = phydev->autoneg;
2536 tp->link_config.orig_advertising = phydev->advertising;
2537
2538 advertising = ADVERTISED_TP |
2539 ADVERTISED_Pause |
2540 ADVERTISED_Autoneg |
2541 ADVERTISED_10baseT_Half;
2542
2543 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2544 device_should_wake) {
2545 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2546 advertising |=
2547 ADVERTISED_100baseT_Half |
2548 ADVERTISED_100baseT_Full |
2549 ADVERTISED_10baseT_Full;
2550 else
2551 advertising |= ADVERTISED_10baseT_Full;
2552 }
2553
2554 phydev->advertising = advertising;
2555
2556 phy_start_aneg(phydev);
2557
2558 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2559 if (phyid != PHY_ID_BCMAC131) {
2560 phyid &= PHY_BCM_OUI_MASK;
2561 if (phyid == PHY_BCM_OUI_1 ||
2562 phyid == PHY_BCM_OUI_2 ||
2563 phyid == PHY_BCM_OUI_3)
2564 do_low_power = true;
2565 }
2566 }
2567 } else {
2568 do_low_power = true;
2569
2570 if (tp->link_config.phy_is_low_power == 0) {
2571 tp->link_config.phy_is_low_power = 1;
2572 tp->link_config.orig_speed = tp->link_config.speed;
2573 tp->link_config.orig_duplex = tp->link_config.duplex;
2574 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2575 }
2576
2577 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2578 tp->link_config.speed = SPEED_10;
2579 tp->link_config.duplex = DUPLEX_HALF;
2580 tp->link_config.autoneg = AUTONEG_ENABLE;
2581 tg3_setup_phy(tp, 0);
2582 }
2583 }
2584
2585 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2586 u32 val;
2587
2588 val = tr32(GRC_VCPU_EXT_CTRL);
2589 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2590 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2591 int i;
2592 u32 val;
2593
2594 for (i = 0; i < 200; i++) {
2595 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2596 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2597 break;
2598 msleep(1);
2599 }
2600 }
2601 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2602 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2603 WOL_DRV_STATE_SHUTDOWN |
2604 WOL_DRV_WOL |
2605 WOL_SET_MAGIC_PKT);
2606
2607 if (device_should_wake) {
2608 u32 mac_mode;
2609
2610 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2611 if (do_low_power) {
2612 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2613 udelay(40);
2614 }
2615
2616 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2617 mac_mode = MAC_MODE_PORT_MODE_GMII;
2618 else
2619 mac_mode = MAC_MODE_PORT_MODE_MII;
2620
2621 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2622 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2623 ASIC_REV_5700) {
2624 u32 speed = (tp->tg3_flags &
2625 TG3_FLAG_WOL_SPEED_100MB) ?
2626 SPEED_100 : SPEED_10;
2627 if (tg3_5700_link_polarity(tp, speed))
2628 mac_mode |= MAC_MODE_LINK_POLARITY;
2629 else
2630 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2631 }
2632 } else {
2633 mac_mode = MAC_MODE_PORT_MODE_TBI;
2634 }
2635
2636 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2637 tw32(MAC_LED_CTRL, tp->led_ctrl);
2638
2639 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2640 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2641 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2642 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2643 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2644 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2645
2646 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2647 mac_mode |= tp->mac_mode &
2648 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2649 if (mac_mode & MAC_MODE_APE_TX_EN)
2650 mac_mode |= MAC_MODE_TDE_ENABLE;
2651 }
2652
2653 tw32_f(MAC_MODE, mac_mode);
2654 udelay(100);
2655
2656 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2657 udelay(10);
2658 }
2659
2660 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2661 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2662 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2663 u32 base_val;
2664
2665 base_val = tp->pci_clock_ctrl;
2666 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2667 CLOCK_CTRL_TXCLK_DISABLE);
2668
2669 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2670 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2671 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2672 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2673 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2674 /* do nothing */
2675 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2676 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2677 u32 newbits1, newbits2;
2678
2679 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2680 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2681 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2682 CLOCK_CTRL_TXCLK_DISABLE |
2683 CLOCK_CTRL_ALTCLK);
2684 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2685 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2686 newbits1 = CLOCK_CTRL_625_CORE;
2687 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2688 } else {
2689 newbits1 = CLOCK_CTRL_ALTCLK;
2690 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2691 }
2692
2693 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2694 40);
2695
2696 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2697 40);
2698
2699 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2700 u32 newbits3;
2701
2702 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2703 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2704 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2705 CLOCK_CTRL_TXCLK_DISABLE |
2706 CLOCK_CTRL_44MHZ_CORE);
2707 } else {
2708 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2709 }
2710
2711 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2712 tp->pci_clock_ctrl | newbits3, 40);
2713 }
2714 }
2715
2716 if (!(device_should_wake) &&
2717 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2718 tg3_power_down_phy(tp, do_low_power);
2719
2720 tg3_frob_aux_power(tp);
2721
2722 /* Workaround for unstable PLL clock */
2723 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2724 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2725 u32 val = tr32(0x7d00);
2726
2727 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2728 tw32(0x7d00, val);
2729 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2730 int err;
2731
2732 err = tg3_nvram_lock(tp);
2733 tg3_halt_cpu(tp, RX_CPU_BASE);
2734 if (!err)
2735 tg3_nvram_unlock(tp);
2736 }
2737 }
2738
2739 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2740
2741 if (device_should_wake)
2742 pci_enable_wake(tp->pdev, state, true);
2743
2744 /* Finally, set the new power state. */
2745 pci_set_power_state(tp->pdev, state);
2746
2747 return 0;
2748 }
2749
2750 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2751 {
2752 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2753 case MII_TG3_AUX_STAT_10HALF:
2754 *speed = SPEED_10;
2755 *duplex = DUPLEX_HALF;
2756 break;
2757
2758 case MII_TG3_AUX_STAT_10FULL:
2759 *speed = SPEED_10;
2760 *duplex = DUPLEX_FULL;
2761 break;
2762
2763 case MII_TG3_AUX_STAT_100HALF:
2764 *speed = SPEED_100;
2765 *duplex = DUPLEX_HALF;
2766 break;
2767
2768 case MII_TG3_AUX_STAT_100FULL:
2769 *speed = SPEED_100;
2770 *duplex = DUPLEX_FULL;
2771 break;
2772
2773 case MII_TG3_AUX_STAT_1000HALF:
2774 *speed = SPEED_1000;
2775 *duplex = DUPLEX_HALF;
2776 break;
2777
2778 case MII_TG3_AUX_STAT_1000FULL:
2779 *speed = SPEED_1000;
2780 *duplex = DUPLEX_FULL;
2781 break;
2782
2783 default:
2784 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2785 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2786 SPEED_10;
2787 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2788 DUPLEX_HALF;
2789 break;
2790 }
2791 *speed = SPEED_INVALID;
2792 *duplex = DUPLEX_INVALID;
2793 break;
2794 }
2795 }
2796
2797 static void tg3_phy_copper_begin(struct tg3 *tp)
2798 {
2799 u32 new_adv;
2800 int i;
2801
2802 if (tp->link_config.phy_is_low_power) {
2803 /* Entering low power mode. Disable gigabit and
2804 * 100baseT advertisements.
2805 */
2806 tg3_writephy(tp, MII_TG3_CTRL, 0);
2807
2808 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2809 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2810 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2811 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2812
2813 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2814 } else if (tp->link_config.speed == SPEED_INVALID) {
2815 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2816 tp->link_config.advertising &=
2817 ~(ADVERTISED_1000baseT_Half |
2818 ADVERTISED_1000baseT_Full);
2819
2820 new_adv = ADVERTISE_CSMA;
2821 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2822 new_adv |= ADVERTISE_10HALF;
2823 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2824 new_adv |= ADVERTISE_10FULL;
2825 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2826 new_adv |= ADVERTISE_100HALF;
2827 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2828 new_adv |= ADVERTISE_100FULL;
2829
2830 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2831
2832 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2833
2834 if (tp->link_config.advertising &
2835 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2836 new_adv = 0;
2837 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2838 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2839 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2840 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2841 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2842 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2843 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2844 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2845 MII_TG3_CTRL_ENABLE_AS_MASTER);
2846 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2847 } else {
2848 tg3_writephy(tp, MII_TG3_CTRL, 0);
2849 }
2850 } else {
2851 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2852 new_adv |= ADVERTISE_CSMA;
2853
2854 /* Asking for a specific link mode. */
2855 if (tp->link_config.speed == SPEED_1000) {
2856 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2857
2858 if (tp->link_config.duplex == DUPLEX_FULL)
2859 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2860 else
2861 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2862 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2863 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2864 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2865 MII_TG3_CTRL_ENABLE_AS_MASTER);
2866 } else {
2867 if (tp->link_config.speed == SPEED_100) {
2868 if (tp->link_config.duplex == DUPLEX_FULL)
2869 new_adv |= ADVERTISE_100FULL;
2870 else
2871 new_adv |= ADVERTISE_100HALF;
2872 } else {
2873 if (tp->link_config.duplex == DUPLEX_FULL)
2874 new_adv |= ADVERTISE_10FULL;
2875 else
2876 new_adv |= ADVERTISE_10HALF;
2877 }
2878 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2879
2880 new_adv = 0;
2881 }
2882
2883 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2884 }
2885
2886 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2887 tp->link_config.speed != SPEED_INVALID) {
2888 u32 bmcr, orig_bmcr;
2889
2890 tp->link_config.active_speed = tp->link_config.speed;
2891 tp->link_config.active_duplex = tp->link_config.duplex;
2892
2893 bmcr = 0;
2894 switch (tp->link_config.speed) {
2895 default:
2896 case SPEED_10:
2897 break;
2898
2899 case SPEED_100:
2900 bmcr |= BMCR_SPEED100;
2901 break;
2902
2903 case SPEED_1000:
2904 bmcr |= TG3_BMCR_SPEED1000;
2905 break;
2906 }
2907
2908 if (tp->link_config.duplex == DUPLEX_FULL)
2909 bmcr |= BMCR_FULLDPLX;
2910
2911 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2912 (bmcr != orig_bmcr)) {
2913 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2914 for (i = 0; i < 1500; i++) {
2915 u32 tmp;
2916
2917 udelay(10);
2918 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2919 tg3_readphy(tp, MII_BMSR, &tmp))
2920 continue;
2921 if (!(tmp & BMSR_LSTATUS)) {
2922 udelay(40);
2923 break;
2924 }
2925 }
2926 tg3_writephy(tp, MII_BMCR, bmcr);
2927 udelay(40);
2928 }
2929 } else {
2930 tg3_writephy(tp, MII_BMCR,
2931 BMCR_ANENABLE | BMCR_ANRESTART);
2932 }
2933 }
2934
2935 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2936 {
2937 int err;
2938
2939 /* Turn off tap power management. */
2940 /* Set Extended packet length bit */
2941 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2942
2943 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2944 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2945
2946 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2947 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2948
2949 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2950 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2951
2952 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2953 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2954
2955 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2956 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2957
2958 udelay(40);
2959
2960 return err;
2961 }
2962
2963 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2964 {
2965 u32 adv_reg, all_mask = 0;
2966
2967 if (mask & ADVERTISED_10baseT_Half)
2968 all_mask |= ADVERTISE_10HALF;
2969 if (mask & ADVERTISED_10baseT_Full)
2970 all_mask |= ADVERTISE_10FULL;
2971 if (mask & ADVERTISED_100baseT_Half)
2972 all_mask |= ADVERTISE_100HALF;
2973 if (mask & ADVERTISED_100baseT_Full)
2974 all_mask |= ADVERTISE_100FULL;
2975
2976 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2977 return 0;
2978
2979 if ((adv_reg & all_mask) != all_mask)
2980 return 0;
2981 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2982 u32 tg3_ctrl;
2983
2984 all_mask = 0;
2985 if (mask & ADVERTISED_1000baseT_Half)
2986 all_mask |= ADVERTISE_1000HALF;
2987 if (mask & ADVERTISED_1000baseT_Full)
2988 all_mask |= ADVERTISE_1000FULL;
2989
2990 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2991 return 0;
2992
2993 if ((tg3_ctrl & all_mask) != all_mask)
2994 return 0;
2995 }
2996 return 1;
2997 }
2998
2999 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3000 {
3001 u32 curadv, reqadv;
3002
3003 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3004 return 1;
3005
3006 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3007 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3008
3009 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3010 if (curadv != reqadv)
3011 return 0;
3012
3013 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3014 tg3_readphy(tp, MII_LPA, rmtadv);
3015 } else {
3016 /* Reprogram the advertisement register, even if it
3017 * does not affect the current link. If the link
3018 * gets renegotiated in the future, we can save an
3019 * additional renegotiation cycle by advertising
3020 * it correctly in the first place.
3021 */
3022 if (curadv != reqadv) {
3023 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3024 ADVERTISE_PAUSE_ASYM);
3025 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3026 }
3027 }
3028
3029 return 1;
3030 }
3031
3032 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3033 {
3034 int current_link_up;
3035 u32 bmsr, dummy;
3036 u32 lcl_adv, rmt_adv;
3037 u16 current_speed;
3038 u8 current_duplex;
3039 int i, err;
3040
3041 tw32(MAC_EVENT, 0);
3042
3043 tw32_f(MAC_STATUS,
3044 (MAC_STATUS_SYNC_CHANGED |
3045 MAC_STATUS_CFG_CHANGED |
3046 MAC_STATUS_MI_COMPLETION |
3047 MAC_STATUS_LNKSTATE_CHANGED));
3048 udelay(40);
3049
3050 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3051 tw32_f(MAC_MI_MODE,
3052 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3053 udelay(80);
3054 }
3055
3056 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3057
3058 /* Some third-party PHYs need to be reset on link going
3059 * down.
3060 */
3061 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3062 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3063 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3064 netif_carrier_ok(tp->dev)) {
3065 tg3_readphy(tp, MII_BMSR, &bmsr);
3066 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3067 !(bmsr & BMSR_LSTATUS))
3068 force_reset = 1;
3069 }
3070 if (force_reset)
3071 tg3_phy_reset(tp);
3072
3073 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3074 tg3_readphy(tp, MII_BMSR, &bmsr);
3075 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3076 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3077 bmsr = 0;
3078
3079 if (!(bmsr & BMSR_LSTATUS)) {
3080 err = tg3_init_5401phy_dsp(tp);
3081 if (err)
3082 return err;
3083
3084 tg3_readphy(tp, MII_BMSR, &bmsr);
3085 for (i = 0; i < 1000; i++) {
3086 udelay(10);
3087 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3088 (bmsr & BMSR_LSTATUS)) {
3089 udelay(40);
3090 break;
3091 }
3092 }
3093
3094 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3095 TG3_PHY_REV_BCM5401_B0 &&
3096 !(bmsr & BMSR_LSTATUS) &&
3097 tp->link_config.active_speed == SPEED_1000) {
3098 err = tg3_phy_reset(tp);
3099 if (!err)
3100 err = tg3_init_5401phy_dsp(tp);
3101 if (err)
3102 return err;
3103 }
3104 }
3105 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3106 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3107 /* 5701 {A0,B0} CRC bug workaround */
3108 tg3_writephy(tp, 0x15, 0x0a75);
3109 tg3_writephy(tp, 0x1c, 0x8c68);
3110 tg3_writephy(tp, 0x1c, 0x8d68);
3111 tg3_writephy(tp, 0x1c, 0x8c68);
3112 }
3113
3114 /* Clear pending interrupts... */
3115 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3116 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3117
3118 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3119 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3120 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3121 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3122
3123 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3124 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3125 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3126 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3127 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3128 else
3129 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3130 }
3131
3132 current_link_up = 0;
3133 current_speed = SPEED_INVALID;
3134 current_duplex = DUPLEX_INVALID;
3135
3136 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3137 u32 val;
3138
3139 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3140 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3141 if (!(val & (1 << 10))) {
3142 val |= (1 << 10);
3143 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3144 goto relink;
3145 }
3146 }
3147
3148 bmsr = 0;
3149 for (i = 0; i < 100; i++) {
3150 tg3_readphy(tp, MII_BMSR, &bmsr);
3151 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3152 (bmsr & BMSR_LSTATUS))
3153 break;
3154 udelay(40);
3155 }
3156
3157 if (bmsr & BMSR_LSTATUS) {
3158 u32 aux_stat, bmcr;
3159
3160 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3161 for (i = 0; i < 2000; i++) {
3162 udelay(10);
3163 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3164 aux_stat)
3165 break;
3166 }
3167
3168 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3169 &current_speed,
3170 &current_duplex);
3171
3172 bmcr = 0;
3173 for (i = 0; i < 200; i++) {
3174 tg3_readphy(tp, MII_BMCR, &bmcr);
3175 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3176 continue;
3177 if (bmcr && bmcr != 0x7fff)
3178 break;
3179 udelay(10);
3180 }
3181
3182 lcl_adv = 0;
3183 rmt_adv = 0;
3184
3185 tp->link_config.active_speed = current_speed;
3186 tp->link_config.active_duplex = current_duplex;
3187
3188 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3189 if ((bmcr & BMCR_ANENABLE) &&
3190 tg3_copper_is_advertising_all(tp,
3191 tp->link_config.advertising)) {
3192 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3193 &rmt_adv))
3194 current_link_up = 1;
3195 }
3196 } else {
3197 if (!(bmcr & BMCR_ANENABLE) &&
3198 tp->link_config.speed == current_speed &&
3199 tp->link_config.duplex == current_duplex &&
3200 tp->link_config.flowctrl ==
3201 tp->link_config.active_flowctrl) {
3202 current_link_up = 1;
3203 }
3204 }
3205
3206 if (current_link_up == 1 &&
3207 tp->link_config.active_duplex == DUPLEX_FULL)
3208 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3209 }
3210
3211 relink:
3212 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3213 u32 tmp;
3214
3215 tg3_phy_copper_begin(tp);
3216
3217 tg3_readphy(tp, MII_BMSR, &tmp);
3218 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3219 (tmp & BMSR_LSTATUS))
3220 current_link_up = 1;
3221 }
3222
3223 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3224 if (current_link_up == 1) {
3225 if (tp->link_config.active_speed == SPEED_100 ||
3226 tp->link_config.active_speed == SPEED_10)
3227 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3228 else
3229 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3230 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3231 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3232 else
3233 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3234
3235 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3236 if (tp->link_config.active_duplex == DUPLEX_HALF)
3237 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3238
3239 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3240 if (current_link_up == 1 &&
3241 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3242 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3243 else
3244 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3245 }
3246
3247 /* ??? Without this setting Netgear GA302T PHY does not
3248 * ??? send/receive packets...
3249 */
3250 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3251 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3252 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3253 tw32_f(MAC_MI_MODE, tp->mi_mode);
3254 udelay(80);
3255 }
3256
3257 tw32_f(MAC_MODE, tp->mac_mode);
3258 udelay(40);
3259
3260 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3261 /* Polled via timer. */
3262 tw32_f(MAC_EVENT, 0);
3263 } else {
3264 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3265 }
3266 udelay(40);
3267
3268 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3269 current_link_up == 1 &&
3270 tp->link_config.active_speed == SPEED_1000 &&
3271 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3272 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3273 udelay(120);
3274 tw32_f(MAC_STATUS,
3275 (MAC_STATUS_SYNC_CHANGED |
3276 MAC_STATUS_CFG_CHANGED));
3277 udelay(40);
3278 tg3_write_mem(tp,
3279 NIC_SRAM_FIRMWARE_MBOX,
3280 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3281 }
3282
3283 /* Prevent send BD corruption. */
3284 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3285 u16 oldlnkctl, newlnkctl;
3286
3287 pci_read_config_word(tp->pdev,
3288 tp->pcie_cap + PCI_EXP_LNKCTL,
3289 &oldlnkctl);
3290 if (tp->link_config.active_speed == SPEED_100 ||
3291 tp->link_config.active_speed == SPEED_10)
3292 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3293 else
3294 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3295 if (newlnkctl != oldlnkctl)
3296 pci_write_config_word(tp->pdev,
3297 tp->pcie_cap + PCI_EXP_LNKCTL,
3298 newlnkctl);
3299 }
3300
3301 if (current_link_up != netif_carrier_ok(tp->dev)) {
3302 if (current_link_up)
3303 netif_carrier_on(tp->dev);
3304 else
3305 netif_carrier_off(tp->dev);
3306 tg3_link_report(tp);
3307 }
3308
3309 return 0;
3310 }
3311
3312 struct tg3_fiber_aneginfo {
3313 int state;
3314 #define ANEG_STATE_UNKNOWN 0
3315 #define ANEG_STATE_AN_ENABLE 1
3316 #define ANEG_STATE_RESTART_INIT 2
3317 #define ANEG_STATE_RESTART 3
3318 #define ANEG_STATE_DISABLE_LINK_OK 4
3319 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3320 #define ANEG_STATE_ABILITY_DETECT 6
3321 #define ANEG_STATE_ACK_DETECT_INIT 7
3322 #define ANEG_STATE_ACK_DETECT 8
3323 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3324 #define ANEG_STATE_COMPLETE_ACK 10
3325 #define ANEG_STATE_IDLE_DETECT_INIT 11
3326 #define ANEG_STATE_IDLE_DETECT 12
3327 #define ANEG_STATE_LINK_OK 13
3328 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3329 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3330
3331 u32 flags;
3332 #define MR_AN_ENABLE 0x00000001
3333 #define MR_RESTART_AN 0x00000002
3334 #define MR_AN_COMPLETE 0x00000004
3335 #define MR_PAGE_RX 0x00000008
3336 #define MR_NP_LOADED 0x00000010
3337 #define MR_TOGGLE_TX 0x00000020
3338 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3339 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3340 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3341 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3342 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3343 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3344 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3345 #define MR_TOGGLE_RX 0x00002000
3346 #define MR_NP_RX 0x00004000
3347
3348 #define MR_LINK_OK 0x80000000
3349
3350 unsigned long link_time, cur_time;
3351
3352 u32 ability_match_cfg;
3353 int ability_match_count;
3354
3355 char ability_match, idle_match, ack_match;
3356
3357 u32 txconfig, rxconfig;
3358 #define ANEG_CFG_NP 0x00000080
3359 #define ANEG_CFG_ACK 0x00000040
3360 #define ANEG_CFG_RF2 0x00000020
3361 #define ANEG_CFG_RF1 0x00000010
3362 #define ANEG_CFG_PS2 0x00000001
3363 #define ANEG_CFG_PS1 0x00008000
3364 #define ANEG_CFG_HD 0x00004000
3365 #define ANEG_CFG_FD 0x00002000
3366 #define ANEG_CFG_INVAL 0x00001f06
3367
3368 };
3369 #define ANEG_OK 0
3370 #define ANEG_DONE 1
3371 #define ANEG_TIMER_ENAB 2
3372 #define ANEG_FAILED -1
3373
3374 #define ANEG_STATE_SETTLE_TIME 10000
3375
3376 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3377 struct tg3_fiber_aneginfo *ap)
3378 {
3379 u16 flowctrl;
3380 unsigned long delta;
3381 u32 rx_cfg_reg;
3382 int ret;
3383
3384 if (ap->state == ANEG_STATE_UNKNOWN) {
3385 ap->rxconfig = 0;
3386 ap->link_time = 0;
3387 ap->cur_time = 0;
3388 ap->ability_match_cfg = 0;
3389 ap->ability_match_count = 0;
3390 ap->ability_match = 0;
3391 ap->idle_match = 0;
3392 ap->ack_match = 0;
3393 }
3394 ap->cur_time++;
3395
3396 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3397 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3398
3399 if (rx_cfg_reg != ap->ability_match_cfg) {
3400 ap->ability_match_cfg = rx_cfg_reg;
3401 ap->ability_match = 0;
3402 ap->ability_match_count = 0;
3403 } else {
3404 if (++ap->ability_match_count > 1) {
3405 ap->ability_match = 1;
3406 ap->ability_match_cfg = rx_cfg_reg;
3407 }
3408 }
3409 if (rx_cfg_reg & ANEG_CFG_ACK)
3410 ap->ack_match = 1;
3411 else
3412 ap->ack_match = 0;
3413
3414 ap->idle_match = 0;
3415 } else {
3416 ap->idle_match = 1;
3417 ap->ability_match_cfg = 0;
3418 ap->ability_match_count = 0;
3419 ap->ability_match = 0;
3420 ap->ack_match = 0;
3421
3422 rx_cfg_reg = 0;
3423 }
3424
3425 ap->rxconfig = rx_cfg_reg;
3426 ret = ANEG_OK;
3427
3428 switch(ap->state) {
3429 case ANEG_STATE_UNKNOWN:
3430 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3431 ap->state = ANEG_STATE_AN_ENABLE;
3432
3433 /* fallthru */
3434 case ANEG_STATE_AN_ENABLE:
3435 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3436 if (ap->flags & MR_AN_ENABLE) {
3437 ap->link_time = 0;
3438 ap->cur_time = 0;
3439 ap->ability_match_cfg = 0;
3440 ap->ability_match_count = 0;
3441 ap->ability_match = 0;
3442 ap->idle_match = 0;
3443 ap->ack_match = 0;
3444
3445 ap->state = ANEG_STATE_RESTART_INIT;
3446 } else {
3447 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3448 }
3449 break;
3450
3451 case ANEG_STATE_RESTART_INIT:
3452 ap->link_time = ap->cur_time;
3453 ap->flags &= ~(MR_NP_LOADED);
3454 ap->txconfig = 0;
3455 tw32(MAC_TX_AUTO_NEG, 0);
3456 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3457 tw32_f(MAC_MODE, tp->mac_mode);
3458 udelay(40);
3459
3460 ret = ANEG_TIMER_ENAB;
3461 ap->state = ANEG_STATE_RESTART;
3462
3463 /* fallthru */
3464 case ANEG_STATE_RESTART:
3465 delta = ap->cur_time - ap->link_time;
3466 if (delta > ANEG_STATE_SETTLE_TIME) {
3467 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3468 } else {
3469 ret = ANEG_TIMER_ENAB;
3470 }
3471 break;
3472
3473 case ANEG_STATE_DISABLE_LINK_OK:
3474 ret = ANEG_DONE;
3475 break;
3476
3477 case ANEG_STATE_ABILITY_DETECT_INIT:
3478 ap->flags &= ~(MR_TOGGLE_TX);
3479 ap->txconfig = ANEG_CFG_FD;
3480 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3481 if (flowctrl & ADVERTISE_1000XPAUSE)
3482 ap->txconfig |= ANEG_CFG_PS1;
3483 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3484 ap->txconfig |= ANEG_CFG_PS2;
3485 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3486 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3487 tw32_f(MAC_MODE, tp->mac_mode);
3488 udelay(40);
3489
3490 ap->state = ANEG_STATE_ABILITY_DETECT;
3491 break;
3492
3493 case ANEG_STATE_ABILITY_DETECT:
3494 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3495 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3496 }
3497 break;
3498
3499 case ANEG_STATE_ACK_DETECT_INIT:
3500 ap->txconfig |= ANEG_CFG_ACK;
3501 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3502 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3503 tw32_f(MAC_MODE, tp->mac_mode);
3504 udelay(40);
3505
3506 ap->state = ANEG_STATE_ACK_DETECT;
3507
3508 /* fallthru */
3509 case ANEG_STATE_ACK_DETECT:
3510 if (ap->ack_match != 0) {
3511 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3512 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3513 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3514 } else {
3515 ap->state = ANEG_STATE_AN_ENABLE;
3516 }
3517 } else if (ap->ability_match != 0 &&
3518 ap->rxconfig == 0) {
3519 ap->state = ANEG_STATE_AN_ENABLE;
3520 }
3521 break;
3522
3523 case ANEG_STATE_COMPLETE_ACK_INIT:
3524 if (ap->rxconfig & ANEG_CFG_INVAL) {
3525 ret = ANEG_FAILED;
3526 break;
3527 }
3528 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3529 MR_LP_ADV_HALF_DUPLEX |
3530 MR_LP_ADV_SYM_PAUSE |
3531 MR_LP_ADV_ASYM_PAUSE |
3532 MR_LP_ADV_REMOTE_FAULT1 |
3533 MR_LP_ADV_REMOTE_FAULT2 |
3534 MR_LP_ADV_NEXT_PAGE |
3535 MR_TOGGLE_RX |
3536 MR_NP_RX);
3537 if (ap->rxconfig & ANEG_CFG_FD)
3538 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3539 if (ap->rxconfig & ANEG_CFG_HD)
3540 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3541 if (ap->rxconfig & ANEG_CFG_PS1)
3542 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3543 if (ap->rxconfig & ANEG_CFG_PS2)
3544 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3545 if (ap->rxconfig & ANEG_CFG_RF1)
3546 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3547 if (ap->rxconfig & ANEG_CFG_RF2)
3548 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3549 if (ap->rxconfig & ANEG_CFG_NP)
3550 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3551
3552 ap->link_time = ap->cur_time;
3553
3554 ap->flags ^= (MR_TOGGLE_TX);
3555 if (ap->rxconfig & 0x0008)
3556 ap->flags |= MR_TOGGLE_RX;
3557 if (ap->rxconfig & ANEG_CFG_NP)
3558 ap->flags |= MR_NP_RX;
3559 ap->flags |= MR_PAGE_RX;
3560
3561 ap->state = ANEG_STATE_COMPLETE_ACK;
3562 ret = ANEG_TIMER_ENAB;
3563 break;
3564
3565 case ANEG_STATE_COMPLETE_ACK:
3566 if (ap->ability_match != 0 &&
3567 ap->rxconfig == 0) {
3568 ap->state = ANEG_STATE_AN_ENABLE;
3569 break;
3570 }
3571 delta = ap->cur_time - ap->link_time;
3572 if (delta > ANEG_STATE_SETTLE_TIME) {
3573 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3574 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3575 } else {
3576 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3577 !(ap->flags & MR_NP_RX)) {
3578 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3579 } else {
3580 ret = ANEG_FAILED;
3581 }
3582 }
3583 }
3584 break;
3585
3586 case ANEG_STATE_IDLE_DETECT_INIT:
3587 ap->link_time = ap->cur_time;
3588 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3589 tw32_f(MAC_MODE, tp->mac_mode);
3590 udelay(40);
3591
3592 ap->state = ANEG_STATE_IDLE_DETECT;
3593 ret = ANEG_TIMER_ENAB;
3594 break;
3595
3596 case ANEG_STATE_IDLE_DETECT:
3597 if (ap->ability_match != 0 &&
3598 ap->rxconfig == 0) {
3599 ap->state = ANEG_STATE_AN_ENABLE;
3600 break;
3601 }
3602 delta = ap->cur_time - ap->link_time;
3603 if (delta > ANEG_STATE_SETTLE_TIME) {
3604 /* XXX another gem from the Broadcom driver :( */
3605 ap->state = ANEG_STATE_LINK_OK;
3606 }
3607 break;
3608
3609 case ANEG_STATE_LINK_OK:
3610 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3611 ret = ANEG_DONE;
3612 break;
3613
3614 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3615 /* ??? unimplemented */
3616 break;
3617
3618 case ANEG_STATE_NEXT_PAGE_WAIT:
3619 /* ??? unimplemented */
3620 break;
3621
3622 default:
3623 ret = ANEG_FAILED;
3624 break;
3625 }
3626
3627 return ret;
3628 }
3629
3630 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3631 {
3632 int res = 0;
3633 struct tg3_fiber_aneginfo aninfo;
3634 int status = ANEG_FAILED;
3635 unsigned int tick;
3636 u32 tmp;
3637
3638 tw32_f(MAC_TX_AUTO_NEG, 0);
3639
3640 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3641 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3642 udelay(40);
3643
3644 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3645 udelay(40);
3646
3647 memset(&aninfo, 0, sizeof(aninfo));
3648 aninfo.flags |= MR_AN_ENABLE;
3649 aninfo.state = ANEG_STATE_UNKNOWN;
3650 aninfo.cur_time = 0;
3651 tick = 0;
3652 while (++tick < 195000) {
3653 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3654 if (status == ANEG_DONE || status == ANEG_FAILED)
3655 break;
3656
3657 udelay(1);
3658 }
3659
3660 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3661 tw32_f(MAC_MODE, tp->mac_mode);
3662 udelay(40);
3663
3664 *txflags = aninfo.txconfig;
3665 *rxflags = aninfo.flags;
3666
3667 if (status == ANEG_DONE &&
3668 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3669 MR_LP_ADV_FULL_DUPLEX)))
3670 res = 1;
3671
3672 return res;
3673 }
3674
3675 static void tg3_init_bcm8002(struct tg3 *tp)
3676 {
3677 u32 mac_status = tr32(MAC_STATUS);
3678 int i;
3679
3680 /* Reset when initting first time or we have a link. */
3681 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3682 !(mac_status & MAC_STATUS_PCS_SYNCED))
3683 return;
3684
3685 /* Set PLL lock range. */
3686 tg3_writephy(tp, 0x16, 0x8007);
3687
3688 /* SW reset */
3689 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3690
3691 /* Wait for reset to complete. */
3692 /* XXX schedule_timeout() ... */
3693 for (i = 0; i < 500; i++)
3694 udelay(10);
3695
3696 /* Config mode; select PMA/Ch 1 regs. */
3697 tg3_writephy(tp, 0x10, 0x8411);
3698
3699 /* Enable auto-lock and comdet, select txclk for tx. */
3700 tg3_writephy(tp, 0x11, 0x0a10);
3701
3702 tg3_writephy(tp, 0x18, 0x00a0);
3703 tg3_writephy(tp, 0x16, 0x41ff);
3704
3705 /* Assert and deassert POR. */
3706 tg3_writephy(tp, 0x13, 0x0400);
3707 udelay(40);
3708 tg3_writephy(tp, 0x13, 0x0000);
3709
3710 tg3_writephy(tp, 0x11, 0x0a50);
3711 udelay(40);
3712 tg3_writephy(tp, 0x11, 0x0a10);
3713
3714 /* Wait for signal to stabilize */
3715 /* XXX schedule_timeout() ... */
3716 for (i = 0; i < 15000; i++)
3717 udelay(10);
3718
3719 /* Deselect the channel register so we can read the PHYID
3720 * later.
3721 */
3722 tg3_writephy(tp, 0x10, 0x8011);
3723 }
3724
3725 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3726 {
3727 u16 flowctrl;
3728 u32 sg_dig_ctrl, sg_dig_status;
3729 u32 serdes_cfg, expected_sg_dig_ctrl;
3730 int workaround, port_a;
3731 int current_link_up;
3732
3733 serdes_cfg = 0;
3734 expected_sg_dig_ctrl = 0;
3735 workaround = 0;
3736 port_a = 1;
3737 current_link_up = 0;
3738
3739 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3740 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3741 workaround = 1;
3742 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3743 port_a = 0;
3744
3745 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3746 /* preserve bits 20-23 for voltage regulator */
3747 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3748 }
3749
3750 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3751
3752 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3753 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3754 if (workaround) {
3755 u32 val = serdes_cfg;
3756
3757 if (port_a)
3758 val |= 0xc010000;
3759 else
3760 val |= 0x4010000;
3761 tw32_f(MAC_SERDES_CFG, val);
3762 }
3763
3764 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3765 }
3766 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3767 tg3_setup_flow_control(tp, 0, 0);
3768 current_link_up = 1;
3769 }
3770 goto out;
3771 }
3772
3773 /* Want auto-negotiation. */
3774 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3775
3776 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3777 if (flowctrl & ADVERTISE_1000XPAUSE)
3778 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3779 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3780 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3781
3782 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3783 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3784 tp->serdes_counter &&
3785 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3786 MAC_STATUS_RCVD_CFG)) ==
3787 MAC_STATUS_PCS_SYNCED)) {
3788 tp->serdes_counter--;
3789 current_link_up = 1;
3790 goto out;
3791 }
3792 restart_autoneg:
3793 if (workaround)
3794 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3795 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3796 udelay(5);
3797 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3798
3799 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3800 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3801 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3802 MAC_STATUS_SIGNAL_DET)) {
3803 sg_dig_status = tr32(SG_DIG_STATUS);
3804 mac_status = tr32(MAC_STATUS);
3805
3806 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3807 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3808 u32 local_adv = 0, remote_adv = 0;
3809
3810 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3811 local_adv |= ADVERTISE_1000XPAUSE;
3812 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3813 local_adv |= ADVERTISE_1000XPSE_ASYM;
3814
3815 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3816 remote_adv |= LPA_1000XPAUSE;
3817 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3818 remote_adv |= LPA_1000XPAUSE_ASYM;
3819
3820 tg3_setup_flow_control(tp, local_adv, remote_adv);
3821 current_link_up = 1;
3822 tp->serdes_counter = 0;
3823 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3824 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3825 if (tp->serdes_counter)
3826 tp->serdes_counter--;
3827 else {
3828 if (workaround) {
3829 u32 val = serdes_cfg;
3830
3831 if (port_a)
3832 val |= 0xc010000;
3833 else
3834 val |= 0x4010000;
3835
3836 tw32_f(MAC_SERDES_CFG, val);
3837 }
3838
3839 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3840 udelay(40);
3841
3842 /* Link parallel detection - link is up */
3843 /* only if we have PCS_SYNC and not */
3844 /* receiving config code words */
3845 mac_status = tr32(MAC_STATUS);
3846 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3847 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3848 tg3_setup_flow_control(tp, 0, 0);
3849 current_link_up = 1;
3850 tp->tg3_flags2 |=
3851 TG3_FLG2_PARALLEL_DETECT;
3852 tp->serdes_counter =
3853 SERDES_PARALLEL_DET_TIMEOUT;
3854 } else
3855 goto restart_autoneg;
3856 }
3857 }
3858 } else {
3859 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3860 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3861 }
3862
3863 out:
3864 return current_link_up;
3865 }
3866
3867 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3868 {
3869 int current_link_up = 0;
3870
3871 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3872 goto out;
3873
3874 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3875 u32 txflags, rxflags;
3876 int i;
3877
3878 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3879 u32 local_adv = 0, remote_adv = 0;
3880
3881 if (txflags & ANEG_CFG_PS1)
3882 local_adv |= ADVERTISE_1000XPAUSE;
3883 if (txflags & ANEG_CFG_PS2)
3884 local_adv |= ADVERTISE_1000XPSE_ASYM;
3885
3886 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3887 remote_adv |= LPA_1000XPAUSE;
3888 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3889 remote_adv |= LPA_1000XPAUSE_ASYM;
3890
3891 tg3_setup_flow_control(tp, local_adv, remote_adv);
3892
3893 current_link_up = 1;
3894 }
3895 for (i = 0; i < 30; i++) {
3896 udelay(20);
3897 tw32_f(MAC_STATUS,
3898 (MAC_STATUS_SYNC_CHANGED |
3899 MAC_STATUS_CFG_CHANGED));
3900 udelay(40);
3901 if ((tr32(MAC_STATUS) &
3902 (MAC_STATUS_SYNC_CHANGED |
3903 MAC_STATUS_CFG_CHANGED)) == 0)
3904 break;
3905 }
3906
3907 mac_status = tr32(MAC_STATUS);
3908 if (current_link_up == 0 &&
3909 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3910 !(mac_status & MAC_STATUS_RCVD_CFG))
3911 current_link_up = 1;
3912 } else {
3913 tg3_setup_flow_control(tp, 0, 0);
3914
3915 /* Forcing 1000FD link up. */
3916 current_link_up = 1;
3917
3918 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3919 udelay(40);
3920
3921 tw32_f(MAC_MODE, tp->mac_mode);
3922 udelay(40);
3923 }
3924
3925 out:
3926 return current_link_up;
3927 }
3928
3929 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3930 {
3931 u32 orig_pause_cfg;
3932 u16 orig_active_speed;
3933 u8 orig_active_duplex;
3934 u32 mac_status;
3935 int current_link_up;
3936 int i;
3937
3938 orig_pause_cfg = tp->link_config.active_flowctrl;
3939 orig_active_speed = tp->link_config.active_speed;
3940 orig_active_duplex = tp->link_config.active_duplex;
3941
3942 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3943 netif_carrier_ok(tp->dev) &&
3944 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3945 mac_status = tr32(MAC_STATUS);
3946 mac_status &= (MAC_STATUS_PCS_SYNCED |
3947 MAC_STATUS_SIGNAL_DET |
3948 MAC_STATUS_CFG_CHANGED |
3949 MAC_STATUS_RCVD_CFG);
3950 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3951 MAC_STATUS_SIGNAL_DET)) {
3952 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3953 MAC_STATUS_CFG_CHANGED));
3954 return 0;
3955 }
3956 }
3957
3958 tw32_f(MAC_TX_AUTO_NEG, 0);
3959
3960 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3961 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3962 tw32_f(MAC_MODE, tp->mac_mode);
3963 udelay(40);
3964
3965 if (tp->phy_id == TG3_PHY_ID_BCM8002)
3966 tg3_init_bcm8002(tp);
3967
3968 /* Enable link change event even when serdes polling. */
3969 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3970 udelay(40);
3971
3972 current_link_up = 0;
3973 mac_status = tr32(MAC_STATUS);
3974
3975 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3976 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3977 else
3978 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3979
3980 tp->napi[0].hw_status->status =
3981 (SD_STATUS_UPDATED |
3982 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3983
3984 for (i = 0; i < 100; i++) {
3985 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3986 MAC_STATUS_CFG_CHANGED));
3987 udelay(5);
3988 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3989 MAC_STATUS_CFG_CHANGED |
3990 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3991 break;
3992 }
3993
3994 mac_status = tr32(MAC_STATUS);
3995 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3996 current_link_up = 0;
3997 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3998 tp->serdes_counter == 0) {
3999 tw32_f(MAC_MODE, (tp->mac_mode |
4000 MAC_MODE_SEND_CONFIGS));
4001 udelay(1);
4002 tw32_f(MAC_MODE, tp->mac_mode);
4003 }
4004 }
4005
4006 if (current_link_up == 1) {
4007 tp->link_config.active_speed = SPEED_1000;
4008 tp->link_config.active_duplex = DUPLEX_FULL;
4009 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4010 LED_CTRL_LNKLED_OVERRIDE |
4011 LED_CTRL_1000MBPS_ON));
4012 } else {
4013 tp->link_config.active_speed = SPEED_INVALID;
4014 tp->link_config.active_duplex = DUPLEX_INVALID;
4015 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4016 LED_CTRL_LNKLED_OVERRIDE |
4017 LED_CTRL_TRAFFIC_OVERRIDE));
4018 }
4019
4020 if (current_link_up != netif_carrier_ok(tp->dev)) {
4021 if (current_link_up)
4022 netif_carrier_on(tp->dev);
4023 else
4024 netif_carrier_off(tp->dev);
4025 tg3_link_report(tp);
4026 } else {
4027 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4028 if (orig_pause_cfg != now_pause_cfg ||
4029 orig_active_speed != tp->link_config.active_speed ||
4030 orig_active_duplex != tp->link_config.active_duplex)
4031 tg3_link_report(tp);
4032 }
4033
4034 return 0;
4035 }
4036
4037 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4038 {
4039 int current_link_up, err = 0;
4040 u32 bmsr, bmcr;
4041 u16 current_speed;
4042 u8 current_duplex;
4043 u32 local_adv, remote_adv;
4044
4045 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4046 tw32_f(MAC_MODE, tp->mac_mode);
4047 udelay(40);
4048
4049 tw32(MAC_EVENT, 0);
4050
4051 tw32_f(MAC_STATUS,
4052 (MAC_STATUS_SYNC_CHANGED |
4053 MAC_STATUS_CFG_CHANGED |
4054 MAC_STATUS_MI_COMPLETION |
4055 MAC_STATUS_LNKSTATE_CHANGED));
4056 udelay(40);
4057
4058 if (force_reset)
4059 tg3_phy_reset(tp);
4060
4061 current_link_up = 0;
4062 current_speed = SPEED_INVALID;
4063 current_duplex = DUPLEX_INVALID;
4064
4065 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4066 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4067 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4068 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4069 bmsr |= BMSR_LSTATUS;
4070 else
4071 bmsr &= ~BMSR_LSTATUS;
4072 }
4073
4074 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4075
4076 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4077 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4078 /* do nothing, just check for link up at the end */
4079 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4080 u32 adv, new_adv;
4081
4082 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4083 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4084 ADVERTISE_1000XPAUSE |
4085 ADVERTISE_1000XPSE_ASYM |
4086 ADVERTISE_SLCT);
4087
4088 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4089
4090 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4091 new_adv |= ADVERTISE_1000XHALF;
4092 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4093 new_adv |= ADVERTISE_1000XFULL;
4094
4095 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4096 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4097 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4098 tg3_writephy(tp, MII_BMCR, bmcr);
4099
4100 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4101 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4102 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4103
4104 return err;
4105 }
4106 } else {
4107 u32 new_bmcr;
4108
4109 bmcr &= ~BMCR_SPEED1000;
4110 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4111
4112 if (tp->link_config.duplex == DUPLEX_FULL)
4113 new_bmcr |= BMCR_FULLDPLX;
4114
4115 if (new_bmcr != bmcr) {
4116 /* BMCR_SPEED1000 is a reserved bit that needs
4117 * to be set on write.
4118 */
4119 new_bmcr |= BMCR_SPEED1000;
4120
4121 /* Force a linkdown */
4122 if (netif_carrier_ok(tp->dev)) {
4123 u32 adv;
4124
4125 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4126 adv &= ~(ADVERTISE_1000XFULL |
4127 ADVERTISE_1000XHALF |
4128 ADVERTISE_SLCT);
4129 tg3_writephy(tp, MII_ADVERTISE, adv);
4130 tg3_writephy(tp, MII_BMCR, bmcr |
4131 BMCR_ANRESTART |
4132 BMCR_ANENABLE);
4133 udelay(10);
4134 netif_carrier_off(tp->dev);
4135 }
4136 tg3_writephy(tp, MII_BMCR, new_bmcr);
4137 bmcr = new_bmcr;
4138 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4139 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4140 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4141 ASIC_REV_5714) {
4142 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4143 bmsr |= BMSR_LSTATUS;
4144 else
4145 bmsr &= ~BMSR_LSTATUS;
4146 }
4147 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4148 }
4149 }
4150
4151 if (bmsr & BMSR_LSTATUS) {
4152 current_speed = SPEED_1000;
4153 current_link_up = 1;
4154 if (bmcr & BMCR_FULLDPLX)
4155 current_duplex = DUPLEX_FULL;
4156 else
4157 current_duplex = DUPLEX_HALF;
4158
4159 local_adv = 0;
4160 remote_adv = 0;
4161
4162 if (bmcr & BMCR_ANENABLE) {
4163 u32 common;
4164
4165 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4166 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4167 common = local_adv & remote_adv;
4168 if (common & (ADVERTISE_1000XHALF |
4169 ADVERTISE_1000XFULL)) {
4170 if (common & ADVERTISE_1000XFULL)
4171 current_duplex = DUPLEX_FULL;
4172 else
4173 current_duplex = DUPLEX_HALF;
4174 }
4175 else
4176 current_link_up = 0;
4177 }
4178 }
4179
4180 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4181 tg3_setup_flow_control(tp, local_adv, remote_adv);
4182
4183 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4184 if (tp->link_config.active_duplex == DUPLEX_HALF)
4185 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4186
4187 tw32_f(MAC_MODE, tp->mac_mode);
4188 udelay(40);
4189
4190 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4191
4192 tp->link_config.active_speed = current_speed;
4193 tp->link_config.active_duplex = current_duplex;
4194
4195 if (current_link_up != netif_carrier_ok(tp->dev)) {
4196 if (current_link_up)
4197 netif_carrier_on(tp->dev);
4198 else {
4199 netif_carrier_off(tp->dev);
4200 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4201 }
4202 tg3_link_report(tp);
4203 }
4204 return err;
4205 }
4206
4207 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4208 {
4209 if (tp->serdes_counter) {
4210 /* Give autoneg time to complete. */
4211 tp->serdes_counter--;
4212 return;
4213 }
4214 if (!netif_carrier_ok(tp->dev) &&
4215 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4216 u32 bmcr;
4217
4218 tg3_readphy(tp, MII_BMCR, &bmcr);
4219 if (bmcr & BMCR_ANENABLE) {
4220 u32 phy1, phy2;
4221
4222 /* Select shadow register 0x1f */
4223 tg3_writephy(tp, 0x1c, 0x7c00);
4224 tg3_readphy(tp, 0x1c, &phy1);
4225
4226 /* Select expansion interrupt status register */
4227 tg3_writephy(tp, 0x17, 0x0f01);
4228 tg3_readphy(tp, 0x15, &phy2);
4229 tg3_readphy(tp, 0x15, &phy2);
4230
4231 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4232 /* We have signal detect and not receiving
4233 * config code words, link is up by parallel
4234 * detection.
4235 */
4236
4237 bmcr &= ~BMCR_ANENABLE;
4238 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4239 tg3_writephy(tp, MII_BMCR, bmcr);
4240 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4241 }
4242 }
4243 }
4244 else if (netif_carrier_ok(tp->dev) &&
4245 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4246 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4247 u32 phy2;
4248
4249 /* Select expansion interrupt status register */
4250 tg3_writephy(tp, 0x17, 0x0f01);
4251 tg3_readphy(tp, 0x15, &phy2);
4252 if (phy2 & 0x20) {
4253 u32 bmcr;
4254
4255 /* Config code words received, turn on autoneg. */
4256 tg3_readphy(tp, MII_BMCR, &bmcr);
4257 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4258
4259 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4260
4261 }
4262 }
4263 }
4264
4265 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4266 {
4267 int err;
4268
4269 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4270 err = tg3_setup_fiber_phy(tp, force_reset);
4271 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4272 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4273 } else {
4274 err = tg3_setup_copper_phy(tp, force_reset);
4275 }
4276
4277 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4278 u32 val, scale;
4279
4280 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4281 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4282 scale = 65;
4283 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4284 scale = 6;
4285 else
4286 scale = 12;
4287
4288 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4289 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4290 tw32(GRC_MISC_CFG, val);
4291 }
4292
4293 if (tp->link_config.active_speed == SPEED_1000 &&
4294 tp->link_config.active_duplex == DUPLEX_HALF)
4295 tw32(MAC_TX_LENGTHS,
4296 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4297 (6 << TX_LENGTHS_IPG_SHIFT) |
4298 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4299 else
4300 tw32(MAC_TX_LENGTHS,
4301 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4302 (6 << TX_LENGTHS_IPG_SHIFT) |
4303 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4304
4305 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4306 if (netif_carrier_ok(tp->dev)) {
4307 tw32(HOSTCC_STAT_COAL_TICKS,
4308 tp->coal.stats_block_coalesce_usecs);
4309 } else {
4310 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4311 }
4312 }
4313
4314 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4315 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4316 if (!netif_carrier_ok(tp->dev))
4317 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4318 tp->pwrmgmt_thresh;
4319 else
4320 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4321 tw32(PCIE_PWR_MGMT_THRESH, val);
4322 }
4323
4324 return err;
4325 }
4326
4327 /* This is called whenever we suspect that the system chipset is re-
4328 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4329 * is bogus tx completions. We try to recover by setting the
4330 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4331 * in the workqueue.
4332 */
4333 static void tg3_tx_recover(struct tg3 *tp)
4334 {
4335 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4336 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4337
4338 netdev_warn(tp->dev, "The system may be re-ordering memory-mapped I/O cycles to the network device, attempting to recover\n"
4339 "Please report the problem to the driver maintainer and include system chipset information.\n");
4340
4341 spin_lock(&tp->lock);
4342 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4343 spin_unlock(&tp->lock);
4344 }
4345
4346 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4347 {
4348 smp_mb();
4349 return tnapi->tx_pending -
4350 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4351 }
4352
4353 /* Tigon3 never reports partial packet sends. So we do not
4354 * need special logic to handle SKBs that have not had all
4355 * of their frags sent yet, like SunGEM does.
4356 */
4357 static void tg3_tx(struct tg3_napi *tnapi)
4358 {
4359 struct tg3 *tp = tnapi->tp;
4360 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4361 u32 sw_idx = tnapi->tx_cons;
4362 struct netdev_queue *txq;
4363 int index = tnapi - tp->napi;
4364
4365 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4366 index--;
4367
4368 txq = netdev_get_tx_queue(tp->dev, index);
4369
4370 while (sw_idx != hw_idx) {
4371 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4372 struct sk_buff *skb = ri->skb;
4373 int i, tx_bug = 0;
4374
4375 if (unlikely(skb == NULL)) {
4376 tg3_tx_recover(tp);
4377 return;
4378 }
4379
4380 pci_unmap_single(tp->pdev,
4381 pci_unmap_addr(ri, mapping),
4382 skb_headlen(skb),
4383 PCI_DMA_TODEVICE);
4384
4385 ri->skb = NULL;
4386
4387 sw_idx = NEXT_TX(sw_idx);
4388
4389 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4390 ri = &tnapi->tx_buffers[sw_idx];
4391 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4392 tx_bug = 1;
4393
4394 pci_unmap_page(tp->pdev,
4395 pci_unmap_addr(ri, mapping),
4396 skb_shinfo(skb)->frags[i].size,
4397 PCI_DMA_TODEVICE);
4398 sw_idx = NEXT_TX(sw_idx);
4399 }
4400
4401 dev_kfree_skb(skb);
4402
4403 if (unlikely(tx_bug)) {
4404 tg3_tx_recover(tp);
4405 return;
4406 }
4407 }
4408
4409 tnapi->tx_cons = sw_idx;
4410
4411 /* Need to make the tx_cons update visible to tg3_start_xmit()
4412 * before checking for netif_queue_stopped(). Without the
4413 * memory barrier, there is a small possibility that tg3_start_xmit()
4414 * will miss it and cause the queue to be stopped forever.
4415 */
4416 smp_mb();
4417
4418 if (unlikely(netif_tx_queue_stopped(txq) &&
4419 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4420 __netif_tx_lock(txq, smp_processor_id());
4421 if (netif_tx_queue_stopped(txq) &&
4422 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4423 netif_tx_wake_queue(txq);
4424 __netif_tx_unlock(txq);
4425 }
4426 }
4427
4428 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4429 {
4430 if (!ri->skb)
4431 return;
4432
4433 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4434 map_sz, PCI_DMA_FROMDEVICE);
4435 dev_kfree_skb_any(ri->skb);
4436 ri->skb = NULL;
4437 }
4438
4439 /* Returns size of skb allocated or < 0 on error.
4440 *
4441 * We only need to fill in the address because the other members
4442 * of the RX descriptor are invariant, see tg3_init_rings.
4443 *
4444 * Note the purposeful assymetry of cpu vs. chip accesses. For
4445 * posting buffers we only dirty the first cache line of the RX
4446 * descriptor (containing the address). Whereas for the RX status
4447 * buffers the cpu only reads the last cacheline of the RX descriptor
4448 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4449 */
4450 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4451 u32 opaque_key, u32 dest_idx_unmasked)
4452 {
4453 struct tg3_rx_buffer_desc *desc;
4454 struct ring_info *map, *src_map;
4455 struct sk_buff *skb;
4456 dma_addr_t mapping;
4457 int skb_size, dest_idx;
4458
4459 src_map = NULL;
4460 switch (opaque_key) {
4461 case RXD_OPAQUE_RING_STD:
4462 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4463 desc = &tpr->rx_std[dest_idx];
4464 map = &tpr->rx_std_buffers[dest_idx];
4465 skb_size = tp->rx_pkt_map_sz;
4466 break;
4467
4468 case RXD_OPAQUE_RING_JUMBO:
4469 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4470 desc = &tpr->rx_jmb[dest_idx].std;
4471 map = &tpr->rx_jmb_buffers[dest_idx];
4472 skb_size = TG3_RX_JMB_MAP_SZ;
4473 break;
4474
4475 default:
4476 return -EINVAL;
4477 }
4478
4479 /* Do not overwrite any of the map or rp information
4480 * until we are sure we can commit to a new buffer.
4481 *
4482 * Callers depend upon this behavior and assume that
4483 * we leave everything unchanged if we fail.
4484 */
4485 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4486 if (skb == NULL)
4487 return -ENOMEM;
4488
4489 skb_reserve(skb, tp->rx_offset);
4490
4491 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4492 PCI_DMA_FROMDEVICE);
4493 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4494 dev_kfree_skb(skb);
4495 return -EIO;
4496 }
4497
4498 map->skb = skb;
4499 pci_unmap_addr_set(map, mapping, mapping);
4500
4501 desc->addr_hi = ((u64)mapping >> 32);
4502 desc->addr_lo = ((u64)mapping & 0xffffffff);
4503
4504 return skb_size;
4505 }
4506
4507 /* We only need to move over in the address because the other
4508 * members of the RX descriptor are invariant. See notes above
4509 * tg3_alloc_rx_skb for full details.
4510 */
4511 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4512 struct tg3_rx_prodring_set *dpr,
4513 u32 opaque_key, int src_idx,
4514 u32 dest_idx_unmasked)
4515 {
4516 struct tg3 *tp = tnapi->tp;
4517 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4518 struct ring_info *src_map, *dest_map;
4519 int dest_idx;
4520 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4521
4522 switch (opaque_key) {
4523 case RXD_OPAQUE_RING_STD:
4524 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4525 dest_desc = &dpr->rx_std[dest_idx];
4526 dest_map = &dpr->rx_std_buffers[dest_idx];
4527 src_desc = &spr->rx_std[src_idx];
4528 src_map = &spr->rx_std_buffers[src_idx];
4529 break;
4530
4531 case RXD_OPAQUE_RING_JUMBO:
4532 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4533 dest_desc = &dpr->rx_jmb[dest_idx].std;
4534 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4535 src_desc = &spr->rx_jmb[src_idx].std;
4536 src_map = &spr->rx_jmb_buffers[src_idx];
4537 break;
4538
4539 default:
4540 return;
4541 }
4542
4543 dest_map->skb = src_map->skb;
4544 pci_unmap_addr_set(dest_map, mapping,
4545 pci_unmap_addr(src_map, mapping));
4546 dest_desc->addr_hi = src_desc->addr_hi;
4547 dest_desc->addr_lo = src_desc->addr_lo;
4548
4549 /* Ensure that the update to the skb happens after the physical
4550 * addresses have been transferred to the new BD location.
4551 */
4552 smp_wmb();
4553
4554 src_map->skb = NULL;
4555 }
4556
4557 /* The RX ring scheme is composed of multiple rings which post fresh
4558 * buffers to the chip, and one special ring the chip uses to report
4559 * status back to the host.
4560 *
4561 * The special ring reports the status of received packets to the
4562 * host. The chip does not write into the original descriptor the
4563 * RX buffer was obtained from. The chip simply takes the original
4564 * descriptor as provided by the host, updates the status and length
4565 * field, then writes this into the next status ring entry.
4566 *
4567 * Each ring the host uses to post buffers to the chip is described
4568 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4569 * it is first placed into the on-chip ram. When the packet's length
4570 * is known, it walks down the TG3_BDINFO entries to select the ring.
4571 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4572 * which is within the range of the new packet's length is chosen.
4573 *
4574 * The "separate ring for rx status" scheme may sound queer, but it makes
4575 * sense from a cache coherency perspective. If only the host writes
4576 * to the buffer post rings, and only the chip writes to the rx status
4577 * rings, then cache lines never move beyond shared-modified state.
4578 * If both the host and chip were to write into the same ring, cache line
4579 * eviction could occur since both entities want it in an exclusive state.
4580 */
4581 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4582 {
4583 struct tg3 *tp = tnapi->tp;
4584 u32 work_mask, rx_std_posted = 0;
4585 u32 std_prod_idx, jmb_prod_idx;
4586 u32 sw_idx = tnapi->rx_rcb_ptr;
4587 u16 hw_idx;
4588 int received;
4589 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4590
4591 hw_idx = *(tnapi->rx_rcb_prod_idx);
4592 /*
4593 * We need to order the read of hw_idx and the read of
4594 * the opaque cookie.
4595 */
4596 rmb();
4597 work_mask = 0;
4598 received = 0;
4599 std_prod_idx = tpr->rx_std_prod_idx;
4600 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4601 while (sw_idx != hw_idx && budget > 0) {
4602 struct ring_info *ri;
4603 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4604 unsigned int len;
4605 struct sk_buff *skb;
4606 dma_addr_t dma_addr;
4607 u32 opaque_key, desc_idx, *post_ptr;
4608
4609 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4610 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4611 if (opaque_key == RXD_OPAQUE_RING_STD) {
4612 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4613 dma_addr = pci_unmap_addr(ri, mapping);
4614 skb = ri->skb;
4615 post_ptr = &std_prod_idx;
4616 rx_std_posted++;
4617 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4618 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4619 dma_addr = pci_unmap_addr(ri, mapping);
4620 skb = ri->skb;
4621 post_ptr = &jmb_prod_idx;
4622 } else
4623 goto next_pkt_nopost;
4624
4625 work_mask |= opaque_key;
4626
4627 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4628 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4629 drop_it:
4630 tg3_recycle_rx(tnapi, tpr, opaque_key,
4631 desc_idx, *post_ptr);
4632 drop_it_no_recycle:
4633 /* Other statistics kept track of by card. */
4634 tp->net_stats.rx_dropped++;
4635 goto next_pkt;
4636 }
4637
4638 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4639 ETH_FCS_LEN;
4640
4641 if (len > RX_COPY_THRESHOLD &&
4642 tp->rx_offset == NET_IP_ALIGN) {
4643 /* rx_offset will likely not equal NET_IP_ALIGN
4644 * if this is a 5701 card running in PCI-X mode
4645 * [see tg3_get_invariants()]
4646 */
4647 int skb_size;
4648
4649 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4650 *post_ptr);
4651 if (skb_size < 0)
4652 goto drop_it;
4653
4654 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4655 PCI_DMA_FROMDEVICE);
4656
4657 /* Ensure that the update to the skb happens
4658 * after the usage of the old DMA mapping.
4659 */
4660 smp_wmb();
4661
4662 ri->skb = NULL;
4663
4664 skb_put(skb, len);
4665 } else {
4666 struct sk_buff *copy_skb;
4667
4668 tg3_recycle_rx(tnapi, tpr, opaque_key,
4669 desc_idx, *post_ptr);
4670
4671 copy_skb = netdev_alloc_skb(tp->dev,
4672 len + TG3_RAW_IP_ALIGN);
4673 if (copy_skb == NULL)
4674 goto drop_it_no_recycle;
4675
4676 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4677 skb_put(copy_skb, len);
4678 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4679 skb_copy_from_linear_data(skb, copy_skb->data, len);
4680 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4681
4682 /* We'll reuse the original ring buffer. */
4683 skb = copy_skb;
4684 }
4685
4686 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4687 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4688 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4689 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4690 skb->ip_summed = CHECKSUM_UNNECESSARY;
4691 else
4692 skb->ip_summed = CHECKSUM_NONE;
4693
4694 skb->protocol = eth_type_trans(skb, tp->dev);
4695
4696 if (len > (tp->dev->mtu + ETH_HLEN) &&
4697 skb->protocol != htons(ETH_P_8021Q)) {
4698 dev_kfree_skb(skb);
4699 goto next_pkt;
4700 }
4701
4702 #if TG3_VLAN_TAG_USED
4703 if (tp->vlgrp != NULL &&
4704 desc->type_flags & RXD_FLAG_VLAN) {
4705 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4706 desc->err_vlan & RXD_VLAN_MASK, skb);
4707 } else
4708 #endif
4709 napi_gro_receive(&tnapi->napi, skb);
4710
4711 received++;
4712 budget--;
4713
4714 next_pkt:
4715 (*post_ptr)++;
4716
4717 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4718 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4719 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4720 tpr->rx_std_prod_idx);
4721 work_mask &= ~RXD_OPAQUE_RING_STD;
4722 rx_std_posted = 0;
4723 }
4724 next_pkt_nopost:
4725 sw_idx++;
4726 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4727
4728 /* Refresh hw_idx to see if there is new work */
4729 if (sw_idx == hw_idx) {
4730 hw_idx = *(tnapi->rx_rcb_prod_idx);
4731 rmb();
4732 }
4733 }
4734
4735 /* ACK the status ring. */
4736 tnapi->rx_rcb_ptr = sw_idx;
4737 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4738
4739 /* Refill RX ring(s). */
4740 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4741 if (work_mask & RXD_OPAQUE_RING_STD) {
4742 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4743 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4744 tpr->rx_std_prod_idx);
4745 }
4746 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4747 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4748 TG3_RX_JUMBO_RING_SIZE;
4749 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4750 tpr->rx_jmb_prod_idx);
4751 }
4752 mmiowb();
4753 } else if (work_mask) {
4754 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4755 * updated before the producer indices can be updated.
4756 */
4757 smp_wmb();
4758
4759 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4760 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4761
4762 if (tnapi != &tp->napi[1])
4763 napi_schedule(&tp->napi[1].napi);
4764 }
4765
4766 return received;
4767 }
4768
4769 static void tg3_poll_link(struct tg3 *tp)
4770 {
4771 /* handle link change and other phy events */
4772 if (!(tp->tg3_flags &
4773 (TG3_FLAG_USE_LINKCHG_REG |
4774 TG3_FLAG_POLL_SERDES))) {
4775 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4776
4777 if (sblk->status & SD_STATUS_LINK_CHG) {
4778 sblk->status = SD_STATUS_UPDATED |
4779 (sblk->status & ~SD_STATUS_LINK_CHG);
4780 spin_lock(&tp->lock);
4781 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4782 tw32_f(MAC_STATUS,
4783 (MAC_STATUS_SYNC_CHANGED |
4784 MAC_STATUS_CFG_CHANGED |
4785 MAC_STATUS_MI_COMPLETION |
4786 MAC_STATUS_LNKSTATE_CHANGED));
4787 udelay(40);
4788 } else
4789 tg3_setup_phy(tp, 0);
4790 spin_unlock(&tp->lock);
4791 }
4792 }
4793 }
4794
4795 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4796 struct tg3_rx_prodring_set *dpr,
4797 struct tg3_rx_prodring_set *spr)
4798 {
4799 u32 si, di, cpycnt, src_prod_idx;
4800 int i, err = 0;
4801
4802 while (1) {
4803 src_prod_idx = spr->rx_std_prod_idx;
4804
4805 /* Make sure updates to the rx_std_buffers[] entries and the
4806 * standard producer index are seen in the correct order.
4807 */
4808 smp_rmb();
4809
4810 if (spr->rx_std_cons_idx == src_prod_idx)
4811 break;
4812
4813 if (spr->rx_std_cons_idx < src_prod_idx)
4814 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4815 else
4816 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4817
4818 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4819
4820 si = spr->rx_std_cons_idx;
4821 di = dpr->rx_std_prod_idx;
4822
4823 for (i = di; i < di + cpycnt; i++) {
4824 if (dpr->rx_std_buffers[i].skb) {
4825 cpycnt = i - di;
4826 err = -ENOSPC;
4827 break;
4828 }
4829 }
4830
4831 if (!cpycnt)
4832 break;
4833
4834 /* Ensure that updates to the rx_std_buffers ring and the
4835 * shadowed hardware producer ring from tg3_recycle_skb() are
4836 * ordered correctly WRT the skb check above.
4837 */
4838 smp_rmb();
4839
4840 memcpy(&dpr->rx_std_buffers[di],
4841 &spr->rx_std_buffers[si],
4842 cpycnt * sizeof(struct ring_info));
4843
4844 for (i = 0; i < cpycnt; i++, di++, si++) {
4845 struct tg3_rx_buffer_desc *sbd, *dbd;
4846 sbd = &spr->rx_std[si];
4847 dbd = &dpr->rx_std[di];
4848 dbd->addr_hi = sbd->addr_hi;
4849 dbd->addr_lo = sbd->addr_lo;
4850 }
4851
4852 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4853 TG3_RX_RING_SIZE;
4854 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4855 TG3_RX_RING_SIZE;
4856 }
4857
4858 while (1) {
4859 src_prod_idx = spr->rx_jmb_prod_idx;
4860
4861 /* Make sure updates to the rx_jmb_buffers[] entries and
4862 * the jumbo producer index are seen in the correct order.
4863 */
4864 smp_rmb();
4865
4866 if (spr->rx_jmb_cons_idx == src_prod_idx)
4867 break;
4868
4869 if (spr->rx_jmb_cons_idx < src_prod_idx)
4870 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4871 else
4872 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4873
4874 cpycnt = min(cpycnt,
4875 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4876
4877 si = spr->rx_jmb_cons_idx;
4878 di = dpr->rx_jmb_prod_idx;
4879
4880 for (i = di; i < di + cpycnt; i++) {
4881 if (dpr->rx_jmb_buffers[i].skb) {
4882 cpycnt = i - di;
4883 err = -ENOSPC;
4884 break;
4885 }
4886 }
4887
4888 if (!cpycnt)
4889 break;
4890
4891 /* Ensure that updates to the rx_jmb_buffers ring and the
4892 * shadowed hardware producer ring from tg3_recycle_skb() are
4893 * ordered correctly WRT the skb check above.
4894 */
4895 smp_rmb();
4896
4897 memcpy(&dpr->rx_jmb_buffers[di],
4898 &spr->rx_jmb_buffers[si],
4899 cpycnt * sizeof(struct ring_info));
4900
4901 for (i = 0; i < cpycnt; i++, di++, si++) {
4902 struct tg3_rx_buffer_desc *sbd, *dbd;
4903 sbd = &spr->rx_jmb[si].std;
4904 dbd = &dpr->rx_jmb[di].std;
4905 dbd->addr_hi = sbd->addr_hi;
4906 dbd->addr_lo = sbd->addr_lo;
4907 }
4908
4909 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4910 TG3_RX_JUMBO_RING_SIZE;
4911 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4912 TG3_RX_JUMBO_RING_SIZE;
4913 }
4914
4915 return err;
4916 }
4917
4918 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4919 {
4920 struct tg3 *tp = tnapi->tp;
4921
4922 /* run TX completion thread */
4923 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4924 tg3_tx(tnapi);
4925 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4926 return work_done;
4927 }
4928
4929 /* run RX thread, within the bounds set by NAPI.
4930 * All RX "locking" is done by ensuring outside
4931 * code synchronizes with tg3->napi.poll()
4932 */
4933 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4934 work_done += tg3_rx(tnapi, budget - work_done);
4935
4936 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4937 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4938 int i, err = 0;
4939 u32 std_prod_idx = dpr->rx_std_prod_idx;
4940 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4941
4942 for (i = 1; i < tp->irq_cnt; i++)
4943 err |= tg3_rx_prodring_xfer(tp, dpr,
4944 tp->napi[i].prodring);
4945
4946 wmb();
4947
4948 if (std_prod_idx != dpr->rx_std_prod_idx)
4949 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4950 dpr->rx_std_prod_idx);
4951
4952 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4953 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4954 dpr->rx_jmb_prod_idx);
4955
4956 mmiowb();
4957
4958 if (err)
4959 tw32_f(HOSTCC_MODE, tp->coal_now);
4960 }
4961
4962 return work_done;
4963 }
4964
4965 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4966 {
4967 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4968 struct tg3 *tp = tnapi->tp;
4969 int work_done = 0;
4970 struct tg3_hw_status *sblk = tnapi->hw_status;
4971
4972 while (1) {
4973 work_done = tg3_poll_work(tnapi, work_done, budget);
4974
4975 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4976 goto tx_recovery;
4977
4978 if (unlikely(work_done >= budget))
4979 break;
4980
4981 /* tp->last_tag is used in tg3_restart_ints() below
4982 * to tell the hw how much work has been processed,
4983 * so we must read it before checking for more work.
4984 */
4985 tnapi->last_tag = sblk->status_tag;
4986 tnapi->last_irq_tag = tnapi->last_tag;
4987 rmb();
4988
4989 /* check for RX/TX work to do */
4990 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4991 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4992 napi_complete(napi);
4993 /* Reenable interrupts. */
4994 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4995 mmiowb();
4996 break;
4997 }
4998 }
4999
5000 return work_done;
5001
5002 tx_recovery:
5003 /* work_done is guaranteed to be less than budget. */
5004 napi_complete(napi);
5005 schedule_work(&tp->reset_task);
5006 return work_done;
5007 }
5008
5009 static int tg3_poll(struct napi_struct *napi, int budget)
5010 {
5011 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5012 struct tg3 *tp = tnapi->tp;
5013 int work_done = 0;
5014 struct tg3_hw_status *sblk = tnapi->hw_status;
5015
5016 while (1) {
5017 tg3_poll_link(tp);
5018
5019 work_done = tg3_poll_work(tnapi, work_done, budget);
5020
5021 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5022 goto tx_recovery;
5023
5024 if (unlikely(work_done >= budget))
5025 break;
5026
5027 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5028 /* tp->last_tag is used in tg3_int_reenable() below
5029 * to tell the hw how much work has been processed,
5030 * so we must read it before checking for more work.
5031 */
5032 tnapi->last_tag = sblk->status_tag;
5033 tnapi->last_irq_tag = tnapi->last_tag;
5034 rmb();
5035 } else
5036 sblk->status &= ~SD_STATUS_UPDATED;
5037
5038 if (likely(!tg3_has_work(tnapi))) {
5039 napi_complete(napi);
5040 tg3_int_reenable(tnapi);
5041 break;
5042 }
5043 }
5044
5045 return work_done;
5046
5047 tx_recovery:
5048 /* work_done is guaranteed to be less than budget. */
5049 napi_complete(napi);
5050 schedule_work(&tp->reset_task);
5051 return work_done;
5052 }
5053
5054 static void tg3_irq_quiesce(struct tg3 *tp)
5055 {
5056 int i;
5057
5058 BUG_ON(tp->irq_sync);
5059
5060 tp->irq_sync = 1;
5061 smp_mb();
5062
5063 for (i = 0; i < tp->irq_cnt; i++)
5064 synchronize_irq(tp->napi[i].irq_vec);
5065 }
5066
5067 static inline int tg3_irq_sync(struct tg3 *tp)
5068 {
5069 return tp->irq_sync;
5070 }
5071
5072 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5073 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5074 * with as well. Most of the time, this is not necessary except when
5075 * shutting down the device.
5076 */
5077 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5078 {
5079 spin_lock_bh(&tp->lock);
5080 if (irq_sync)
5081 tg3_irq_quiesce(tp);
5082 }
5083
5084 static inline void tg3_full_unlock(struct tg3 *tp)
5085 {
5086 spin_unlock_bh(&tp->lock);
5087 }
5088
5089 /* One-shot MSI handler - Chip automatically disables interrupt
5090 * after sending MSI so driver doesn't have to do it.
5091 */
5092 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5093 {
5094 struct tg3_napi *tnapi = dev_id;
5095 struct tg3 *tp = tnapi->tp;
5096
5097 prefetch(tnapi->hw_status);
5098 if (tnapi->rx_rcb)
5099 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5100
5101 if (likely(!tg3_irq_sync(tp)))
5102 napi_schedule(&tnapi->napi);
5103
5104 return IRQ_HANDLED;
5105 }
5106
5107 /* MSI ISR - No need to check for interrupt sharing and no need to
5108 * flush status block and interrupt mailbox. PCI ordering rules
5109 * guarantee that MSI will arrive after the status block.
5110 */
5111 static irqreturn_t tg3_msi(int irq, void *dev_id)
5112 {
5113 struct tg3_napi *tnapi = dev_id;
5114 struct tg3 *tp = tnapi->tp;
5115
5116 prefetch(tnapi->hw_status);
5117 if (tnapi->rx_rcb)
5118 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5119 /*
5120 * Writing any value to intr-mbox-0 clears PCI INTA# and
5121 * chip-internal interrupt pending events.
5122 * Writing non-zero to intr-mbox-0 additional tells the
5123 * NIC to stop sending us irqs, engaging "in-intr-handler"
5124 * event coalescing.
5125 */
5126 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5127 if (likely(!tg3_irq_sync(tp)))
5128 napi_schedule(&tnapi->napi);
5129
5130 return IRQ_RETVAL(1);
5131 }
5132
5133 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5134 {
5135 struct tg3_napi *tnapi = dev_id;
5136 struct tg3 *tp = tnapi->tp;
5137 struct tg3_hw_status *sblk = tnapi->hw_status;
5138 unsigned int handled = 1;
5139
5140 /* In INTx mode, it is possible for the interrupt to arrive at
5141 * the CPU before the status block posted prior to the interrupt.
5142 * Reading the PCI State register will confirm whether the
5143 * interrupt is ours and will flush the status block.
5144 */
5145 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5146 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5147 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5148 handled = 0;
5149 goto out;
5150 }
5151 }
5152
5153 /*
5154 * Writing any value to intr-mbox-0 clears PCI INTA# and
5155 * chip-internal interrupt pending events.
5156 * Writing non-zero to intr-mbox-0 additional tells the
5157 * NIC to stop sending us irqs, engaging "in-intr-handler"
5158 * event coalescing.
5159 *
5160 * Flush the mailbox to de-assert the IRQ immediately to prevent
5161 * spurious interrupts. The flush impacts performance but
5162 * excessive spurious interrupts can be worse in some cases.
5163 */
5164 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5165 if (tg3_irq_sync(tp))
5166 goto out;
5167 sblk->status &= ~SD_STATUS_UPDATED;
5168 if (likely(tg3_has_work(tnapi))) {
5169 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5170 napi_schedule(&tnapi->napi);
5171 } else {
5172 /* No work, shared interrupt perhaps? re-enable
5173 * interrupts, and flush that PCI write
5174 */
5175 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5176 0x00000000);
5177 }
5178 out:
5179 return IRQ_RETVAL(handled);
5180 }
5181
5182 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5183 {
5184 struct tg3_napi *tnapi = dev_id;
5185 struct tg3 *tp = tnapi->tp;
5186 struct tg3_hw_status *sblk = tnapi->hw_status;
5187 unsigned int handled = 1;
5188
5189 /* In INTx mode, it is possible for the interrupt to arrive at
5190 * the CPU before the status block posted prior to the interrupt.
5191 * Reading the PCI State register will confirm whether the
5192 * interrupt is ours and will flush the status block.
5193 */
5194 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5195 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5196 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5197 handled = 0;
5198 goto out;
5199 }
5200 }
5201
5202 /*
5203 * writing any value to intr-mbox-0 clears PCI INTA# and
5204 * chip-internal interrupt pending events.
5205 * writing non-zero to intr-mbox-0 additional tells the
5206 * NIC to stop sending us irqs, engaging "in-intr-handler"
5207 * event coalescing.
5208 *
5209 * Flush the mailbox to de-assert the IRQ immediately to prevent
5210 * spurious interrupts. The flush impacts performance but
5211 * excessive spurious interrupts can be worse in some cases.
5212 */
5213 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5214
5215 /*
5216 * In a shared interrupt configuration, sometimes other devices'
5217 * interrupts will scream. We record the current status tag here
5218 * so that the above check can report that the screaming interrupts
5219 * are unhandled. Eventually they will be silenced.
5220 */
5221 tnapi->last_irq_tag = sblk->status_tag;
5222
5223 if (tg3_irq_sync(tp))
5224 goto out;
5225
5226 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5227
5228 napi_schedule(&tnapi->napi);
5229
5230 out:
5231 return IRQ_RETVAL(handled);
5232 }
5233
5234 /* ISR for interrupt test */
5235 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5236 {
5237 struct tg3_napi *tnapi = dev_id;
5238 struct tg3 *tp = tnapi->tp;
5239 struct tg3_hw_status *sblk = tnapi->hw_status;
5240
5241 if ((sblk->status & SD_STATUS_UPDATED) ||
5242 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5243 tg3_disable_ints(tp);
5244 return IRQ_RETVAL(1);
5245 }
5246 return IRQ_RETVAL(0);
5247 }
5248
5249 static int tg3_init_hw(struct tg3 *, int);
5250 static int tg3_halt(struct tg3 *, int, int);
5251
5252 /* Restart hardware after configuration changes, self-test, etc.
5253 * Invoked with tp->lock held.
5254 */
5255 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5256 __releases(tp->lock)
5257 __acquires(tp->lock)
5258 {
5259 int err;
5260
5261 err = tg3_init_hw(tp, reset_phy);
5262 if (err) {
5263 netdev_err(tp->dev, "Failed to re-initialize device, aborting\n");
5264 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5265 tg3_full_unlock(tp);
5266 del_timer_sync(&tp->timer);
5267 tp->irq_sync = 0;
5268 tg3_napi_enable(tp);
5269 dev_close(tp->dev);
5270 tg3_full_lock(tp, 0);
5271 }
5272 return err;
5273 }
5274
5275 #ifdef CONFIG_NET_POLL_CONTROLLER
5276 static void tg3_poll_controller(struct net_device *dev)
5277 {
5278 int i;
5279 struct tg3 *tp = netdev_priv(dev);
5280
5281 for (i = 0; i < tp->irq_cnt; i++)
5282 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5283 }
5284 #endif
5285
5286 static void tg3_reset_task(struct work_struct *work)
5287 {
5288 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5289 int err;
5290 unsigned int restart_timer;
5291
5292 tg3_full_lock(tp, 0);
5293
5294 if (!netif_running(tp->dev)) {
5295 tg3_full_unlock(tp);
5296 return;
5297 }
5298
5299 tg3_full_unlock(tp);
5300
5301 tg3_phy_stop(tp);
5302
5303 tg3_netif_stop(tp);
5304
5305 tg3_full_lock(tp, 1);
5306
5307 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5308 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5309
5310 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5311 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5312 tp->write32_rx_mbox = tg3_write_flush_reg32;
5313 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5314 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5315 }
5316
5317 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5318 err = tg3_init_hw(tp, 1);
5319 if (err)
5320 goto out;
5321
5322 tg3_netif_start(tp);
5323
5324 if (restart_timer)
5325 mod_timer(&tp->timer, jiffies + 1);
5326
5327 out:
5328 tg3_full_unlock(tp);
5329
5330 if (!err)
5331 tg3_phy_start(tp);
5332 }
5333
5334 static void tg3_dump_short_state(struct tg3 *tp)
5335 {
5336 netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5337 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5338 netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5339 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5340 }
5341
5342 static void tg3_tx_timeout(struct net_device *dev)
5343 {
5344 struct tg3 *tp = netdev_priv(dev);
5345
5346 if (netif_msg_tx_err(tp)) {
5347 netdev_err(dev, "transmit timed out, resetting\n");
5348 tg3_dump_short_state(tp);
5349 }
5350
5351 schedule_work(&tp->reset_task);
5352 }
5353
5354 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5355 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5356 {
5357 u32 base = (u32) mapping & 0xffffffff;
5358
5359 return ((base > 0xffffdcc0) &&
5360 (base + len + 8 < base));
5361 }
5362
5363 /* Test for DMA addresses > 40-bit */
5364 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5365 int len)
5366 {
5367 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5368 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5369 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5370 return 0;
5371 #else
5372 return 0;
5373 #endif
5374 }
5375
5376 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5377
5378 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5379 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5380 struct sk_buff *skb, u32 last_plus_one,
5381 u32 *start, u32 base_flags, u32 mss)
5382 {
5383 struct tg3 *tp = tnapi->tp;
5384 struct sk_buff *new_skb;
5385 dma_addr_t new_addr = 0;
5386 u32 entry = *start;
5387 int i, ret = 0;
5388
5389 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5390 new_skb = skb_copy(skb, GFP_ATOMIC);
5391 else {
5392 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5393
5394 new_skb = skb_copy_expand(skb,
5395 skb_headroom(skb) + more_headroom,
5396 skb_tailroom(skb), GFP_ATOMIC);
5397 }
5398
5399 if (!new_skb) {
5400 ret = -1;
5401 } else {
5402 /* New SKB is guaranteed to be linear. */
5403 entry = *start;
5404 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5405 PCI_DMA_TODEVICE);
5406 /* Make sure the mapping succeeded */
5407 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5408 ret = -1;
5409 dev_kfree_skb(new_skb);
5410 new_skb = NULL;
5411
5412 /* Make sure new skb does not cross any 4G boundaries.
5413 * Drop the packet if it does.
5414 */
5415 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5416 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5417 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5418 PCI_DMA_TODEVICE);
5419 ret = -1;
5420 dev_kfree_skb(new_skb);
5421 new_skb = NULL;
5422 } else {
5423 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5424 base_flags, 1 | (mss << 1));
5425 *start = NEXT_TX(entry);
5426 }
5427 }
5428
5429 /* Now clean up the sw ring entries. */
5430 i = 0;
5431 while (entry != last_plus_one) {
5432 int len;
5433
5434 if (i == 0)
5435 len = skb_headlen(skb);
5436 else
5437 len = skb_shinfo(skb)->frags[i-1].size;
5438
5439 pci_unmap_single(tp->pdev,
5440 pci_unmap_addr(&tnapi->tx_buffers[entry],
5441 mapping),
5442 len, PCI_DMA_TODEVICE);
5443 if (i == 0) {
5444 tnapi->tx_buffers[entry].skb = new_skb;
5445 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5446 new_addr);
5447 } else {
5448 tnapi->tx_buffers[entry].skb = NULL;
5449 }
5450 entry = NEXT_TX(entry);
5451 i++;
5452 }
5453
5454 dev_kfree_skb(skb);
5455
5456 return ret;
5457 }
5458
5459 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5460 dma_addr_t mapping, int len, u32 flags,
5461 u32 mss_and_is_end)
5462 {
5463 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5464 int is_end = (mss_and_is_end & 0x1);
5465 u32 mss = (mss_and_is_end >> 1);
5466 u32 vlan_tag = 0;
5467
5468 if (is_end)
5469 flags |= TXD_FLAG_END;
5470 if (flags & TXD_FLAG_VLAN) {
5471 vlan_tag = flags >> 16;
5472 flags &= 0xffff;
5473 }
5474 vlan_tag |= (mss << TXD_MSS_SHIFT);
5475
5476 txd->addr_hi = ((u64) mapping >> 32);
5477 txd->addr_lo = ((u64) mapping & 0xffffffff);
5478 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5479 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5480 }
5481
5482 /* hard_start_xmit for devices that don't have any bugs and
5483 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5484 */
5485 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5486 struct net_device *dev)
5487 {
5488 struct tg3 *tp = netdev_priv(dev);
5489 u32 len, entry, base_flags, mss;
5490 dma_addr_t mapping;
5491 struct tg3_napi *tnapi;
5492 struct netdev_queue *txq;
5493 unsigned int i, last;
5494
5495
5496 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5497 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5498 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5499 tnapi++;
5500
5501 /* We are running in BH disabled context with netif_tx_lock
5502 * and TX reclaim runs via tp->napi.poll inside of a software
5503 * interrupt. Furthermore, IRQ processing runs lockless so we have
5504 * no IRQ context deadlocks to worry about either. Rejoice!
5505 */
5506 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5507 if (!netif_tx_queue_stopped(txq)) {
5508 netif_tx_stop_queue(txq);
5509
5510 /* This is a hard error, log it. */
5511 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
5512 }
5513 return NETDEV_TX_BUSY;
5514 }
5515
5516 entry = tnapi->tx_prod;
5517 base_flags = 0;
5518 mss = 0;
5519 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5520 int tcp_opt_len, ip_tcp_len;
5521 u32 hdrlen;
5522
5523 if (skb_header_cloned(skb) &&
5524 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5525 dev_kfree_skb(skb);
5526 goto out_unlock;
5527 }
5528
5529 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5530 hdrlen = skb_headlen(skb) - ETH_HLEN;
5531 else {
5532 struct iphdr *iph = ip_hdr(skb);
5533
5534 tcp_opt_len = tcp_optlen(skb);
5535 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5536
5537 iph->check = 0;
5538 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5539 hdrlen = ip_tcp_len + tcp_opt_len;
5540 }
5541
5542 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5543 mss |= (hdrlen & 0xc) << 12;
5544 if (hdrlen & 0x10)
5545 base_flags |= 0x00000010;
5546 base_flags |= (hdrlen & 0x3e0) << 5;
5547 } else
5548 mss |= hdrlen << 9;
5549
5550 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5551 TXD_FLAG_CPU_POST_DMA);
5552
5553 tcp_hdr(skb)->check = 0;
5554
5555 }
5556 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5557 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5558 #if TG3_VLAN_TAG_USED
5559 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5560 base_flags |= (TXD_FLAG_VLAN |
5561 (vlan_tx_tag_get(skb) << 16));
5562 #endif
5563
5564 len = skb_headlen(skb);
5565
5566 /* Queue skb data, a.k.a. the main skb fragment. */
5567 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5568 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5569 dev_kfree_skb(skb);
5570 goto out_unlock;
5571 }
5572
5573 tnapi->tx_buffers[entry].skb = skb;
5574 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5575
5576 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5577 !mss && skb->len > ETH_DATA_LEN)
5578 base_flags |= TXD_FLAG_JMB_PKT;
5579
5580 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5581 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5582
5583 entry = NEXT_TX(entry);
5584
5585 /* Now loop through additional data fragments, and queue them. */
5586 if (skb_shinfo(skb)->nr_frags > 0) {
5587 last = skb_shinfo(skb)->nr_frags - 1;
5588 for (i = 0; i <= last; i++) {
5589 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5590
5591 len = frag->size;
5592 mapping = pci_map_page(tp->pdev,
5593 frag->page,
5594 frag->page_offset,
5595 len, PCI_DMA_TODEVICE);
5596 if (pci_dma_mapping_error(tp->pdev, mapping))
5597 goto dma_error;
5598
5599 tnapi->tx_buffers[entry].skb = NULL;
5600 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5601 mapping);
5602
5603 tg3_set_txd(tnapi, entry, mapping, len,
5604 base_flags, (i == last) | (mss << 1));
5605
5606 entry = NEXT_TX(entry);
5607 }
5608 }
5609
5610 /* Packets are ready, update Tx producer idx local and on card. */
5611 tw32_tx_mbox(tnapi->prodmbox, entry);
5612
5613 tnapi->tx_prod = entry;
5614 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5615 netif_tx_stop_queue(txq);
5616 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5617 netif_tx_wake_queue(txq);
5618 }
5619
5620 out_unlock:
5621 mmiowb();
5622
5623 return NETDEV_TX_OK;
5624
5625 dma_error:
5626 last = i;
5627 entry = tnapi->tx_prod;
5628 tnapi->tx_buffers[entry].skb = NULL;
5629 pci_unmap_single(tp->pdev,
5630 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5631 skb_headlen(skb),
5632 PCI_DMA_TODEVICE);
5633 for (i = 0; i <= last; i++) {
5634 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5635 entry = NEXT_TX(entry);
5636
5637 pci_unmap_page(tp->pdev,
5638 pci_unmap_addr(&tnapi->tx_buffers[entry],
5639 mapping),
5640 frag->size, PCI_DMA_TODEVICE);
5641 }
5642
5643 dev_kfree_skb(skb);
5644 return NETDEV_TX_OK;
5645 }
5646
5647 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5648 struct net_device *);
5649
5650 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5651 * TSO header is greater than 80 bytes.
5652 */
5653 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5654 {
5655 struct sk_buff *segs, *nskb;
5656 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5657
5658 /* Estimate the number of fragments in the worst case */
5659 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5660 netif_stop_queue(tp->dev);
5661 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5662 return NETDEV_TX_BUSY;
5663
5664 netif_wake_queue(tp->dev);
5665 }
5666
5667 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5668 if (IS_ERR(segs))
5669 goto tg3_tso_bug_end;
5670
5671 do {
5672 nskb = segs;
5673 segs = segs->next;
5674 nskb->next = NULL;
5675 tg3_start_xmit_dma_bug(nskb, tp->dev);
5676 } while (segs);
5677
5678 tg3_tso_bug_end:
5679 dev_kfree_skb(skb);
5680
5681 return NETDEV_TX_OK;
5682 }
5683
5684 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5685 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5686 */
5687 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5688 struct net_device *dev)
5689 {
5690 struct tg3 *tp = netdev_priv(dev);
5691 u32 len, entry, base_flags, mss;
5692 int would_hit_hwbug;
5693 dma_addr_t mapping;
5694 struct tg3_napi *tnapi;
5695 struct netdev_queue *txq;
5696 unsigned int i, last;
5697
5698
5699 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5700 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5701 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5702 tnapi++;
5703
5704 /* We are running in BH disabled context with netif_tx_lock
5705 * and TX reclaim runs via tp->napi.poll inside of a software
5706 * interrupt. Furthermore, IRQ processing runs lockless so we have
5707 * no IRQ context deadlocks to worry about either. Rejoice!
5708 */
5709 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5710 if (!netif_tx_queue_stopped(txq)) {
5711 netif_tx_stop_queue(txq);
5712
5713 /* This is a hard error, log it. */
5714 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
5715 }
5716 return NETDEV_TX_BUSY;
5717 }
5718
5719 entry = tnapi->tx_prod;
5720 base_flags = 0;
5721 if (skb->ip_summed == CHECKSUM_PARTIAL)
5722 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5723
5724 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5725 struct iphdr *iph;
5726 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5727
5728 if (skb_header_cloned(skb) &&
5729 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5730 dev_kfree_skb(skb);
5731 goto out_unlock;
5732 }
5733
5734 tcp_opt_len = tcp_optlen(skb);
5735 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5736
5737 hdr_len = ip_tcp_len + tcp_opt_len;
5738 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5739 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5740 return (tg3_tso_bug(tp, skb));
5741
5742 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5743 TXD_FLAG_CPU_POST_DMA);
5744
5745 iph = ip_hdr(skb);
5746 iph->check = 0;
5747 iph->tot_len = htons(mss + hdr_len);
5748 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5749 tcp_hdr(skb)->check = 0;
5750 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5751 } else
5752 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5753 iph->daddr, 0,
5754 IPPROTO_TCP,
5755 0);
5756
5757 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5758 mss |= (hdr_len & 0xc) << 12;
5759 if (hdr_len & 0x10)
5760 base_flags |= 0x00000010;
5761 base_flags |= (hdr_len & 0x3e0) << 5;
5762 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5763 mss |= hdr_len << 9;
5764 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5765 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5766 if (tcp_opt_len || iph->ihl > 5) {
5767 int tsflags;
5768
5769 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5770 mss |= (tsflags << 11);
5771 }
5772 } else {
5773 if (tcp_opt_len || iph->ihl > 5) {
5774 int tsflags;
5775
5776 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5777 base_flags |= tsflags << 12;
5778 }
5779 }
5780 }
5781 #if TG3_VLAN_TAG_USED
5782 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5783 base_flags |= (TXD_FLAG_VLAN |
5784 (vlan_tx_tag_get(skb) << 16));
5785 #endif
5786
5787 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5788 !mss && skb->len > ETH_DATA_LEN)
5789 base_flags |= TXD_FLAG_JMB_PKT;
5790
5791 len = skb_headlen(skb);
5792
5793 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5794 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5795 dev_kfree_skb(skb);
5796 goto out_unlock;
5797 }
5798
5799 tnapi->tx_buffers[entry].skb = skb;
5800 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5801
5802 would_hit_hwbug = 0;
5803
5804 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5805 would_hit_hwbug = 1;
5806
5807 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5808 tg3_4g_overflow_test(mapping, len))
5809 would_hit_hwbug = 1;
5810
5811 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5812 tg3_40bit_overflow_test(tp, mapping, len))
5813 would_hit_hwbug = 1;
5814
5815 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5816 would_hit_hwbug = 1;
5817
5818 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5819 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5820
5821 entry = NEXT_TX(entry);
5822
5823 /* Now loop through additional data fragments, and queue them. */
5824 if (skb_shinfo(skb)->nr_frags > 0) {
5825 last = skb_shinfo(skb)->nr_frags - 1;
5826 for (i = 0; i <= last; i++) {
5827 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5828
5829 len = frag->size;
5830 mapping = pci_map_page(tp->pdev,
5831 frag->page,
5832 frag->page_offset,
5833 len, PCI_DMA_TODEVICE);
5834
5835 tnapi->tx_buffers[entry].skb = NULL;
5836 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5837 mapping);
5838 if (pci_dma_mapping_error(tp->pdev, mapping))
5839 goto dma_error;
5840
5841 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5842 len <= 8)
5843 would_hit_hwbug = 1;
5844
5845 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5846 tg3_4g_overflow_test(mapping, len))
5847 would_hit_hwbug = 1;
5848
5849 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5850 tg3_40bit_overflow_test(tp, mapping, len))
5851 would_hit_hwbug = 1;
5852
5853 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5854 tg3_set_txd(tnapi, entry, mapping, len,
5855 base_flags, (i == last)|(mss << 1));
5856 else
5857 tg3_set_txd(tnapi, entry, mapping, len,
5858 base_flags, (i == last));
5859
5860 entry = NEXT_TX(entry);
5861 }
5862 }
5863
5864 if (would_hit_hwbug) {
5865 u32 last_plus_one = entry;
5866 u32 start;
5867
5868 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5869 start &= (TG3_TX_RING_SIZE - 1);
5870
5871 /* If the workaround fails due to memory/mapping
5872 * failure, silently drop this packet.
5873 */
5874 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5875 &start, base_flags, mss))
5876 goto out_unlock;
5877
5878 entry = start;
5879 }
5880
5881 /* Packets are ready, update Tx producer idx local and on card. */
5882 tw32_tx_mbox(tnapi->prodmbox, entry);
5883
5884 tnapi->tx_prod = entry;
5885 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5886 netif_tx_stop_queue(txq);
5887 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5888 netif_tx_wake_queue(txq);
5889 }
5890
5891 out_unlock:
5892 mmiowb();
5893
5894 return NETDEV_TX_OK;
5895
5896 dma_error:
5897 last = i;
5898 entry = tnapi->tx_prod;
5899 tnapi->tx_buffers[entry].skb = NULL;
5900 pci_unmap_single(tp->pdev,
5901 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5902 skb_headlen(skb),
5903 PCI_DMA_TODEVICE);
5904 for (i = 0; i <= last; i++) {
5905 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5906 entry = NEXT_TX(entry);
5907
5908 pci_unmap_page(tp->pdev,
5909 pci_unmap_addr(&tnapi->tx_buffers[entry],
5910 mapping),
5911 frag->size, PCI_DMA_TODEVICE);
5912 }
5913
5914 dev_kfree_skb(skb);
5915 return NETDEV_TX_OK;
5916 }
5917
5918 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5919 int new_mtu)
5920 {
5921 dev->mtu = new_mtu;
5922
5923 if (new_mtu > ETH_DATA_LEN) {
5924 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5925 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5926 ethtool_op_set_tso(dev, 0);
5927 }
5928 else
5929 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5930 } else {
5931 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5932 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5933 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5934 }
5935 }
5936
5937 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5938 {
5939 struct tg3 *tp = netdev_priv(dev);
5940 int err;
5941
5942 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5943 return -EINVAL;
5944
5945 if (!netif_running(dev)) {
5946 /* We'll just catch it later when the
5947 * device is up'd.
5948 */
5949 tg3_set_mtu(dev, tp, new_mtu);
5950 return 0;
5951 }
5952
5953 tg3_phy_stop(tp);
5954
5955 tg3_netif_stop(tp);
5956
5957 tg3_full_lock(tp, 1);
5958
5959 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5960
5961 tg3_set_mtu(dev, tp, new_mtu);
5962
5963 err = tg3_restart_hw(tp, 0);
5964
5965 if (!err)
5966 tg3_netif_start(tp);
5967
5968 tg3_full_unlock(tp);
5969
5970 if (!err)
5971 tg3_phy_start(tp);
5972
5973 return err;
5974 }
5975
5976 static void tg3_rx_prodring_free(struct tg3 *tp,
5977 struct tg3_rx_prodring_set *tpr)
5978 {
5979 int i;
5980
5981 if (tpr != &tp->prodring[0]) {
5982 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5983 i = (i + 1) % TG3_RX_RING_SIZE)
5984 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5985 tp->rx_pkt_map_sz);
5986
5987 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5988 for (i = tpr->rx_jmb_cons_idx;
5989 i != tpr->rx_jmb_prod_idx;
5990 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5991 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5992 TG3_RX_JMB_MAP_SZ);
5993 }
5994 }
5995
5996 return;
5997 }
5998
5999 for (i = 0; i < TG3_RX_RING_SIZE; i++)
6000 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6001 tp->rx_pkt_map_sz);
6002
6003 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6004 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6005 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6006 TG3_RX_JMB_MAP_SZ);
6007 }
6008 }
6009
6010 /* Initialize tx/rx rings for packet processing.
6011 *
6012 * The chip has been shut down and the driver detached from
6013 * the networking, so no interrupts or new tx packets will
6014 * end up in the driver. tp->{tx,}lock are held and thus
6015 * we may not sleep.
6016 */
6017 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6018 struct tg3_rx_prodring_set *tpr)
6019 {
6020 u32 i, rx_pkt_dma_sz;
6021
6022 tpr->rx_std_cons_idx = 0;
6023 tpr->rx_std_prod_idx = 0;
6024 tpr->rx_jmb_cons_idx = 0;
6025 tpr->rx_jmb_prod_idx = 0;
6026
6027 if (tpr != &tp->prodring[0]) {
6028 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6029 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6030 memset(&tpr->rx_jmb_buffers[0], 0,
6031 TG3_RX_JMB_BUFF_RING_SIZE);
6032 goto done;
6033 }
6034
6035 /* Zero out all descriptors. */
6036 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6037
6038 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6039 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6040 tp->dev->mtu > ETH_DATA_LEN)
6041 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6042 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6043
6044 /* Initialize invariants of the rings, we only set this
6045 * stuff once. This works because the card does not
6046 * write into the rx buffer posting rings.
6047 */
6048 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6049 struct tg3_rx_buffer_desc *rxd;
6050
6051 rxd = &tpr->rx_std[i];
6052 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6053 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6054 rxd->opaque = (RXD_OPAQUE_RING_STD |
6055 (i << RXD_OPAQUE_INDEX_SHIFT));
6056 }
6057
6058 /* Now allocate fresh SKBs for each rx ring. */
6059 for (i = 0; i < tp->rx_pending; i++) {
6060 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6061 netdev_warn(tp->dev, "Using a smaller RX standard ring, only %d out of %d buffers were allocated successfully\n",
6062 i, tp->rx_pending);
6063 if (i == 0)
6064 goto initfail;
6065 tp->rx_pending = i;
6066 break;
6067 }
6068 }
6069
6070 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6071 goto done;
6072
6073 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6074
6075 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6076 goto done;
6077
6078 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6079 struct tg3_rx_buffer_desc *rxd;
6080
6081 rxd = &tpr->rx_jmb[i].std;
6082 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6083 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6084 RXD_FLAG_JUMBO;
6085 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6086 (i << RXD_OPAQUE_INDEX_SHIFT));
6087 }
6088
6089 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6090 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6091 netdev_warn(tp->dev, "Using a smaller RX jumbo ring, only %d out of %d buffers were allocated successfully\n",
6092 i, tp->rx_jumbo_pending);
6093 if (i == 0)
6094 goto initfail;
6095 tp->rx_jumbo_pending = i;
6096 break;
6097 }
6098 }
6099
6100 done:
6101 return 0;
6102
6103 initfail:
6104 tg3_rx_prodring_free(tp, tpr);
6105 return -ENOMEM;
6106 }
6107
6108 static void tg3_rx_prodring_fini(struct tg3 *tp,
6109 struct tg3_rx_prodring_set *tpr)
6110 {
6111 kfree(tpr->rx_std_buffers);
6112 tpr->rx_std_buffers = NULL;
6113 kfree(tpr->rx_jmb_buffers);
6114 tpr->rx_jmb_buffers = NULL;
6115 if (tpr->rx_std) {
6116 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6117 tpr->rx_std, tpr->rx_std_mapping);
6118 tpr->rx_std = NULL;
6119 }
6120 if (tpr->rx_jmb) {
6121 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6122 tpr->rx_jmb, tpr->rx_jmb_mapping);
6123 tpr->rx_jmb = NULL;
6124 }
6125 }
6126
6127 static int tg3_rx_prodring_init(struct tg3 *tp,
6128 struct tg3_rx_prodring_set *tpr)
6129 {
6130 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6131 if (!tpr->rx_std_buffers)
6132 return -ENOMEM;
6133
6134 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6135 &tpr->rx_std_mapping);
6136 if (!tpr->rx_std)
6137 goto err_out;
6138
6139 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6140 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6141 GFP_KERNEL);
6142 if (!tpr->rx_jmb_buffers)
6143 goto err_out;
6144
6145 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6146 TG3_RX_JUMBO_RING_BYTES,
6147 &tpr->rx_jmb_mapping);
6148 if (!tpr->rx_jmb)
6149 goto err_out;
6150 }
6151
6152 return 0;
6153
6154 err_out:
6155 tg3_rx_prodring_fini(tp, tpr);
6156 return -ENOMEM;
6157 }
6158
6159 /* Free up pending packets in all rx/tx rings.
6160 *
6161 * The chip has been shut down and the driver detached from
6162 * the networking, so no interrupts or new tx packets will
6163 * end up in the driver. tp->{tx,}lock is not held and we are not
6164 * in an interrupt context and thus may sleep.
6165 */
6166 static void tg3_free_rings(struct tg3 *tp)
6167 {
6168 int i, j;
6169
6170 for (j = 0; j < tp->irq_cnt; j++) {
6171 struct tg3_napi *tnapi = &tp->napi[j];
6172
6173 if (!tnapi->tx_buffers)
6174 continue;
6175
6176 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6177 struct ring_info *txp;
6178 struct sk_buff *skb;
6179 unsigned int k;
6180
6181 txp = &tnapi->tx_buffers[i];
6182 skb = txp->skb;
6183
6184 if (skb == NULL) {
6185 i++;
6186 continue;
6187 }
6188
6189 pci_unmap_single(tp->pdev,
6190 pci_unmap_addr(txp, mapping),
6191 skb_headlen(skb),
6192 PCI_DMA_TODEVICE);
6193 txp->skb = NULL;
6194
6195 i++;
6196
6197 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6198 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6199 pci_unmap_page(tp->pdev,
6200 pci_unmap_addr(txp, mapping),
6201 skb_shinfo(skb)->frags[k].size,
6202 PCI_DMA_TODEVICE);
6203 i++;
6204 }
6205
6206 dev_kfree_skb_any(skb);
6207 }
6208
6209 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6210 }
6211 }
6212
6213 /* Initialize tx/rx rings for packet processing.
6214 *
6215 * The chip has been shut down and the driver detached from
6216 * the networking, so no interrupts or new tx packets will
6217 * end up in the driver. tp->{tx,}lock are held and thus
6218 * we may not sleep.
6219 */
6220 static int tg3_init_rings(struct tg3 *tp)
6221 {
6222 int i;
6223
6224 /* Free up all the SKBs. */
6225 tg3_free_rings(tp);
6226
6227 for (i = 0; i < tp->irq_cnt; i++) {
6228 struct tg3_napi *tnapi = &tp->napi[i];
6229
6230 tnapi->last_tag = 0;
6231 tnapi->last_irq_tag = 0;
6232 tnapi->hw_status->status = 0;
6233 tnapi->hw_status->status_tag = 0;
6234 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6235
6236 tnapi->tx_prod = 0;
6237 tnapi->tx_cons = 0;
6238 if (tnapi->tx_ring)
6239 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6240
6241 tnapi->rx_rcb_ptr = 0;
6242 if (tnapi->rx_rcb)
6243 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6244
6245 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6246 tg3_free_rings(tp);
6247 return -ENOMEM;
6248 }
6249 }
6250
6251 return 0;
6252 }
6253
6254 /*
6255 * Must not be invoked with interrupt sources disabled and
6256 * the hardware shutdown down.
6257 */
6258 static void tg3_free_consistent(struct tg3 *tp)
6259 {
6260 int i;
6261
6262 for (i = 0; i < tp->irq_cnt; i++) {
6263 struct tg3_napi *tnapi = &tp->napi[i];
6264
6265 if (tnapi->tx_ring) {
6266 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6267 tnapi->tx_ring, tnapi->tx_desc_mapping);
6268 tnapi->tx_ring = NULL;
6269 }
6270
6271 kfree(tnapi->tx_buffers);
6272 tnapi->tx_buffers = NULL;
6273
6274 if (tnapi->rx_rcb) {
6275 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6276 tnapi->rx_rcb,
6277 tnapi->rx_rcb_mapping);
6278 tnapi->rx_rcb = NULL;
6279 }
6280
6281 if (tnapi->hw_status) {
6282 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6283 tnapi->hw_status,
6284 tnapi->status_mapping);
6285 tnapi->hw_status = NULL;
6286 }
6287 }
6288
6289 if (tp->hw_stats) {
6290 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6291 tp->hw_stats, tp->stats_mapping);
6292 tp->hw_stats = NULL;
6293 }
6294
6295 for (i = 0; i < tp->irq_cnt; i++)
6296 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6297 }
6298
6299 /*
6300 * Must not be invoked with interrupt sources disabled and
6301 * the hardware shutdown down. Can sleep.
6302 */
6303 static int tg3_alloc_consistent(struct tg3 *tp)
6304 {
6305 int i;
6306
6307 for (i = 0; i < tp->irq_cnt; i++) {
6308 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6309 goto err_out;
6310 }
6311
6312 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6313 sizeof(struct tg3_hw_stats),
6314 &tp->stats_mapping);
6315 if (!tp->hw_stats)
6316 goto err_out;
6317
6318 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6319
6320 for (i = 0; i < tp->irq_cnt; i++) {
6321 struct tg3_napi *tnapi = &tp->napi[i];
6322 struct tg3_hw_status *sblk;
6323
6324 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6325 TG3_HW_STATUS_SIZE,
6326 &tnapi->status_mapping);
6327 if (!tnapi->hw_status)
6328 goto err_out;
6329
6330 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6331 sblk = tnapi->hw_status;
6332
6333 /* If multivector TSS is enabled, vector 0 does not handle
6334 * tx interrupts. Don't allocate any resources for it.
6335 */
6336 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6337 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6338 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6339 TG3_TX_RING_SIZE,
6340 GFP_KERNEL);
6341 if (!tnapi->tx_buffers)
6342 goto err_out;
6343
6344 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6345 TG3_TX_RING_BYTES,
6346 &tnapi->tx_desc_mapping);
6347 if (!tnapi->tx_ring)
6348 goto err_out;
6349 }
6350
6351 /*
6352 * When RSS is enabled, the status block format changes
6353 * slightly. The "rx_jumbo_consumer", "reserved",
6354 * and "rx_mini_consumer" members get mapped to the
6355 * other three rx return ring producer indexes.
6356 */
6357 switch (i) {
6358 default:
6359 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6360 break;
6361 case 2:
6362 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6363 break;
6364 case 3:
6365 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6366 break;
6367 case 4:
6368 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6369 break;
6370 }
6371
6372 tnapi->prodring = &tp->prodring[i];
6373
6374 /*
6375 * If multivector RSS is enabled, vector 0 does not handle
6376 * rx or tx interrupts. Don't allocate any resources for it.
6377 */
6378 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6379 continue;
6380
6381 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6382 TG3_RX_RCB_RING_BYTES(tp),
6383 &tnapi->rx_rcb_mapping);
6384 if (!tnapi->rx_rcb)
6385 goto err_out;
6386
6387 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6388 }
6389
6390 return 0;
6391
6392 err_out:
6393 tg3_free_consistent(tp);
6394 return -ENOMEM;
6395 }
6396
6397 #define MAX_WAIT_CNT 1000
6398
6399 /* To stop a block, clear the enable bit and poll till it
6400 * clears. tp->lock is held.
6401 */
6402 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6403 {
6404 unsigned int i;
6405 u32 val;
6406
6407 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6408 switch (ofs) {
6409 case RCVLSC_MODE:
6410 case DMAC_MODE:
6411 case MBFREE_MODE:
6412 case BUFMGR_MODE:
6413 case MEMARB_MODE:
6414 /* We can't enable/disable these bits of the
6415 * 5705/5750, just say success.
6416 */
6417 return 0;
6418
6419 default:
6420 break;
6421 }
6422 }
6423
6424 val = tr32(ofs);
6425 val &= ~enable_bit;
6426 tw32_f(ofs, val);
6427
6428 for (i = 0; i < MAX_WAIT_CNT; i++) {
6429 udelay(100);
6430 val = tr32(ofs);
6431 if ((val & enable_bit) == 0)
6432 break;
6433 }
6434
6435 if (i == MAX_WAIT_CNT && !silent) {
6436 pr_err("tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6437 ofs, enable_bit);
6438 return -ENODEV;
6439 }
6440
6441 return 0;
6442 }
6443
6444 /* tp->lock is held. */
6445 static int tg3_abort_hw(struct tg3 *tp, int silent)
6446 {
6447 int i, err;
6448
6449 tg3_disable_ints(tp);
6450
6451 tp->rx_mode &= ~RX_MODE_ENABLE;
6452 tw32_f(MAC_RX_MODE, tp->rx_mode);
6453 udelay(10);
6454
6455 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6456 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6457 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6458 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6459 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6460 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6461
6462 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6463 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6464 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6465 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6466 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6467 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6468 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6469
6470 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6471 tw32_f(MAC_MODE, tp->mac_mode);
6472 udelay(40);
6473
6474 tp->tx_mode &= ~TX_MODE_ENABLE;
6475 tw32_f(MAC_TX_MODE, tp->tx_mode);
6476
6477 for (i = 0; i < MAX_WAIT_CNT; i++) {
6478 udelay(100);
6479 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6480 break;
6481 }
6482 if (i >= MAX_WAIT_CNT) {
6483 netdev_err(tp->dev, "%s timed out, TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6484 __func__, tr32(MAC_TX_MODE));
6485 err |= -ENODEV;
6486 }
6487
6488 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6489 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6490 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6491
6492 tw32(FTQ_RESET, 0xffffffff);
6493 tw32(FTQ_RESET, 0x00000000);
6494
6495 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6496 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6497
6498 for (i = 0; i < tp->irq_cnt; i++) {
6499 struct tg3_napi *tnapi = &tp->napi[i];
6500 if (tnapi->hw_status)
6501 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6502 }
6503 if (tp->hw_stats)
6504 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6505
6506 return err;
6507 }
6508
6509 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6510 {
6511 int i;
6512 u32 apedata;
6513
6514 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6515 if (apedata != APE_SEG_SIG_MAGIC)
6516 return;
6517
6518 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6519 if (!(apedata & APE_FW_STATUS_READY))
6520 return;
6521
6522 /* Wait for up to 1 millisecond for APE to service previous event. */
6523 for (i = 0; i < 10; i++) {
6524 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6525 return;
6526
6527 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6528
6529 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6530 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6531 event | APE_EVENT_STATUS_EVENT_PENDING);
6532
6533 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6534
6535 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6536 break;
6537
6538 udelay(100);
6539 }
6540
6541 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6542 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6543 }
6544
6545 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6546 {
6547 u32 event;
6548 u32 apedata;
6549
6550 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6551 return;
6552
6553 switch (kind) {
6554 case RESET_KIND_INIT:
6555 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6556 APE_HOST_SEG_SIG_MAGIC);
6557 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6558 APE_HOST_SEG_LEN_MAGIC);
6559 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6560 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6561 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6562 APE_HOST_DRIVER_ID_MAGIC);
6563 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6564 APE_HOST_BEHAV_NO_PHYLOCK);
6565
6566 event = APE_EVENT_STATUS_STATE_START;
6567 break;
6568 case RESET_KIND_SHUTDOWN:
6569 /* With the interface we are currently using,
6570 * APE does not track driver state. Wiping
6571 * out the HOST SEGMENT SIGNATURE forces
6572 * the APE to assume OS absent status.
6573 */
6574 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6575
6576 event = APE_EVENT_STATUS_STATE_UNLOAD;
6577 break;
6578 case RESET_KIND_SUSPEND:
6579 event = APE_EVENT_STATUS_STATE_SUSPEND;
6580 break;
6581 default:
6582 return;
6583 }
6584
6585 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6586
6587 tg3_ape_send_event(tp, event);
6588 }
6589
6590 /* tp->lock is held. */
6591 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6592 {
6593 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6594 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6595
6596 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6597 switch (kind) {
6598 case RESET_KIND_INIT:
6599 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6600 DRV_STATE_START);
6601 break;
6602
6603 case RESET_KIND_SHUTDOWN:
6604 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6605 DRV_STATE_UNLOAD);
6606 break;
6607
6608 case RESET_KIND_SUSPEND:
6609 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6610 DRV_STATE_SUSPEND);
6611 break;
6612
6613 default:
6614 break;
6615 }
6616 }
6617
6618 if (kind == RESET_KIND_INIT ||
6619 kind == RESET_KIND_SUSPEND)
6620 tg3_ape_driver_state_change(tp, kind);
6621 }
6622
6623 /* tp->lock is held. */
6624 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6625 {
6626 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6627 switch (kind) {
6628 case RESET_KIND_INIT:
6629 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6630 DRV_STATE_START_DONE);
6631 break;
6632
6633 case RESET_KIND_SHUTDOWN:
6634 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6635 DRV_STATE_UNLOAD_DONE);
6636 break;
6637
6638 default:
6639 break;
6640 }
6641 }
6642
6643 if (kind == RESET_KIND_SHUTDOWN)
6644 tg3_ape_driver_state_change(tp, kind);
6645 }
6646
6647 /* tp->lock is held. */
6648 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6649 {
6650 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6651 switch (kind) {
6652 case RESET_KIND_INIT:
6653 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6654 DRV_STATE_START);
6655 break;
6656
6657 case RESET_KIND_SHUTDOWN:
6658 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6659 DRV_STATE_UNLOAD);
6660 break;
6661
6662 case RESET_KIND_SUSPEND:
6663 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6664 DRV_STATE_SUSPEND);
6665 break;
6666
6667 default:
6668 break;
6669 }
6670 }
6671 }
6672
6673 static int tg3_poll_fw(struct tg3 *tp)
6674 {
6675 int i;
6676 u32 val;
6677
6678 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6679 /* Wait up to 20ms for init done. */
6680 for (i = 0; i < 200; i++) {
6681 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6682 return 0;
6683 udelay(100);
6684 }
6685 return -ENODEV;
6686 }
6687
6688 /* Wait for firmware initialization to complete. */
6689 for (i = 0; i < 100000; i++) {
6690 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6691 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6692 break;
6693 udelay(10);
6694 }
6695
6696 /* Chip might not be fitted with firmware. Some Sun onboard
6697 * parts are configured like that. So don't signal the timeout
6698 * of the above loop as an error, but do report the lack of
6699 * running firmware once.
6700 */
6701 if (i >= 100000 &&
6702 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6703 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6704
6705 netdev_info(tp->dev, "No firmware running\n");
6706 }
6707
6708 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6709 /* The 57765 A0 needs a little more
6710 * time to do some important work.
6711 */
6712 mdelay(10);
6713 }
6714
6715 return 0;
6716 }
6717
6718 /* Save PCI command register before chip reset */
6719 static void tg3_save_pci_state(struct tg3 *tp)
6720 {
6721 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6722 }
6723
6724 /* Restore PCI state after chip reset */
6725 static void tg3_restore_pci_state(struct tg3 *tp)
6726 {
6727 u32 val;
6728
6729 /* Re-enable indirect register accesses. */
6730 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6731 tp->misc_host_ctrl);
6732
6733 /* Set MAX PCI retry to zero. */
6734 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6735 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6736 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6737 val |= PCISTATE_RETRY_SAME_DMA;
6738 /* Allow reads and writes to the APE register and memory space. */
6739 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6740 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6741 PCISTATE_ALLOW_APE_SHMEM_WR;
6742 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6743
6744 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6745
6746 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6747 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6748 pcie_set_readrq(tp->pdev, 4096);
6749 else {
6750 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6751 tp->pci_cacheline_sz);
6752 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6753 tp->pci_lat_timer);
6754 }
6755 }
6756
6757 /* Make sure PCI-X relaxed ordering bit is clear. */
6758 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6759 u16 pcix_cmd;
6760
6761 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6762 &pcix_cmd);
6763 pcix_cmd &= ~PCI_X_CMD_ERO;
6764 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6765 pcix_cmd);
6766 }
6767
6768 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6769
6770 /* Chip reset on 5780 will reset MSI enable bit,
6771 * so need to restore it.
6772 */
6773 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6774 u16 ctrl;
6775
6776 pci_read_config_word(tp->pdev,
6777 tp->msi_cap + PCI_MSI_FLAGS,
6778 &ctrl);
6779 pci_write_config_word(tp->pdev,
6780 tp->msi_cap + PCI_MSI_FLAGS,
6781 ctrl | PCI_MSI_FLAGS_ENABLE);
6782 val = tr32(MSGINT_MODE);
6783 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6784 }
6785 }
6786 }
6787
6788 static void tg3_stop_fw(struct tg3 *);
6789
6790 /* tp->lock is held. */
6791 static int tg3_chip_reset(struct tg3 *tp)
6792 {
6793 u32 val;
6794 void (*write_op)(struct tg3 *, u32, u32);
6795 int i, err;
6796
6797 tg3_nvram_lock(tp);
6798
6799 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6800
6801 /* No matching tg3_nvram_unlock() after this because
6802 * chip reset below will undo the nvram lock.
6803 */
6804 tp->nvram_lock_cnt = 0;
6805
6806 /* GRC_MISC_CFG core clock reset will clear the memory
6807 * enable bit in PCI register 4 and the MSI enable bit
6808 * on some chips, so we save relevant registers here.
6809 */
6810 tg3_save_pci_state(tp);
6811
6812 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6813 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6814 tw32(GRC_FASTBOOT_PC, 0);
6815
6816 /*
6817 * We must avoid the readl() that normally takes place.
6818 * It locks machines, causes machine checks, and other
6819 * fun things. So, temporarily disable the 5701
6820 * hardware workaround, while we do the reset.
6821 */
6822 write_op = tp->write32;
6823 if (write_op == tg3_write_flush_reg32)
6824 tp->write32 = tg3_write32;
6825
6826 /* Prevent the irq handler from reading or writing PCI registers
6827 * during chip reset when the memory enable bit in the PCI command
6828 * register may be cleared. The chip does not generate interrupt
6829 * at this time, but the irq handler may still be called due to irq
6830 * sharing or irqpoll.
6831 */
6832 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6833 for (i = 0; i < tp->irq_cnt; i++) {
6834 struct tg3_napi *tnapi = &tp->napi[i];
6835 if (tnapi->hw_status) {
6836 tnapi->hw_status->status = 0;
6837 tnapi->hw_status->status_tag = 0;
6838 }
6839 tnapi->last_tag = 0;
6840 tnapi->last_irq_tag = 0;
6841 }
6842 smp_mb();
6843
6844 for (i = 0; i < tp->irq_cnt; i++)
6845 synchronize_irq(tp->napi[i].irq_vec);
6846
6847 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6848 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6849 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6850 }
6851
6852 /* do the reset */
6853 val = GRC_MISC_CFG_CORECLK_RESET;
6854
6855 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6856 if (tr32(0x7e2c) == 0x60) {
6857 tw32(0x7e2c, 0x20);
6858 }
6859 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6860 tw32(GRC_MISC_CFG, (1 << 29));
6861 val |= (1 << 29);
6862 }
6863 }
6864
6865 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6866 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6867 tw32(GRC_VCPU_EXT_CTRL,
6868 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6869 }
6870
6871 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6872 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6873 tw32(GRC_MISC_CFG, val);
6874
6875 /* restore 5701 hardware bug workaround write method */
6876 tp->write32 = write_op;
6877
6878 /* Unfortunately, we have to delay before the PCI read back.
6879 * Some 575X chips even will not respond to a PCI cfg access
6880 * when the reset command is given to the chip.
6881 *
6882 * How do these hardware designers expect things to work
6883 * properly if the PCI write is posted for a long period
6884 * of time? It is always necessary to have some method by
6885 * which a register read back can occur to push the write
6886 * out which does the reset.
6887 *
6888 * For most tg3 variants the trick below was working.
6889 * Ho hum...
6890 */
6891 udelay(120);
6892
6893 /* Flush PCI posted writes. The normal MMIO registers
6894 * are inaccessible at this time so this is the only
6895 * way to make this reliably (actually, this is no longer
6896 * the case, see above). I tried to use indirect
6897 * register read/write but this upset some 5701 variants.
6898 */
6899 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6900
6901 udelay(120);
6902
6903 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6904 u16 val16;
6905
6906 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6907 int i;
6908 u32 cfg_val;
6909
6910 /* Wait for link training to complete. */
6911 for (i = 0; i < 5000; i++)
6912 udelay(100);
6913
6914 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6915 pci_write_config_dword(tp->pdev, 0xc4,
6916 cfg_val | (1 << 15));
6917 }
6918
6919 /* Clear the "no snoop" and "relaxed ordering" bits. */
6920 pci_read_config_word(tp->pdev,
6921 tp->pcie_cap + PCI_EXP_DEVCTL,
6922 &val16);
6923 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6924 PCI_EXP_DEVCTL_NOSNOOP_EN);
6925 /*
6926 * Older PCIe devices only support the 128 byte
6927 * MPS setting. Enforce the restriction.
6928 */
6929 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6930 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6931 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6932 pci_write_config_word(tp->pdev,
6933 tp->pcie_cap + PCI_EXP_DEVCTL,
6934 val16);
6935
6936 pcie_set_readrq(tp->pdev, 4096);
6937
6938 /* Clear error status */
6939 pci_write_config_word(tp->pdev,
6940 tp->pcie_cap + PCI_EXP_DEVSTA,
6941 PCI_EXP_DEVSTA_CED |
6942 PCI_EXP_DEVSTA_NFED |
6943 PCI_EXP_DEVSTA_FED |
6944 PCI_EXP_DEVSTA_URD);
6945 }
6946
6947 tg3_restore_pci_state(tp);
6948
6949 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6950
6951 val = 0;
6952 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6953 val = tr32(MEMARB_MODE);
6954 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6955
6956 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6957 tg3_stop_fw(tp);
6958 tw32(0x5000, 0x400);
6959 }
6960
6961 tw32(GRC_MODE, tp->grc_mode);
6962
6963 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6964 val = tr32(0xc4);
6965
6966 tw32(0xc4, val | (1 << 15));
6967 }
6968
6969 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6970 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6971 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6972 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6973 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6974 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6975 }
6976
6977 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6978 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6979 tw32_f(MAC_MODE, tp->mac_mode);
6980 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6981 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6982 tw32_f(MAC_MODE, tp->mac_mode);
6983 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6984 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6985 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6986 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6987 tw32_f(MAC_MODE, tp->mac_mode);
6988 } else
6989 tw32_f(MAC_MODE, 0);
6990 udelay(40);
6991
6992 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6993
6994 err = tg3_poll_fw(tp);
6995 if (err)
6996 return err;
6997
6998 tg3_mdio_start(tp);
6999
7000 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7001 u8 phy_addr;
7002
7003 phy_addr = tp->phy_addr;
7004 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7005
7006 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7007 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7008 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7009 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7010 TG3_PCIEPHY_TX0CTRL1_NB_EN;
7011 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7012 udelay(10);
7013
7014 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7015 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7016 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7017 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7018 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7019 udelay(10);
7020
7021 tp->phy_addr = phy_addr;
7022 }
7023
7024 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7025 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7026 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7027 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7028 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
7029 val = tr32(0x7c00);
7030
7031 tw32(0x7c00, val | (1 << 25));
7032 }
7033
7034 /* Reprobe ASF enable state. */
7035 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7036 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7037 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7038 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7039 u32 nic_cfg;
7040
7041 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7042 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7043 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7044 tp->last_event_jiffies = jiffies;
7045 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7046 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7047 }
7048 }
7049
7050 return 0;
7051 }
7052
7053 /* tp->lock is held. */
7054 static void tg3_stop_fw(struct tg3 *tp)
7055 {
7056 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7057 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7058 /* Wait for RX cpu to ACK the previous event. */
7059 tg3_wait_for_event_ack(tp);
7060
7061 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7062
7063 tg3_generate_fw_event(tp);
7064
7065 /* Wait for RX cpu to ACK this event. */
7066 tg3_wait_for_event_ack(tp);
7067 }
7068 }
7069
7070 /* tp->lock is held. */
7071 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7072 {
7073 int err;
7074
7075 tg3_stop_fw(tp);
7076
7077 tg3_write_sig_pre_reset(tp, kind);
7078
7079 tg3_abort_hw(tp, silent);
7080 err = tg3_chip_reset(tp);
7081
7082 __tg3_set_mac_addr(tp, 0);
7083
7084 tg3_write_sig_legacy(tp, kind);
7085 tg3_write_sig_post_reset(tp, kind);
7086
7087 if (err)
7088 return err;
7089
7090 return 0;
7091 }
7092
7093 #define RX_CPU_SCRATCH_BASE 0x30000
7094 #define RX_CPU_SCRATCH_SIZE 0x04000
7095 #define TX_CPU_SCRATCH_BASE 0x34000
7096 #define TX_CPU_SCRATCH_SIZE 0x04000
7097
7098 /* tp->lock is held. */
7099 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7100 {
7101 int i;
7102
7103 BUG_ON(offset == TX_CPU_BASE &&
7104 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7105
7106 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7107 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7108
7109 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7110 return 0;
7111 }
7112 if (offset == RX_CPU_BASE) {
7113 for (i = 0; i < 10000; i++) {
7114 tw32(offset + CPU_STATE, 0xffffffff);
7115 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7116 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7117 break;
7118 }
7119
7120 tw32(offset + CPU_STATE, 0xffffffff);
7121 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7122 udelay(10);
7123 } else {
7124 for (i = 0; i < 10000; i++) {
7125 tw32(offset + CPU_STATE, 0xffffffff);
7126 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7127 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7128 break;
7129 }
7130 }
7131
7132 if (i >= 10000) {
7133 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7134 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7135 return -ENODEV;
7136 }
7137
7138 /* Clear firmware's nvram arbitration. */
7139 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7140 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7141 return 0;
7142 }
7143
7144 struct fw_info {
7145 unsigned int fw_base;
7146 unsigned int fw_len;
7147 const __be32 *fw_data;
7148 };
7149
7150 /* tp->lock is held. */
7151 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7152 int cpu_scratch_size, struct fw_info *info)
7153 {
7154 int err, lock_err, i;
7155 void (*write_op)(struct tg3 *, u32, u32);
7156
7157 if (cpu_base == TX_CPU_BASE &&
7158 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7159 netdev_err(tp->dev, "%s: Trying to load TX cpu firmware which is 5705\n",
7160 __func__);
7161 return -EINVAL;
7162 }
7163
7164 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7165 write_op = tg3_write_mem;
7166 else
7167 write_op = tg3_write_indirect_reg32;
7168
7169 /* It is possible that bootcode is still loading at this point.
7170 * Get the nvram lock first before halting the cpu.
7171 */
7172 lock_err = tg3_nvram_lock(tp);
7173 err = tg3_halt_cpu(tp, cpu_base);
7174 if (!lock_err)
7175 tg3_nvram_unlock(tp);
7176 if (err)
7177 goto out;
7178
7179 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7180 write_op(tp, cpu_scratch_base + i, 0);
7181 tw32(cpu_base + CPU_STATE, 0xffffffff);
7182 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7183 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7184 write_op(tp, (cpu_scratch_base +
7185 (info->fw_base & 0xffff) +
7186 (i * sizeof(u32))),
7187 be32_to_cpu(info->fw_data[i]));
7188
7189 err = 0;
7190
7191 out:
7192 return err;
7193 }
7194
7195 /* tp->lock is held. */
7196 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7197 {
7198 struct fw_info info;
7199 const __be32 *fw_data;
7200 int err, i;
7201
7202 fw_data = (void *)tp->fw->data;
7203
7204 /* Firmware blob starts with version numbers, followed by
7205 start address and length. We are setting complete length.
7206 length = end_address_of_bss - start_address_of_text.
7207 Remainder is the blob to be loaded contiguously
7208 from start address. */
7209
7210 info.fw_base = be32_to_cpu(fw_data[1]);
7211 info.fw_len = tp->fw->size - 12;
7212 info.fw_data = &fw_data[3];
7213
7214 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7215 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7216 &info);
7217 if (err)
7218 return err;
7219
7220 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7221 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7222 &info);
7223 if (err)
7224 return err;
7225
7226 /* Now startup only the RX cpu. */
7227 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7228 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7229
7230 for (i = 0; i < 5; i++) {
7231 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7232 break;
7233 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7234 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7235 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7236 udelay(1000);
7237 }
7238 if (i >= 5) {
7239 netdev_err(tp->dev, "tg3_load_firmware fails to set RX CPU PC, is %08x should be %08x\n",
7240 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7241 return -ENODEV;
7242 }
7243 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7244 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7245
7246 return 0;
7247 }
7248
7249 /* 5705 needs a special version of the TSO firmware. */
7250
7251 /* tp->lock is held. */
7252 static int tg3_load_tso_firmware(struct tg3 *tp)
7253 {
7254 struct fw_info info;
7255 const __be32 *fw_data;
7256 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7257 int err, i;
7258
7259 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7260 return 0;
7261
7262 fw_data = (void *)tp->fw->data;
7263
7264 /* Firmware blob starts with version numbers, followed by
7265 start address and length. We are setting complete length.
7266 length = end_address_of_bss - start_address_of_text.
7267 Remainder is the blob to be loaded contiguously
7268 from start address. */
7269
7270 info.fw_base = be32_to_cpu(fw_data[1]);
7271 cpu_scratch_size = tp->fw_len;
7272 info.fw_len = tp->fw->size - 12;
7273 info.fw_data = &fw_data[3];
7274
7275 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7276 cpu_base = RX_CPU_BASE;
7277 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7278 } else {
7279 cpu_base = TX_CPU_BASE;
7280 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7281 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7282 }
7283
7284 err = tg3_load_firmware_cpu(tp, cpu_base,
7285 cpu_scratch_base, cpu_scratch_size,
7286 &info);
7287 if (err)
7288 return err;
7289
7290 /* Now startup the cpu. */
7291 tw32(cpu_base + CPU_STATE, 0xffffffff);
7292 tw32_f(cpu_base + CPU_PC, info.fw_base);
7293
7294 for (i = 0; i < 5; i++) {
7295 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7296 break;
7297 tw32(cpu_base + CPU_STATE, 0xffffffff);
7298 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7299 tw32_f(cpu_base + CPU_PC, info.fw_base);
7300 udelay(1000);
7301 }
7302 if (i >= 5) {
7303 netdev_err(tp->dev, "%s fails to set CPU PC, is %08x should be %08x\n",
7304 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7305 return -ENODEV;
7306 }
7307 tw32(cpu_base + CPU_STATE, 0xffffffff);
7308 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7309 return 0;
7310 }
7311
7312
7313 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7314 {
7315 struct tg3 *tp = netdev_priv(dev);
7316 struct sockaddr *addr = p;
7317 int err = 0, skip_mac_1 = 0;
7318
7319 if (!is_valid_ether_addr(addr->sa_data))
7320 return -EINVAL;
7321
7322 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7323
7324 if (!netif_running(dev))
7325 return 0;
7326
7327 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7328 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7329
7330 addr0_high = tr32(MAC_ADDR_0_HIGH);
7331 addr0_low = tr32(MAC_ADDR_0_LOW);
7332 addr1_high = tr32(MAC_ADDR_1_HIGH);
7333 addr1_low = tr32(MAC_ADDR_1_LOW);
7334
7335 /* Skip MAC addr 1 if ASF is using it. */
7336 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7337 !(addr1_high == 0 && addr1_low == 0))
7338 skip_mac_1 = 1;
7339 }
7340 spin_lock_bh(&tp->lock);
7341 __tg3_set_mac_addr(tp, skip_mac_1);
7342 spin_unlock_bh(&tp->lock);
7343
7344 return err;
7345 }
7346
7347 /* tp->lock is held. */
7348 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7349 dma_addr_t mapping, u32 maxlen_flags,
7350 u32 nic_addr)
7351 {
7352 tg3_write_mem(tp,
7353 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7354 ((u64) mapping >> 32));
7355 tg3_write_mem(tp,
7356 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7357 ((u64) mapping & 0xffffffff));
7358 tg3_write_mem(tp,
7359 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7360 maxlen_flags);
7361
7362 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7363 tg3_write_mem(tp,
7364 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7365 nic_addr);
7366 }
7367
7368 static void __tg3_set_rx_mode(struct net_device *);
7369 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7370 {
7371 int i;
7372
7373 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7374 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7375 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7376 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7377 } else {
7378 tw32(HOSTCC_TXCOL_TICKS, 0);
7379 tw32(HOSTCC_TXMAX_FRAMES, 0);
7380 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7381 }
7382
7383 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7384 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7385 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7386 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7387 } else {
7388 tw32(HOSTCC_RXCOL_TICKS, 0);
7389 tw32(HOSTCC_RXMAX_FRAMES, 0);
7390 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7391 }
7392
7393 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7394 u32 val = ec->stats_block_coalesce_usecs;
7395
7396 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7397 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7398
7399 if (!netif_carrier_ok(tp->dev))
7400 val = 0;
7401
7402 tw32(HOSTCC_STAT_COAL_TICKS, val);
7403 }
7404
7405 for (i = 0; i < tp->irq_cnt - 1; i++) {
7406 u32 reg;
7407
7408 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7409 tw32(reg, ec->rx_coalesce_usecs);
7410 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7411 tw32(reg, ec->rx_max_coalesced_frames);
7412 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7413 tw32(reg, ec->rx_max_coalesced_frames_irq);
7414
7415 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7416 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7417 tw32(reg, ec->tx_coalesce_usecs);
7418 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7419 tw32(reg, ec->tx_max_coalesced_frames);
7420 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7421 tw32(reg, ec->tx_max_coalesced_frames_irq);
7422 }
7423 }
7424
7425 for (; i < tp->irq_max - 1; i++) {
7426 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7427 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7428 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7429
7430 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7431 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7432 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7433 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7434 }
7435 }
7436 }
7437
7438 /* tp->lock is held. */
7439 static void tg3_rings_reset(struct tg3 *tp)
7440 {
7441 int i;
7442 u32 stblk, txrcb, rxrcb, limit;
7443 struct tg3_napi *tnapi = &tp->napi[0];
7444
7445 /* Disable all transmit rings but the first. */
7446 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7447 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7448 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7449 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7450 else
7451 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7452
7453 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7454 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7455 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7456 BDINFO_FLAGS_DISABLED);
7457
7458
7459 /* Disable all receive return rings but the first. */
7460 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7461 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7462 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7463 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7464 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7465 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7466 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7467 else
7468 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7469
7470 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7471 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7472 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7473 BDINFO_FLAGS_DISABLED);
7474
7475 /* Disable interrupts */
7476 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7477
7478 /* Zero mailbox registers. */
7479 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7480 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7481 tp->napi[i].tx_prod = 0;
7482 tp->napi[i].tx_cons = 0;
7483 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7484 tw32_mailbox(tp->napi[i].prodmbox, 0);
7485 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7486 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7487 }
7488 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7489 tw32_mailbox(tp->napi[0].prodmbox, 0);
7490 } else {
7491 tp->napi[0].tx_prod = 0;
7492 tp->napi[0].tx_cons = 0;
7493 tw32_mailbox(tp->napi[0].prodmbox, 0);
7494 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7495 }
7496
7497 /* Make sure the NIC-based send BD rings are disabled. */
7498 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7499 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7500 for (i = 0; i < 16; i++)
7501 tw32_tx_mbox(mbox + i * 8, 0);
7502 }
7503
7504 txrcb = NIC_SRAM_SEND_RCB;
7505 rxrcb = NIC_SRAM_RCV_RET_RCB;
7506
7507 /* Clear status block in ram. */
7508 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7509
7510 /* Set status block DMA address */
7511 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7512 ((u64) tnapi->status_mapping >> 32));
7513 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7514 ((u64) tnapi->status_mapping & 0xffffffff));
7515
7516 if (tnapi->tx_ring) {
7517 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7518 (TG3_TX_RING_SIZE <<
7519 BDINFO_FLAGS_MAXLEN_SHIFT),
7520 NIC_SRAM_TX_BUFFER_DESC);
7521 txrcb += TG3_BDINFO_SIZE;
7522 }
7523
7524 if (tnapi->rx_rcb) {
7525 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7526 (TG3_RX_RCB_RING_SIZE(tp) <<
7527 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7528 rxrcb += TG3_BDINFO_SIZE;
7529 }
7530
7531 stblk = HOSTCC_STATBLCK_RING1;
7532
7533 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7534 u64 mapping = (u64)tnapi->status_mapping;
7535 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7536 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7537
7538 /* Clear status block in ram. */
7539 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7540
7541 if (tnapi->tx_ring) {
7542 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7543 (TG3_TX_RING_SIZE <<
7544 BDINFO_FLAGS_MAXLEN_SHIFT),
7545 NIC_SRAM_TX_BUFFER_DESC);
7546 txrcb += TG3_BDINFO_SIZE;
7547 }
7548
7549 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7550 (TG3_RX_RCB_RING_SIZE(tp) <<
7551 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7552
7553 stblk += 8;
7554 rxrcb += TG3_BDINFO_SIZE;
7555 }
7556 }
7557
7558 /* tp->lock is held. */
7559 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7560 {
7561 u32 val, rdmac_mode;
7562 int i, err, limit;
7563 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7564
7565 tg3_disable_ints(tp);
7566
7567 tg3_stop_fw(tp);
7568
7569 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7570
7571 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7572 tg3_abort_hw(tp, 1);
7573 }
7574
7575 if (reset_phy)
7576 tg3_phy_reset(tp);
7577
7578 err = tg3_chip_reset(tp);
7579 if (err)
7580 return err;
7581
7582 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7583
7584 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7585 val = tr32(TG3_CPMU_CTRL);
7586 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7587 tw32(TG3_CPMU_CTRL, val);
7588
7589 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7590 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7591 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7592 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7593
7594 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7595 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7596 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7597 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7598
7599 val = tr32(TG3_CPMU_HST_ACC);
7600 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7601 val |= CPMU_HST_ACC_MACCLK_6_25;
7602 tw32(TG3_CPMU_HST_ACC, val);
7603 }
7604
7605 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7606 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7607 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7608 PCIE_PWR_MGMT_L1_THRESH_4MS;
7609 tw32(PCIE_PWR_MGMT_THRESH, val);
7610
7611 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7612 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7613
7614 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7615
7616 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7617 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7618 }
7619
7620 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7621 u32 grc_mode = tr32(GRC_MODE);
7622
7623 /* Access the lower 1K of PL PCIE block registers. */
7624 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7625 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7626
7627 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7628 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7629 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7630
7631 tw32(GRC_MODE, grc_mode);
7632 }
7633
7634 /* This works around an issue with Athlon chipsets on
7635 * B3 tigon3 silicon. This bit has no effect on any
7636 * other revision. But do not set this on PCI Express
7637 * chips and don't even touch the clocks if the CPMU is present.
7638 */
7639 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7640 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7641 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7642 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7643 }
7644
7645 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7646 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7647 val = tr32(TG3PCI_PCISTATE);
7648 val |= PCISTATE_RETRY_SAME_DMA;
7649 tw32(TG3PCI_PCISTATE, val);
7650 }
7651
7652 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7653 /* Allow reads and writes to the
7654 * APE register and memory space.
7655 */
7656 val = tr32(TG3PCI_PCISTATE);
7657 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7658 PCISTATE_ALLOW_APE_SHMEM_WR;
7659 tw32(TG3PCI_PCISTATE, val);
7660 }
7661
7662 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7663 /* Enable some hw fixes. */
7664 val = tr32(TG3PCI_MSI_DATA);
7665 val |= (1 << 26) | (1 << 28) | (1 << 29);
7666 tw32(TG3PCI_MSI_DATA, val);
7667 }
7668
7669 /* Descriptor ring init may make accesses to the
7670 * NIC SRAM area to setup the TX descriptors, so we
7671 * can only do this after the hardware has been
7672 * successfully reset.
7673 */
7674 err = tg3_init_rings(tp);
7675 if (err)
7676 return err;
7677
7678 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7679 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7680 val = tr32(TG3PCI_DMA_RW_CTRL) &
7681 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7682 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7683 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7684 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7685 /* This value is determined during the probe time DMA
7686 * engine test, tg3_test_dma.
7687 */
7688 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7689 }
7690
7691 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7692 GRC_MODE_4X_NIC_SEND_RINGS |
7693 GRC_MODE_NO_TX_PHDR_CSUM |
7694 GRC_MODE_NO_RX_PHDR_CSUM);
7695 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7696
7697 /* Pseudo-header checksum is done by hardware logic and not
7698 * the offload processers, so make the chip do the pseudo-
7699 * header checksums on receive. For transmit it is more
7700 * convenient to do the pseudo-header checksum in software
7701 * as Linux does that on transmit for us in all cases.
7702 */
7703 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7704
7705 tw32(GRC_MODE,
7706 tp->grc_mode |
7707 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7708
7709 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7710 val = tr32(GRC_MISC_CFG);
7711 val &= ~0xff;
7712 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7713 tw32(GRC_MISC_CFG, val);
7714
7715 /* Initialize MBUF/DESC pool. */
7716 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7717 /* Do nothing. */
7718 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7719 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7720 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7721 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7722 else
7723 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7724 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7725 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7726 }
7727 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7728 int fw_len;
7729
7730 fw_len = tp->fw_len;
7731 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7732 tw32(BUFMGR_MB_POOL_ADDR,
7733 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7734 tw32(BUFMGR_MB_POOL_SIZE,
7735 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7736 }
7737
7738 if (tp->dev->mtu <= ETH_DATA_LEN) {
7739 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7740 tp->bufmgr_config.mbuf_read_dma_low_water);
7741 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7742 tp->bufmgr_config.mbuf_mac_rx_low_water);
7743 tw32(BUFMGR_MB_HIGH_WATER,
7744 tp->bufmgr_config.mbuf_high_water);
7745 } else {
7746 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7747 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7748 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7749 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7750 tw32(BUFMGR_MB_HIGH_WATER,
7751 tp->bufmgr_config.mbuf_high_water_jumbo);
7752 }
7753 tw32(BUFMGR_DMA_LOW_WATER,
7754 tp->bufmgr_config.dma_low_water);
7755 tw32(BUFMGR_DMA_HIGH_WATER,
7756 tp->bufmgr_config.dma_high_water);
7757
7758 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7759 for (i = 0; i < 2000; i++) {
7760 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7761 break;
7762 udelay(10);
7763 }
7764 if (i >= 2000) {
7765 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7766 return -ENODEV;
7767 }
7768
7769 /* Setup replenish threshold. */
7770 val = tp->rx_pending / 8;
7771 if (val == 0)
7772 val = 1;
7773 else if (val > tp->rx_std_max_post)
7774 val = tp->rx_std_max_post;
7775 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7776 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7777 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7778
7779 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7780 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7781 }
7782
7783 tw32(RCVBDI_STD_THRESH, val);
7784
7785 /* Initialize TG3_BDINFO's at:
7786 * RCVDBDI_STD_BD: standard eth size rx ring
7787 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7788 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7789 *
7790 * like so:
7791 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7792 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7793 * ring attribute flags
7794 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7795 *
7796 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7797 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7798 *
7799 * The size of each ring is fixed in the firmware, but the location is
7800 * configurable.
7801 */
7802 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7803 ((u64) tpr->rx_std_mapping >> 32));
7804 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7805 ((u64) tpr->rx_std_mapping & 0xffffffff));
7806 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7807 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7808 NIC_SRAM_RX_BUFFER_DESC);
7809
7810 /* Disable the mini ring */
7811 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7812 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7813 BDINFO_FLAGS_DISABLED);
7814
7815 /* Program the jumbo buffer descriptor ring control
7816 * blocks on those devices that have them.
7817 */
7818 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7819 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7820 /* Setup replenish threshold. */
7821 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7822
7823 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7824 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7825 ((u64) tpr->rx_jmb_mapping >> 32));
7826 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7827 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7828 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7829 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7830 BDINFO_FLAGS_USE_EXT_RECV);
7831 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7832 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7833 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7834 } else {
7835 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7836 BDINFO_FLAGS_DISABLED);
7837 }
7838
7839 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7840 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7841 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7842 (RX_STD_MAX_SIZE << 2);
7843 else
7844 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7845 } else
7846 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7847
7848 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7849
7850 tpr->rx_std_prod_idx = tp->rx_pending;
7851 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7852
7853 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7854 tp->rx_jumbo_pending : 0;
7855 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7856
7857 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7858 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7859 tw32(STD_REPLENISH_LWM, 32);
7860 tw32(JMB_REPLENISH_LWM, 16);
7861 }
7862
7863 tg3_rings_reset(tp);
7864
7865 /* Initialize MAC address and backoff seed. */
7866 __tg3_set_mac_addr(tp, 0);
7867
7868 /* MTU + ethernet header + FCS + optional VLAN tag */
7869 tw32(MAC_RX_MTU_SIZE,
7870 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7871
7872 /* The slot time is changed by tg3_setup_phy if we
7873 * run at gigabit with half duplex.
7874 */
7875 tw32(MAC_TX_LENGTHS,
7876 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7877 (6 << TX_LENGTHS_IPG_SHIFT) |
7878 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7879
7880 /* Receive rules. */
7881 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7882 tw32(RCVLPC_CONFIG, 0x0181);
7883
7884 /* Calculate RDMAC_MODE setting early, we need it to determine
7885 * the RCVLPC_STATE_ENABLE mask.
7886 */
7887 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7888 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7889 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7890 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7891 RDMAC_MODE_LNGREAD_ENAB);
7892
7893 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7894 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7895
7896 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7897 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7898 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7899 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7900 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7901 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7902
7903 /* If statement applies to 5705 and 5750 PCI devices only */
7904 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7905 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7906 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7907 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7908 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7909 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7910 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7911 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7912 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7913 }
7914 }
7915
7916 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7917 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7918
7919 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7920 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7921
7922 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7923 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7924 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7925 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7926
7927 /* Receive/send statistics. */
7928 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7929 val = tr32(RCVLPC_STATS_ENABLE);
7930 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7931 tw32(RCVLPC_STATS_ENABLE, val);
7932 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7933 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7934 val = tr32(RCVLPC_STATS_ENABLE);
7935 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7936 tw32(RCVLPC_STATS_ENABLE, val);
7937 } else {
7938 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7939 }
7940 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7941 tw32(SNDDATAI_STATSENAB, 0xffffff);
7942 tw32(SNDDATAI_STATSCTRL,
7943 (SNDDATAI_SCTRL_ENABLE |
7944 SNDDATAI_SCTRL_FASTUPD));
7945
7946 /* Setup host coalescing engine. */
7947 tw32(HOSTCC_MODE, 0);
7948 for (i = 0; i < 2000; i++) {
7949 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7950 break;
7951 udelay(10);
7952 }
7953
7954 __tg3_set_coalesce(tp, &tp->coal);
7955
7956 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7957 /* Status/statistics block address. See tg3_timer,
7958 * the tg3_periodic_fetch_stats call there, and
7959 * tg3_get_stats to see how this works for 5705/5750 chips.
7960 */
7961 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7962 ((u64) tp->stats_mapping >> 32));
7963 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7964 ((u64) tp->stats_mapping & 0xffffffff));
7965 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7966
7967 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7968
7969 /* Clear statistics and status block memory areas */
7970 for (i = NIC_SRAM_STATS_BLK;
7971 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7972 i += sizeof(u32)) {
7973 tg3_write_mem(tp, i, 0);
7974 udelay(40);
7975 }
7976 }
7977
7978 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7979
7980 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7981 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7982 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7983 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7984
7985 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7986 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7987 /* reset to prevent losing 1st rx packet intermittently */
7988 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7989 udelay(10);
7990 }
7991
7992 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7993 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7994 else
7995 tp->mac_mode = 0;
7996 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7997 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7998 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7999 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8000 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8001 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8002 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8003 udelay(40);
8004
8005 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8006 * If TG3_FLG2_IS_NIC is zero, we should read the
8007 * register to preserve the GPIO settings for LOMs. The GPIOs,
8008 * whether used as inputs or outputs, are set by boot code after
8009 * reset.
8010 */
8011 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8012 u32 gpio_mask;
8013
8014 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8015 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8016 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8017
8018 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8019 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8020 GRC_LCLCTRL_GPIO_OUTPUT3;
8021
8022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8023 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8024
8025 tp->grc_local_ctrl &= ~gpio_mask;
8026 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8027
8028 /* GPIO1 must be driven high for eeprom write protect */
8029 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8030 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8031 GRC_LCLCTRL_GPIO_OUTPUT1);
8032 }
8033 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8034 udelay(100);
8035
8036 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8037 val = tr32(MSGINT_MODE);
8038 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8039 tw32(MSGINT_MODE, val);
8040 }
8041
8042 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8043 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8044 udelay(40);
8045 }
8046
8047 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8048 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8049 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8050 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8051 WDMAC_MODE_LNGREAD_ENAB);
8052
8053 /* If statement applies to 5705 and 5750 PCI devices only */
8054 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8055 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8056 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8057 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8058 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8059 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8060 /* nothing */
8061 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8062 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8063 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8064 val |= WDMAC_MODE_RX_ACCEL;
8065 }
8066 }
8067
8068 /* Enable host coalescing bug fix */
8069 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8070 val |= WDMAC_MODE_STATUS_TAG_FIX;
8071
8072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8073 val |= WDMAC_MODE_BURST_ALL_DATA;
8074
8075 tw32_f(WDMAC_MODE, val);
8076 udelay(40);
8077
8078 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8079 u16 pcix_cmd;
8080
8081 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8082 &pcix_cmd);
8083 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8084 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8085 pcix_cmd |= PCI_X_CMD_READ_2K;
8086 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8087 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8088 pcix_cmd |= PCI_X_CMD_READ_2K;
8089 }
8090 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8091 pcix_cmd);
8092 }
8093
8094 tw32_f(RDMAC_MODE, rdmac_mode);
8095 udelay(40);
8096
8097 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8098 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8099 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8100
8101 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8102 tw32(SNDDATAC_MODE,
8103 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8104 else
8105 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8106
8107 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8108 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8109 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8110 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8111 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8112 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8113 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8114 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8115 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8116 tw32(SNDBDI_MODE, val);
8117 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8118
8119 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8120 err = tg3_load_5701_a0_firmware_fix(tp);
8121 if (err)
8122 return err;
8123 }
8124
8125 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8126 err = tg3_load_tso_firmware(tp);
8127 if (err)
8128 return err;
8129 }
8130
8131 tp->tx_mode = TX_MODE_ENABLE;
8132 tw32_f(MAC_TX_MODE, tp->tx_mode);
8133 udelay(100);
8134
8135 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8136 u32 reg = MAC_RSS_INDIR_TBL_0;
8137 u8 *ent = (u8 *)&val;
8138
8139 /* Setup the indirection table */
8140 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8141 int idx = i % sizeof(val);
8142
8143 ent[idx] = i % (tp->irq_cnt - 1);
8144 if (idx == sizeof(val) - 1) {
8145 tw32(reg, val);
8146 reg += 4;
8147 }
8148 }
8149
8150 /* Setup the "secret" hash key. */
8151 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8152 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8153 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8154 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8155 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8156 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8157 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8158 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8159 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8160 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8161 }
8162
8163 tp->rx_mode = RX_MODE_ENABLE;
8164 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8165 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8166
8167 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8168 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8169 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8170 RX_MODE_RSS_IPV6_HASH_EN |
8171 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8172 RX_MODE_RSS_IPV4_HASH_EN |
8173 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8174
8175 tw32_f(MAC_RX_MODE, tp->rx_mode);
8176 udelay(10);
8177
8178 tw32(MAC_LED_CTRL, tp->led_ctrl);
8179
8180 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8181 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8182 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8183 udelay(10);
8184 }
8185 tw32_f(MAC_RX_MODE, tp->rx_mode);
8186 udelay(10);
8187
8188 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8189 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8190 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8191 /* Set drive transmission level to 1.2V */
8192 /* only if the signal pre-emphasis bit is not set */
8193 val = tr32(MAC_SERDES_CFG);
8194 val &= 0xfffff000;
8195 val |= 0x880;
8196 tw32(MAC_SERDES_CFG, val);
8197 }
8198 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8199 tw32(MAC_SERDES_CFG, 0x616000);
8200 }
8201
8202 /* Prevent chip from dropping frames when flow control
8203 * is enabled.
8204 */
8205 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8206 val = 1;
8207 else
8208 val = 2;
8209 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8210
8211 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8212 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8213 /* Use hardware link auto-negotiation */
8214 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8215 }
8216
8217 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8218 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8219 u32 tmp;
8220
8221 tmp = tr32(SERDES_RX_CTRL);
8222 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8223 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8224 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8225 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8226 }
8227
8228 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8229 if (tp->link_config.phy_is_low_power) {
8230 tp->link_config.phy_is_low_power = 0;
8231 tp->link_config.speed = tp->link_config.orig_speed;
8232 tp->link_config.duplex = tp->link_config.orig_duplex;
8233 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8234 }
8235
8236 err = tg3_setup_phy(tp, 0);
8237 if (err)
8238 return err;
8239
8240 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8241 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8242 u32 tmp;
8243
8244 /* Clear CRC stats. */
8245 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8246 tg3_writephy(tp, MII_TG3_TEST1,
8247 tmp | MII_TG3_TEST1_CRC_EN);
8248 tg3_readphy(tp, 0x14, &tmp);
8249 }
8250 }
8251 }
8252
8253 __tg3_set_rx_mode(tp->dev);
8254
8255 /* Initialize receive rules. */
8256 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8257 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8258 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8259 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8260
8261 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8262 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8263 limit = 8;
8264 else
8265 limit = 16;
8266 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8267 limit -= 4;
8268 switch (limit) {
8269 case 16:
8270 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8271 case 15:
8272 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8273 case 14:
8274 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8275 case 13:
8276 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8277 case 12:
8278 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8279 case 11:
8280 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8281 case 10:
8282 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8283 case 9:
8284 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8285 case 8:
8286 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8287 case 7:
8288 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8289 case 6:
8290 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8291 case 5:
8292 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8293 case 4:
8294 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8295 case 3:
8296 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8297 case 2:
8298 case 1:
8299
8300 default:
8301 break;
8302 }
8303
8304 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8305 /* Write our heartbeat update interval to APE. */
8306 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8307 APE_HOST_HEARTBEAT_INT_DISABLE);
8308
8309 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8310
8311 return 0;
8312 }
8313
8314 /* Called at device open time to get the chip ready for
8315 * packet processing. Invoked with tp->lock held.
8316 */
8317 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8318 {
8319 tg3_switch_clocks(tp);
8320
8321 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8322
8323 return tg3_reset_hw(tp, reset_phy);
8324 }
8325
8326 #define TG3_STAT_ADD32(PSTAT, REG) \
8327 do { u32 __val = tr32(REG); \
8328 (PSTAT)->low += __val; \
8329 if ((PSTAT)->low < __val) \
8330 (PSTAT)->high += 1; \
8331 } while (0)
8332
8333 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8334 {
8335 struct tg3_hw_stats *sp = tp->hw_stats;
8336
8337 if (!netif_carrier_ok(tp->dev))
8338 return;
8339
8340 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8341 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8342 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8343 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8344 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8345 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8346 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8347 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8348 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8349 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8350 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8351 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8352 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8353
8354 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8355 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8356 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8357 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8358 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8359 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8360 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8361 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8362 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8363 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8364 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8365 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8366 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8367 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8368
8369 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8370 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8371 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8372 }
8373
8374 static void tg3_timer(unsigned long __opaque)
8375 {
8376 struct tg3 *tp = (struct tg3 *) __opaque;
8377
8378 if (tp->irq_sync)
8379 goto restart_timer;
8380
8381 spin_lock(&tp->lock);
8382
8383 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8384 /* All of this garbage is because when using non-tagged
8385 * IRQ status the mailbox/status_block protocol the chip
8386 * uses with the cpu is race prone.
8387 */
8388 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8389 tw32(GRC_LOCAL_CTRL,
8390 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8391 } else {
8392 tw32(HOSTCC_MODE, tp->coalesce_mode |
8393 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8394 }
8395
8396 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8397 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8398 spin_unlock(&tp->lock);
8399 schedule_work(&tp->reset_task);
8400 return;
8401 }
8402 }
8403
8404 /* This part only runs once per second. */
8405 if (!--tp->timer_counter) {
8406 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8407 tg3_periodic_fetch_stats(tp);
8408
8409 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8410 u32 mac_stat;
8411 int phy_event;
8412
8413 mac_stat = tr32(MAC_STATUS);
8414
8415 phy_event = 0;
8416 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8417 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8418 phy_event = 1;
8419 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8420 phy_event = 1;
8421
8422 if (phy_event)
8423 tg3_setup_phy(tp, 0);
8424 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8425 u32 mac_stat = tr32(MAC_STATUS);
8426 int need_setup = 0;
8427
8428 if (netif_carrier_ok(tp->dev) &&
8429 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8430 need_setup = 1;
8431 }
8432 if (! netif_carrier_ok(tp->dev) &&
8433 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8434 MAC_STATUS_SIGNAL_DET))) {
8435 need_setup = 1;
8436 }
8437 if (need_setup) {
8438 if (!tp->serdes_counter) {
8439 tw32_f(MAC_MODE,
8440 (tp->mac_mode &
8441 ~MAC_MODE_PORT_MODE_MASK));
8442 udelay(40);
8443 tw32_f(MAC_MODE, tp->mac_mode);
8444 udelay(40);
8445 }
8446 tg3_setup_phy(tp, 0);
8447 }
8448 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8449 tg3_serdes_parallel_detect(tp);
8450
8451 tp->timer_counter = tp->timer_multiplier;
8452 }
8453
8454 /* Heartbeat is only sent once every 2 seconds.
8455 *
8456 * The heartbeat is to tell the ASF firmware that the host
8457 * driver is still alive. In the event that the OS crashes,
8458 * ASF needs to reset the hardware to free up the FIFO space
8459 * that may be filled with rx packets destined for the host.
8460 * If the FIFO is full, ASF will no longer function properly.
8461 *
8462 * Unintended resets have been reported on real time kernels
8463 * where the timer doesn't run on time. Netpoll will also have
8464 * same problem.
8465 *
8466 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8467 * to check the ring condition when the heartbeat is expiring
8468 * before doing the reset. This will prevent most unintended
8469 * resets.
8470 */
8471 if (!--tp->asf_counter) {
8472 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8473 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8474 tg3_wait_for_event_ack(tp);
8475
8476 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8477 FWCMD_NICDRV_ALIVE3);
8478 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8479 /* 5 seconds timeout */
8480 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8481
8482 tg3_generate_fw_event(tp);
8483 }
8484 tp->asf_counter = tp->asf_multiplier;
8485 }
8486
8487 spin_unlock(&tp->lock);
8488
8489 restart_timer:
8490 tp->timer.expires = jiffies + tp->timer_offset;
8491 add_timer(&tp->timer);
8492 }
8493
8494 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8495 {
8496 irq_handler_t fn;
8497 unsigned long flags;
8498 char *name;
8499 struct tg3_napi *tnapi = &tp->napi[irq_num];
8500
8501 if (tp->irq_cnt == 1)
8502 name = tp->dev->name;
8503 else {
8504 name = &tnapi->irq_lbl[0];
8505 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8506 name[IFNAMSIZ-1] = 0;
8507 }
8508
8509 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8510 fn = tg3_msi;
8511 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8512 fn = tg3_msi_1shot;
8513 flags = IRQF_SAMPLE_RANDOM;
8514 } else {
8515 fn = tg3_interrupt;
8516 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8517 fn = tg3_interrupt_tagged;
8518 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8519 }
8520
8521 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8522 }
8523
8524 static int tg3_test_interrupt(struct tg3 *tp)
8525 {
8526 struct tg3_napi *tnapi = &tp->napi[0];
8527 struct net_device *dev = tp->dev;
8528 int err, i, intr_ok = 0;
8529 u32 val;
8530
8531 if (!netif_running(dev))
8532 return -ENODEV;
8533
8534 tg3_disable_ints(tp);
8535
8536 free_irq(tnapi->irq_vec, tnapi);
8537
8538 /*
8539 * Turn off MSI one shot mode. Otherwise this test has no
8540 * observable way to know whether the interrupt was delivered.
8541 */
8542 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8543 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8544 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8545 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8546 tw32(MSGINT_MODE, val);
8547 }
8548
8549 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8550 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8551 if (err)
8552 return err;
8553
8554 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8555 tg3_enable_ints(tp);
8556
8557 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8558 tnapi->coal_now);
8559
8560 for (i = 0; i < 5; i++) {
8561 u32 int_mbox, misc_host_ctrl;
8562
8563 int_mbox = tr32_mailbox(tnapi->int_mbox);
8564 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8565
8566 if ((int_mbox != 0) ||
8567 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8568 intr_ok = 1;
8569 break;
8570 }
8571
8572 msleep(10);
8573 }
8574
8575 tg3_disable_ints(tp);
8576
8577 free_irq(tnapi->irq_vec, tnapi);
8578
8579 err = tg3_request_irq(tp, 0);
8580
8581 if (err)
8582 return err;
8583
8584 if (intr_ok) {
8585 /* Reenable MSI one shot mode. */
8586 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8587 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8588 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8589 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8590 tw32(MSGINT_MODE, val);
8591 }
8592 return 0;
8593 }
8594
8595 return -EIO;
8596 }
8597
8598 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8599 * successfully restored
8600 */
8601 static int tg3_test_msi(struct tg3 *tp)
8602 {
8603 int err;
8604 u16 pci_cmd;
8605
8606 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8607 return 0;
8608
8609 /* Turn off SERR reporting in case MSI terminates with Master
8610 * Abort.
8611 */
8612 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8613 pci_write_config_word(tp->pdev, PCI_COMMAND,
8614 pci_cmd & ~PCI_COMMAND_SERR);
8615
8616 err = tg3_test_interrupt(tp);
8617
8618 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8619
8620 if (!err)
8621 return 0;
8622
8623 /* other failures */
8624 if (err != -EIO)
8625 return err;
8626
8627 /* MSI test failed, go back to INTx mode */
8628 netdev_warn(tp->dev, "No interrupt was generated using MSI, switching to INTx mode\n"
8629 "Please report this failure to the PCI maintainer and include system chipset information\n");
8630
8631 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8632
8633 pci_disable_msi(tp->pdev);
8634
8635 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8636 tp->napi[0].irq_vec = tp->pdev->irq;
8637
8638 err = tg3_request_irq(tp, 0);
8639 if (err)
8640 return err;
8641
8642 /* Need to reset the chip because the MSI cycle may have terminated
8643 * with Master Abort.
8644 */
8645 tg3_full_lock(tp, 1);
8646
8647 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8648 err = tg3_init_hw(tp, 1);
8649
8650 tg3_full_unlock(tp);
8651
8652 if (err)
8653 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8654
8655 return err;
8656 }
8657
8658 static int tg3_request_firmware(struct tg3 *tp)
8659 {
8660 const __be32 *fw_data;
8661
8662 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8663 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8664 tp->fw_needed);
8665 return -ENOENT;
8666 }
8667
8668 fw_data = (void *)tp->fw->data;
8669
8670 /* Firmware blob starts with version numbers, followed by
8671 * start address and _full_ length including BSS sections
8672 * (which must be longer than the actual data, of course
8673 */
8674
8675 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8676 if (tp->fw_len < (tp->fw->size - 12)) {
8677 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8678 tp->fw_len, tp->fw_needed);
8679 release_firmware(tp->fw);
8680 tp->fw = NULL;
8681 return -EINVAL;
8682 }
8683
8684 /* We no longer need firmware; we have it. */
8685 tp->fw_needed = NULL;
8686 return 0;
8687 }
8688
8689 static bool tg3_enable_msix(struct tg3 *tp)
8690 {
8691 int i, rc, cpus = num_online_cpus();
8692 struct msix_entry msix_ent[tp->irq_max];
8693
8694 if (cpus == 1)
8695 /* Just fallback to the simpler MSI mode. */
8696 return false;
8697
8698 /*
8699 * We want as many rx rings enabled as there are cpus.
8700 * The first MSIX vector only deals with link interrupts, etc,
8701 * so we add one to the number of vectors we are requesting.
8702 */
8703 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8704
8705 for (i = 0; i < tp->irq_max; i++) {
8706 msix_ent[i].entry = i;
8707 msix_ent[i].vector = 0;
8708 }
8709
8710 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8711 if (rc != 0) {
8712 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8713 return false;
8714 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8715 return false;
8716 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8717 tp->irq_cnt, rc);
8718 tp->irq_cnt = rc;
8719 }
8720
8721 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8722
8723 for (i = 0; i < tp->irq_max; i++)
8724 tp->napi[i].irq_vec = msix_ent[i].vector;
8725
8726 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8727 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8728 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8729 } else
8730 tp->dev->real_num_tx_queues = 1;
8731
8732 return true;
8733 }
8734
8735 static void tg3_ints_init(struct tg3 *tp)
8736 {
8737 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8738 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8739 /* All MSI supporting chips should support tagged
8740 * status. Assert that this is the case.
8741 */
8742 netdev_warn(tp->dev, "MSI without TAGGED? Not using MSI\n");
8743 goto defcfg;
8744 }
8745
8746 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8747 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8748 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8749 pci_enable_msi(tp->pdev) == 0)
8750 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8751
8752 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8753 u32 msi_mode = tr32(MSGINT_MODE);
8754 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8755 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8756 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8757 }
8758 defcfg:
8759 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8760 tp->irq_cnt = 1;
8761 tp->napi[0].irq_vec = tp->pdev->irq;
8762 tp->dev->real_num_tx_queues = 1;
8763 }
8764 }
8765
8766 static void tg3_ints_fini(struct tg3 *tp)
8767 {
8768 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8769 pci_disable_msix(tp->pdev);
8770 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8771 pci_disable_msi(tp->pdev);
8772 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8773 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8774 }
8775
8776 static int tg3_open(struct net_device *dev)
8777 {
8778 struct tg3 *tp = netdev_priv(dev);
8779 int i, err;
8780
8781 if (tp->fw_needed) {
8782 err = tg3_request_firmware(tp);
8783 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8784 if (err)
8785 return err;
8786 } else if (err) {
8787 netdev_warn(tp->dev, "TSO capability disabled\n");
8788 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8789 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8790 netdev_notice(tp->dev, "TSO capability restored\n");
8791 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8792 }
8793 }
8794
8795 netif_carrier_off(tp->dev);
8796
8797 err = tg3_set_power_state(tp, PCI_D0);
8798 if (err)
8799 return err;
8800
8801 tg3_full_lock(tp, 0);
8802
8803 tg3_disable_ints(tp);
8804 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8805
8806 tg3_full_unlock(tp);
8807
8808 /*
8809 * Setup interrupts first so we know how
8810 * many NAPI resources to allocate
8811 */
8812 tg3_ints_init(tp);
8813
8814 /* The placement of this call is tied
8815 * to the setup and use of Host TX descriptors.
8816 */
8817 err = tg3_alloc_consistent(tp);
8818 if (err)
8819 goto err_out1;
8820
8821 tg3_napi_enable(tp);
8822
8823 for (i = 0; i < tp->irq_cnt; i++) {
8824 struct tg3_napi *tnapi = &tp->napi[i];
8825 err = tg3_request_irq(tp, i);
8826 if (err) {
8827 for (i--; i >= 0; i--)
8828 free_irq(tnapi->irq_vec, tnapi);
8829 break;
8830 }
8831 }
8832
8833 if (err)
8834 goto err_out2;
8835
8836 tg3_full_lock(tp, 0);
8837
8838 err = tg3_init_hw(tp, 1);
8839 if (err) {
8840 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8841 tg3_free_rings(tp);
8842 } else {
8843 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8844 tp->timer_offset = HZ;
8845 else
8846 tp->timer_offset = HZ / 10;
8847
8848 BUG_ON(tp->timer_offset > HZ);
8849 tp->timer_counter = tp->timer_multiplier =
8850 (HZ / tp->timer_offset);
8851 tp->asf_counter = tp->asf_multiplier =
8852 ((HZ / tp->timer_offset) * 2);
8853
8854 init_timer(&tp->timer);
8855 tp->timer.expires = jiffies + tp->timer_offset;
8856 tp->timer.data = (unsigned long) tp;
8857 tp->timer.function = tg3_timer;
8858 }
8859
8860 tg3_full_unlock(tp);
8861
8862 if (err)
8863 goto err_out3;
8864
8865 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8866 err = tg3_test_msi(tp);
8867
8868 if (err) {
8869 tg3_full_lock(tp, 0);
8870 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8871 tg3_free_rings(tp);
8872 tg3_full_unlock(tp);
8873
8874 goto err_out2;
8875 }
8876
8877 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8878 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8879 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8880 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8881 u32 val = tr32(PCIE_TRANSACTION_CFG);
8882
8883 tw32(PCIE_TRANSACTION_CFG,
8884 val | PCIE_TRANS_CFG_1SHOT_MSI);
8885 }
8886 }
8887
8888 tg3_phy_start(tp);
8889
8890 tg3_full_lock(tp, 0);
8891
8892 add_timer(&tp->timer);
8893 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8894 tg3_enable_ints(tp);
8895
8896 tg3_full_unlock(tp);
8897
8898 netif_tx_start_all_queues(dev);
8899
8900 return 0;
8901
8902 err_out3:
8903 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8904 struct tg3_napi *tnapi = &tp->napi[i];
8905 free_irq(tnapi->irq_vec, tnapi);
8906 }
8907
8908 err_out2:
8909 tg3_napi_disable(tp);
8910 tg3_free_consistent(tp);
8911
8912 err_out1:
8913 tg3_ints_fini(tp);
8914 return err;
8915 }
8916
8917 #if 0
8918 /*static*/ void tg3_dump_state(struct tg3 *tp)
8919 {
8920 u32 val32, val32_2, val32_3, val32_4, val32_5;
8921 u16 val16;
8922 int i;
8923 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8924
8925 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8926 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8927 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8928 val16, val32);
8929
8930 /* MAC block */
8931 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8932 tr32(MAC_MODE), tr32(MAC_STATUS));
8933 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8934 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8935 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8936 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8937 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8938 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8939
8940 /* Send data initiator control block */
8941 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8942 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8943 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8944 tr32(SNDDATAI_STATSCTRL));
8945
8946 /* Send data completion control block */
8947 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8948
8949 /* Send BD ring selector block */
8950 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8951 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8952
8953 /* Send BD initiator control block */
8954 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8955 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8956
8957 /* Send BD completion control block */
8958 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8959
8960 /* Receive list placement control block */
8961 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8962 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8963 printk(" RCVLPC_STATSCTRL[%08x]\n",
8964 tr32(RCVLPC_STATSCTRL));
8965
8966 /* Receive data and receive BD initiator control block */
8967 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8968 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8969
8970 /* Receive data completion control block */
8971 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8972 tr32(RCVDCC_MODE));
8973
8974 /* Receive BD initiator control block */
8975 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8976 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8977
8978 /* Receive BD completion control block */
8979 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8980 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8981
8982 /* Receive list selector control block */
8983 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8984 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8985
8986 /* Mbuf cluster free block */
8987 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8988 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8989
8990 /* Host coalescing control block */
8991 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8992 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8993 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8994 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8995 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8996 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8997 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8998 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8999 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
9000 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
9001 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
9002 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
9003
9004 /* Memory arbiter control block */
9005 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
9006 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
9007
9008 /* Buffer manager control block */
9009 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
9010 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
9011 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
9012 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
9013 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
9014 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
9015 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
9016 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
9017
9018 /* Read DMA control block */
9019 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
9020 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
9021
9022 /* Write DMA control block */
9023 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
9024 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
9025
9026 /* DMA completion block */
9027 printk("DEBUG: DMAC_MODE[%08x]\n",
9028 tr32(DMAC_MODE));
9029
9030 /* GRC block */
9031 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
9032 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
9033 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
9034 tr32(GRC_LOCAL_CTRL));
9035
9036 /* TG3_BDINFOs */
9037 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9038 tr32(RCVDBDI_JUMBO_BD + 0x0),
9039 tr32(RCVDBDI_JUMBO_BD + 0x4),
9040 tr32(RCVDBDI_JUMBO_BD + 0x8),
9041 tr32(RCVDBDI_JUMBO_BD + 0xc));
9042 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9043 tr32(RCVDBDI_STD_BD + 0x0),
9044 tr32(RCVDBDI_STD_BD + 0x4),
9045 tr32(RCVDBDI_STD_BD + 0x8),
9046 tr32(RCVDBDI_STD_BD + 0xc));
9047 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9048 tr32(RCVDBDI_MINI_BD + 0x0),
9049 tr32(RCVDBDI_MINI_BD + 0x4),
9050 tr32(RCVDBDI_MINI_BD + 0x8),
9051 tr32(RCVDBDI_MINI_BD + 0xc));
9052
9053 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9054 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9055 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9056 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9057 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9058 val32, val32_2, val32_3, val32_4);
9059
9060 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9061 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9062 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9063 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9064 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9065 val32, val32_2, val32_3, val32_4);
9066
9067 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9068 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9069 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9070 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9071 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9072 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9073 val32, val32_2, val32_3, val32_4, val32_5);
9074
9075 /* SW status block */
9076 printk(KERN_DEBUG
9077 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9078 sblk->status,
9079 sblk->status_tag,
9080 sblk->rx_jumbo_consumer,
9081 sblk->rx_consumer,
9082 sblk->rx_mini_consumer,
9083 sblk->idx[0].rx_producer,
9084 sblk->idx[0].tx_consumer);
9085
9086 /* SW statistics block */
9087 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9088 ((u32 *)tp->hw_stats)[0],
9089 ((u32 *)tp->hw_stats)[1],
9090 ((u32 *)tp->hw_stats)[2],
9091 ((u32 *)tp->hw_stats)[3]);
9092
9093 /* Mailboxes */
9094 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
9095 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9096 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9097 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9098 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
9099
9100 /* NIC side send descriptors. */
9101 for (i = 0; i < 6; i++) {
9102 unsigned long txd;
9103
9104 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9105 + (i * sizeof(struct tg3_tx_buffer_desc));
9106 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9107 i,
9108 readl(txd + 0x0), readl(txd + 0x4),
9109 readl(txd + 0x8), readl(txd + 0xc));
9110 }
9111
9112 /* NIC side RX descriptors. */
9113 for (i = 0; i < 6; i++) {
9114 unsigned long rxd;
9115
9116 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9117 + (i * sizeof(struct tg3_rx_buffer_desc));
9118 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9119 i,
9120 readl(rxd + 0x0), readl(rxd + 0x4),
9121 readl(rxd + 0x8), readl(rxd + 0xc));
9122 rxd += (4 * sizeof(u32));
9123 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9124 i,
9125 readl(rxd + 0x0), readl(rxd + 0x4),
9126 readl(rxd + 0x8), readl(rxd + 0xc));
9127 }
9128
9129 for (i = 0; i < 6; i++) {
9130 unsigned long rxd;
9131
9132 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9133 + (i * sizeof(struct tg3_rx_buffer_desc));
9134 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9135 i,
9136 readl(rxd + 0x0), readl(rxd + 0x4),
9137 readl(rxd + 0x8), readl(rxd + 0xc));
9138 rxd += (4 * sizeof(u32));
9139 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9140 i,
9141 readl(rxd + 0x0), readl(rxd + 0x4),
9142 readl(rxd + 0x8), readl(rxd + 0xc));
9143 }
9144 }
9145 #endif
9146
9147 static struct net_device_stats *tg3_get_stats(struct net_device *);
9148 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9149
9150 static int tg3_close(struct net_device *dev)
9151 {
9152 int i;
9153 struct tg3 *tp = netdev_priv(dev);
9154
9155 tg3_napi_disable(tp);
9156 cancel_work_sync(&tp->reset_task);
9157
9158 netif_tx_stop_all_queues(dev);
9159
9160 del_timer_sync(&tp->timer);
9161
9162 tg3_phy_stop(tp);
9163
9164 tg3_full_lock(tp, 1);
9165 #if 0
9166 tg3_dump_state(tp);
9167 #endif
9168
9169 tg3_disable_ints(tp);
9170
9171 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9172 tg3_free_rings(tp);
9173 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9174
9175 tg3_full_unlock(tp);
9176
9177 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9178 struct tg3_napi *tnapi = &tp->napi[i];
9179 free_irq(tnapi->irq_vec, tnapi);
9180 }
9181
9182 tg3_ints_fini(tp);
9183
9184 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9185 sizeof(tp->net_stats_prev));
9186 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9187 sizeof(tp->estats_prev));
9188
9189 tg3_free_consistent(tp);
9190
9191 tg3_set_power_state(tp, PCI_D3hot);
9192
9193 netif_carrier_off(tp->dev);
9194
9195 return 0;
9196 }
9197
9198 static inline unsigned long get_stat64(tg3_stat64_t *val)
9199 {
9200 unsigned long ret;
9201
9202 #if (BITS_PER_LONG == 32)
9203 ret = val->low;
9204 #else
9205 ret = ((u64)val->high << 32) | ((u64)val->low);
9206 #endif
9207 return ret;
9208 }
9209
9210 static inline u64 get_estat64(tg3_stat64_t *val)
9211 {
9212 return ((u64)val->high << 32) | ((u64)val->low);
9213 }
9214
9215 static unsigned long calc_crc_errors(struct tg3 *tp)
9216 {
9217 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9218
9219 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9220 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9221 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9222 u32 val;
9223
9224 spin_lock_bh(&tp->lock);
9225 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9226 tg3_writephy(tp, MII_TG3_TEST1,
9227 val | MII_TG3_TEST1_CRC_EN);
9228 tg3_readphy(tp, 0x14, &val);
9229 } else
9230 val = 0;
9231 spin_unlock_bh(&tp->lock);
9232
9233 tp->phy_crc_errors += val;
9234
9235 return tp->phy_crc_errors;
9236 }
9237
9238 return get_stat64(&hw_stats->rx_fcs_errors);
9239 }
9240
9241 #define ESTAT_ADD(member) \
9242 estats->member = old_estats->member + \
9243 get_estat64(&hw_stats->member)
9244
9245 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9246 {
9247 struct tg3_ethtool_stats *estats = &tp->estats;
9248 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9249 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9250
9251 if (!hw_stats)
9252 return old_estats;
9253
9254 ESTAT_ADD(rx_octets);
9255 ESTAT_ADD(rx_fragments);
9256 ESTAT_ADD(rx_ucast_packets);
9257 ESTAT_ADD(rx_mcast_packets);
9258 ESTAT_ADD(rx_bcast_packets);
9259 ESTAT_ADD(rx_fcs_errors);
9260 ESTAT_ADD(rx_align_errors);
9261 ESTAT_ADD(rx_xon_pause_rcvd);
9262 ESTAT_ADD(rx_xoff_pause_rcvd);
9263 ESTAT_ADD(rx_mac_ctrl_rcvd);
9264 ESTAT_ADD(rx_xoff_entered);
9265 ESTAT_ADD(rx_frame_too_long_errors);
9266 ESTAT_ADD(rx_jabbers);
9267 ESTAT_ADD(rx_undersize_packets);
9268 ESTAT_ADD(rx_in_length_errors);
9269 ESTAT_ADD(rx_out_length_errors);
9270 ESTAT_ADD(rx_64_or_less_octet_packets);
9271 ESTAT_ADD(rx_65_to_127_octet_packets);
9272 ESTAT_ADD(rx_128_to_255_octet_packets);
9273 ESTAT_ADD(rx_256_to_511_octet_packets);
9274 ESTAT_ADD(rx_512_to_1023_octet_packets);
9275 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9276 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9277 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9278 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9279 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9280
9281 ESTAT_ADD(tx_octets);
9282 ESTAT_ADD(tx_collisions);
9283 ESTAT_ADD(tx_xon_sent);
9284 ESTAT_ADD(tx_xoff_sent);
9285 ESTAT_ADD(tx_flow_control);
9286 ESTAT_ADD(tx_mac_errors);
9287 ESTAT_ADD(tx_single_collisions);
9288 ESTAT_ADD(tx_mult_collisions);
9289 ESTAT_ADD(tx_deferred);
9290 ESTAT_ADD(tx_excessive_collisions);
9291 ESTAT_ADD(tx_late_collisions);
9292 ESTAT_ADD(tx_collide_2times);
9293 ESTAT_ADD(tx_collide_3times);
9294 ESTAT_ADD(tx_collide_4times);
9295 ESTAT_ADD(tx_collide_5times);
9296 ESTAT_ADD(tx_collide_6times);
9297 ESTAT_ADD(tx_collide_7times);
9298 ESTAT_ADD(tx_collide_8times);
9299 ESTAT_ADD(tx_collide_9times);
9300 ESTAT_ADD(tx_collide_10times);
9301 ESTAT_ADD(tx_collide_11times);
9302 ESTAT_ADD(tx_collide_12times);
9303 ESTAT_ADD(tx_collide_13times);
9304 ESTAT_ADD(tx_collide_14times);
9305 ESTAT_ADD(tx_collide_15times);
9306 ESTAT_ADD(tx_ucast_packets);
9307 ESTAT_ADD(tx_mcast_packets);
9308 ESTAT_ADD(tx_bcast_packets);
9309 ESTAT_ADD(tx_carrier_sense_errors);
9310 ESTAT_ADD(tx_discards);
9311 ESTAT_ADD(tx_errors);
9312
9313 ESTAT_ADD(dma_writeq_full);
9314 ESTAT_ADD(dma_write_prioq_full);
9315 ESTAT_ADD(rxbds_empty);
9316 ESTAT_ADD(rx_discards);
9317 ESTAT_ADD(rx_errors);
9318 ESTAT_ADD(rx_threshold_hit);
9319
9320 ESTAT_ADD(dma_readq_full);
9321 ESTAT_ADD(dma_read_prioq_full);
9322 ESTAT_ADD(tx_comp_queue_full);
9323
9324 ESTAT_ADD(ring_set_send_prod_index);
9325 ESTAT_ADD(ring_status_update);
9326 ESTAT_ADD(nic_irqs);
9327 ESTAT_ADD(nic_avoided_irqs);
9328 ESTAT_ADD(nic_tx_threshold_hit);
9329
9330 return estats;
9331 }
9332
9333 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9334 {
9335 struct tg3 *tp = netdev_priv(dev);
9336 struct net_device_stats *stats = &tp->net_stats;
9337 struct net_device_stats *old_stats = &tp->net_stats_prev;
9338 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9339
9340 if (!hw_stats)
9341 return old_stats;
9342
9343 stats->rx_packets = old_stats->rx_packets +
9344 get_stat64(&hw_stats->rx_ucast_packets) +
9345 get_stat64(&hw_stats->rx_mcast_packets) +
9346 get_stat64(&hw_stats->rx_bcast_packets);
9347
9348 stats->tx_packets = old_stats->tx_packets +
9349 get_stat64(&hw_stats->tx_ucast_packets) +
9350 get_stat64(&hw_stats->tx_mcast_packets) +
9351 get_stat64(&hw_stats->tx_bcast_packets);
9352
9353 stats->rx_bytes = old_stats->rx_bytes +
9354 get_stat64(&hw_stats->rx_octets);
9355 stats->tx_bytes = old_stats->tx_bytes +
9356 get_stat64(&hw_stats->tx_octets);
9357
9358 stats->rx_errors = old_stats->rx_errors +
9359 get_stat64(&hw_stats->rx_errors);
9360 stats->tx_errors = old_stats->tx_errors +
9361 get_stat64(&hw_stats->tx_errors) +
9362 get_stat64(&hw_stats->tx_mac_errors) +
9363 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9364 get_stat64(&hw_stats->tx_discards);
9365
9366 stats->multicast = old_stats->multicast +
9367 get_stat64(&hw_stats->rx_mcast_packets);
9368 stats->collisions = old_stats->collisions +
9369 get_stat64(&hw_stats->tx_collisions);
9370
9371 stats->rx_length_errors = old_stats->rx_length_errors +
9372 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9373 get_stat64(&hw_stats->rx_undersize_packets);
9374
9375 stats->rx_over_errors = old_stats->rx_over_errors +
9376 get_stat64(&hw_stats->rxbds_empty);
9377 stats->rx_frame_errors = old_stats->rx_frame_errors +
9378 get_stat64(&hw_stats->rx_align_errors);
9379 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9380 get_stat64(&hw_stats->tx_discards);
9381 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9382 get_stat64(&hw_stats->tx_carrier_sense_errors);
9383
9384 stats->rx_crc_errors = old_stats->rx_crc_errors +
9385 calc_crc_errors(tp);
9386
9387 stats->rx_missed_errors = old_stats->rx_missed_errors +
9388 get_stat64(&hw_stats->rx_discards);
9389
9390 return stats;
9391 }
9392
9393 static inline u32 calc_crc(unsigned char *buf, int len)
9394 {
9395 u32 reg;
9396 u32 tmp;
9397 int j, k;
9398
9399 reg = 0xffffffff;
9400
9401 for (j = 0; j < len; j++) {
9402 reg ^= buf[j];
9403
9404 for (k = 0; k < 8; k++) {
9405 tmp = reg & 0x01;
9406
9407 reg >>= 1;
9408
9409 if (tmp) {
9410 reg ^= 0xedb88320;
9411 }
9412 }
9413 }
9414
9415 return ~reg;
9416 }
9417
9418 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9419 {
9420 /* accept or reject all multicast frames */
9421 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9422 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9423 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9424 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9425 }
9426
9427 static void __tg3_set_rx_mode(struct net_device *dev)
9428 {
9429 struct tg3 *tp = netdev_priv(dev);
9430 u32 rx_mode;
9431
9432 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9433 RX_MODE_KEEP_VLAN_TAG);
9434
9435 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9436 * flag clear.
9437 */
9438 #if TG3_VLAN_TAG_USED
9439 if (!tp->vlgrp &&
9440 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9441 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9442 #else
9443 /* By definition, VLAN is disabled always in this
9444 * case.
9445 */
9446 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9447 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9448 #endif
9449
9450 if (dev->flags & IFF_PROMISC) {
9451 /* Promiscuous mode. */
9452 rx_mode |= RX_MODE_PROMISC;
9453 } else if (dev->flags & IFF_ALLMULTI) {
9454 /* Accept all multicast. */
9455 tg3_set_multi (tp, 1);
9456 } else if (netdev_mc_empty(dev)) {
9457 /* Reject all multicast. */
9458 tg3_set_multi (tp, 0);
9459 } else {
9460 /* Accept one or more multicast(s). */
9461 struct dev_mc_list *mclist;
9462 u32 mc_filter[4] = { 0, };
9463 u32 regidx;
9464 u32 bit;
9465 u32 crc;
9466
9467 netdev_for_each_mc_addr(mclist, dev) {
9468 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9469 bit = ~crc & 0x7f;
9470 regidx = (bit & 0x60) >> 5;
9471 bit &= 0x1f;
9472 mc_filter[regidx] |= (1 << bit);
9473 }
9474
9475 tw32(MAC_HASH_REG_0, mc_filter[0]);
9476 tw32(MAC_HASH_REG_1, mc_filter[1]);
9477 tw32(MAC_HASH_REG_2, mc_filter[2]);
9478 tw32(MAC_HASH_REG_3, mc_filter[3]);
9479 }
9480
9481 if (rx_mode != tp->rx_mode) {
9482 tp->rx_mode = rx_mode;
9483 tw32_f(MAC_RX_MODE, rx_mode);
9484 udelay(10);
9485 }
9486 }
9487
9488 static void tg3_set_rx_mode(struct net_device *dev)
9489 {
9490 struct tg3 *tp = netdev_priv(dev);
9491
9492 if (!netif_running(dev))
9493 return;
9494
9495 tg3_full_lock(tp, 0);
9496 __tg3_set_rx_mode(dev);
9497 tg3_full_unlock(tp);
9498 }
9499
9500 #define TG3_REGDUMP_LEN (32 * 1024)
9501
9502 static int tg3_get_regs_len(struct net_device *dev)
9503 {
9504 return TG3_REGDUMP_LEN;
9505 }
9506
9507 static void tg3_get_regs(struct net_device *dev,
9508 struct ethtool_regs *regs, void *_p)
9509 {
9510 u32 *p = _p;
9511 struct tg3 *tp = netdev_priv(dev);
9512 u8 *orig_p = _p;
9513 int i;
9514
9515 regs->version = 0;
9516
9517 memset(p, 0, TG3_REGDUMP_LEN);
9518
9519 if (tp->link_config.phy_is_low_power)
9520 return;
9521
9522 tg3_full_lock(tp, 0);
9523
9524 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9525 #define GET_REG32_LOOP(base,len) \
9526 do { p = (u32 *)(orig_p + (base)); \
9527 for (i = 0; i < len; i += 4) \
9528 __GET_REG32((base) + i); \
9529 } while (0)
9530 #define GET_REG32_1(reg) \
9531 do { p = (u32 *)(orig_p + (reg)); \
9532 __GET_REG32((reg)); \
9533 } while (0)
9534
9535 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9536 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9537 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9538 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9539 GET_REG32_1(SNDDATAC_MODE);
9540 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9541 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9542 GET_REG32_1(SNDBDC_MODE);
9543 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9544 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9545 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9546 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9547 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9548 GET_REG32_1(RCVDCC_MODE);
9549 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9550 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9551 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9552 GET_REG32_1(MBFREE_MODE);
9553 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9554 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9555 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9556 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9557 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9558 GET_REG32_1(RX_CPU_MODE);
9559 GET_REG32_1(RX_CPU_STATE);
9560 GET_REG32_1(RX_CPU_PGMCTR);
9561 GET_REG32_1(RX_CPU_HWBKPT);
9562 GET_REG32_1(TX_CPU_MODE);
9563 GET_REG32_1(TX_CPU_STATE);
9564 GET_REG32_1(TX_CPU_PGMCTR);
9565 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9566 GET_REG32_LOOP(FTQ_RESET, 0x120);
9567 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9568 GET_REG32_1(DMAC_MODE);
9569 GET_REG32_LOOP(GRC_MODE, 0x4c);
9570 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9571 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9572
9573 #undef __GET_REG32
9574 #undef GET_REG32_LOOP
9575 #undef GET_REG32_1
9576
9577 tg3_full_unlock(tp);
9578 }
9579
9580 static int tg3_get_eeprom_len(struct net_device *dev)
9581 {
9582 struct tg3 *tp = netdev_priv(dev);
9583
9584 return tp->nvram_size;
9585 }
9586
9587 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9588 {
9589 struct tg3 *tp = netdev_priv(dev);
9590 int ret;
9591 u8 *pd;
9592 u32 i, offset, len, b_offset, b_count;
9593 __be32 val;
9594
9595 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9596 return -EINVAL;
9597
9598 if (tp->link_config.phy_is_low_power)
9599 return -EAGAIN;
9600
9601 offset = eeprom->offset;
9602 len = eeprom->len;
9603 eeprom->len = 0;
9604
9605 eeprom->magic = TG3_EEPROM_MAGIC;
9606
9607 if (offset & 3) {
9608 /* adjustments to start on required 4 byte boundary */
9609 b_offset = offset & 3;
9610 b_count = 4 - b_offset;
9611 if (b_count > len) {
9612 /* i.e. offset=1 len=2 */
9613 b_count = len;
9614 }
9615 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9616 if (ret)
9617 return ret;
9618 memcpy(data, ((char*)&val) + b_offset, b_count);
9619 len -= b_count;
9620 offset += b_count;
9621 eeprom->len += b_count;
9622 }
9623
9624 /* read bytes upto the last 4 byte boundary */
9625 pd = &data[eeprom->len];
9626 for (i = 0; i < (len - (len & 3)); i += 4) {
9627 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9628 if (ret) {
9629 eeprom->len += i;
9630 return ret;
9631 }
9632 memcpy(pd + i, &val, 4);
9633 }
9634 eeprom->len += i;
9635
9636 if (len & 3) {
9637 /* read last bytes not ending on 4 byte boundary */
9638 pd = &data[eeprom->len];
9639 b_count = len & 3;
9640 b_offset = offset + len - b_count;
9641 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9642 if (ret)
9643 return ret;
9644 memcpy(pd, &val, b_count);
9645 eeprom->len += b_count;
9646 }
9647 return 0;
9648 }
9649
9650 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9651
9652 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9653 {
9654 struct tg3 *tp = netdev_priv(dev);
9655 int ret;
9656 u32 offset, len, b_offset, odd_len;
9657 u8 *buf;
9658 __be32 start, end;
9659
9660 if (tp->link_config.phy_is_low_power)
9661 return -EAGAIN;
9662
9663 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9664 eeprom->magic != TG3_EEPROM_MAGIC)
9665 return -EINVAL;
9666
9667 offset = eeprom->offset;
9668 len = eeprom->len;
9669
9670 if ((b_offset = (offset & 3))) {
9671 /* adjustments to start on required 4 byte boundary */
9672 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9673 if (ret)
9674 return ret;
9675 len += b_offset;
9676 offset &= ~3;
9677 if (len < 4)
9678 len = 4;
9679 }
9680
9681 odd_len = 0;
9682 if (len & 3) {
9683 /* adjustments to end on required 4 byte boundary */
9684 odd_len = 1;
9685 len = (len + 3) & ~3;
9686 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9687 if (ret)
9688 return ret;
9689 }
9690
9691 buf = data;
9692 if (b_offset || odd_len) {
9693 buf = kmalloc(len, GFP_KERNEL);
9694 if (!buf)
9695 return -ENOMEM;
9696 if (b_offset)
9697 memcpy(buf, &start, 4);
9698 if (odd_len)
9699 memcpy(buf+len-4, &end, 4);
9700 memcpy(buf + b_offset, data, eeprom->len);
9701 }
9702
9703 ret = tg3_nvram_write_block(tp, offset, len, buf);
9704
9705 if (buf != data)
9706 kfree(buf);
9707
9708 return ret;
9709 }
9710
9711 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9712 {
9713 struct tg3 *tp = netdev_priv(dev);
9714
9715 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9716 struct phy_device *phydev;
9717 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9718 return -EAGAIN;
9719 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9720 return phy_ethtool_gset(phydev, cmd);
9721 }
9722
9723 cmd->supported = (SUPPORTED_Autoneg);
9724
9725 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9726 cmd->supported |= (SUPPORTED_1000baseT_Half |
9727 SUPPORTED_1000baseT_Full);
9728
9729 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9730 cmd->supported |= (SUPPORTED_100baseT_Half |
9731 SUPPORTED_100baseT_Full |
9732 SUPPORTED_10baseT_Half |
9733 SUPPORTED_10baseT_Full |
9734 SUPPORTED_TP);
9735 cmd->port = PORT_TP;
9736 } else {
9737 cmd->supported |= SUPPORTED_FIBRE;
9738 cmd->port = PORT_FIBRE;
9739 }
9740
9741 cmd->advertising = tp->link_config.advertising;
9742 if (netif_running(dev)) {
9743 cmd->speed = tp->link_config.active_speed;
9744 cmd->duplex = tp->link_config.active_duplex;
9745 }
9746 cmd->phy_address = tp->phy_addr;
9747 cmd->transceiver = XCVR_INTERNAL;
9748 cmd->autoneg = tp->link_config.autoneg;
9749 cmd->maxtxpkt = 0;
9750 cmd->maxrxpkt = 0;
9751 return 0;
9752 }
9753
9754 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9755 {
9756 struct tg3 *tp = netdev_priv(dev);
9757
9758 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9759 struct phy_device *phydev;
9760 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9761 return -EAGAIN;
9762 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9763 return phy_ethtool_sset(phydev, cmd);
9764 }
9765
9766 if (cmd->autoneg != AUTONEG_ENABLE &&
9767 cmd->autoneg != AUTONEG_DISABLE)
9768 return -EINVAL;
9769
9770 if (cmd->autoneg == AUTONEG_DISABLE &&
9771 cmd->duplex != DUPLEX_FULL &&
9772 cmd->duplex != DUPLEX_HALF)
9773 return -EINVAL;
9774
9775 if (cmd->autoneg == AUTONEG_ENABLE) {
9776 u32 mask = ADVERTISED_Autoneg |
9777 ADVERTISED_Pause |
9778 ADVERTISED_Asym_Pause;
9779
9780 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9781 mask |= ADVERTISED_1000baseT_Half |
9782 ADVERTISED_1000baseT_Full;
9783
9784 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9785 mask |= ADVERTISED_100baseT_Half |
9786 ADVERTISED_100baseT_Full |
9787 ADVERTISED_10baseT_Half |
9788 ADVERTISED_10baseT_Full |
9789 ADVERTISED_TP;
9790 else
9791 mask |= ADVERTISED_FIBRE;
9792
9793 if (cmd->advertising & ~mask)
9794 return -EINVAL;
9795
9796 mask &= (ADVERTISED_1000baseT_Half |
9797 ADVERTISED_1000baseT_Full |
9798 ADVERTISED_100baseT_Half |
9799 ADVERTISED_100baseT_Full |
9800 ADVERTISED_10baseT_Half |
9801 ADVERTISED_10baseT_Full);
9802
9803 cmd->advertising &= mask;
9804 } else {
9805 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9806 if (cmd->speed != SPEED_1000)
9807 return -EINVAL;
9808
9809 if (cmd->duplex != DUPLEX_FULL)
9810 return -EINVAL;
9811 } else {
9812 if (cmd->speed != SPEED_100 &&
9813 cmd->speed != SPEED_10)
9814 return -EINVAL;
9815 }
9816 }
9817
9818 tg3_full_lock(tp, 0);
9819
9820 tp->link_config.autoneg = cmd->autoneg;
9821 if (cmd->autoneg == AUTONEG_ENABLE) {
9822 tp->link_config.advertising = (cmd->advertising |
9823 ADVERTISED_Autoneg);
9824 tp->link_config.speed = SPEED_INVALID;
9825 tp->link_config.duplex = DUPLEX_INVALID;
9826 } else {
9827 tp->link_config.advertising = 0;
9828 tp->link_config.speed = cmd->speed;
9829 tp->link_config.duplex = cmd->duplex;
9830 }
9831
9832 tp->link_config.orig_speed = tp->link_config.speed;
9833 tp->link_config.orig_duplex = tp->link_config.duplex;
9834 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9835
9836 if (netif_running(dev))
9837 tg3_setup_phy(tp, 1);
9838
9839 tg3_full_unlock(tp);
9840
9841 return 0;
9842 }
9843
9844 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9845 {
9846 struct tg3 *tp = netdev_priv(dev);
9847
9848 strcpy(info->driver, DRV_MODULE_NAME);
9849 strcpy(info->version, DRV_MODULE_VERSION);
9850 strcpy(info->fw_version, tp->fw_ver);
9851 strcpy(info->bus_info, pci_name(tp->pdev));
9852 }
9853
9854 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9855 {
9856 struct tg3 *tp = netdev_priv(dev);
9857
9858 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9859 device_can_wakeup(&tp->pdev->dev))
9860 wol->supported = WAKE_MAGIC;
9861 else
9862 wol->supported = 0;
9863 wol->wolopts = 0;
9864 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9865 device_can_wakeup(&tp->pdev->dev))
9866 wol->wolopts = WAKE_MAGIC;
9867 memset(&wol->sopass, 0, sizeof(wol->sopass));
9868 }
9869
9870 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9871 {
9872 struct tg3 *tp = netdev_priv(dev);
9873 struct device *dp = &tp->pdev->dev;
9874
9875 if (wol->wolopts & ~WAKE_MAGIC)
9876 return -EINVAL;
9877 if ((wol->wolopts & WAKE_MAGIC) &&
9878 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9879 return -EINVAL;
9880
9881 spin_lock_bh(&tp->lock);
9882 if (wol->wolopts & WAKE_MAGIC) {
9883 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9884 device_set_wakeup_enable(dp, true);
9885 } else {
9886 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9887 device_set_wakeup_enable(dp, false);
9888 }
9889 spin_unlock_bh(&tp->lock);
9890
9891 return 0;
9892 }
9893
9894 static u32 tg3_get_msglevel(struct net_device *dev)
9895 {
9896 struct tg3 *tp = netdev_priv(dev);
9897 return tp->msg_enable;
9898 }
9899
9900 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9901 {
9902 struct tg3 *tp = netdev_priv(dev);
9903 tp->msg_enable = value;
9904 }
9905
9906 static int tg3_set_tso(struct net_device *dev, u32 value)
9907 {
9908 struct tg3 *tp = netdev_priv(dev);
9909
9910 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9911 if (value)
9912 return -EINVAL;
9913 return 0;
9914 }
9915 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9916 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9917 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9918 if (value) {
9919 dev->features |= NETIF_F_TSO6;
9920 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9921 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9922 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9923 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9924 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9925 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9926 dev->features |= NETIF_F_TSO_ECN;
9927 } else
9928 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9929 }
9930 return ethtool_op_set_tso(dev, value);
9931 }
9932
9933 static int tg3_nway_reset(struct net_device *dev)
9934 {
9935 struct tg3 *tp = netdev_priv(dev);
9936 int r;
9937
9938 if (!netif_running(dev))
9939 return -EAGAIN;
9940
9941 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9942 return -EINVAL;
9943
9944 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9945 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9946 return -EAGAIN;
9947 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9948 } else {
9949 u32 bmcr;
9950
9951 spin_lock_bh(&tp->lock);
9952 r = -EINVAL;
9953 tg3_readphy(tp, MII_BMCR, &bmcr);
9954 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9955 ((bmcr & BMCR_ANENABLE) ||
9956 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9957 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9958 BMCR_ANENABLE);
9959 r = 0;
9960 }
9961 spin_unlock_bh(&tp->lock);
9962 }
9963
9964 return r;
9965 }
9966
9967 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9968 {
9969 struct tg3 *tp = netdev_priv(dev);
9970
9971 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9972 ering->rx_mini_max_pending = 0;
9973 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9974 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9975 else
9976 ering->rx_jumbo_max_pending = 0;
9977
9978 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9979
9980 ering->rx_pending = tp->rx_pending;
9981 ering->rx_mini_pending = 0;
9982 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9983 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9984 else
9985 ering->rx_jumbo_pending = 0;
9986
9987 ering->tx_pending = tp->napi[0].tx_pending;
9988 }
9989
9990 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9991 {
9992 struct tg3 *tp = netdev_priv(dev);
9993 int i, irq_sync = 0, err = 0;
9994
9995 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9996 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9997 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9998 (ering->tx_pending <= MAX_SKB_FRAGS) ||
9999 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10000 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10001 return -EINVAL;
10002
10003 if (netif_running(dev)) {
10004 tg3_phy_stop(tp);
10005 tg3_netif_stop(tp);
10006 irq_sync = 1;
10007 }
10008
10009 tg3_full_lock(tp, irq_sync);
10010
10011 tp->rx_pending = ering->rx_pending;
10012
10013 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10014 tp->rx_pending > 63)
10015 tp->rx_pending = 63;
10016 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10017
10018 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
10019 tp->napi[i].tx_pending = ering->tx_pending;
10020
10021 if (netif_running(dev)) {
10022 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10023 err = tg3_restart_hw(tp, 1);
10024 if (!err)
10025 tg3_netif_start(tp);
10026 }
10027
10028 tg3_full_unlock(tp);
10029
10030 if (irq_sync && !err)
10031 tg3_phy_start(tp);
10032
10033 return err;
10034 }
10035
10036 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10037 {
10038 struct tg3 *tp = netdev_priv(dev);
10039
10040 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10041
10042 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10043 epause->rx_pause = 1;
10044 else
10045 epause->rx_pause = 0;
10046
10047 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10048 epause->tx_pause = 1;
10049 else
10050 epause->tx_pause = 0;
10051 }
10052
10053 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10054 {
10055 struct tg3 *tp = netdev_priv(dev);
10056 int err = 0;
10057
10058 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10059 u32 newadv;
10060 struct phy_device *phydev;
10061
10062 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10063
10064 if (!(phydev->supported & SUPPORTED_Pause) ||
10065 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10066 ((epause->rx_pause && !epause->tx_pause) ||
10067 (!epause->rx_pause && epause->tx_pause))))
10068 return -EINVAL;
10069
10070 tp->link_config.flowctrl = 0;
10071 if (epause->rx_pause) {
10072 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10073
10074 if (epause->tx_pause) {
10075 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10076 newadv = ADVERTISED_Pause;
10077 } else
10078 newadv = ADVERTISED_Pause |
10079 ADVERTISED_Asym_Pause;
10080 } else if (epause->tx_pause) {
10081 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10082 newadv = ADVERTISED_Asym_Pause;
10083 } else
10084 newadv = 0;
10085
10086 if (epause->autoneg)
10087 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10088 else
10089 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10090
10091 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10092 u32 oldadv = phydev->advertising &
10093 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10094 if (oldadv != newadv) {
10095 phydev->advertising &=
10096 ~(ADVERTISED_Pause |
10097 ADVERTISED_Asym_Pause);
10098 phydev->advertising |= newadv;
10099 if (phydev->autoneg) {
10100 /*
10101 * Always renegotiate the link to
10102 * inform our link partner of our
10103 * flow control settings, even if the
10104 * flow control is forced. Let
10105 * tg3_adjust_link() do the final
10106 * flow control setup.
10107 */
10108 return phy_start_aneg(phydev);
10109 }
10110 }
10111
10112 if (!epause->autoneg)
10113 tg3_setup_flow_control(tp, 0, 0);
10114 } else {
10115 tp->link_config.orig_advertising &=
10116 ~(ADVERTISED_Pause |
10117 ADVERTISED_Asym_Pause);
10118 tp->link_config.orig_advertising |= newadv;
10119 }
10120 } else {
10121 int irq_sync = 0;
10122
10123 if (netif_running(dev)) {
10124 tg3_netif_stop(tp);
10125 irq_sync = 1;
10126 }
10127
10128 tg3_full_lock(tp, irq_sync);
10129
10130 if (epause->autoneg)
10131 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10132 else
10133 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10134 if (epause->rx_pause)
10135 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10136 else
10137 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10138 if (epause->tx_pause)
10139 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10140 else
10141 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10142
10143 if (netif_running(dev)) {
10144 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10145 err = tg3_restart_hw(tp, 1);
10146 if (!err)
10147 tg3_netif_start(tp);
10148 }
10149
10150 tg3_full_unlock(tp);
10151 }
10152
10153 return err;
10154 }
10155
10156 static u32 tg3_get_rx_csum(struct net_device *dev)
10157 {
10158 struct tg3 *tp = netdev_priv(dev);
10159 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10160 }
10161
10162 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10163 {
10164 struct tg3 *tp = netdev_priv(dev);
10165
10166 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10167 if (data != 0)
10168 return -EINVAL;
10169 return 0;
10170 }
10171
10172 spin_lock_bh(&tp->lock);
10173 if (data)
10174 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10175 else
10176 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10177 spin_unlock_bh(&tp->lock);
10178
10179 return 0;
10180 }
10181
10182 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10183 {
10184 struct tg3 *tp = netdev_priv(dev);
10185
10186 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10187 if (data != 0)
10188 return -EINVAL;
10189 return 0;
10190 }
10191
10192 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10193 ethtool_op_set_tx_ipv6_csum(dev, data);
10194 else
10195 ethtool_op_set_tx_csum(dev, data);
10196
10197 return 0;
10198 }
10199
10200 static int tg3_get_sset_count (struct net_device *dev, int sset)
10201 {
10202 switch (sset) {
10203 case ETH_SS_TEST:
10204 return TG3_NUM_TEST;
10205 case ETH_SS_STATS:
10206 return TG3_NUM_STATS;
10207 default:
10208 return -EOPNOTSUPP;
10209 }
10210 }
10211
10212 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10213 {
10214 switch (stringset) {
10215 case ETH_SS_STATS:
10216 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10217 break;
10218 case ETH_SS_TEST:
10219 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10220 break;
10221 default:
10222 WARN_ON(1); /* we need a WARN() */
10223 break;
10224 }
10225 }
10226
10227 static int tg3_phys_id(struct net_device *dev, u32 data)
10228 {
10229 struct tg3 *tp = netdev_priv(dev);
10230 int i;
10231
10232 if (!netif_running(tp->dev))
10233 return -EAGAIN;
10234
10235 if (data == 0)
10236 data = UINT_MAX / 2;
10237
10238 for (i = 0; i < (data * 2); i++) {
10239 if ((i % 2) == 0)
10240 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10241 LED_CTRL_1000MBPS_ON |
10242 LED_CTRL_100MBPS_ON |
10243 LED_CTRL_10MBPS_ON |
10244 LED_CTRL_TRAFFIC_OVERRIDE |
10245 LED_CTRL_TRAFFIC_BLINK |
10246 LED_CTRL_TRAFFIC_LED);
10247
10248 else
10249 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10250 LED_CTRL_TRAFFIC_OVERRIDE);
10251
10252 if (msleep_interruptible(500))
10253 break;
10254 }
10255 tw32(MAC_LED_CTRL, tp->led_ctrl);
10256 return 0;
10257 }
10258
10259 static void tg3_get_ethtool_stats (struct net_device *dev,
10260 struct ethtool_stats *estats, u64 *tmp_stats)
10261 {
10262 struct tg3 *tp = netdev_priv(dev);
10263 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10264 }
10265
10266 #define NVRAM_TEST_SIZE 0x100
10267 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10268 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10269 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10270 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10271 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10272
10273 static int tg3_test_nvram(struct tg3 *tp)
10274 {
10275 u32 csum, magic;
10276 __be32 *buf;
10277 int i, j, k, err = 0, size;
10278
10279 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10280 return 0;
10281
10282 if (tg3_nvram_read(tp, 0, &magic) != 0)
10283 return -EIO;
10284
10285 if (magic == TG3_EEPROM_MAGIC)
10286 size = NVRAM_TEST_SIZE;
10287 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10288 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10289 TG3_EEPROM_SB_FORMAT_1) {
10290 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10291 case TG3_EEPROM_SB_REVISION_0:
10292 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10293 break;
10294 case TG3_EEPROM_SB_REVISION_2:
10295 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10296 break;
10297 case TG3_EEPROM_SB_REVISION_3:
10298 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10299 break;
10300 default:
10301 return 0;
10302 }
10303 } else
10304 return 0;
10305 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10306 size = NVRAM_SELFBOOT_HW_SIZE;
10307 else
10308 return -EIO;
10309
10310 buf = kmalloc(size, GFP_KERNEL);
10311 if (buf == NULL)
10312 return -ENOMEM;
10313
10314 err = -EIO;
10315 for (i = 0, j = 0; i < size; i += 4, j++) {
10316 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10317 if (err)
10318 break;
10319 }
10320 if (i < size)
10321 goto out;
10322
10323 /* Selfboot format */
10324 magic = be32_to_cpu(buf[0]);
10325 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10326 TG3_EEPROM_MAGIC_FW) {
10327 u8 *buf8 = (u8 *) buf, csum8 = 0;
10328
10329 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10330 TG3_EEPROM_SB_REVISION_2) {
10331 /* For rev 2, the csum doesn't include the MBA. */
10332 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10333 csum8 += buf8[i];
10334 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10335 csum8 += buf8[i];
10336 } else {
10337 for (i = 0; i < size; i++)
10338 csum8 += buf8[i];
10339 }
10340
10341 if (csum8 == 0) {
10342 err = 0;
10343 goto out;
10344 }
10345
10346 err = -EIO;
10347 goto out;
10348 }
10349
10350 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10351 TG3_EEPROM_MAGIC_HW) {
10352 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10353 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10354 u8 *buf8 = (u8 *) buf;
10355
10356 /* Separate the parity bits and the data bytes. */
10357 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10358 if ((i == 0) || (i == 8)) {
10359 int l;
10360 u8 msk;
10361
10362 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10363 parity[k++] = buf8[i] & msk;
10364 i++;
10365 }
10366 else if (i == 16) {
10367 int l;
10368 u8 msk;
10369
10370 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10371 parity[k++] = buf8[i] & msk;
10372 i++;
10373
10374 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10375 parity[k++] = buf8[i] & msk;
10376 i++;
10377 }
10378 data[j++] = buf8[i];
10379 }
10380
10381 err = -EIO;
10382 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10383 u8 hw8 = hweight8(data[i]);
10384
10385 if ((hw8 & 0x1) && parity[i])
10386 goto out;
10387 else if (!(hw8 & 0x1) && !parity[i])
10388 goto out;
10389 }
10390 err = 0;
10391 goto out;
10392 }
10393
10394 /* Bootstrap checksum at offset 0x10 */
10395 csum = calc_crc((unsigned char *) buf, 0x10);
10396 if (csum != be32_to_cpu(buf[0x10/4]))
10397 goto out;
10398
10399 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10400 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10401 if (csum != be32_to_cpu(buf[0xfc/4]))
10402 goto out;
10403
10404 err = 0;
10405
10406 out:
10407 kfree(buf);
10408 return err;
10409 }
10410
10411 #define TG3_SERDES_TIMEOUT_SEC 2
10412 #define TG3_COPPER_TIMEOUT_SEC 6
10413
10414 static int tg3_test_link(struct tg3 *tp)
10415 {
10416 int i, max;
10417
10418 if (!netif_running(tp->dev))
10419 return -ENODEV;
10420
10421 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10422 max = TG3_SERDES_TIMEOUT_SEC;
10423 else
10424 max = TG3_COPPER_TIMEOUT_SEC;
10425
10426 for (i = 0; i < max; i++) {
10427 if (netif_carrier_ok(tp->dev))
10428 return 0;
10429
10430 if (msleep_interruptible(1000))
10431 break;
10432 }
10433
10434 return -EIO;
10435 }
10436
10437 /* Only test the commonly used registers */
10438 static int tg3_test_registers(struct tg3 *tp)
10439 {
10440 int i, is_5705, is_5750;
10441 u32 offset, read_mask, write_mask, val, save_val, read_val;
10442 static struct {
10443 u16 offset;
10444 u16 flags;
10445 #define TG3_FL_5705 0x1
10446 #define TG3_FL_NOT_5705 0x2
10447 #define TG3_FL_NOT_5788 0x4
10448 #define TG3_FL_NOT_5750 0x8
10449 u32 read_mask;
10450 u32 write_mask;
10451 } reg_tbl[] = {
10452 /* MAC Control Registers */
10453 { MAC_MODE, TG3_FL_NOT_5705,
10454 0x00000000, 0x00ef6f8c },
10455 { MAC_MODE, TG3_FL_5705,
10456 0x00000000, 0x01ef6b8c },
10457 { MAC_STATUS, TG3_FL_NOT_5705,
10458 0x03800107, 0x00000000 },
10459 { MAC_STATUS, TG3_FL_5705,
10460 0x03800100, 0x00000000 },
10461 { MAC_ADDR_0_HIGH, 0x0000,
10462 0x00000000, 0x0000ffff },
10463 { MAC_ADDR_0_LOW, 0x0000,
10464 0x00000000, 0xffffffff },
10465 { MAC_RX_MTU_SIZE, 0x0000,
10466 0x00000000, 0x0000ffff },
10467 { MAC_TX_MODE, 0x0000,
10468 0x00000000, 0x00000070 },
10469 { MAC_TX_LENGTHS, 0x0000,
10470 0x00000000, 0x00003fff },
10471 { MAC_RX_MODE, TG3_FL_NOT_5705,
10472 0x00000000, 0x000007fc },
10473 { MAC_RX_MODE, TG3_FL_5705,
10474 0x00000000, 0x000007dc },
10475 { MAC_HASH_REG_0, 0x0000,
10476 0x00000000, 0xffffffff },
10477 { MAC_HASH_REG_1, 0x0000,
10478 0x00000000, 0xffffffff },
10479 { MAC_HASH_REG_2, 0x0000,
10480 0x00000000, 0xffffffff },
10481 { MAC_HASH_REG_3, 0x0000,
10482 0x00000000, 0xffffffff },
10483
10484 /* Receive Data and Receive BD Initiator Control Registers. */
10485 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10486 0x00000000, 0xffffffff },
10487 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10488 0x00000000, 0xffffffff },
10489 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10490 0x00000000, 0x00000003 },
10491 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10492 0x00000000, 0xffffffff },
10493 { RCVDBDI_STD_BD+0, 0x0000,
10494 0x00000000, 0xffffffff },
10495 { RCVDBDI_STD_BD+4, 0x0000,
10496 0x00000000, 0xffffffff },
10497 { RCVDBDI_STD_BD+8, 0x0000,
10498 0x00000000, 0xffff0002 },
10499 { RCVDBDI_STD_BD+0xc, 0x0000,
10500 0x00000000, 0xffffffff },
10501
10502 /* Receive BD Initiator Control Registers. */
10503 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10504 0x00000000, 0xffffffff },
10505 { RCVBDI_STD_THRESH, TG3_FL_5705,
10506 0x00000000, 0x000003ff },
10507 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10508 0x00000000, 0xffffffff },
10509
10510 /* Host Coalescing Control Registers. */
10511 { HOSTCC_MODE, TG3_FL_NOT_5705,
10512 0x00000000, 0x00000004 },
10513 { HOSTCC_MODE, TG3_FL_5705,
10514 0x00000000, 0x000000f6 },
10515 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10516 0x00000000, 0xffffffff },
10517 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10518 0x00000000, 0x000003ff },
10519 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10520 0x00000000, 0xffffffff },
10521 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10522 0x00000000, 0x000003ff },
10523 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10524 0x00000000, 0xffffffff },
10525 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10526 0x00000000, 0x000000ff },
10527 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10528 0x00000000, 0xffffffff },
10529 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10530 0x00000000, 0x000000ff },
10531 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10532 0x00000000, 0xffffffff },
10533 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10534 0x00000000, 0xffffffff },
10535 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10536 0x00000000, 0xffffffff },
10537 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10538 0x00000000, 0x000000ff },
10539 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10540 0x00000000, 0xffffffff },
10541 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10542 0x00000000, 0x000000ff },
10543 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10544 0x00000000, 0xffffffff },
10545 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10546 0x00000000, 0xffffffff },
10547 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10548 0x00000000, 0xffffffff },
10549 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10550 0x00000000, 0xffffffff },
10551 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10552 0x00000000, 0xffffffff },
10553 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10554 0xffffffff, 0x00000000 },
10555 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10556 0xffffffff, 0x00000000 },
10557
10558 /* Buffer Manager Control Registers. */
10559 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10560 0x00000000, 0x007fff80 },
10561 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10562 0x00000000, 0x007fffff },
10563 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10564 0x00000000, 0x0000003f },
10565 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10566 0x00000000, 0x000001ff },
10567 { BUFMGR_MB_HIGH_WATER, 0x0000,
10568 0x00000000, 0x000001ff },
10569 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10570 0xffffffff, 0x00000000 },
10571 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10572 0xffffffff, 0x00000000 },
10573
10574 /* Mailbox Registers */
10575 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10576 0x00000000, 0x000001ff },
10577 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10578 0x00000000, 0x000001ff },
10579 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10580 0x00000000, 0x000007ff },
10581 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10582 0x00000000, 0x000001ff },
10583
10584 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10585 };
10586
10587 is_5705 = is_5750 = 0;
10588 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10589 is_5705 = 1;
10590 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10591 is_5750 = 1;
10592 }
10593
10594 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10595 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10596 continue;
10597
10598 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10599 continue;
10600
10601 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10602 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10603 continue;
10604
10605 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10606 continue;
10607
10608 offset = (u32) reg_tbl[i].offset;
10609 read_mask = reg_tbl[i].read_mask;
10610 write_mask = reg_tbl[i].write_mask;
10611
10612 /* Save the original register content */
10613 save_val = tr32(offset);
10614
10615 /* Determine the read-only value. */
10616 read_val = save_val & read_mask;
10617
10618 /* Write zero to the register, then make sure the read-only bits
10619 * are not changed and the read/write bits are all zeros.
10620 */
10621 tw32(offset, 0);
10622
10623 val = tr32(offset);
10624
10625 /* Test the read-only and read/write bits. */
10626 if (((val & read_mask) != read_val) || (val & write_mask))
10627 goto out;
10628
10629 /* Write ones to all the bits defined by RdMask and WrMask, then
10630 * make sure the read-only bits are not changed and the
10631 * read/write bits are all ones.
10632 */
10633 tw32(offset, read_mask | write_mask);
10634
10635 val = tr32(offset);
10636
10637 /* Test the read-only bits. */
10638 if ((val & read_mask) != read_val)
10639 goto out;
10640
10641 /* Test the read/write bits. */
10642 if ((val & write_mask) != write_mask)
10643 goto out;
10644
10645 tw32(offset, save_val);
10646 }
10647
10648 return 0;
10649
10650 out:
10651 if (netif_msg_hw(tp))
10652 pr_err("Register test failed at offset %x\n", offset);
10653 tw32(offset, save_val);
10654 return -EIO;
10655 }
10656
10657 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10658 {
10659 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10660 int i;
10661 u32 j;
10662
10663 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10664 for (j = 0; j < len; j += 4) {
10665 u32 val;
10666
10667 tg3_write_mem(tp, offset + j, test_pattern[i]);
10668 tg3_read_mem(tp, offset + j, &val);
10669 if (val != test_pattern[i])
10670 return -EIO;
10671 }
10672 }
10673 return 0;
10674 }
10675
10676 static int tg3_test_memory(struct tg3 *tp)
10677 {
10678 static struct mem_entry {
10679 u32 offset;
10680 u32 len;
10681 } mem_tbl_570x[] = {
10682 { 0x00000000, 0x00b50},
10683 { 0x00002000, 0x1c000},
10684 { 0xffffffff, 0x00000}
10685 }, mem_tbl_5705[] = {
10686 { 0x00000100, 0x0000c},
10687 { 0x00000200, 0x00008},
10688 { 0x00004000, 0x00800},
10689 { 0x00006000, 0x01000},
10690 { 0x00008000, 0x02000},
10691 { 0x00010000, 0x0e000},
10692 { 0xffffffff, 0x00000}
10693 }, mem_tbl_5755[] = {
10694 { 0x00000200, 0x00008},
10695 { 0x00004000, 0x00800},
10696 { 0x00006000, 0x00800},
10697 { 0x00008000, 0x02000},
10698 { 0x00010000, 0x0c000},
10699 { 0xffffffff, 0x00000}
10700 }, mem_tbl_5906[] = {
10701 { 0x00000200, 0x00008},
10702 { 0x00004000, 0x00400},
10703 { 0x00006000, 0x00400},
10704 { 0x00008000, 0x01000},
10705 { 0x00010000, 0x01000},
10706 { 0xffffffff, 0x00000}
10707 }, mem_tbl_5717[] = {
10708 { 0x00000200, 0x00008},
10709 { 0x00010000, 0x0a000},
10710 { 0x00020000, 0x13c00},
10711 { 0xffffffff, 0x00000}
10712 }, mem_tbl_57765[] = {
10713 { 0x00000200, 0x00008},
10714 { 0x00004000, 0x00800},
10715 { 0x00006000, 0x09800},
10716 { 0x00010000, 0x0a000},
10717 { 0xffffffff, 0x00000}
10718 };
10719 struct mem_entry *mem_tbl;
10720 int err = 0;
10721 int i;
10722
10723 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10724 mem_tbl = mem_tbl_5717;
10725 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10726 mem_tbl = mem_tbl_57765;
10727 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10728 mem_tbl = mem_tbl_5755;
10729 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10730 mem_tbl = mem_tbl_5906;
10731 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10732 mem_tbl = mem_tbl_5705;
10733 else
10734 mem_tbl = mem_tbl_570x;
10735
10736 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10737 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10738 mem_tbl[i].len)) != 0)
10739 break;
10740 }
10741
10742 return err;
10743 }
10744
10745 #define TG3_MAC_LOOPBACK 0
10746 #define TG3_PHY_LOOPBACK 1
10747
10748 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10749 {
10750 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10751 u32 desc_idx, coal_now;
10752 struct sk_buff *skb, *rx_skb;
10753 u8 *tx_data;
10754 dma_addr_t map;
10755 int num_pkts, tx_len, rx_len, i, err;
10756 struct tg3_rx_buffer_desc *desc;
10757 struct tg3_napi *tnapi, *rnapi;
10758 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10759
10760 tnapi = &tp->napi[0];
10761 rnapi = &tp->napi[0];
10762 if (tp->irq_cnt > 1) {
10763 rnapi = &tp->napi[1];
10764 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10765 tnapi = &tp->napi[1];
10766 }
10767 coal_now = tnapi->coal_now | rnapi->coal_now;
10768
10769 if (loopback_mode == TG3_MAC_LOOPBACK) {
10770 /* HW errata - mac loopback fails in some cases on 5780.
10771 * Normal traffic and PHY loopback are not affected by
10772 * errata.
10773 */
10774 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10775 return 0;
10776
10777 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10778 MAC_MODE_PORT_INT_LPBACK;
10779 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10780 mac_mode |= MAC_MODE_LINK_POLARITY;
10781 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10782 mac_mode |= MAC_MODE_PORT_MODE_MII;
10783 else
10784 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10785 tw32(MAC_MODE, mac_mode);
10786 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10787 u32 val;
10788
10789 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10790 tg3_phy_fet_toggle_apd(tp, false);
10791 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10792 } else
10793 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10794
10795 tg3_phy_toggle_automdix(tp, 0);
10796
10797 tg3_writephy(tp, MII_BMCR, val);
10798 udelay(40);
10799
10800 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10801 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10802 tg3_writephy(tp, MII_TG3_FET_PTEST,
10803 MII_TG3_FET_PTEST_FRC_TX_LINK |
10804 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10805 /* The write needs to be flushed for the AC131 */
10806 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10807 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10808 mac_mode |= MAC_MODE_PORT_MODE_MII;
10809 } else
10810 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10811
10812 /* reset to prevent losing 1st rx packet intermittently */
10813 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10814 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10815 udelay(10);
10816 tw32_f(MAC_RX_MODE, tp->rx_mode);
10817 }
10818 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10819 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10820 if (masked_phy_id == TG3_PHY_ID_BCM5401)
10821 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10822 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10823 mac_mode |= MAC_MODE_LINK_POLARITY;
10824 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10825 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10826 }
10827 tw32(MAC_MODE, mac_mode);
10828 }
10829 else
10830 return -EINVAL;
10831
10832 err = -EIO;
10833
10834 tx_len = 1514;
10835 skb = netdev_alloc_skb(tp->dev, tx_len);
10836 if (!skb)
10837 return -ENOMEM;
10838
10839 tx_data = skb_put(skb, tx_len);
10840 memcpy(tx_data, tp->dev->dev_addr, 6);
10841 memset(tx_data + 6, 0x0, 8);
10842
10843 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10844
10845 for (i = 14; i < tx_len; i++)
10846 tx_data[i] = (u8) (i & 0xff);
10847
10848 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10849 if (pci_dma_mapping_error(tp->pdev, map)) {
10850 dev_kfree_skb(skb);
10851 return -EIO;
10852 }
10853
10854 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10855 rnapi->coal_now);
10856
10857 udelay(10);
10858
10859 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10860
10861 num_pkts = 0;
10862
10863 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10864
10865 tnapi->tx_prod++;
10866 num_pkts++;
10867
10868 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10869 tr32_mailbox(tnapi->prodmbox);
10870
10871 udelay(10);
10872
10873 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10874 for (i = 0; i < 35; i++) {
10875 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10876 coal_now);
10877
10878 udelay(10);
10879
10880 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10881 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10882 if ((tx_idx == tnapi->tx_prod) &&
10883 (rx_idx == (rx_start_idx + num_pkts)))
10884 break;
10885 }
10886
10887 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10888 dev_kfree_skb(skb);
10889
10890 if (tx_idx != tnapi->tx_prod)
10891 goto out;
10892
10893 if (rx_idx != rx_start_idx + num_pkts)
10894 goto out;
10895
10896 desc = &rnapi->rx_rcb[rx_start_idx];
10897 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10898 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10899 if (opaque_key != RXD_OPAQUE_RING_STD)
10900 goto out;
10901
10902 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10903 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10904 goto out;
10905
10906 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10907 if (rx_len != tx_len)
10908 goto out;
10909
10910 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10911
10912 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10913 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10914
10915 for (i = 14; i < tx_len; i++) {
10916 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10917 goto out;
10918 }
10919 err = 0;
10920
10921 /* tg3_free_rings will unmap and free the rx_skb */
10922 out:
10923 return err;
10924 }
10925
10926 #define TG3_MAC_LOOPBACK_FAILED 1
10927 #define TG3_PHY_LOOPBACK_FAILED 2
10928 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10929 TG3_PHY_LOOPBACK_FAILED)
10930
10931 static int tg3_test_loopback(struct tg3 *tp)
10932 {
10933 int err = 0;
10934 u32 cpmuctrl = 0;
10935
10936 if (!netif_running(tp->dev))
10937 return TG3_LOOPBACK_FAILED;
10938
10939 err = tg3_reset_hw(tp, 1);
10940 if (err)
10941 return TG3_LOOPBACK_FAILED;
10942
10943 /* Turn off gphy autopowerdown. */
10944 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10945 tg3_phy_toggle_apd(tp, false);
10946
10947 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10948 int i;
10949 u32 status;
10950
10951 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10952
10953 /* Wait for up to 40 microseconds to acquire lock. */
10954 for (i = 0; i < 4; i++) {
10955 status = tr32(TG3_CPMU_MUTEX_GNT);
10956 if (status == CPMU_MUTEX_GNT_DRIVER)
10957 break;
10958 udelay(10);
10959 }
10960
10961 if (status != CPMU_MUTEX_GNT_DRIVER)
10962 return TG3_LOOPBACK_FAILED;
10963
10964 /* Turn off link-based power management. */
10965 cpmuctrl = tr32(TG3_CPMU_CTRL);
10966 tw32(TG3_CPMU_CTRL,
10967 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10968 CPMU_CTRL_LINK_AWARE_MODE));
10969 }
10970
10971 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10972 err |= TG3_MAC_LOOPBACK_FAILED;
10973
10974 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10975 tw32(TG3_CPMU_CTRL, cpmuctrl);
10976
10977 /* Release the mutex */
10978 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10979 }
10980
10981 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10982 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10983 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10984 err |= TG3_PHY_LOOPBACK_FAILED;
10985 }
10986
10987 /* Re-enable gphy autopowerdown. */
10988 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10989 tg3_phy_toggle_apd(tp, true);
10990
10991 return err;
10992 }
10993
10994 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10995 u64 *data)
10996 {
10997 struct tg3 *tp = netdev_priv(dev);
10998
10999 if (tp->link_config.phy_is_low_power)
11000 tg3_set_power_state(tp, PCI_D0);
11001
11002 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11003
11004 if (tg3_test_nvram(tp) != 0) {
11005 etest->flags |= ETH_TEST_FL_FAILED;
11006 data[0] = 1;
11007 }
11008 if (tg3_test_link(tp) != 0) {
11009 etest->flags |= ETH_TEST_FL_FAILED;
11010 data[1] = 1;
11011 }
11012 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11013 int err, err2 = 0, irq_sync = 0;
11014
11015 if (netif_running(dev)) {
11016 tg3_phy_stop(tp);
11017 tg3_netif_stop(tp);
11018 irq_sync = 1;
11019 }
11020
11021 tg3_full_lock(tp, irq_sync);
11022
11023 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11024 err = tg3_nvram_lock(tp);
11025 tg3_halt_cpu(tp, RX_CPU_BASE);
11026 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11027 tg3_halt_cpu(tp, TX_CPU_BASE);
11028 if (!err)
11029 tg3_nvram_unlock(tp);
11030
11031 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
11032 tg3_phy_reset(tp);
11033
11034 if (tg3_test_registers(tp) != 0) {
11035 etest->flags |= ETH_TEST_FL_FAILED;
11036 data[2] = 1;
11037 }
11038 if (tg3_test_memory(tp) != 0) {
11039 etest->flags |= ETH_TEST_FL_FAILED;
11040 data[3] = 1;
11041 }
11042 if ((data[4] = tg3_test_loopback(tp)) != 0)
11043 etest->flags |= ETH_TEST_FL_FAILED;
11044
11045 tg3_full_unlock(tp);
11046
11047 if (tg3_test_interrupt(tp) != 0) {
11048 etest->flags |= ETH_TEST_FL_FAILED;
11049 data[5] = 1;
11050 }
11051
11052 tg3_full_lock(tp, 0);
11053
11054 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11055 if (netif_running(dev)) {
11056 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11057 err2 = tg3_restart_hw(tp, 1);
11058 if (!err2)
11059 tg3_netif_start(tp);
11060 }
11061
11062 tg3_full_unlock(tp);
11063
11064 if (irq_sync && !err2)
11065 tg3_phy_start(tp);
11066 }
11067 if (tp->link_config.phy_is_low_power)
11068 tg3_set_power_state(tp, PCI_D3hot);
11069
11070 }
11071
11072 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11073 {
11074 struct mii_ioctl_data *data = if_mii(ifr);
11075 struct tg3 *tp = netdev_priv(dev);
11076 int err;
11077
11078 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11079 struct phy_device *phydev;
11080 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11081 return -EAGAIN;
11082 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11083 return phy_mii_ioctl(phydev, data, cmd);
11084 }
11085
11086 switch(cmd) {
11087 case SIOCGMIIPHY:
11088 data->phy_id = tp->phy_addr;
11089
11090 /* fallthru */
11091 case SIOCGMIIREG: {
11092 u32 mii_regval;
11093
11094 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11095 break; /* We have no PHY */
11096
11097 if (tp->link_config.phy_is_low_power)
11098 return -EAGAIN;
11099
11100 spin_lock_bh(&tp->lock);
11101 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11102 spin_unlock_bh(&tp->lock);
11103
11104 data->val_out = mii_regval;
11105
11106 return err;
11107 }
11108
11109 case SIOCSMIIREG:
11110 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11111 break; /* We have no PHY */
11112
11113 if (tp->link_config.phy_is_low_power)
11114 return -EAGAIN;
11115
11116 spin_lock_bh(&tp->lock);
11117 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11118 spin_unlock_bh(&tp->lock);
11119
11120 return err;
11121
11122 default:
11123 /* do nothing */
11124 break;
11125 }
11126 return -EOPNOTSUPP;
11127 }
11128
11129 #if TG3_VLAN_TAG_USED
11130 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11131 {
11132 struct tg3 *tp = netdev_priv(dev);
11133
11134 if (!netif_running(dev)) {
11135 tp->vlgrp = grp;
11136 return;
11137 }
11138
11139 tg3_netif_stop(tp);
11140
11141 tg3_full_lock(tp, 0);
11142
11143 tp->vlgrp = grp;
11144
11145 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11146 __tg3_set_rx_mode(dev);
11147
11148 tg3_netif_start(tp);
11149
11150 tg3_full_unlock(tp);
11151 }
11152 #endif
11153
11154 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11155 {
11156 struct tg3 *tp = netdev_priv(dev);
11157
11158 memcpy(ec, &tp->coal, sizeof(*ec));
11159 return 0;
11160 }
11161
11162 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11163 {
11164 struct tg3 *tp = netdev_priv(dev);
11165 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11166 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11167
11168 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11169 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11170 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11171 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11172 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11173 }
11174
11175 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11176 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11177 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11178 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11179 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11180 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11181 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11182 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11183 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11184 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11185 return -EINVAL;
11186
11187 /* No rx interrupts will be generated if both are zero */
11188 if ((ec->rx_coalesce_usecs == 0) &&
11189 (ec->rx_max_coalesced_frames == 0))
11190 return -EINVAL;
11191
11192 /* No tx interrupts will be generated if both are zero */
11193 if ((ec->tx_coalesce_usecs == 0) &&
11194 (ec->tx_max_coalesced_frames == 0))
11195 return -EINVAL;
11196
11197 /* Only copy relevant parameters, ignore all others. */
11198 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11199 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11200 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11201 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11202 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11203 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11204 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11205 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11206 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11207
11208 if (netif_running(dev)) {
11209 tg3_full_lock(tp, 0);
11210 __tg3_set_coalesce(tp, &tp->coal);
11211 tg3_full_unlock(tp);
11212 }
11213 return 0;
11214 }
11215
11216 static const struct ethtool_ops tg3_ethtool_ops = {
11217 .get_settings = tg3_get_settings,
11218 .set_settings = tg3_set_settings,
11219 .get_drvinfo = tg3_get_drvinfo,
11220 .get_regs_len = tg3_get_regs_len,
11221 .get_regs = tg3_get_regs,
11222 .get_wol = tg3_get_wol,
11223 .set_wol = tg3_set_wol,
11224 .get_msglevel = tg3_get_msglevel,
11225 .set_msglevel = tg3_set_msglevel,
11226 .nway_reset = tg3_nway_reset,
11227 .get_link = ethtool_op_get_link,
11228 .get_eeprom_len = tg3_get_eeprom_len,
11229 .get_eeprom = tg3_get_eeprom,
11230 .set_eeprom = tg3_set_eeprom,
11231 .get_ringparam = tg3_get_ringparam,
11232 .set_ringparam = tg3_set_ringparam,
11233 .get_pauseparam = tg3_get_pauseparam,
11234 .set_pauseparam = tg3_set_pauseparam,
11235 .get_rx_csum = tg3_get_rx_csum,
11236 .set_rx_csum = tg3_set_rx_csum,
11237 .set_tx_csum = tg3_set_tx_csum,
11238 .set_sg = ethtool_op_set_sg,
11239 .set_tso = tg3_set_tso,
11240 .self_test = tg3_self_test,
11241 .get_strings = tg3_get_strings,
11242 .phys_id = tg3_phys_id,
11243 .get_ethtool_stats = tg3_get_ethtool_stats,
11244 .get_coalesce = tg3_get_coalesce,
11245 .set_coalesce = tg3_set_coalesce,
11246 .get_sset_count = tg3_get_sset_count,
11247 };
11248
11249 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11250 {
11251 u32 cursize, val, magic;
11252
11253 tp->nvram_size = EEPROM_CHIP_SIZE;
11254
11255 if (tg3_nvram_read(tp, 0, &magic) != 0)
11256 return;
11257
11258 if ((magic != TG3_EEPROM_MAGIC) &&
11259 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11260 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11261 return;
11262
11263 /*
11264 * Size the chip by reading offsets at increasing powers of two.
11265 * When we encounter our validation signature, we know the addressing
11266 * has wrapped around, and thus have our chip size.
11267 */
11268 cursize = 0x10;
11269
11270 while (cursize < tp->nvram_size) {
11271 if (tg3_nvram_read(tp, cursize, &val) != 0)
11272 return;
11273
11274 if (val == magic)
11275 break;
11276
11277 cursize <<= 1;
11278 }
11279
11280 tp->nvram_size = cursize;
11281 }
11282
11283 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11284 {
11285 u32 val;
11286
11287 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11288 tg3_nvram_read(tp, 0, &val) != 0)
11289 return;
11290
11291 /* Selfboot format */
11292 if (val != TG3_EEPROM_MAGIC) {
11293 tg3_get_eeprom_size(tp);
11294 return;
11295 }
11296
11297 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11298 if (val != 0) {
11299 /* This is confusing. We want to operate on the
11300 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11301 * call will read from NVRAM and byteswap the data
11302 * according to the byteswapping settings for all
11303 * other register accesses. This ensures the data we
11304 * want will always reside in the lower 16-bits.
11305 * However, the data in NVRAM is in LE format, which
11306 * means the data from the NVRAM read will always be
11307 * opposite the endianness of the CPU. The 16-bit
11308 * byteswap then brings the data to CPU endianness.
11309 */
11310 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11311 return;
11312 }
11313 }
11314 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11315 }
11316
11317 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11318 {
11319 u32 nvcfg1;
11320
11321 nvcfg1 = tr32(NVRAM_CFG1);
11322 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11323 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11324 } else {
11325 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11326 tw32(NVRAM_CFG1, nvcfg1);
11327 }
11328
11329 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11330 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11331 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11332 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11333 tp->nvram_jedecnum = JEDEC_ATMEL;
11334 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11335 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11336 break;
11337 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11338 tp->nvram_jedecnum = JEDEC_ATMEL;
11339 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11340 break;
11341 case FLASH_VENDOR_ATMEL_EEPROM:
11342 tp->nvram_jedecnum = JEDEC_ATMEL;
11343 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11344 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11345 break;
11346 case FLASH_VENDOR_ST:
11347 tp->nvram_jedecnum = JEDEC_ST;
11348 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11349 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11350 break;
11351 case FLASH_VENDOR_SAIFUN:
11352 tp->nvram_jedecnum = JEDEC_SAIFUN;
11353 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11354 break;
11355 case FLASH_VENDOR_SST_SMALL:
11356 case FLASH_VENDOR_SST_LARGE:
11357 tp->nvram_jedecnum = JEDEC_SST;
11358 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11359 break;
11360 }
11361 } else {
11362 tp->nvram_jedecnum = JEDEC_ATMEL;
11363 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11364 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11365 }
11366 }
11367
11368 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11369 {
11370 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11371 case FLASH_5752PAGE_SIZE_256:
11372 tp->nvram_pagesize = 256;
11373 break;
11374 case FLASH_5752PAGE_SIZE_512:
11375 tp->nvram_pagesize = 512;
11376 break;
11377 case FLASH_5752PAGE_SIZE_1K:
11378 tp->nvram_pagesize = 1024;
11379 break;
11380 case FLASH_5752PAGE_SIZE_2K:
11381 tp->nvram_pagesize = 2048;
11382 break;
11383 case FLASH_5752PAGE_SIZE_4K:
11384 tp->nvram_pagesize = 4096;
11385 break;
11386 case FLASH_5752PAGE_SIZE_264:
11387 tp->nvram_pagesize = 264;
11388 break;
11389 case FLASH_5752PAGE_SIZE_528:
11390 tp->nvram_pagesize = 528;
11391 break;
11392 }
11393 }
11394
11395 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11396 {
11397 u32 nvcfg1;
11398
11399 nvcfg1 = tr32(NVRAM_CFG1);
11400
11401 /* NVRAM protection for TPM */
11402 if (nvcfg1 & (1 << 27))
11403 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11404
11405 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11406 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11407 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11408 tp->nvram_jedecnum = JEDEC_ATMEL;
11409 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11410 break;
11411 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11412 tp->nvram_jedecnum = JEDEC_ATMEL;
11413 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11414 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11415 break;
11416 case FLASH_5752VENDOR_ST_M45PE10:
11417 case FLASH_5752VENDOR_ST_M45PE20:
11418 case FLASH_5752VENDOR_ST_M45PE40:
11419 tp->nvram_jedecnum = JEDEC_ST;
11420 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11421 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11422 break;
11423 }
11424
11425 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11426 tg3_nvram_get_pagesize(tp, nvcfg1);
11427 } else {
11428 /* For eeprom, set pagesize to maximum eeprom size */
11429 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11430
11431 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11432 tw32(NVRAM_CFG1, nvcfg1);
11433 }
11434 }
11435
11436 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11437 {
11438 u32 nvcfg1, protect = 0;
11439
11440 nvcfg1 = tr32(NVRAM_CFG1);
11441
11442 /* NVRAM protection for TPM */
11443 if (nvcfg1 & (1 << 27)) {
11444 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11445 protect = 1;
11446 }
11447
11448 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11449 switch (nvcfg1) {
11450 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11451 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11452 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11453 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11454 tp->nvram_jedecnum = JEDEC_ATMEL;
11455 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11456 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11457 tp->nvram_pagesize = 264;
11458 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11459 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11460 tp->nvram_size = (protect ? 0x3e200 :
11461 TG3_NVRAM_SIZE_512KB);
11462 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11463 tp->nvram_size = (protect ? 0x1f200 :
11464 TG3_NVRAM_SIZE_256KB);
11465 else
11466 tp->nvram_size = (protect ? 0x1f200 :
11467 TG3_NVRAM_SIZE_128KB);
11468 break;
11469 case FLASH_5752VENDOR_ST_M45PE10:
11470 case FLASH_5752VENDOR_ST_M45PE20:
11471 case FLASH_5752VENDOR_ST_M45PE40:
11472 tp->nvram_jedecnum = JEDEC_ST;
11473 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11474 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11475 tp->nvram_pagesize = 256;
11476 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11477 tp->nvram_size = (protect ?
11478 TG3_NVRAM_SIZE_64KB :
11479 TG3_NVRAM_SIZE_128KB);
11480 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11481 tp->nvram_size = (protect ?
11482 TG3_NVRAM_SIZE_64KB :
11483 TG3_NVRAM_SIZE_256KB);
11484 else
11485 tp->nvram_size = (protect ?
11486 TG3_NVRAM_SIZE_128KB :
11487 TG3_NVRAM_SIZE_512KB);
11488 break;
11489 }
11490 }
11491
11492 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11493 {
11494 u32 nvcfg1;
11495
11496 nvcfg1 = tr32(NVRAM_CFG1);
11497
11498 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11499 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11500 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11501 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11502 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11503 tp->nvram_jedecnum = JEDEC_ATMEL;
11504 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11505 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11506
11507 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11508 tw32(NVRAM_CFG1, nvcfg1);
11509 break;
11510 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11511 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11512 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11513 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11514 tp->nvram_jedecnum = JEDEC_ATMEL;
11515 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11516 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11517 tp->nvram_pagesize = 264;
11518 break;
11519 case FLASH_5752VENDOR_ST_M45PE10:
11520 case FLASH_5752VENDOR_ST_M45PE20:
11521 case FLASH_5752VENDOR_ST_M45PE40:
11522 tp->nvram_jedecnum = JEDEC_ST;
11523 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11524 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11525 tp->nvram_pagesize = 256;
11526 break;
11527 }
11528 }
11529
11530 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11531 {
11532 u32 nvcfg1, protect = 0;
11533
11534 nvcfg1 = tr32(NVRAM_CFG1);
11535
11536 /* NVRAM protection for TPM */
11537 if (nvcfg1 & (1 << 27)) {
11538 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11539 protect = 1;
11540 }
11541
11542 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11543 switch (nvcfg1) {
11544 case FLASH_5761VENDOR_ATMEL_ADB021D:
11545 case FLASH_5761VENDOR_ATMEL_ADB041D:
11546 case FLASH_5761VENDOR_ATMEL_ADB081D:
11547 case FLASH_5761VENDOR_ATMEL_ADB161D:
11548 case FLASH_5761VENDOR_ATMEL_MDB021D:
11549 case FLASH_5761VENDOR_ATMEL_MDB041D:
11550 case FLASH_5761VENDOR_ATMEL_MDB081D:
11551 case FLASH_5761VENDOR_ATMEL_MDB161D:
11552 tp->nvram_jedecnum = JEDEC_ATMEL;
11553 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11554 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11555 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11556 tp->nvram_pagesize = 256;
11557 break;
11558 case FLASH_5761VENDOR_ST_A_M45PE20:
11559 case FLASH_5761VENDOR_ST_A_M45PE40:
11560 case FLASH_5761VENDOR_ST_A_M45PE80:
11561 case FLASH_5761VENDOR_ST_A_M45PE16:
11562 case FLASH_5761VENDOR_ST_M_M45PE20:
11563 case FLASH_5761VENDOR_ST_M_M45PE40:
11564 case FLASH_5761VENDOR_ST_M_M45PE80:
11565 case FLASH_5761VENDOR_ST_M_M45PE16:
11566 tp->nvram_jedecnum = JEDEC_ST;
11567 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11568 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11569 tp->nvram_pagesize = 256;
11570 break;
11571 }
11572
11573 if (protect) {
11574 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11575 } else {
11576 switch (nvcfg1) {
11577 case FLASH_5761VENDOR_ATMEL_ADB161D:
11578 case FLASH_5761VENDOR_ATMEL_MDB161D:
11579 case FLASH_5761VENDOR_ST_A_M45PE16:
11580 case FLASH_5761VENDOR_ST_M_M45PE16:
11581 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11582 break;
11583 case FLASH_5761VENDOR_ATMEL_ADB081D:
11584 case FLASH_5761VENDOR_ATMEL_MDB081D:
11585 case FLASH_5761VENDOR_ST_A_M45PE80:
11586 case FLASH_5761VENDOR_ST_M_M45PE80:
11587 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11588 break;
11589 case FLASH_5761VENDOR_ATMEL_ADB041D:
11590 case FLASH_5761VENDOR_ATMEL_MDB041D:
11591 case FLASH_5761VENDOR_ST_A_M45PE40:
11592 case FLASH_5761VENDOR_ST_M_M45PE40:
11593 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11594 break;
11595 case FLASH_5761VENDOR_ATMEL_ADB021D:
11596 case FLASH_5761VENDOR_ATMEL_MDB021D:
11597 case FLASH_5761VENDOR_ST_A_M45PE20:
11598 case FLASH_5761VENDOR_ST_M_M45PE20:
11599 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11600 break;
11601 }
11602 }
11603 }
11604
11605 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11606 {
11607 tp->nvram_jedecnum = JEDEC_ATMEL;
11608 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11609 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11610 }
11611
11612 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11613 {
11614 u32 nvcfg1;
11615
11616 nvcfg1 = tr32(NVRAM_CFG1);
11617
11618 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11619 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11620 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11621 tp->nvram_jedecnum = JEDEC_ATMEL;
11622 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11623 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11624
11625 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11626 tw32(NVRAM_CFG1, nvcfg1);
11627 return;
11628 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11629 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11630 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11631 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11632 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11633 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11634 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11635 tp->nvram_jedecnum = JEDEC_ATMEL;
11636 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11637 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11638
11639 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11640 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11641 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11642 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11643 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11644 break;
11645 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11646 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11647 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11648 break;
11649 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11650 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11651 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11652 break;
11653 }
11654 break;
11655 case FLASH_5752VENDOR_ST_M45PE10:
11656 case FLASH_5752VENDOR_ST_M45PE20:
11657 case FLASH_5752VENDOR_ST_M45PE40:
11658 tp->nvram_jedecnum = JEDEC_ST;
11659 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11660 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11661
11662 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11663 case FLASH_5752VENDOR_ST_M45PE10:
11664 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11665 break;
11666 case FLASH_5752VENDOR_ST_M45PE20:
11667 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11668 break;
11669 case FLASH_5752VENDOR_ST_M45PE40:
11670 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11671 break;
11672 }
11673 break;
11674 default:
11675 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11676 return;
11677 }
11678
11679 tg3_nvram_get_pagesize(tp, nvcfg1);
11680 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11681 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11682 }
11683
11684
11685 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11686 {
11687 u32 nvcfg1;
11688
11689 nvcfg1 = tr32(NVRAM_CFG1);
11690
11691 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11692 case FLASH_5717VENDOR_ATMEL_EEPROM:
11693 case FLASH_5717VENDOR_MICRO_EEPROM:
11694 tp->nvram_jedecnum = JEDEC_ATMEL;
11695 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11696 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11697
11698 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11699 tw32(NVRAM_CFG1, nvcfg1);
11700 return;
11701 case FLASH_5717VENDOR_ATMEL_MDB011D:
11702 case FLASH_5717VENDOR_ATMEL_ADB011B:
11703 case FLASH_5717VENDOR_ATMEL_ADB011D:
11704 case FLASH_5717VENDOR_ATMEL_MDB021D:
11705 case FLASH_5717VENDOR_ATMEL_ADB021B:
11706 case FLASH_5717VENDOR_ATMEL_ADB021D:
11707 case FLASH_5717VENDOR_ATMEL_45USPT:
11708 tp->nvram_jedecnum = JEDEC_ATMEL;
11709 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11710 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11711
11712 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11713 case FLASH_5717VENDOR_ATMEL_MDB021D:
11714 case FLASH_5717VENDOR_ATMEL_ADB021B:
11715 case FLASH_5717VENDOR_ATMEL_ADB021D:
11716 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11717 break;
11718 default:
11719 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11720 break;
11721 }
11722 break;
11723 case FLASH_5717VENDOR_ST_M_M25PE10:
11724 case FLASH_5717VENDOR_ST_A_M25PE10:
11725 case FLASH_5717VENDOR_ST_M_M45PE10:
11726 case FLASH_5717VENDOR_ST_A_M45PE10:
11727 case FLASH_5717VENDOR_ST_M_M25PE20:
11728 case FLASH_5717VENDOR_ST_A_M25PE20:
11729 case FLASH_5717VENDOR_ST_M_M45PE20:
11730 case FLASH_5717VENDOR_ST_A_M45PE20:
11731 case FLASH_5717VENDOR_ST_25USPT:
11732 case FLASH_5717VENDOR_ST_45USPT:
11733 tp->nvram_jedecnum = JEDEC_ST;
11734 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11735 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11736
11737 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11738 case FLASH_5717VENDOR_ST_M_M25PE20:
11739 case FLASH_5717VENDOR_ST_A_M25PE20:
11740 case FLASH_5717VENDOR_ST_M_M45PE20:
11741 case FLASH_5717VENDOR_ST_A_M45PE20:
11742 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11743 break;
11744 default:
11745 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11746 break;
11747 }
11748 break;
11749 default:
11750 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11751 return;
11752 }
11753
11754 tg3_nvram_get_pagesize(tp, nvcfg1);
11755 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11756 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11757 }
11758
11759 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11760 static void __devinit tg3_nvram_init(struct tg3 *tp)
11761 {
11762 tw32_f(GRC_EEPROM_ADDR,
11763 (EEPROM_ADDR_FSM_RESET |
11764 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11765 EEPROM_ADDR_CLKPERD_SHIFT)));
11766
11767 msleep(1);
11768
11769 /* Enable seeprom accesses. */
11770 tw32_f(GRC_LOCAL_CTRL,
11771 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11772 udelay(100);
11773
11774 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11775 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11776 tp->tg3_flags |= TG3_FLAG_NVRAM;
11777
11778 if (tg3_nvram_lock(tp)) {
11779 netdev_warn(tp->dev, "Cannot get nvram lock, %s failed\n",
11780 __func__);
11781 return;
11782 }
11783 tg3_enable_nvram_access(tp);
11784
11785 tp->nvram_size = 0;
11786
11787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11788 tg3_get_5752_nvram_info(tp);
11789 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11790 tg3_get_5755_nvram_info(tp);
11791 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11792 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11793 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11794 tg3_get_5787_nvram_info(tp);
11795 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11796 tg3_get_5761_nvram_info(tp);
11797 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11798 tg3_get_5906_nvram_info(tp);
11799 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11800 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11801 tg3_get_57780_nvram_info(tp);
11802 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11803 tg3_get_5717_nvram_info(tp);
11804 else
11805 tg3_get_nvram_info(tp);
11806
11807 if (tp->nvram_size == 0)
11808 tg3_get_nvram_size(tp);
11809
11810 tg3_disable_nvram_access(tp);
11811 tg3_nvram_unlock(tp);
11812
11813 } else {
11814 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11815
11816 tg3_get_eeprom_size(tp);
11817 }
11818 }
11819
11820 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11821 u32 offset, u32 len, u8 *buf)
11822 {
11823 int i, j, rc = 0;
11824 u32 val;
11825
11826 for (i = 0; i < len; i += 4) {
11827 u32 addr;
11828 __be32 data;
11829
11830 addr = offset + i;
11831
11832 memcpy(&data, buf + i, 4);
11833
11834 /*
11835 * The SEEPROM interface expects the data to always be opposite
11836 * the native endian format. We accomplish this by reversing
11837 * all the operations that would have been performed on the
11838 * data from a call to tg3_nvram_read_be32().
11839 */
11840 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11841
11842 val = tr32(GRC_EEPROM_ADDR);
11843 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11844
11845 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11846 EEPROM_ADDR_READ);
11847 tw32(GRC_EEPROM_ADDR, val |
11848 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11849 (addr & EEPROM_ADDR_ADDR_MASK) |
11850 EEPROM_ADDR_START |
11851 EEPROM_ADDR_WRITE);
11852
11853 for (j = 0; j < 1000; j++) {
11854 val = tr32(GRC_EEPROM_ADDR);
11855
11856 if (val & EEPROM_ADDR_COMPLETE)
11857 break;
11858 msleep(1);
11859 }
11860 if (!(val & EEPROM_ADDR_COMPLETE)) {
11861 rc = -EBUSY;
11862 break;
11863 }
11864 }
11865
11866 return rc;
11867 }
11868
11869 /* offset and length are dword aligned */
11870 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11871 u8 *buf)
11872 {
11873 int ret = 0;
11874 u32 pagesize = tp->nvram_pagesize;
11875 u32 pagemask = pagesize - 1;
11876 u32 nvram_cmd;
11877 u8 *tmp;
11878
11879 tmp = kmalloc(pagesize, GFP_KERNEL);
11880 if (tmp == NULL)
11881 return -ENOMEM;
11882
11883 while (len) {
11884 int j;
11885 u32 phy_addr, page_off, size;
11886
11887 phy_addr = offset & ~pagemask;
11888
11889 for (j = 0; j < pagesize; j += 4) {
11890 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11891 (__be32 *) (tmp + j));
11892 if (ret)
11893 break;
11894 }
11895 if (ret)
11896 break;
11897
11898 page_off = offset & pagemask;
11899 size = pagesize;
11900 if (len < size)
11901 size = len;
11902
11903 len -= size;
11904
11905 memcpy(tmp + page_off, buf, size);
11906
11907 offset = offset + (pagesize - page_off);
11908
11909 tg3_enable_nvram_access(tp);
11910
11911 /*
11912 * Before we can erase the flash page, we need
11913 * to issue a special "write enable" command.
11914 */
11915 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11916
11917 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11918 break;
11919
11920 /* Erase the target page */
11921 tw32(NVRAM_ADDR, phy_addr);
11922
11923 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11924 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11925
11926 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11927 break;
11928
11929 /* Issue another write enable to start the write. */
11930 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11931
11932 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11933 break;
11934
11935 for (j = 0; j < pagesize; j += 4) {
11936 __be32 data;
11937
11938 data = *((__be32 *) (tmp + j));
11939
11940 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11941
11942 tw32(NVRAM_ADDR, phy_addr + j);
11943
11944 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11945 NVRAM_CMD_WR;
11946
11947 if (j == 0)
11948 nvram_cmd |= NVRAM_CMD_FIRST;
11949 else if (j == (pagesize - 4))
11950 nvram_cmd |= NVRAM_CMD_LAST;
11951
11952 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11953 break;
11954 }
11955 if (ret)
11956 break;
11957 }
11958
11959 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11960 tg3_nvram_exec_cmd(tp, nvram_cmd);
11961
11962 kfree(tmp);
11963
11964 return ret;
11965 }
11966
11967 /* offset and length are dword aligned */
11968 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11969 u8 *buf)
11970 {
11971 int i, ret = 0;
11972
11973 for (i = 0; i < len; i += 4, offset += 4) {
11974 u32 page_off, phy_addr, nvram_cmd;
11975 __be32 data;
11976
11977 memcpy(&data, buf + i, 4);
11978 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11979
11980 page_off = offset % tp->nvram_pagesize;
11981
11982 phy_addr = tg3_nvram_phys_addr(tp, offset);
11983
11984 tw32(NVRAM_ADDR, phy_addr);
11985
11986 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11987
11988 if ((page_off == 0) || (i == 0))
11989 nvram_cmd |= NVRAM_CMD_FIRST;
11990 if (page_off == (tp->nvram_pagesize - 4))
11991 nvram_cmd |= NVRAM_CMD_LAST;
11992
11993 if (i == (len - 4))
11994 nvram_cmd |= NVRAM_CMD_LAST;
11995
11996 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11997 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11998 (tp->nvram_jedecnum == JEDEC_ST) &&
11999 (nvram_cmd & NVRAM_CMD_FIRST)) {
12000
12001 if ((ret = tg3_nvram_exec_cmd(tp,
12002 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12003 NVRAM_CMD_DONE)))
12004
12005 break;
12006 }
12007 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12008 /* We always do complete word writes to eeprom. */
12009 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12010 }
12011
12012 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12013 break;
12014 }
12015 return ret;
12016 }
12017
12018 /* offset and length are dword aligned */
12019 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12020 {
12021 int ret;
12022
12023 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12024 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12025 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12026 udelay(40);
12027 }
12028
12029 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12030 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12031 }
12032 else {
12033 u32 grc_mode;
12034
12035 ret = tg3_nvram_lock(tp);
12036 if (ret)
12037 return ret;
12038
12039 tg3_enable_nvram_access(tp);
12040 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12041 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12042 tw32(NVRAM_WRITE1, 0x406);
12043
12044 grc_mode = tr32(GRC_MODE);
12045 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12046
12047 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12048 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12049
12050 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12051 buf);
12052 }
12053 else {
12054 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12055 buf);
12056 }
12057
12058 grc_mode = tr32(GRC_MODE);
12059 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12060
12061 tg3_disable_nvram_access(tp);
12062 tg3_nvram_unlock(tp);
12063 }
12064
12065 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12066 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12067 udelay(40);
12068 }
12069
12070 return ret;
12071 }
12072
12073 struct subsys_tbl_ent {
12074 u16 subsys_vendor, subsys_devid;
12075 u32 phy_id;
12076 };
12077
12078 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12079 /* Broadcom boards. */
12080 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12081 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12082 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12083 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12084 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12085 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12086 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12087 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12088 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12089 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12090 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12091 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12092 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12093 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12094 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12095 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12096 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12097 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12098 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12099 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12100 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12101 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12102
12103 /* 3com boards. */
12104 { TG3PCI_SUBVENDOR_ID_3COM,
12105 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12106 { TG3PCI_SUBVENDOR_ID_3COM,
12107 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12108 { TG3PCI_SUBVENDOR_ID_3COM,
12109 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12110 { TG3PCI_SUBVENDOR_ID_3COM,
12111 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12112 { TG3PCI_SUBVENDOR_ID_3COM,
12113 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12114
12115 /* DELL boards. */
12116 { TG3PCI_SUBVENDOR_ID_DELL,
12117 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12118 { TG3PCI_SUBVENDOR_ID_DELL,
12119 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12120 { TG3PCI_SUBVENDOR_ID_DELL,
12121 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12122 { TG3PCI_SUBVENDOR_ID_DELL,
12123 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12124
12125 /* Compaq boards. */
12126 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12127 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12128 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12129 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12130 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12131 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12132 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12133 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12134 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12135 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12136
12137 /* IBM boards. */
12138 { TG3PCI_SUBVENDOR_ID_IBM,
12139 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12140 };
12141
12142 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12143 {
12144 int i;
12145
12146 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12147 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12148 tp->pdev->subsystem_vendor) &&
12149 (subsys_id_to_phy_id[i].subsys_devid ==
12150 tp->pdev->subsystem_device))
12151 return &subsys_id_to_phy_id[i];
12152 }
12153 return NULL;
12154 }
12155
12156 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12157 {
12158 u32 val;
12159 u16 pmcsr;
12160
12161 /* On some early chips the SRAM cannot be accessed in D3hot state,
12162 * so need make sure we're in D0.
12163 */
12164 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12165 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12166 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12167 msleep(1);
12168
12169 /* Make sure register accesses (indirect or otherwise)
12170 * will function correctly.
12171 */
12172 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12173 tp->misc_host_ctrl);
12174
12175 /* The memory arbiter has to be enabled in order for SRAM accesses
12176 * to succeed. Normally on powerup the tg3 chip firmware will make
12177 * sure it is enabled, but other entities such as system netboot
12178 * code might disable it.
12179 */
12180 val = tr32(MEMARB_MODE);
12181 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12182
12183 tp->phy_id = TG3_PHY_ID_INVALID;
12184 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12185
12186 /* Assume an onboard device and WOL capable by default. */
12187 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12188
12189 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12190 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12191 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12192 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12193 }
12194 val = tr32(VCPU_CFGSHDW);
12195 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12196 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12197 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12198 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12199 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12200 goto done;
12201 }
12202
12203 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12204 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12205 u32 nic_cfg, led_cfg;
12206 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12207 int eeprom_phy_serdes = 0;
12208
12209 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12210 tp->nic_sram_data_cfg = nic_cfg;
12211
12212 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12213 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12214 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12215 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12216 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12217 (ver > 0) && (ver < 0x100))
12218 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12219
12220 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12221 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12222
12223 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12224 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12225 eeprom_phy_serdes = 1;
12226
12227 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12228 if (nic_phy_id != 0) {
12229 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12230 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12231
12232 eeprom_phy_id = (id1 >> 16) << 10;
12233 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12234 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12235 } else
12236 eeprom_phy_id = 0;
12237
12238 tp->phy_id = eeprom_phy_id;
12239 if (eeprom_phy_serdes) {
12240 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12241 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12242 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12243 else
12244 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12245 }
12246
12247 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12248 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12249 SHASTA_EXT_LED_MODE_MASK);
12250 else
12251 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12252
12253 switch (led_cfg) {
12254 default:
12255 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12256 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12257 break;
12258
12259 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12260 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12261 break;
12262
12263 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12264 tp->led_ctrl = LED_CTRL_MODE_MAC;
12265
12266 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12267 * read on some older 5700/5701 bootcode.
12268 */
12269 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12270 ASIC_REV_5700 ||
12271 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12272 ASIC_REV_5701)
12273 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12274
12275 break;
12276
12277 case SHASTA_EXT_LED_SHARED:
12278 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12279 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12280 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12281 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12282 LED_CTRL_MODE_PHY_2);
12283 break;
12284
12285 case SHASTA_EXT_LED_MAC:
12286 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12287 break;
12288
12289 case SHASTA_EXT_LED_COMBO:
12290 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12291 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12292 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12293 LED_CTRL_MODE_PHY_2);
12294 break;
12295
12296 }
12297
12298 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12299 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12300 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12301 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12302
12303 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12304 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12305
12306 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12307 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12308 if ((tp->pdev->subsystem_vendor ==
12309 PCI_VENDOR_ID_ARIMA) &&
12310 (tp->pdev->subsystem_device == 0x205a ||
12311 tp->pdev->subsystem_device == 0x2063))
12312 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12313 } else {
12314 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12315 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12316 }
12317
12318 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12319 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12320 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12321 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12322 }
12323
12324 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12325 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12326 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12327
12328 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12329 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12330 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12331
12332 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12333 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12334 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12335
12336 if (cfg2 & (1 << 17))
12337 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12338
12339 /* serdes signal pre-emphasis in register 0x590 set by */
12340 /* bootcode if bit 18 is set */
12341 if (cfg2 & (1 << 18))
12342 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12343
12344 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12345 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12346 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12347 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12348
12349 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12350 u32 cfg3;
12351
12352 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12353 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12354 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12355 }
12356
12357 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12358 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12359 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12360 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12361 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12362 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12363 }
12364 done:
12365 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12366 device_set_wakeup_enable(&tp->pdev->dev,
12367 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12368 }
12369
12370 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12371 {
12372 int i;
12373 u32 val;
12374
12375 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12376 tw32(OTP_CTRL, cmd);
12377
12378 /* Wait for up to 1 ms for command to execute. */
12379 for (i = 0; i < 100; i++) {
12380 val = tr32(OTP_STATUS);
12381 if (val & OTP_STATUS_CMD_DONE)
12382 break;
12383 udelay(10);
12384 }
12385
12386 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12387 }
12388
12389 /* Read the gphy configuration from the OTP region of the chip. The gphy
12390 * configuration is a 32-bit value that straddles the alignment boundary.
12391 * We do two 32-bit reads and then shift and merge the results.
12392 */
12393 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12394 {
12395 u32 bhalf_otp, thalf_otp;
12396
12397 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12398
12399 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12400 return 0;
12401
12402 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12403
12404 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12405 return 0;
12406
12407 thalf_otp = tr32(OTP_READ_DATA);
12408
12409 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12410
12411 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12412 return 0;
12413
12414 bhalf_otp = tr32(OTP_READ_DATA);
12415
12416 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12417 }
12418
12419 static int __devinit tg3_phy_probe(struct tg3 *tp)
12420 {
12421 u32 hw_phy_id_1, hw_phy_id_2;
12422 u32 hw_phy_id, hw_phy_id_masked;
12423 int err;
12424
12425 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12426 return tg3_phy_init(tp);
12427
12428 /* Reading the PHY ID register can conflict with ASF
12429 * firmware access to the PHY hardware.
12430 */
12431 err = 0;
12432 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12433 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12434 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12435 } else {
12436 /* Now read the physical PHY_ID from the chip and verify
12437 * that it is sane. If it doesn't look good, we fall back
12438 * to either the hard-coded table based PHY_ID and failing
12439 * that the value found in the eeprom area.
12440 */
12441 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12442 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12443
12444 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12445 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12446 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12447
12448 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12449 }
12450
12451 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12452 tp->phy_id = hw_phy_id;
12453 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12454 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12455 else
12456 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12457 } else {
12458 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12459 /* Do nothing, phy ID already set up in
12460 * tg3_get_eeprom_hw_cfg().
12461 */
12462 } else {
12463 struct subsys_tbl_ent *p;
12464
12465 /* No eeprom signature? Try the hardcoded
12466 * subsys device table.
12467 */
12468 p = tg3_lookup_by_subsys(tp);
12469 if (!p)
12470 return -ENODEV;
12471
12472 tp->phy_id = p->phy_id;
12473 if (!tp->phy_id ||
12474 tp->phy_id == TG3_PHY_ID_BCM8002)
12475 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12476 }
12477 }
12478
12479 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12480 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12481 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12482 u32 bmsr, adv_reg, tg3_ctrl, mask;
12483
12484 tg3_readphy(tp, MII_BMSR, &bmsr);
12485 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12486 (bmsr & BMSR_LSTATUS))
12487 goto skip_phy_reset;
12488
12489 err = tg3_phy_reset(tp);
12490 if (err)
12491 return err;
12492
12493 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12494 ADVERTISE_100HALF | ADVERTISE_100FULL |
12495 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12496 tg3_ctrl = 0;
12497 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12498 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12499 MII_TG3_CTRL_ADV_1000_FULL);
12500 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12501 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12502 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12503 MII_TG3_CTRL_ENABLE_AS_MASTER);
12504 }
12505
12506 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12507 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12508 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12509 if (!tg3_copper_is_advertising_all(tp, mask)) {
12510 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12511
12512 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12513 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12514
12515 tg3_writephy(tp, MII_BMCR,
12516 BMCR_ANENABLE | BMCR_ANRESTART);
12517 }
12518 tg3_phy_set_wirespeed(tp);
12519
12520 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12521 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12522 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12523 }
12524
12525 skip_phy_reset:
12526 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12527 err = tg3_init_5401phy_dsp(tp);
12528 if (err)
12529 return err;
12530
12531 err = tg3_init_5401phy_dsp(tp);
12532 }
12533
12534 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12535 tp->link_config.advertising =
12536 (ADVERTISED_1000baseT_Half |
12537 ADVERTISED_1000baseT_Full |
12538 ADVERTISED_Autoneg |
12539 ADVERTISED_FIBRE);
12540 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12541 tp->link_config.advertising &=
12542 ~(ADVERTISED_1000baseT_Half |
12543 ADVERTISED_1000baseT_Full);
12544
12545 return err;
12546 }
12547
12548 static void __devinit tg3_read_partno(struct tg3 *tp)
12549 {
12550 unsigned char vpd_data[TG3_NVM_VPD_LEN]; /* in little-endian format */
12551 unsigned int block_end, rosize, len;
12552 int i = 0;
12553 u32 magic;
12554
12555 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12556 tg3_nvram_read(tp, 0x0, &magic))
12557 goto out_not_found;
12558
12559 if (magic == TG3_EEPROM_MAGIC) {
12560 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12561 u32 tmp;
12562
12563 /* The data is in little-endian format in NVRAM.
12564 * Use the big-endian read routines to preserve
12565 * the byte order as it exists in NVRAM.
12566 */
12567 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12568 goto out_not_found;
12569
12570 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12571 }
12572 } else {
12573 ssize_t cnt;
12574 unsigned int pos = 0;
12575
12576 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12577 cnt = pci_read_vpd(tp->pdev, pos,
12578 TG3_NVM_VPD_LEN - pos,
12579 &vpd_data[pos]);
12580 if (cnt == -ETIMEDOUT || -EINTR)
12581 cnt = 0;
12582 else if (cnt < 0)
12583 goto out_not_found;
12584 }
12585 if (pos != TG3_NVM_VPD_LEN)
12586 goto out_not_found;
12587 }
12588
12589 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12590 PCI_VPD_LRDT_RO_DATA);
12591 if (i < 0)
12592 goto out_not_found;
12593
12594 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12595 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12596 i += PCI_VPD_LRDT_TAG_SIZE;
12597
12598 if (block_end > TG3_NVM_VPD_LEN)
12599 goto out_not_found;
12600
12601 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12602 PCI_VPD_RO_KEYWORD_PARTNO);
12603 if (i < 0)
12604 goto out_not_found;
12605
12606 len = pci_vpd_info_field_size(&vpd_data[i]);
12607
12608 i += PCI_VPD_INFO_FLD_HDR_SIZE;
12609 if (len > TG3_BPN_SIZE ||
12610 (len + i) > TG3_NVM_VPD_LEN)
12611 goto out_not_found;
12612
12613 memcpy(tp->board_part_number, &vpd_data[i], len);
12614
12615 return;
12616
12617 out_not_found:
12618 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12619 strcpy(tp->board_part_number, "BCM95906");
12620 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12621 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12622 strcpy(tp->board_part_number, "BCM57780");
12623 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12624 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12625 strcpy(tp->board_part_number, "BCM57760");
12626 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12627 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12628 strcpy(tp->board_part_number, "BCM57790");
12629 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12630 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12631 strcpy(tp->board_part_number, "BCM57788");
12632 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12633 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12634 strcpy(tp->board_part_number, "BCM57761");
12635 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12636 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12637 strcpy(tp->board_part_number, "BCM57765");
12638 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12639 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12640 strcpy(tp->board_part_number, "BCM57781");
12641 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12642 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12643 strcpy(tp->board_part_number, "BCM57785");
12644 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12645 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12646 strcpy(tp->board_part_number, "BCM57791");
12647 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12648 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12649 strcpy(tp->board_part_number, "BCM57795");
12650 else
12651 strcpy(tp->board_part_number, "none");
12652 }
12653
12654 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12655 {
12656 u32 val;
12657
12658 if (tg3_nvram_read(tp, offset, &val) ||
12659 (val & 0xfc000000) != 0x0c000000 ||
12660 tg3_nvram_read(tp, offset + 4, &val) ||
12661 val != 0)
12662 return 0;
12663
12664 return 1;
12665 }
12666
12667 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12668 {
12669 u32 val, offset, start, ver_offset;
12670 int i;
12671 bool newver = false;
12672
12673 if (tg3_nvram_read(tp, 0xc, &offset) ||
12674 tg3_nvram_read(tp, 0x4, &start))
12675 return;
12676
12677 offset = tg3_nvram_logical_addr(tp, offset);
12678
12679 if (tg3_nvram_read(tp, offset, &val))
12680 return;
12681
12682 if ((val & 0xfc000000) == 0x0c000000) {
12683 if (tg3_nvram_read(tp, offset + 4, &val))
12684 return;
12685
12686 if (val == 0)
12687 newver = true;
12688 }
12689
12690 if (newver) {
12691 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12692 return;
12693
12694 offset = offset + ver_offset - start;
12695 for (i = 0; i < 16; i += 4) {
12696 __be32 v;
12697 if (tg3_nvram_read_be32(tp, offset + i, &v))
12698 return;
12699
12700 memcpy(tp->fw_ver + i, &v, sizeof(v));
12701 }
12702 } else {
12703 u32 major, minor;
12704
12705 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12706 return;
12707
12708 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12709 TG3_NVM_BCVER_MAJSFT;
12710 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12711 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12712 }
12713 }
12714
12715 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12716 {
12717 u32 val, major, minor;
12718
12719 /* Use native endian representation */
12720 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12721 return;
12722
12723 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12724 TG3_NVM_HWSB_CFG1_MAJSFT;
12725 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12726 TG3_NVM_HWSB_CFG1_MINSFT;
12727
12728 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12729 }
12730
12731 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12732 {
12733 u32 offset, major, minor, build;
12734
12735 tp->fw_ver[0] = 's';
12736 tp->fw_ver[1] = 'b';
12737 tp->fw_ver[2] = '\0';
12738
12739 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12740 return;
12741
12742 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12743 case TG3_EEPROM_SB_REVISION_0:
12744 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12745 break;
12746 case TG3_EEPROM_SB_REVISION_2:
12747 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12748 break;
12749 case TG3_EEPROM_SB_REVISION_3:
12750 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12751 break;
12752 case TG3_EEPROM_SB_REVISION_4:
12753 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12754 break;
12755 case TG3_EEPROM_SB_REVISION_5:
12756 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12757 break;
12758 default:
12759 return;
12760 }
12761
12762 if (tg3_nvram_read(tp, offset, &val))
12763 return;
12764
12765 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12766 TG3_EEPROM_SB_EDH_BLD_SHFT;
12767 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12768 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12769 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12770
12771 if (minor > 99 || build > 26)
12772 return;
12773
12774 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12775
12776 if (build > 0) {
12777 tp->fw_ver[8] = 'a' + build - 1;
12778 tp->fw_ver[9] = '\0';
12779 }
12780 }
12781
12782 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12783 {
12784 u32 val, offset, start;
12785 int i, vlen;
12786
12787 for (offset = TG3_NVM_DIR_START;
12788 offset < TG3_NVM_DIR_END;
12789 offset += TG3_NVM_DIRENT_SIZE) {
12790 if (tg3_nvram_read(tp, offset, &val))
12791 return;
12792
12793 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12794 break;
12795 }
12796
12797 if (offset == TG3_NVM_DIR_END)
12798 return;
12799
12800 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12801 start = 0x08000000;
12802 else if (tg3_nvram_read(tp, offset - 4, &start))
12803 return;
12804
12805 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12806 !tg3_fw_img_is_valid(tp, offset) ||
12807 tg3_nvram_read(tp, offset + 8, &val))
12808 return;
12809
12810 offset += val - start;
12811
12812 vlen = strlen(tp->fw_ver);
12813
12814 tp->fw_ver[vlen++] = ',';
12815 tp->fw_ver[vlen++] = ' ';
12816
12817 for (i = 0; i < 4; i++) {
12818 __be32 v;
12819 if (tg3_nvram_read_be32(tp, offset, &v))
12820 return;
12821
12822 offset += sizeof(v);
12823
12824 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12825 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12826 break;
12827 }
12828
12829 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12830 vlen += sizeof(v);
12831 }
12832 }
12833
12834 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12835 {
12836 int vlen;
12837 u32 apedata;
12838
12839 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12840 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12841 return;
12842
12843 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12844 if (apedata != APE_SEG_SIG_MAGIC)
12845 return;
12846
12847 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12848 if (!(apedata & APE_FW_STATUS_READY))
12849 return;
12850
12851 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12852
12853 vlen = strlen(tp->fw_ver);
12854
12855 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12856 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12857 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12858 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12859 (apedata & APE_FW_VERSION_BLDMSK));
12860 }
12861
12862 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12863 {
12864 u32 val;
12865
12866 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12867 tp->fw_ver[0] = 's';
12868 tp->fw_ver[1] = 'b';
12869 tp->fw_ver[2] = '\0';
12870
12871 return;
12872 }
12873
12874 if (tg3_nvram_read(tp, 0, &val))
12875 return;
12876
12877 if (val == TG3_EEPROM_MAGIC)
12878 tg3_read_bc_ver(tp);
12879 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12880 tg3_read_sb_ver(tp, val);
12881 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12882 tg3_read_hwsb_ver(tp);
12883 else
12884 return;
12885
12886 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12887 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12888 return;
12889
12890 tg3_read_mgmtfw_ver(tp);
12891
12892 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12893 }
12894
12895 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12896
12897 static int __devinit tg3_get_invariants(struct tg3 *tp)
12898 {
12899 static struct pci_device_id write_reorder_chipsets[] = {
12900 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12901 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12902 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12903 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12904 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12905 PCI_DEVICE_ID_VIA_8385_0) },
12906 { },
12907 };
12908 u32 misc_ctrl_reg;
12909 u32 pci_state_reg, grc_misc_cfg;
12910 u32 val;
12911 u16 pci_cmd;
12912 int err;
12913
12914 /* Force memory write invalidate off. If we leave it on,
12915 * then on 5700_BX chips we have to enable a workaround.
12916 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12917 * to match the cacheline size. The Broadcom driver have this
12918 * workaround but turns MWI off all the times so never uses
12919 * it. This seems to suggest that the workaround is insufficient.
12920 */
12921 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12922 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12923 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12924
12925 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12926 * has the register indirect write enable bit set before
12927 * we try to access any of the MMIO registers. It is also
12928 * critical that the PCI-X hw workaround situation is decided
12929 * before that as well.
12930 */
12931 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12932 &misc_ctrl_reg);
12933
12934 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12935 MISC_HOST_CTRL_CHIPREV_SHIFT);
12936 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12937 u32 prod_id_asic_rev;
12938
12939 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12940 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12941 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12942 pci_read_config_dword(tp->pdev,
12943 TG3PCI_GEN2_PRODID_ASICREV,
12944 &prod_id_asic_rev);
12945 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12946 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12947 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12948 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12949 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12950 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12951 pci_read_config_dword(tp->pdev,
12952 TG3PCI_GEN15_PRODID_ASICREV,
12953 &prod_id_asic_rev);
12954 else
12955 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12956 &prod_id_asic_rev);
12957
12958 tp->pci_chip_rev_id = prod_id_asic_rev;
12959 }
12960
12961 /* Wrong chip ID in 5752 A0. This code can be removed later
12962 * as A0 is not in production.
12963 */
12964 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12965 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12966
12967 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12968 * we need to disable memory and use config. cycles
12969 * only to access all registers. The 5702/03 chips
12970 * can mistakenly decode the special cycles from the
12971 * ICH chipsets as memory write cycles, causing corruption
12972 * of register and memory space. Only certain ICH bridges
12973 * will drive special cycles with non-zero data during the
12974 * address phase which can fall within the 5703's address
12975 * range. This is not an ICH bug as the PCI spec allows
12976 * non-zero address during special cycles. However, only
12977 * these ICH bridges are known to drive non-zero addresses
12978 * during special cycles.
12979 *
12980 * Since special cycles do not cross PCI bridges, we only
12981 * enable this workaround if the 5703 is on the secondary
12982 * bus of these ICH bridges.
12983 */
12984 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12985 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12986 static struct tg3_dev_id {
12987 u32 vendor;
12988 u32 device;
12989 u32 rev;
12990 } ich_chipsets[] = {
12991 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12992 PCI_ANY_ID },
12993 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12994 PCI_ANY_ID },
12995 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12996 0xa },
12997 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12998 PCI_ANY_ID },
12999 { },
13000 };
13001 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13002 struct pci_dev *bridge = NULL;
13003
13004 while (pci_id->vendor != 0) {
13005 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13006 bridge);
13007 if (!bridge) {
13008 pci_id++;
13009 continue;
13010 }
13011 if (pci_id->rev != PCI_ANY_ID) {
13012 if (bridge->revision > pci_id->rev)
13013 continue;
13014 }
13015 if (bridge->subordinate &&
13016 (bridge->subordinate->number ==
13017 tp->pdev->bus->number)) {
13018
13019 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13020 pci_dev_put(bridge);
13021 break;
13022 }
13023 }
13024 }
13025
13026 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13027 static struct tg3_dev_id {
13028 u32 vendor;
13029 u32 device;
13030 } bridge_chipsets[] = {
13031 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13032 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13033 { },
13034 };
13035 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13036 struct pci_dev *bridge = NULL;
13037
13038 while (pci_id->vendor != 0) {
13039 bridge = pci_get_device(pci_id->vendor,
13040 pci_id->device,
13041 bridge);
13042 if (!bridge) {
13043 pci_id++;
13044 continue;
13045 }
13046 if (bridge->subordinate &&
13047 (bridge->subordinate->number <=
13048 tp->pdev->bus->number) &&
13049 (bridge->subordinate->subordinate >=
13050 tp->pdev->bus->number)) {
13051 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13052 pci_dev_put(bridge);
13053 break;
13054 }
13055 }
13056 }
13057
13058 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13059 * DMA addresses > 40-bit. This bridge may have other additional
13060 * 57xx devices behind it in some 4-port NIC designs for example.
13061 * Any tg3 device found behind the bridge will also need the 40-bit
13062 * DMA workaround.
13063 */
13064 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13065 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13066 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13067 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13068 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13069 }
13070 else {
13071 struct pci_dev *bridge = NULL;
13072
13073 do {
13074 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13075 PCI_DEVICE_ID_SERVERWORKS_EPB,
13076 bridge);
13077 if (bridge && bridge->subordinate &&
13078 (bridge->subordinate->number <=
13079 tp->pdev->bus->number) &&
13080 (bridge->subordinate->subordinate >=
13081 tp->pdev->bus->number)) {
13082 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13083 pci_dev_put(bridge);
13084 break;
13085 }
13086 } while (bridge);
13087 }
13088
13089 /* Initialize misc host control in PCI block. */
13090 tp->misc_host_ctrl |= (misc_ctrl_reg &
13091 MISC_HOST_CTRL_CHIPREV);
13092 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13093 tp->misc_host_ctrl);
13094
13095 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13096 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13097 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13098 tp->pdev_peer = tg3_find_peer(tp);
13099
13100 /* Intentionally exclude ASIC_REV_5906 */
13101 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13102 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13103 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13104 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13105 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13106 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13107 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13108 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13109 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13110
13111 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13112 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13113 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13114 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13115 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13116 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13117
13118 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13119 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13120 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13121
13122 /* 5700 B0 chips do not support checksumming correctly due
13123 * to hardware bugs.
13124 */
13125 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13126 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13127 else {
13128 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13129 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13130 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13131 tp->dev->features |= NETIF_F_IPV6_CSUM;
13132 }
13133
13134 /* Determine TSO capabilities */
13135 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13136 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13137 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13138 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13139 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13140 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13141 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13142 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13143 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13144 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13145 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13146 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13147 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13148 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13149 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13150 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13151 tp->fw_needed = FIRMWARE_TG3TSO5;
13152 else
13153 tp->fw_needed = FIRMWARE_TG3TSO;
13154 }
13155
13156 tp->irq_max = 1;
13157
13158 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13159 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13160 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13161 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13162 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13163 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13164 tp->pdev_peer == tp->pdev))
13165 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13166
13167 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13168 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13169 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13170 }
13171
13172 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13173 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13174 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13175 tp->irq_max = TG3_IRQ_MAX_VECS;
13176 }
13177 }
13178
13179 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13180 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13181 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13182 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13183 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13184 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13185 }
13186
13187 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13188 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13189 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13190
13191 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13192 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13193 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13194 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13195
13196 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13197 &pci_state_reg);
13198
13199 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13200 if (tp->pcie_cap != 0) {
13201 u16 lnkctl;
13202
13203 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13204
13205 pcie_set_readrq(tp->pdev, 4096);
13206
13207 pci_read_config_word(tp->pdev,
13208 tp->pcie_cap + PCI_EXP_LNKCTL,
13209 &lnkctl);
13210 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13211 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13212 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13213 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13214 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13215 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13216 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13217 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13218 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13219 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13220 }
13221 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13222 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13223 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13224 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13225 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13226 if (!tp->pcix_cap) {
13227 pr_err("Cannot find PCI-X capability, aborting\n");
13228 return -EIO;
13229 }
13230
13231 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13232 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13233 }
13234
13235 /* If we have an AMD 762 or VIA K8T800 chipset, write
13236 * reordering to the mailbox registers done by the host
13237 * controller can cause major troubles. We read back from
13238 * every mailbox register write to force the writes to be
13239 * posted to the chip in order.
13240 */
13241 if (pci_dev_present(write_reorder_chipsets) &&
13242 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13243 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13244
13245 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13246 &tp->pci_cacheline_sz);
13247 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13248 &tp->pci_lat_timer);
13249 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13250 tp->pci_lat_timer < 64) {
13251 tp->pci_lat_timer = 64;
13252 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13253 tp->pci_lat_timer);
13254 }
13255
13256 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13257 /* 5700 BX chips need to have their TX producer index
13258 * mailboxes written twice to workaround a bug.
13259 */
13260 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13261
13262 /* If we are in PCI-X mode, enable register write workaround.
13263 *
13264 * The workaround is to use indirect register accesses
13265 * for all chip writes not to mailbox registers.
13266 */
13267 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13268 u32 pm_reg;
13269
13270 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13271
13272 /* The chip can have it's power management PCI config
13273 * space registers clobbered due to this bug.
13274 * So explicitly force the chip into D0 here.
13275 */
13276 pci_read_config_dword(tp->pdev,
13277 tp->pm_cap + PCI_PM_CTRL,
13278 &pm_reg);
13279 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13280 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13281 pci_write_config_dword(tp->pdev,
13282 tp->pm_cap + PCI_PM_CTRL,
13283 pm_reg);
13284
13285 /* Also, force SERR#/PERR# in PCI command. */
13286 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13287 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13288 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13289 }
13290 }
13291
13292 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13293 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13294 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13295 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13296
13297 /* Chip-specific fixup from Broadcom driver */
13298 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13299 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13300 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13301 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13302 }
13303
13304 /* Default fast path register access methods */
13305 tp->read32 = tg3_read32;
13306 tp->write32 = tg3_write32;
13307 tp->read32_mbox = tg3_read32;
13308 tp->write32_mbox = tg3_write32;
13309 tp->write32_tx_mbox = tg3_write32;
13310 tp->write32_rx_mbox = tg3_write32;
13311
13312 /* Various workaround register access methods */
13313 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13314 tp->write32 = tg3_write_indirect_reg32;
13315 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13316 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13317 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13318 /*
13319 * Back to back register writes can cause problems on these
13320 * chips, the workaround is to read back all reg writes
13321 * except those to mailbox regs.
13322 *
13323 * See tg3_write_indirect_reg32().
13324 */
13325 tp->write32 = tg3_write_flush_reg32;
13326 }
13327
13328 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13329 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13330 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13331 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13332 tp->write32_rx_mbox = tg3_write_flush_reg32;
13333 }
13334
13335 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13336 tp->read32 = tg3_read_indirect_reg32;
13337 tp->write32 = tg3_write_indirect_reg32;
13338 tp->read32_mbox = tg3_read_indirect_mbox;
13339 tp->write32_mbox = tg3_write_indirect_mbox;
13340 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13341 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13342
13343 iounmap(tp->regs);
13344 tp->regs = NULL;
13345
13346 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13347 pci_cmd &= ~PCI_COMMAND_MEMORY;
13348 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13349 }
13350 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13351 tp->read32_mbox = tg3_read32_mbox_5906;
13352 tp->write32_mbox = tg3_write32_mbox_5906;
13353 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13354 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13355 }
13356
13357 if (tp->write32 == tg3_write_indirect_reg32 ||
13358 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13359 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13360 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13361 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13362
13363 /* Get eeprom hw config before calling tg3_set_power_state().
13364 * In particular, the TG3_FLG2_IS_NIC flag must be
13365 * determined before calling tg3_set_power_state() so that
13366 * we know whether or not to switch out of Vaux power.
13367 * When the flag is set, it means that GPIO1 is used for eeprom
13368 * write protect and also implies that it is a LOM where GPIOs
13369 * are not used to switch power.
13370 */
13371 tg3_get_eeprom_hw_cfg(tp);
13372
13373 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13374 /* Allow reads and writes to the
13375 * APE register and memory space.
13376 */
13377 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13378 PCISTATE_ALLOW_APE_SHMEM_WR;
13379 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13380 pci_state_reg);
13381 }
13382
13383 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13384 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13385 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13386 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13387 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13388 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13389 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13390
13391 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13392 * GPIO1 driven high will bring 5700's external PHY out of reset.
13393 * It is also used as eeprom write protect on LOMs.
13394 */
13395 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13396 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13397 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13398 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13399 GRC_LCLCTRL_GPIO_OUTPUT1);
13400 /* Unused GPIO3 must be driven as output on 5752 because there
13401 * are no pull-up resistors on unused GPIO pins.
13402 */
13403 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13404 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13405
13406 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13407 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13408 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13409 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13410
13411 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13412 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13413 /* Turn off the debug UART. */
13414 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13415 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13416 /* Keep VMain power. */
13417 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13418 GRC_LCLCTRL_GPIO_OUTPUT0;
13419 }
13420
13421 /* Force the chip into D0. */
13422 err = tg3_set_power_state(tp, PCI_D0);
13423 if (err) {
13424 pr_err("(%s) transition to D0 failed\n", pci_name(tp->pdev));
13425 return err;
13426 }
13427
13428 /* Derive initial jumbo mode from MTU assigned in
13429 * ether_setup() via the alloc_etherdev() call
13430 */
13431 if (tp->dev->mtu > ETH_DATA_LEN &&
13432 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13433 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13434
13435 /* Determine WakeOnLan speed to use. */
13436 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13437 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13438 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13439 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13440 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13441 } else {
13442 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13443 }
13444
13445 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13446 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13447
13448 /* A few boards don't want Ethernet@WireSpeed phy feature */
13449 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13450 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13451 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13452 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13453 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13454 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13455 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13456
13457 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13458 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13459 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13460 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13461 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13462
13463 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13464 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13465 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13466 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13467 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13468 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13469 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13470 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13471 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13472 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13473 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13474 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13475 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13476 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13477 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13478 } else
13479 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13480 }
13481
13482 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13483 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13484 tp->phy_otp = tg3_read_otp_phycfg(tp);
13485 if (tp->phy_otp == 0)
13486 tp->phy_otp = TG3_OTP_DEFAULT;
13487 }
13488
13489 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13490 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13491 else
13492 tp->mi_mode = MAC_MI_MODE_BASE;
13493
13494 tp->coalesce_mode = 0;
13495 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13496 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13497 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13498
13499 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13500 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13501 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13502
13503 err = tg3_mdio_init(tp);
13504 if (err)
13505 return err;
13506
13507 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13508 (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13509 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13510 return -ENOTSUPP;
13511
13512 /* Initialize data/descriptor byte/word swapping. */
13513 val = tr32(GRC_MODE);
13514 val &= GRC_MODE_HOST_STACKUP;
13515 tw32(GRC_MODE, val | tp->grc_mode);
13516
13517 tg3_switch_clocks(tp);
13518
13519 /* Clear this out for sanity. */
13520 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13521
13522 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13523 &pci_state_reg);
13524 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13525 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13526 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13527
13528 if (chiprevid == CHIPREV_ID_5701_A0 ||
13529 chiprevid == CHIPREV_ID_5701_B0 ||
13530 chiprevid == CHIPREV_ID_5701_B2 ||
13531 chiprevid == CHIPREV_ID_5701_B5) {
13532 void __iomem *sram_base;
13533
13534 /* Write some dummy words into the SRAM status block
13535 * area, see if it reads back correctly. If the return
13536 * value is bad, force enable the PCIX workaround.
13537 */
13538 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13539
13540 writel(0x00000000, sram_base);
13541 writel(0x00000000, sram_base + 4);
13542 writel(0xffffffff, sram_base + 4);
13543 if (readl(sram_base) != 0x00000000)
13544 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13545 }
13546 }
13547
13548 udelay(50);
13549 tg3_nvram_init(tp);
13550
13551 grc_misc_cfg = tr32(GRC_MISC_CFG);
13552 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13553
13554 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13555 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13556 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13557 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13558
13559 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13560 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13561 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13562 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13563 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13564 HOSTCC_MODE_CLRTICK_TXBD);
13565
13566 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13567 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13568 tp->misc_host_ctrl);
13569 }
13570
13571 /* Preserve the APE MAC_MODE bits */
13572 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13573 tp->mac_mode = tr32(MAC_MODE) |
13574 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13575 else
13576 tp->mac_mode = TG3_DEF_MAC_MODE;
13577
13578 /* these are limited to 10/100 only */
13579 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13580 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13581 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13582 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13583 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13584 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13585 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13586 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13587 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13588 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13589 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13590 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13591 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13592 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13593 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13594 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13595
13596 err = tg3_phy_probe(tp);
13597 if (err) {
13598 pr_err("(%s) phy probe failed, err %d\n",
13599 pci_name(tp->pdev), err);
13600 /* ... but do not return immediately ... */
13601 tg3_mdio_fini(tp);
13602 }
13603
13604 tg3_read_partno(tp);
13605 tg3_read_fw_ver(tp);
13606
13607 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13608 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13609 } else {
13610 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13611 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13612 else
13613 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13614 }
13615
13616 /* 5700 {AX,BX} chips have a broken status block link
13617 * change bit implementation, so we must use the
13618 * status register in those cases.
13619 */
13620 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13621 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13622 else
13623 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13624
13625 /* The led_ctrl is set during tg3_phy_probe, here we might
13626 * have to force the link status polling mechanism based
13627 * upon subsystem IDs.
13628 */
13629 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13630 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13631 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13632 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13633 TG3_FLAG_USE_LINKCHG_REG);
13634 }
13635
13636 /* For all SERDES we poll the MAC status register. */
13637 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13638 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13639 else
13640 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13641
13642 tp->rx_offset = NET_IP_ALIGN;
13643 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13644 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13645 tp->rx_offset = 0;
13646
13647 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13648
13649 /* Increment the rx prod index on the rx std ring by at most
13650 * 8 for these chips to workaround hw errata.
13651 */
13652 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13653 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13654 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13655 tp->rx_std_max_post = 8;
13656
13657 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13658 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13659 PCIE_PWR_MGMT_L1_THRESH_MSK;
13660
13661 return err;
13662 }
13663
13664 #ifdef CONFIG_SPARC
13665 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13666 {
13667 struct net_device *dev = tp->dev;
13668 struct pci_dev *pdev = tp->pdev;
13669 struct device_node *dp = pci_device_to_OF_node(pdev);
13670 const unsigned char *addr;
13671 int len;
13672
13673 addr = of_get_property(dp, "local-mac-address", &len);
13674 if (addr && len == 6) {
13675 memcpy(dev->dev_addr, addr, 6);
13676 memcpy(dev->perm_addr, dev->dev_addr, 6);
13677 return 0;
13678 }
13679 return -ENODEV;
13680 }
13681
13682 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13683 {
13684 struct net_device *dev = tp->dev;
13685
13686 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13687 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13688 return 0;
13689 }
13690 #endif
13691
13692 static int __devinit tg3_get_device_address(struct tg3 *tp)
13693 {
13694 struct net_device *dev = tp->dev;
13695 u32 hi, lo, mac_offset;
13696 int addr_ok = 0;
13697
13698 #ifdef CONFIG_SPARC
13699 if (!tg3_get_macaddr_sparc(tp))
13700 return 0;
13701 #endif
13702
13703 mac_offset = 0x7c;
13704 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13705 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13706 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13707 mac_offset = 0xcc;
13708 if (tg3_nvram_lock(tp))
13709 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13710 else
13711 tg3_nvram_unlock(tp);
13712 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13713 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13714 mac_offset = 0xcc;
13715 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13716 mac_offset = 0x10;
13717
13718 /* First try to get it from MAC address mailbox. */
13719 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13720 if ((hi >> 16) == 0x484b) {
13721 dev->dev_addr[0] = (hi >> 8) & 0xff;
13722 dev->dev_addr[1] = (hi >> 0) & 0xff;
13723
13724 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13725 dev->dev_addr[2] = (lo >> 24) & 0xff;
13726 dev->dev_addr[3] = (lo >> 16) & 0xff;
13727 dev->dev_addr[4] = (lo >> 8) & 0xff;
13728 dev->dev_addr[5] = (lo >> 0) & 0xff;
13729
13730 /* Some old bootcode may report a 0 MAC address in SRAM */
13731 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13732 }
13733 if (!addr_ok) {
13734 /* Next, try NVRAM. */
13735 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13736 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13737 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13738 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13739 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13740 }
13741 /* Finally just fetch it out of the MAC control regs. */
13742 else {
13743 hi = tr32(MAC_ADDR_0_HIGH);
13744 lo = tr32(MAC_ADDR_0_LOW);
13745
13746 dev->dev_addr[5] = lo & 0xff;
13747 dev->dev_addr[4] = (lo >> 8) & 0xff;
13748 dev->dev_addr[3] = (lo >> 16) & 0xff;
13749 dev->dev_addr[2] = (lo >> 24) & 0xff;
13750 dev->dev_addr[1] = hi & 0xff;
13751 dev->dev_addr[0] = (hi >> 8) & 0xff;
13752 }
13753 }
13754
13755 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13756 #ifdef CONFIG_SPARC
13757 if (!tg3_get_default_macaddr_sparc(tp))
13758 return 0;
13759 #endif
13760 return -EINVAL;
13761 }
13762 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13763 return 0;
13764 }
13765
13766 #define BOUNDARY_SINGLE_CACHELINE 1
13767 #define BOUNDARY_MULTI_CACHELINE 2
13768
13769 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13770 {
13771 int cacheline_size;
13772 u8 byte;
13773 int goal;
13774
13775 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13776 if (byte == 0)
13777 cacheline_size = 1024;
13778 else
13779 cacheline_size = (int) byte * 4;
13780
13781 /* On 5703 and later chips, the boundary bits have no
13782 * effect.
13783 */
13784 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13785 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13786 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13787 goto out;
13788
13789 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13790 goal = BOUNDARY_MULTI_CACHELINE;
13791 #else
13792 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13793 goal = BOUNDARY_SINGLE_CACHELINE;
13794 #else
13795 goal = 0;
13796 #endif
13797 #endif
13798
13799 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13800 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13801 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13802 goto out;
13803 }
13804
13805 if (!goal)
13806 goto out;
13807
13808 /* PCI controllers on most RISC systems tend to disconnect
13809 * when a device tries to burst across a cache-line boundary.
13810 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13811 *
13812 * Unfortunately, for PCI-E there are only limited
13813 * write-side controls for this, and thus for reads
13814 * we will still get the disconnects. We'll also waste
13815 * these PCI cycles for both read and write for chips
13816 * other than 5700 and 5701 which do not implement the
13817 * boundary bits.
13818 */
13819 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13820 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13821 switch (cacheline_size) {
13822 case 16:
13823 case 32:
13824 case 64:
13825 case 128:
13826 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13827 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13828 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13829 } else {
13830 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13831 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13832 }
13833 break;
13834
13835 case 256:
13836 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13837 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13838 break;
13839
13840 default:
13841 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13842 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13843 break;
13844 }
13845 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13846 switch (cacheline_size) {
13847 case 16:
13848 case 32:
13849 case 64:
13850 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13851 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13852 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13853 break;
13854 }
13855 /* fallthrough */
13856 case 128:
13857 default:
13858 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13859 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13860 break;
13861 }
13862 } else {
13863 switch (cacheline_size) {
13864 case 16:
13865 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13866 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13867 DMA_RWCTRL_WRITE_BNDRY_16);
13868 break;
13869 }
13870 /* fallthrough */
13871 case 32:
13872 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13873 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13874 DMA_RWCTRL_WRITE_BNDRY_32);
13875 break;
13876 }
13877 /* fallthrough */
13878 case 64:
13879 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13880 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13881 DMA_RWCTRL_WRITE_BNDRY_64);
13882 break;
13883 }
13884 /* fallthrough */
13885 case 128:
13886 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13887 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13888 DMA_RWCTRL_WRITE_BNDRY_128);
13889 break;
13890 }
13891 /* fallthrough */
13892 case 256:
13893 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13894 DMA_RWCTRL_WRITE_BNDRY_256);
13895 break;
13896 case 512:
13897 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13898 DMA_RWCTRL_WRITE_BNDRY_512);
13899 break;
13900 case 1024:
13901 default:
13902 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13903 DMA_RWCTRL_WRITE_BNDRY_1024);
13904 break;
13905 }
13906 }
13907
13908 out:
13909 return val;
13910 }
13911
13912 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13913 {
13914 struct tg3_internal_buffer_desc test_desc;
13915 u32 sram_dma_descs;
13916 int i, ret;
13917
13918 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13919
13920 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13921 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13922 tw32(RDMAC_STATUS, 0);
13923 tw32(WDMAC_STATUS, 0);
13924
13925 tw32(BUFMGR_MODE, 0);
13926 tw32(FTQ_RESET, 0);
13927
13928 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13929 test_desc.addr_lo = buf_dma & 0xffffffff;
13930 test_desc.nic_mbuf = 0x00002100;
13931 test_desc.len = size;
13932
13933 /*
13934 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13935 * the *second* time the tg3 driver was getting loaded after an
13936 * initial scan.
13937 *
13938 * Broadcom tells me:
13939 * ...the DMA engine is connected to the GRC block and a DMA
13940 * reset may affect the GRC block in some unpredictable way...
13941 * The behavior of resets to individual blocks has not been tested.
13942 *
13943 * Broadcom noted the GRC reset will also reset all sub-components.
13944 */
13945 if (to_device) {
13946 test_desc.cqid_sqid = (13 << 8) | 2;
13947
13948 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13949 udelay(40);
13950 } else {
13951 test_desc.cqid_sqid = (16 << 8) | 7;
13952
13953 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13954 udelay(40);
13955 }
13956 test_desc.flags = 0x00000005;
13957
13958 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13959 u32 val;
13960
13961 val = *(((u32 *)&test_desc) + i);
13962 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13963 sram_dma_descs + (i * sizeof(u32)));
13964 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13965 }
13966 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13967
13968 if (to_device) {
13969 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13970 } else {
13971 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13972 }
13973
13974 ret = -ENODEV;
13975 for (i = 0; i < 40; i++) {
13976 u32 val;
13977
13978 if (to_device)
13979 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13980 else
13981 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13982 if ((val & 0xffff) == sram_dma_descs) {
13983 ret = 0;
13984 break;
13985 }
13986
13987 udelay(100);
13988 }
13989
13990 return ret;
13991 }
13992
13993 #define TEST_BUFFER_SIZE 0x2000
13994
13995 static int __devinit tg3_test_dma(struct tg3 *tp)
13996 {
13997 dma_addr_t buf_dma;
13998 u32 *buf, saved_dma_rwctrl;
13999 int ret = 0;
14000
14001 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
14002 if (!buf) {
14003 ret = -ENOMEM;
14004 goto out_nofree;
14005 }
14006
14007 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14008 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14009
14010 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14011
14012 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14013 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
14014 goto out;
14015
14016 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14017 /* DMA read watermark not used on PCIE */
14018 tp->dma_rwctrl |= 0x00180000;
14019 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14020 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14021 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14022 tp->dma_rwctrl |= 0x003f0000;
14023 else
14024 tp->dma_rwctrl |= 0x003f000f;
14025 } else {
14026 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14027 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14028 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14029 u32 read_water = 0x7;
14030
14031 /* If the 5704 is behind the EPB bridge, we can
14032 * do the less restrictive ONE_DMA workaround for
14033 * better performance.
14034 */
14035 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14036 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14037 tp->dma_rwctrl |= 0x8000;
14038 else if (ccval == 0x6 || ccval == 0x7)
14039 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14040
14041 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14042 read_water = 4;
14043 /* Set bit 23 to enable PCIX hw bug fix */
14044 tp->dma_rwctrl |=
14045 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14046 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14047 (1 << 23);
14048 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14049 /* 5780 always in PCIX mode */
14050 tp->dma_rwctrl |= 0x00144000;
14051 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14052 /* 5714 always in PCIX mode */
14053 tp->dma_rwctrl |= 0x00148000;
14054 } else {
14055 tp->dma_rwctrl |= 0x001b000f;
14056 }
14057 }
14058
14059 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14060 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14061 tp->dma_rwctrl &= 0xfffffff0;
14062
14063 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14064 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14065 /* Remove this if it causes problems for some boards. */
14066 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14067
14068 /* On 5700/5701 chips, we need to set this bit.
14069 * Otherwise the chip will issue cacheline transactions
14070 * to streamable DMA memory with not all the byte
14071 * enables turned on. This is an error on several
14072 * RISC PCI controllers, in particular sparc64.
14073 *
14074 * On 5703/5704 chips, this bit has been reassigned
14075 * a different meaning. In particular, it is used
14076 * on those chips to enable a PCI-X workaround.
14077 */
14078 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14079 }
14080
14081 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14082
14083 #if 0
14084 /* Unneeded, already done by tg3_get_invariants. */
14085 tg3_switch_clocks(tp);
14086 #endif
14087
14088 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14089 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14090 goto out;
14091
14092 /* It is best to perform DMA test with maximum write burst size
14093 * to expose the 5700/5701 write DMA bug.
14094 */
14095 saved_dma_rwctrl = tp->dma_rwctrl;
14096 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14097 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14098
14099 while (1) {
14100 u32 *p = buf, i;
14101
14102 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14103 p[i] = i;
14104
14105 /* Send the buffer to the chip. */
14106 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14107 if (ret) {
14108 pr_err("tg3_test_dma() Write the buffer failed %d\n",
14109 ret);
14110 break;
14111 }
14112
14113 #if 0
14114 /* validate data reached card RAM correctly. */
14115 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14116 u32 val;
14117 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14118 if (le32_to_cpu(val) != p[i]) {
14119 pr_err(" tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n",
14120 val, i);
14121 /* ret = -ENODEV here? */
14122 }
14123 p[i] = 0;
14124 }
14125 #endif
14126 /* Now read it back. */
14127 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14128 if (ret) {
14129 pr_err("tg3_test_dma() Read the buffer failed %d\n",
14130 ret);
14131
14132 break;
14133 }
14134
14135 /* Verify it. */
14136 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14137 if (p[i] == i)
14138 continue;
14139
14140 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14141 DMA_RWCTRL_WRITE_BNDRY_16) {
14142 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14143 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14144 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14145 break;
14146 } else {
14147 pr_err("tg3_test_dma() buffer corrupted on read back! (%d != %d)\n",
14148 p[i], i);
14149 ret = -ENODEV;
14150 goto out;
14151 }
14152 }
14153
14154 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14155 /* Success. */
14156 ret = 0;
14157 break;
14158 }
14159 }
14160 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14161 DMA_RWCTRL_WRITE_BNDRY_16) {
14162 static struct pci_device_id dma_wait_state_chipsets[] = {
14163 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14164 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14165 { },
14166 };
14167
14168 /* DMA test passed without adjusting DMA boundary,
14169 * now look for chipsets that are known to expose the
14170 * DMA bug without failing the test.
14171 */
14172 if (pci_dev_present(dma_wait_state_chipsets)) {
14173 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14174 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14175 }
14176 else
14177 /* Safe to use the calculated DMA boundary. */
14178 tp->dma_rwctrl = saved_dma_rwctrl;
14179
14180 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14181 }
14182
14183 out:
14184 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14185 out_nofree:
14186 return ret;
14187 }
14188
14189 static void __devinit tg3_init_link_config(struct tg3 *tp)
14190 {
14191 tp->link_config.advertising =
14192 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14193 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14194 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14195 ADVERTISED_Autoneg | ADVERTISED_MII);
14196 tp->link_config.speed = SPEED_INVALID;
14197 tp->link_config.duplex = DUPLEX_INVALID;
14198 tp->link_config.autoneg = AUTONEG_ENABLE;
14199 tp->link_config.active_speed = SPEED_INVALID;
14200 tp->link_config.active_duplex = DUPLEX_INVALID;
14201 tp->link_config.phy_is_low_power = 0;
14202 tp->link_config.orig_speed = SPEED_INVALID;
14203 tp->link_config.orig_duplex = DUPLEX_INVALID;
14204 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14205 }
14206
14207 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14208 {
14209 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14210 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14211 tp->bufmgr_config.mbuf_read_dma_low_water =
14212 DEFAULT_MB_RDMA_LOW_WATER_5705;
14213 tp->bufmgr_config.mbuf_mac_rx_low_water =
14214 DEFAULT_MB_MACRX_LOW_WATER_57765;
14215 tp->bufmgr_config.mbuf_high_water =
14216 DEFAULT_MB_HIGH_WATER_57765;
14217
14218 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14219 DEFAULT_MB_RDMA_LOW_WATER_5705;
14220 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14221 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14222 tp->bufmgr_config.mbuf_high_water_jumbo =
14223 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14224 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14225 tp->bufmgr_config.mbuf_read_dma_low_water =
14226 DEFAULT_MB_RDMA_LOW_WATER_5705;
14227 tp->bufmgr_config.mbuf_mac_rx_low_water =
14228 DEFAULT_MB_MACRX_LOW_WATER_5705;
14229 tp->bufmgr_config.mbuf_high_water =
14230 DEFAULT_MB_HIGH_WATER_5705;
14231 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14232 tp->bufmgr_config.mbuf_mac_rx_low_water =
14233 DEFAULT_MB_MACRX_LOW_WATER_5906;
14234 tp->bufmgr_config.mbuf_high_water =
14235 DEFAULT_MB_HIGH_WATER_5906;
14236 }
14237
14238 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14239 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14240 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14241 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14242 tp->bufmgr_config.mbuf_high_water_jumbo =
14243 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14244 } else {
14245 tp->bufmgr_config.mbuf_read_dma_low_water =
14246 DEFAULT_MB_RDMA_LOW_WATER;
14247 tp->bufmgr_config.mbuf_mac_rx_low_water =
14248 DEFAULT_MB_MACRX_LOW_WATER;
14249 tp->bufmgr_config.mbuf_high_water =
14250 DEFAULT_MB_HIGH_WATER;
14251
14252 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14253 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14254 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14255 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14256 tp->bufmgr_config.mbuf_high_water_jumbo =
14257 DEFAULT_MB_HIGH_WATER_JUMBO;
14258 }
14259
14260 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14261 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14262 }
14263
14264 static char * __devinit tg3_phy_string(struct tg3 *tp)
14265 {
14266 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14267 case TG3_PHY_ID_BCM5400: return "5400";
14268 case TG3_PHY_ID_BCM5401: return "5401";
14269 case TG3_PHY_ID_BCM5411: return "5411";
14270 case TG3_PHY_ID_BCM5701: return "5701";
14271 case TG3_PHY_ID_BCM5703: return "5703";
14272 case TG3_PHY_ID_BCM5704: return "5704";
14273 case TG3_PHY_ID_BCM5705: return "5705";
14274 case TG3_PHY_ID_BCM5750: return "5750";
14275 case TG3_PHY_ID_BCM5752: return "5752";
14276 case TG3_PHY_ID_BCM5714: return "5714";
14277 case TG3_PHY_ID_BCM5780: return "5780";
14278 case TG3_PHY_ID_BCM5755: return "5755";
14279 case TG3_PHY_ID_BCM5787: return "5787";
14280 case TG3_PHY_ID_BCM5784: return "5784";
14281 case TG3_PHY_ID_BCM5756: return "5722/5756";
14282 case TG3_PHY_ID_BCM5906: return "5906";
14283 case TG3_PHY_ID_BCM5761: return "5761";
14284 case TG3_PHY_ID_BCM5718C: return "5718C";
14285 case TG3_PHY_ID_BCM5718S: return "5718S";
14286 case TG3_PHY_ID_BCM57765: return "57765";
14287 case TG3_PHY_ID_BCM8002: return "8002/serdes";
14288 case 0: return "serdes";
14289 default: return "unknown";
14290 }
14291 }
14292
14293 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14294 {
14295 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14296 strcpy(str, "PCI Express");
14297 return str;
14298 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14299 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14300
14301 strcpy(str, "PCIX:");
14302
14303 if ((clock_ctrl == 7) ||
14304 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14305 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14306 strcat(str, "133MHz");
14307 else if (clock_ctrl == 0)
14308 strcat(str, "33MHz");
14309 else if (clock_ctrl == 2)
14310 strcat(str, "50MHz");
14311 else if (clock_ctrl == 4)
14312 strcat(str, "66MHz");
14313 else if (clock_ctrl == 6)
14314 strcat(str, "100MHz");
14315 } else {
14316 strcpy(str, "PCI:");
14317 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14318 strcat(str, "66MHz");
14319 else
14320 strcat(str, "33MHz");
14321 }
14322 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14323 strcat(str, ":32-bit");
14324 else
14325 strcat(str, ":64-bit");
14326 return str;
14327 }
14328
14329 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14330 {
14331 struct pci_dev *peer;
14332 unsigned int func, devnr = tp->pdev->devfn & ~7;
14333
14334 for (func = 0; func < 8; func++) {
14335 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14336 if (peer && peer != tp->pdev)
14337 break;
14338 pci_dev_put(peer);
14339 }
14340 /* 5704 can be configured in single-port mode, set peer to
14341 * tp->pdev in that case.
14342 */
14343 if (!peer) {
14344 peer = tp->pdev;
14345 return peer;
14346 }
14347
14348 /*
14349 * We don't need to keep the refcount elevated; there's no way
14350 * to remove one half of this device without removing the other
14351 */
14352 pci_dev_put(peer);
14353
14354 return peer;
14355 }
14356
14357 static void __devinit tg3_init_coal(struct tg3 *tp)
14358 {
14359 struct ethtool_coalesce *ec = &tp->coal;
14360
14361 memset(ec, 0, sizeof(*ec));
14362 ec->cmd = ETHTOOL_GCOALESCE;
14363 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14364 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14365 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14366 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14367 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14368 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14369 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14370 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14371 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14372
14373 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14374 HOSTCC_MODE_CLRTICK_TXBD)) {
14375 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14376 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14377 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14378 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14379 }
14380
14381 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14382 ec->rx_coalesce_usecs_irq = 0;
14383 ec->tx_coalesce_usecs_irq = 0;
14384 ec->stats_block_coalesce_usecs = 0;
14385 }
14386 }
14387
14388 static const struct net_device_ops tg3_netdev_ops = {
14389 .ndo_open = tg3_open,
14390 .ndo_stop = tg3_close,
14391 .ndo_start_xmit = tg3_start_xmit,
14392 .ndo_get_stats = tg3_get_stats,
14393 .ndo_validate_addr = eth_validate_addr,
14394 .ndo_set_multicast_list = tg3_set_rx_mode,
14395 .ndo_set_mac_address = tg3_set_mac_addr,
14396 .ndo_do_ioctl = tg3_ioctl,
14397 .ndo_tx_timeout = tg3_tx_timeout,
14398 .ndo_change_mtu = tg3_change_mtu,
14399 #if TG3_VLAN_TAG_USED
14400 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14401 #endif
14402 #ifdef CONFIG_NET_POLL_CONTROLLER
14403 .ndo_poll_controller = tg3_poll_controller,
14404 #endif
14405 };
14406
14407 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14408 .ndo_open = tg3_open,
14409 .ndo_stop = tg3_close,
14410 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14411 .ndo_get_stats = tg3_get_stats,
14412 .ndo_validate_addr = eth_validate_addr,
14413 .ndo_set_multicast_list = tg3_set_rx_mode,
14414 .ndo_set_mac_address = tg3_set_mac_addr,
14415 .ndo_do_ioctl = tg3_ioctl,
14416 .ndo_tx_timeout = tg3_tx_timeout,
14417 .ndo_change_mtu = tg3_change_mtu,
14418 #if TG3_VLAN_TAG_USED
14419 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14420 #endif
14421 #ifdef CONFIG_NET_POLL_CONTROLLER
14422 .ndo_poll_controller = tg3_poll_controller,
14423 #endif
14424 };
14425
14426 static int __devinit tg3_init_one(struct pci_dev *pdev,
14427 const struct pci_device_id *ent)
14428 {
14429 struct net_device *dev;
14430 struct tg3 *tp;
14431 int i, err, pm_cap;
14432 u32 sndmbx, rcvmbx, intmbx;
14433 char str[40];
14434 u64 dma_mask, persist_dma_mask;
14435
14436 printk_once(KERN_INFO "%s\n", version);
14437
14438 err = pci_enable_device(pdev);
14439 if (err) {
14440 pr_err("Cannot enable PCI device, aborting\n");
14441 return err;
14442 }
14443
14444 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14445 if (err) {
14446 pr_err("Cannot obtain PCI resources, aborting\n");
14447 goto err_out_disable_pdev;
14448 }
14449
14450 pci_set_master(pdev);
14451
14452 /* Find power-management capability. */
14453 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14454 if (pm_cap == 0) {
14455 pr_err("Cannot find PowerManagement capability, aborting\n");
14456 err = -EIO;
14457 goto err_out_free_res;
14458 }
14459
14460 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14461 if (!dev) {
14462 pr_err("Etherdev alloc failed, aborting\n");
14463 err = -ENOMEM;
14464 goto err_out_free_res;
14465 }
14466
14467 SET_NETDEV_DEV(dev, &pdev->dev);
14468
14469 #if TG3_VLAN_TAG_USED
14470 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14471 #endif
14472
14473 tp = netdev_priv(dev);
14474 tp->pdev = pdev;
14475 tp->dev = dev;
14476 tp->pm_cap = pm_cap;
14477 tp->rx_mode = TG3_DEF_RX_MODE;
14478 tp->tx_mode = TG3_DEF_TX_MODE;
14479
14480 if (tg3_debug > 0)
14481 tp->msg_enable = tg3_debug;
14482 else
14483 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14484
14485 /* The word/byte swap controls here control register access byte
14486 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14487 * setting below.
14488 */
14489 tp->misc_host_ctrl =
14490 MISC_HOST_CTRL_MASK_PCI_INT |
14491 MISC_HOST_CTRL_WORD_SWAP |
14492 MISC_HOST_CTRL_INDIR_ACCESS |
14493 MISC_HOST_CTRL_PCISTATE_RW;
14494
14495 /* The NONFRM (non-frame) byte/word swap controls take effect
14496 * on descriptor entries, anything which isn't packet data.
14497 *
14498 * The StrongARM chips on the board (one for tx, one for rx)
14499 * are running in big-endian mode.
14500 */
14501 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14502 GRC_MODE_WSWAP_NONFRM_DATA);
14503 #ifdef __BIG_ENDIAN
14504 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14505 #endif
14506 spin_lock_init(&tp->lock);
14507 spin_lock_init(&tp->indirect_lock);
14508 INIT_WORK(&tp->reset_task, tg3_reset_task);
14509
14510 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14511 if (!tp->regs) {
14512 netdev_err(dev, "Cannot map device registers, aborting\n");
14513 err = -ENOMEM;
14514 goto err_out_free_dev;
14515 }
14516
14517 tg3_init_link_config(tp);
14518
14519 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14520 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14521
14522 dev->ethtool_ops = &tg3_ethtool_ops;
14523 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14524 dev->irq = pdev->irq;
14525
14526 err = tg3_get_invariants(tp);
14527 if (err) {
14528 netdev_err(dev, "Problem fetching invariants of chip, aborting\n");
14529 goto err_out_iounmap;
14530 }
14531
14532 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14533 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14534 dev->netdev_ops = &tg3_netdev_ops;
14535 else
14536 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14537
14538
14539 /* The EPB bridge inside 5714, 5715, and 5780 and any
14540 * device behind the EPB cannot support DMA addresses > 40-bit.
14541 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14542 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14543 * do DMA address check in tg3_start_xmit().
14544 */
14545 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14546 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14547 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14548 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14549 #ifdef CONFIG_HIGHMEM
14550 dma_mask = DMA_BIT_MASK(64);
14551 #endif
14552 } else
14553 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14554
14555 /* Configure DMA attributes. */
14556 if (dma_mask > DMA_BIT_MASK(32)) {
14557 err = pci_set_dma_mask(pdev, dma_mask);
14558 if (!err) {
14559 dev->features |= NETIF_F_HIGHDMA;
14560 err = pci_set_consistent_dma_mask(pdev,
14561 persist_dma_mask);
14562 if (err < 0) {
14563 netdev_err(dev, "Unable to obtain 64 bit DMA for consistent allocations\n");
14564 goto err_out_iounmap;
14565 }
14566 }
14567 }
14568 if (err || dma_mask == DMA_BIT_MASK(32)) {
14569 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14570 if (err) {
14571 netdev_err(dev, "No usable DMA configuration, aborting\n");
14572 goto err_out_iounmap;
14573 }
14574 }
14575
14576 tg3_init_bufmgr_config(tp);
14577
14578 /* Selectively allow TSO based on operating conditions */
14579 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14580 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14581 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14582 else {
14583 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14584 tp->fw_needed = NULL;
14585 }
14586
14587 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14588 tp->fw_needed = FIRMWARE_TG3;
14589
14590 /* TSO is on by default on chips that support hardware TSO.
14591 * Firmware TSO on older chips gives lower performance, so it
14592 * is off by default, but can be enabled using ethtool.
14593 */
14594 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14595 (dev->features & NETIF_F_IP_CSUM))
14596 dev->features |= NETIF_F_TSO;
14597
14598 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14599 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14600 if (dev->features & NETIF_F_IPV6_CSUM)
14601 dev->features |= NETIF_F_TSO6;
14602 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14603 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14604 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14605 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14606 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14607 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14608 dev->features |= NETIF_F_TSO_ECN;
14609 }
14610
14611 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14612 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14613 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14614 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14615 tp->rx_pending = 63;
14616 }
14617
14618 err = tg3_get_device_address(tp);
14619 if (err) {
14620 netdev_err(dev, "Could not obtain valid ethernet address, aborting\n");
14621 goto err_out_iounmap;
14622 }
14623
14624 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14625 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14626 if (!tp->aperegs) {
14627 netdev_err(dev, "Cannot map APE registers, aborting\n");
14628 err = -ENOMEM;
14629 goto err_out_iounmap;
14630 }
14631
14632 tg3_ape_lock_init(tp);
14633
14634 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14635 tg3_read_dash_ver(tp);
14636 }
14637
14638 /*
14639 * Reset chip in case UNDI or EFI driver did not shutdown
14640 * DMA self test will enable WDMAC and we'll see (spurious)
14641 * pending DMA on the PCI bus at that point.
14642 */
14643 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14644 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14645 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14646 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14647 }
14648
14649 err = tg3_test_dma(tp);
14650 if (err) {
14651 netdev_err(dev, "DMA engine test failed, aborting\n");
14652 goto err_out_apeunmap;
14653 }
14654
14655 /* flow control autonegotiation is default behavior */
14656 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14657 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14658
14659 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14660 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14661 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14662 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14663 struct tg3_napi *tnapi = &tp->napi[i];
14664
14665 tnapi->tp = tp;
14666 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14667
14668 tnapi->int_mbox = intmbx;
14669 if (i < 4)
14670 intmbx += 0x8;
14671 else
14672 intmbx += 0x4;
14673
14674 tnapi->consmbox = rcvmbx;
14675 tnapi->prodmbox = sndmbx;
14676
14677 if (i) {
14678 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14679 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14680 } else {
14681 tnapi->coal_now = HOSTCC_MODE_NOW;
14682 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14683 }
14684
14685 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14686 break;
14687
14688 /*
14689 * If we support MSIX, we'll be using RSS. If we're using
14690 * RSS, the first vector only handles link interrupts and the
14691 * remaining vectors handle rx and tx interrupts. Reuse the
14692 * mailbox values for the next iteration. The values we setup
14693 * above are still useful for the single vectored mode.
14694 */
14695 if (!i)
14696 continue;
14697
14698 rcvmbx += 0x8;
14699
14700 if (sndmbx & 0x4)
14701 sndmbx -= 0x4;
14702 else
14703 sndmbx += 0xc;
14704 }
14705
14706 tg3_init_coal(tp);
14707
14708 pci_set_drvdata(pdev, dev);
14709
14710 err = register_netdev(dev);
14711 if (err) {
14712 netdev_err(dev, "Cannot register net device, aborting\n");
14713 goto err_out_apeunmap;
14714 }
14715
14716 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14717 tp->board_part_number,
14718 tp->pci_chip_rev_id,
14719 tg3_bus_string(tp, str),
14720 dev->dev_addr);
14721
14722 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14723 struct phy_device *phydev;
14724 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14725 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14726 phydev->drv->name, dev_name(&phydev->dev));
14727 } else
14728 netdev_info(dev, "attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14729 tg3_phy_string(tp),
14730 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14731 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14732 "10/100/1000Base-T")),
14733 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14734
14735 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14736 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14737 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14738 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14739 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14740 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14741 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14742 tp->dma_rwctrl,
14743 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14744 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14745
14746 return 0;
14747
14748 err_out_apeunmap:
14749 if (tp->aperegs) {
14750 iounmap(tp->aperegs);
14751 tp->aperegs = NULL;
14752 }
14753
14754 err_out_iounmap:
14755 if (tp->regs) {
14756 iounmap(tp->regs);
14757 tp->regs = NULL;
14758 }
14759
14760 err_out_free_dev:
14761 free_netdev(dev);
14762
14763 err_out_free_res:
14764 pci_release_regions(pdev);
14765
14766 err_out_disable_pdev:
14767 pci_disable_device(pdev);
14768 pci_set_drvdata(pdev, NULL);
14769 return err;
14770 }
14771
14772 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14773 {
14774 struct net_device *dev = pci_get_drvdata(pdev);
14775
14776 if (dev) {
14777 struct tg3 *tp = netdev_priv(dev);
14778
14779 if (tp->fw)
14780 release_firmware(tp->fw);
14781
14782 flush_scheduled_work();
14783
14784 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14785 tg3_phy_fini(tp);
14786 tg3_mdio_fini(tp);
14787 }
14788
14789 unregister_netdev(dev);
14790 if (tp->aperegs) {
14791 iounmap(tp->aperegs);
14792 tp->aperegs = NULL;
14793 }
14794 if (tp->regs) {
14795 iounmap(tp->regs);
14796 tp->regs = NULL;
14797 }
14798 free_netdev(dev);
14799 pci_release_regions(pdev);
14800 pci_disable_device(pdev);
14801 pci_set_drvdata(pdev, NULL);
14802 }
14803 }
14804
14805 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14806 {
14807 struct net_device *dev = pci_get_drvdata(pdev);
14808 struct tg3 *tp = netdev_priv(dev);
14809 pci_power_t target_state;
14810 int err;
14811
14812 /* PCI register 4 needs to be saved whether netif_running() or not.
14813 * MSI address and data need to be saved if using MSI and
14814 * netif_running().
14815 */
14816 pci_save_state(pdev);
14817
14818 if (!netif_running(dev))
14819 return 0;
14820
14821 flush_scheduled_work();
14822 tg3_phy_stop(tp);
14823 tg3_netif_stop(tp);
14824
14825 del_timer_sync(&tp->timer);
14826
14827 tg3_full_lock(tp, 1);
14828 tg3_disable_ints(tp);
14829 tg3_full_unlock(tp);
14830
14831 netif_device_detach(dev);
14832
14833 tg3_full_lock(tp, 0);
14834 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14835 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14836 tg3_full_unlock(tp);
14837
14838 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14839
14840 err = tg3_set_power_state(tp, target_state);
14841 if (err) {
14842 int err2;
14843
14844 tg3_full_lock(tp, 0);
14845
14846 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14847 err2 = tg3_restart_hw(tp, 1);
14848 if (err2)
14849 goto out;
14850
14851 tp->timer.expires = jiffies + tp->timer_offset;
14852 add_timer(&tp->timer);
14853
14854 netif_device_attach(dev);
14855 tg3_netif_start(tp);
14856
14857 out:
14858 tg3_full_unlock(tp);
14859
14860 if (!err2)
14861 tg3_phy_start(tp);
14862 }
14863
14864 return err;
14865 }
14866
14867 static int tg3_resume(struct pci_dev *pdev)
14868 {
14869 struct net_device *dev = pci_get_drvdata(pdev);
14870 struct tg3 *tp = netdev_priv(dev);
14871 int err;
14872
14873 pci_restore_state(tp->pdev);
14874
14875 if (!netif_running(dev))
14876 return 0;
14877
14878 err = tg3_set_power_state(tp, PCI_D0);
14879 if (err)
14880 return err;
14881
14882 netif_device_attach(dev);
14883
14884 tg3_full_lock(tp, 0);
14885
14886 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14887 err = tg3_restart_hw(tp, 1);
14888 if (err)
14889 goto out;
14890
14891 tp->timer.expires = jiffies + tp->timer_offset;
14892 add_timer(&tp->timer);
14893
14894 tg3_netif_start(tp);
14895
14896 out:
14897 tg3_full_unlock(tp);
14898
14899 if (!err)
14900 tg3_phy_start(tp);
14901
14902 return err;
14903 }
14904
14905 static struct pci_driver tg3_driver = {
14906 .name = DRV_MODULE_NAME,
14907 .id_table = tg3_pci_tbl,
14908 .probe = tg3_init_one,
14909 .remove = __devexit_p(tg3_remove_one),
14910 .suspend = tg3_suspend,
14911 .resume = tg3_resume
14912 };
14913
14914 static int __init tg3_init(void)
14915 {
14916 return pci_register_driver(&tg3_driver);
14917 }
14918
14919 static void __exit tg3_cleanup(void)
14920 {
14921 pci_unregister_driver(&tg3_driver);
14922 }
14923
14924 module_init(tg3_init);
14925 module_exit(tg3_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree