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ALSA: hda - Add quirk for Dell Vostro 1220
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / i2c / busses / i2c-i801.c
blob299b918455a36999242027de9312fe98ce811db7
1 /*
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 /*
23 Supports the following Intel I/O Controller Hubs (ICH):
24
25 I/O Block I2C
26 region SMBus Block proc. block
27 Chip name PCI ID size PEC buffer call read
28 ----------------------------------------------------------------------
29 82801AA (ICH) 0x2413 16 no no no no
30 82801AB (ICH0) 0x2423 16 no no no no
31 82801BA (ICH2) 0x2443 16 no no no no
32 82801CA (ICH3) 0x2483 32 soft no no no
33 82801DB (ICH4) 0x24c3 32 hard yes no no
34 82801E (ICH5) 0x24d3 32 hard yes yes yes
35 6300ESB 0x25a4 32 hard yes yes yes
36 82801F (ICH6) 0x266a 32 hard yes yes yes
37 6310ESB/6320ESB 0x269b 32 hard yes yes yes
38 82801G (ICH7) 0x27da 32 hard yes yes yes
39 82801H (ICH8) 0x283e 32 hard yes yes yes
40 82801I (ICH9) 0x2930 32 hard yes yes yes
41 Tolapai 0x5032 32 hard yes yes yes
42 ICH10 0x3a30 32 hard yes yes yes
43 ICH10 0x3a60 32 hard yes yes yes
44 3400/5 Series (PCH) 0x3b30 32 hard yes yes yes
45 Cougar Point (PCH) 0x1c22 32 hard yes yes yes
46
47 Features supported by this driver:
48 Software PEC no
49 Hardware PEC yes
50 Block buffer yes
51 Block process call transaction no
52 I2C block read transaction yes (doesn't use the block buffer)
53
54 See the file Documentation/i2c/busses/i2c-i801 for details.
55 */
56
57 /* Note: we assume there can only be one I801, with one SMBus interface */
58
59 #include <linux/module.h>
60 #include <linux/pci.h>
61 #include <linux/kernel.h>
62 #include <linux/stddef.h>
63 #include <linux/delay.h>
64 #include <linux/ioport.h>
65 #include <linux/init.h>
66 #include <linux/i2c.h>
67 #include <linux/acpi.h>
68 #include <linux/io.h>
69 #include <linux/dmi.h>
70
71 /* I801 SMBus address offsets */
72 #define SMBHSTSTS (0 + i801_smba)
73 #define SMBHSTCNT (2 + i801_smba)
74 #define SMBHSTCMD (3 + i801_smba)
75 #define SMBHSTADD (4 + i801_smba)
76 #define SMBHSTDAT0 (5 + i801_smba)
77 #define SMBHSTDAT1 (6 + i801_smba)
78 #define SMBBLKDAT (7 + i801_smba)
79 #define SMBPEC (8 + i801_smba) /* ICH3 and later */
80 #define SMBAUXSTS (12 + i801_smba) /* ICH4 and later */
81 #define SMBAUXCTL (13 + i801_smba) /* ICH4 and later */
82
83 /* PCI Address Constants */
84 #define SMBBAR 4
85 #define SMBHSTCFG 0x040
86
87 /* Host configuration bits for SMBHSTCFG */
88 #define SMBHSTCFG_HST_EN 1
89 #define SMBHSTCFG_SMB_SMI_EN 2
90 #define SMBHSTCFG_I2C_EN 4
91
92 /* Auxillary control register bits, ICH4+ only */
93 #define SMBAUXCTL_CRC 1
94 #define SMBAUXCTL_E32B 2
95
96 /* kill bit for SMBHSTCNT */
97 #define SMBHSTCNT_KILL 2
98
99 /* Other settings */
100 #define MAX_TIMEOUT 100
101 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
102
103 /* I801 command constants */
104 #define I801_QUICK 0x00
105 #define I801_BYTE 0x04
106 #define I801_BYTE_DATA 0x08
107 #define I801_WORD_DATA 0x0C
108 #define I801_PROC_CALL 0x10 /* unimplemented */
109 #define I801_BLOCK_DATA 0x14
110 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
111 #define I801_BLOCK_LAST 0x34
112 #define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
113 #define I801_START 0x40
114 #define I801_PEC_EN 0x80 /* ICH3 and later */
115
116 /* I801 Hosts Status register bits */
117 #define SMBHSTSTS_BYTE_DONE 0x80
118 #define SMBHSTSTS_INUSE_STS 0x40
119 #define SMBHSTSTS_SMBALERT_STS 0x20
120 #define SMBHSTSTS_FAILED 0x10
121 #define SMBHSTSTS_BUS_ERR 0x08
122 #define SMBHSTSTS_DEV_ERR 0x04
123 #define SMBHSTSTS_INTR 0x02
124 #define SMBHSTSTS_HOST_BUSY 0x01
125
126 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
127 SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
128 SMBHSTSTS_INTR)
129
130 static unsigned long i801_smba;
131 static unsigned char i801_original_hstcfg;
132 static struct pci_driver i801_driver;
133 static struct pci_dev *I801_dev;
134
135 #define FEATURE_SMBUS_PEC (1 << 0)
136 #define FEATURE_BLOCK_BUFFER (1 << 1)
137 #define FEATURE_BLOCK_PROC (1 << 2)
138 #define FEATURE_I2C_BLOCK_READ (1 << 3)
139 static unsigned int i801_features;
140
141 /* Make sure the SMBus host is ready to start transmitting.
142 Return 0 if it is, -EBUSY if it is not. */
143 static int i801_check_pre(void)
144 {
145 int status;
146
147 status = inb_p(SMBHSTSTS);
148 if (status & SMBHSTSTS_HOST_BUSY) {
149 dev_err(&I801_dev->dev, "SMBus is busy, can't use it!\n");
150 return -EBUSY;
151 }
152
153 status &= STATUS_FLAGS;
154 if (status) {
155 dev_dbg(&I801_dev->dev, "Clearing status flags (%02x)\n",
156 status);
157 outb_p(status, SMBHSTSTS);
158 status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
159 if (status) {
160 dev_err(&I801_dev->dev,
161 "Failed clearing status flags (%02x)\n",
162 status);
163 return -EBUSY;
164 }
165 }
166
167 return 0;
168 }
169
170 /* Convert the status register to an error code, and clear it. */
171 static int i801_check_post(int status, int timeout)
172 {
173 int result = 0;
174
175 /* If the SMBus is still busy, we give up */
176 if (timeout) {
177 dev_err(&I801_dev->dev, "Transaction timeout\n");
178 /* try to stop the current command */
179 dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
180 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
181 msleep(1);
182 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
183
184 /* Check if it worked */
185 status = inb_p(SMBHSTSTS);
186 if ((status & SMBHSTSTS_HOST_BUSY) ||
187 !(status & SMBHSTSTS_FAILED))
188 dev_err(&I801_dev->dev,
189 "Failed terminating the transaction\n");
190 outb_p(STATUS_FLAGS, SMBHSTSTS);
191 return -ETIMEDOUT;
192 }
193
194 if (status & SMBHSTSTS_FAILED) {
195 result = -EIO;
196 dev_err(&I801_dev->dev, "Transaction failed\n");
197 }
198 if (status & SMBHSTSTS_DEV_ERR) {
199 result = -ENXIO;
200 dev_dbg(&I801_dev->dev, "No response\n");
201 }
202 if (status & SMBHSTSTS_BUS_ERR) {
203 result = -EAGAIN;
204 dev_dbg(&I801_dev->dev, "Lost arbitration\n");
205 }
206
207 if (result) {
208 /* Clear error flags */
209 outb_p(status & STATUS_FLAGS, SMBHSTSTS);
210 status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
211 if (status) {
212 dev_warn(&I801_dev->dev, "Failed clearing status "
213 "flags at end of transaction (%02x)\n",
214 status);
215 }
216 }
217
218 return result;
219 }
220
221 static int i801_transaction(int xact)
222 {
223 int status;
224 int result;
225 int timeout = 0;
226
227 result = i801_check_pre();
228 if (result < 0)
229 return result;
230
231 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
232 * INTREN, SMBSCMD are passed in xact */
233 outb_p(xact | I801_START, SMBHSTCNT);
234
235 /* We will always wait for a fraction of a second! */
236 do {
237 msleep(1);
238 status = inb_p(SMBHSTSTS);
239 } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
240
241 result = i801_check_post(status, timeout > MAX_TIMEOUT);
242 if (result < 0)
243 return result;
244
245 outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
246 return 0;
247 }
248
249 /* wait for INTR bit as advised by Intel */
250 static void i801_wait_hwpec(void)
251 {
252 int timeout = 0;
253 int status;
254
255 do {
256 msleep(1);
257 status = inb_p(SMBHSTSTS);
258 } while ((!(status & SMBHSTSTS_INTR))
259 && (timeout++ < MAX_TIMEOUT));
260
261 if (timeout > MAX_TIMEOUT)
262 dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
263
264 outb_p(status, SMBHSTSTS);
265 }
266
267 static int i801_block_transaction_by_block(union i2c_smbus_data *data,
268 char read_write, int hwpec)
269 {
270 int i, len;
271 int status;
272
273 inb_p(SMBHSTCNT); /* reset the data buffer index */
274
275 /* Use 32-byte buffer to process this transaction */
276 if (read_write == I2C_SMBUS_WRITE) {
277 len = data->block[0];
278 outb_p(len, SMBHSTDAT0);
279 for (i = 0; i < len; i++)
280 outb_p(data->block[i+1], SMBBLKDAT);
281 }
282
283 status = i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 |
284 I801_PEC_EN * hwpec);
285 if (status)
286 return status;
287
288 if (read_write == I2C_SMBUS_READ) {
289 len = inb_p(SMBHSTDAT0);
290 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
291 return -EPROTO;
292
293 data->block[0] = len;
294 for (i = 0; i < len; i++)
295 data->block[i + 1] = inb_p(SMBBLKDAT);
296 }
297 return 0;
298 }
299
300 static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
301 char read_write, int command,
302 int hwpec)
303 {
304 int i, len;
305 int smbcmd;
306 int status;
307 int result;
308 int timeout;
309
310 result = i801_check_pre();
311 if (result < 0)
312 return result;
313
314 len = data->block[0];
315
316 if (read_write == I2C_SMBUS_WRITE) {
317 outb_p(len, SMBHSTDAT0);
318 outb_p(data->block[1], SMBBLKDAT);
319 }
320
321 for (i = 1; i <= len; i++) {
322 if (i == len && read_write == I2C_SMBUS_READ) {
323 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
324 smbcmd = I801_I2C_BLOCK_LAST;
325 else
326 smbcmd = I801_BLOCK_LAST;
327 } else {
328 if (command == I2C_SMBUS_I2C_BLOCK_DATA
329 && read_write == I2C_SMBUS_READ)
330 smbcmd = I801_I2C_BLOCK_DATA;
331 else
332 smbcmd = I801_BLOCK_DATA;
333 }
334 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
335
336 if (i == 1)
337 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
338
339 /* We will always wait for a fraction of a second! */
340 timeout = 0;
341 do {
342 msleep(1);
343 status = inb_p(SMBHSTSTS);
344 }
345 while ((!(status & SMBHSTSTS_BYTE_DONE))
346 && (timeout++ < MAX_TIMEOUT));
347
348 result = i801_check_post(status, timeout > MAX_TIMEOUT);
349 if (result < 0)
350 return result;
351
352 if (i == 1 && read_write == I2C_SMBUS_READ
353 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
354 len = inb_p(SMBHSTDAT0);
355 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
356 dev_err(&I801_dev->dev,
357 "Illegal SMBus block read size %d\n",
358 len);
359 /* Recover */
360 while (inb_p(SMBHSTSTS) & SMBHSTSTS_HOST_BUSY)
361 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS);
362 outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
363 return -EPROTO;
364 }
365 data->block[0] = len;
366 }
367
368 /* Retrieve/store value in SMBBLKDAT */
369 if (read_write == I2C_SMBUS_READ)
370 data->block[i] = inb_p(SMBBLKDAT);
371 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
372 outb_p(data->block[i+1], SMBBLKDAT);
373
374 /* signals SMBBLKDAT ready */
375 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS);
376 }
377
378 return 0;
379 }
380
381 static int i801_set_block_buffer_mode(void)
382 {
383 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL);
384 if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0)
385 return -EIO;
386 return 0;
387 }
388
389 /* Block transaction function */
390 static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
391 int command, int hwpec)
392 {
393 int result = 0;
394 unsigned char hostc;
395
396 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
397 if (read_write == I2C_SMBUS_WRITE) {
398 /* set I2C_EN bit in configuration register */
399 pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
400 pci_write_config_byte(I801_dev, SMBHSTCFG,
401 hostc | SMBHSTCFG_I2C_EN);
402 } else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) {
403 dev_err(&I801_dev->dev,
404 "I2C block read is unsupported!\n");
405 return -EOPNOTSUPP;
406 }
407 }
408
409 if (read_write == I2C_SMBUS_WRITE
410 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
411 if (data->block[0] < 1)
412 data->block[0] = 1;
413 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
414 data->block[0] = I2C_SMBUS_BLOCK_MAX;
415 } else {
416 data->block[0] = 32; /* max for SMBus block reads */
417 }
418
419 /* Experience has shown that the block buffer can only be used for
420 SMBus (not I2C) block transactions, even though the datasheet
421 doesn't mention this limitation. */
422 if ((i801_features & FEATURE_BLOCK_BUFFER)
423 && command != I2C_SMBUS_I2C_BLOCK_DATA
424 && i801_set_block_buffer_mode() == 0)
425 result = i801_block_transaction_by_block(data, read_write,
426 hwpec);
427 else
428 result = i801_block_transaction_byte_by_byte(data, read_write,
429 command, hwpec);
430
431 if (result == 0 && hwpec)
432 i801_wait_hwpec();
433
434 if (command == I2C_SMBUS_I2C_BLOCK_DATA
435 && read_write == I2C_SMBUS_WRITE) {
436 /* restore saved configuration register value */
437 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
438 }
439 return result;
440 }
441
442 /* Return negative errno on error. */
443 static s32 i801_access(struct i2c_adapter * adap, u16 addr,
444 unsigned short flags, char read_write, u8 command,
445 int size, union i2c_smbus_data * data)
446 {
447 int hwpec;
448 int block = 0;
449 int ret, xact = 0;
450
451 hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
452 && size != I2C_SMBUS_QUICK
453 && size != I2C_SMBUS_I2C_BLOCK_DATA;
454
455 switch (size) {
456 case I2C_SMBUS_QUICK:
457 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
458 SMBHSTADD);
459 xact = I801_QUICK;
460 break;
461 case I2C_SMBUS_BYTE:
462 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
463 SMBHSTADD);
464 if (read_write == I2C_SMBUS_WRITE)
465 outb_p(command, SMBHSTCMD);
466 xact = I801_BYTE;
467 break;
468 case I2C_SMBUS_BYTE_DATA:
469 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
470 SMBHSTADD);
471 outb_p(command, SMBHSTCMD);
472 if (read_write == I2C_SMBUS_WRITE)
473 outb_p(data->byte, SMBHSTDAT0);
474 xact = I801_BYTE_DATA;
475 break;
476 case I2C_SMBUS_WORD_DATA:
477 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
478 SMBHSTADD);
479 outb_p(command, SMBHSTCMD);
480 if (read_write == I2C_SMBUS_WRITE) {
481 outb_p(data->word & 0xff, SMBHSTDAT0);
482 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
483 }
484 xact = I801_WORD_DATA;
485 break;
486 case I2C_SMBUS_BLOCK_DATA:
487 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
488 SMBHSTADD);
489 outb_p(command, SMBHSTCMD);
490 block = 1;
491 break;
492 case I2C_SMBUS_I2C_BLOCK_DATA:
493 /* NB: page 240 of ICH5 datasheet shows that the R/#W
494 * bit should be cleared here, even when reading */
495 outb_p((addr & 0x7f) << 1, SMBHSTADD);
496 if (read_write == I2C_SMBUS_READ) {
497 /* NB: page 240 of ICH5 datasheet also shows
498 * that DATA1 is the cmd field when reading */
499 outb_p(command, SMBHSTDAT1);
500 } else
501 outb_p(command, SMBHSTCMD);
502 block = 1;
503 break;
504 default:
505 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
506 return -EOPNOTSUPP;
507 }
508
509 if (hwpec) /* enable/disable hardware PEC */
510 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
511 else
512 outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
513
514 if(block)
515 ret = i801_block_transaction(data, read_write, size, hwpec);
516 else
517 ret = i801_transaction(xact | ENABLE_INT9);
518
519 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
520 time, so we forcibly disable it after every transaction. Turn off
521 E32B for the same reason. */
522 if (hwpec || block)
523 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
524 SMBAUXCTL);
525
526 if(block)
527 return ret;
528 if(ret)
529 return ret;
530 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
531 return 0;
532
533 switch (xact & 0x7f) {
534 case I801_BYTE: /* Result put in SMBHSTDAT0 */
535 case I801_BYTE_DATA:
536 data->byte = inb_p(SMBHSTDAT0);
537 break;
538 case I801_WORD_DATA:
539 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
540 break;
541 }
542 return 0;
543 }
544
545
546 static u32 i801_func(struct i2c_adapter *adapter)
547 {
548 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
549 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
550 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
551 ((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
552 ((i801_features & FEATURE_I2C_BLOCK_READ) ?
553 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
554 }
555
556 static const struct i2c_algorithm smbus_algorithm = {
557 .smbus_xfer = i801_access,
558 .functionality = i801_func,
559 };
560
561 static struct i2c_adapter i801_adapter = {
562 .owner = THIS_MODULE,
563 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
564 .algo = &smbus_algorithm,
565 };
566
567 static const struct pci_device_id i801_ids[] = {
568 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
569 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
570 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
571 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
572 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
573 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
574 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
575 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
576 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
577 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
578 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
579 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
580 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TOLAPAI_1) },
581 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
582 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
583 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PCH_SMBUS) },
584 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CPT_SMBUS) },
585 { 0, }
586 };
587
588 MODULE_DEVICE_TABLE (pci, i801_ids);
589
590 #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
591 static unsigned char apanel_addr;
592
593 /* Scan the system ROM for the signature "FJKEYINF" */
594 static __init const void __iomem *bios_signature(const void __iomem *bios)
595 {
596 ssize_t offset;
597 const unsigned char signature[] = "FJKEYINF";
598
599 for (offset = 0; offset < 0x10000; offset += 0x10) {
600 if (check_signature(bios + offset, signature,
601 sizeof(signature)-1))
602 return bios + offset;
603 }
604 return NULL;
605 }
606
607 static void __init input_apanel_init(void)
608 {
609 void __iomem *bios;
610 const void __iomem *p;
611
612 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
613 p = bios_signature(bios);
614 if (p) {
615 /* just use the first address */
616 apanel_addr = readb(p + 8 + 3) >> 1;
617 }
618 iounmap(bios);
619 }
620 #else
621 static void __init input_apanel_init(void) {}
622 #endif
623
624 #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
625 struct dmi_onboard_device_info {
626 const char *name;
627 u8 type;
628 unsigned short i2c_addr;
629 const char *i2c_type;
630 };
631
632 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
633 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
634 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
635 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
636 };
637
638 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
639 struct i2c_adapter *adap)
640 {
641 int i;
642 struct i2c_board_info info;
643
644 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
645 /* & ~0x80, ignore enabled/disabled bit */
646 if ((type & ~0x80) != dmi_devices[i].type)
647 continue;
648 if (strcmp(name, dmi_devices[i].name))
649 continue;
650
651 memset(&info, 0, sizeof(struct i2c_board_info));
652 info.addr = dmi_devices[i].i2c_addr;
653 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
654 i2c_new_device(adap, &info);
655 break;
656 }
657 }
658
659 /* We use our own function to check for onboard devices instead of
660 dmi_find_device() as some buggy BIOS's have the devices we are interested
661 in marked as disabled */
662 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
663 void *adap)
664 {
665 int i, count;
666
667 if (dm->type != 10)
668 return;
669
670 count = (dm->length - sizeof(struct dmi_header)) / 2;
671 for (i = 0; i < count; i++) {
672 const u8 *d = (char *)(dm + 1) + (i * 2);
673 const char *name = ((char *) dm) + dm->length;
674 u8 type = d[0];
675 u8 s = d[1];
676
677 if (!s)
678 continue;
679 s--;
680 while (s > 0 && name[0]) {
681 name += strlen(name) + 1;
682 s--;
683 }
684 if (name[0] == 0) /* Bogus string reference */
685 continue;
686
687 dmi_check_onboard_device(type, name, adap);
688 }
689 }
690 #endif
691
692 static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
693 {
694 unsigned char temp;
695 int err;
696 #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
697 const char *vendor;
698 #endif
699
700 I801_dev = dev;
701 i801_features = 0;
702 switch (dev->device) {
703 case PCI_DEVICE_ID_INTEL_82801EB_3:
704 case PCI_DEVICE_ID_INTEL_ESB_4:
705 case PCI_DEVICE_ID_INTEL_ICH6_16:
706 case PCI_DEVICE_ID_INTEL_ICH7_17:
707 case PCI_DEVICE_ID_INTEL_ESB2_17:
708 case PCI_DEVICE_ID_INTEL_ICH8_5:
709 case PCI_DEVICE_ID_INTEL_ICH9_6:
710 case PCI_DEVICE_ID_INTEL_TOLAPAI_1:
711 case PCI_DEVICE_ID_INTEL_ICH10_4:
712 case PCI_DEVICE_ID_INTEL_ICH10_5:
713 case PCI_DEVICE_ID_INTEL_PCH_SMBUS:
714 case PCI_DEVICE_ID_INTEL_CPT_SMBUS:
715 i801_features |= FEATURE_I2C_BLOCK_READ;
716 /* fall through */
717 case PCI_DEVICE_ID_INTEL_82801DB_3:
718 i801_features |= FEATURE_SMBUS_PEC;
719 i801_features |= FEATURE_BLOCK_BUFFER;
720 break;
721 }
722
723 err = pci_enable_device(dev);
724 if (err) {
725 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
726 err);
727 goto exit;
728 }
729
730 /* Determine the address of the SMBus area */
731 i801_smba = pci_resource_start(dev, SMBBAR);
732 if (!i801_smba) {
733 dev_err(&dev->dev, "SMBus base address uninitialized, "
734 "upgrade BIOS\n");
735 err = -ENODEV;
736 goto exit;
737 }
738
739 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
740 if (err) {
741 err = -ENODEV;
742 goto exit;
743 }
744
745 err = pci_request_region(dev, SMBBAR, i801_driver.name);
746 if (err) {
747 dev_err(&dev->dev, "Failed to request SMBus region "
748 "0x%lx-0x%Lx\n", i801_smba,
749 (unsigned long long)pci_resource_end(dev, SMBBAR));
750 goto exit;
751 }
752
753 pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
754 i801_original_hstcfg = temp;
755 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
756 if (!(temp & SMBHSTCFG_HST_EN)) {
757 dev_info(&dev->dev, "Enabling SMBus device\n");
758 temp |= SMBHSTCFG_HST_EN;
759 }
760 pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
761
762 if (temp & SMBHSTCFG_SMB_SMI_EN)
763 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
764 else
765 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
766
767 /* Clear special mode bits */
768 if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
769 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
770 SMBAUXCTL);
771
772 /* set up the sysfs linkage to our parent device */
773 i801_adapter.dev.parent = &dev->dev;
774
775 /* Retry up to 3 times on lost arbitration */
776 i801_adapter.retries = 3;
777
778 snprintf(i801_adapter.name, sizeof(i801_adapter.name),
779 "SMBus I801 adapter at %04lx", i801_smba);
780 err = i2c_add_adapter(&i801_adapter);
781 if (err) {
782 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
783 goto exit_release;
784 }
785
786 /* Register optional slaves */
787 #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
788 if (apanel_addr) {
789 struct i2c_board_info info;
790
791 memset(&info, 0, sizeof(struct i2c_board_info));
792 info.addr = apanel_addr;
793 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
794 i2c_new_device(&i801_adapter, &info);
795 }
796 #endif
797 #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
798 vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
799 if (vendor && !strcmp(vendor, "FUJITSU SIEMENS"))
800 dmi_walk(dmi_check_onboard_devices, &i801_adapter);
801 #endif
802
803 return 0;
804
805 exit_release:
806 pci_release_region(dev, SMBBAR);
807 exit:
808 return err;
809 }
810
811 static void __devexit i801_remove(struct pci_dev *dev)
812 {
813 i2c_del_adapter(&i801_adapter);
814 pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg);
815 pci_release_region(dev, SMBBAR);
816 /*
817 * do not call pci_disable_device(dev) since it can cause hard hangs on
818 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
819 */
820 }
821
822 #ifdef CONFIG_PM
823 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
824 {
825 pci_save_state(dev);
826 pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg);
827 pci_set_power_state(dev, pci_choose_state(dev, mesg));
828 return 0;
829 }
830
831 static int i801_resume(struct pci_dev *dev)
832 {
833 pci_set_power_state(dev, PCI_D0);
834 pci_restore_state(dev);
835 return pci_enable_device(dev);
836 }
837 #else
838 #define i801_suspend NULL
839 #define i801_resume NULL
840 #endif
841
842 static struct pci_driver i801_driver = {
843 .name = "i801_smbus",
844 .id_table = i801_ids,
845 .probe = i801_probe,
846 .remove = __devexit_p(i801_remove),
847 .suspend = i801_suspend,
848 .resume = i801_resume,
849 };
850
851 static int __init i2c_i801_init(void)
852 {
853 input_apanel_init();
854 return pci_register_driver(&i801_driver);
855 }
856
857 static void __exit i2c_i801_exit(void)
858 {
859 pci_unregister_driver(&i801_driver);
860 }
861
862 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
863 "Jean Delvare <khali@linux-fr.org>");
864 MODULE_DESCRIPTION("I801 SMBus driver");
865 MODULE_LICENSE("GPL");
866
867 module_init(i2c_i801_init);
868 module_exit(i2c_i801_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree