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ALSA: hda - Add quirk for Dell Vostro 1220
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / i2c / busses / i2c-bfin-twi.c
blobf1e14dd590c977fdbb7e128cd0dfc5285f5379dd
1 /*
2 * Blackfin On-Chip Two Wire Interface Driver
3 *
4 * Copyright 2005-2007 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/i2c.h>
15 #include <linux/slab.h>
16 #include <linux/io.h>
17 #include <linux/mm.h>
18 #include <linux/timer.h>
19 #include <linux/spinlock.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/platform_device.h>
23
24 #include <asm/blackfin.h>
25 #include <asm/portmux.h>
26 #include <asm/irq.h>
27
28 #define POLL_TIMEOUT (2 * HZ)
29
30 /* SMBus mode*/
31 #define TWI_I2C_MODE_STANDARD 1
32 #define TWI_I2C_MODE_STANDARDSUB 2
33 #define TWI_I2C_MODE_COMBINED 3
34 #define TWI_I2C_MODE_REPEAT 4
35
36 struct bfin_twi_iface {
37 int irq;
38 spinlock_t lock;
39 char read_write;
40 u8 command;
41 u8 *transPtr;
42 int readNum;
43 int writeNum;
44 int cur_mode;
45 int manual_stop;
46 int result;
47 int timeout_count;
48 struct timer_list timeout_timer;
49 struct i2c_adapter adap;
50 struct completion complete;
51 struct i2c_msg *pmsg;
52 int msg_num;
53 int cur_msg;
54 u16 saved_clkdiv;
55 u16 saved_control;
56 void __iomem *regs_base;
57 };
58
59
60 #define DEFINE_TWI_REG(reg, off) \
61 static inline u16 read_##reg(struct bfin_twi_iface *iface) \
62 { return bfin_read16(iface->regs_base + (off)); } \
63 static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
64 { bfin_write16(iface->regs_base + (off), v); }
65
66 DEFINE_TWI_REG(CLKDIV, 0x00)
67 DEFINE_TWI_REG(CONTROL, 0x04)
68 DEFINE_TWI_REG(SLAVE_CTL, 0x08)
69 DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
70 DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
71 DEFINE_TWI_REG(MASTER_CTL, 0x14)
72 DEFINE_TWI_REG(MASTER_STAT, 0x18)
73 DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
74 DEFINE_TWI_REG(INT_STAT, 0x20)
75 DEFINE_TWI_REG(INT_MASK, 0x24)
76 DEFINE_TWI_REG(FIFO_CTL, 0x28)
77 DEFINE_TWI_REG(FIFO_STAT, 0x2C)
78 DEFINE_TWI_REG(XMT_DATA8, 0x80)
79 DEFINE_TWI_REG(XMT_DATA16, 0x84)
80 DEFINE_TWI_REG(RCV_DATA8, 0x88)
81 DEFINE_TWI_REG(RCV_DATA16, 0x8C)
82
83 static const u16 pin_req[2][3] = {
84 {P_TWI0_SCL, P_TWI0_SDA, 0},
85 {P_TWI1_SCL, P_TWI1_SDA, 0},
86 };
87
88 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
89 {
90 unsigned short twi_int_status = read_INT_STAT(iface);
91 unsigned short mast_stat = read_MASTER_STAT(iface);
92
93 if (twi_int_status & XMTSERV) {
94 /* Transmit next data */
95 if (iface->writeNum > 0) {
96 write_XMT_DATA8(iface, *(iface->transPtr++));
97 iface->writeNum--;
98 }
99 /* start receive immediately after complete sending in
100 * combine mode.
101 */
102 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
103 write_MASTER_CTL(iface,
104 read_MASTER_CTL(iface) | MDIR | RSTART);
105 else if (iface->manual_stop)
106 write_MASTER_CTL(iface,
107 read_MASTER_CTL(iface) | STOP);
108 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
109 iface->cur_msg + 1 < iface->msg_num) {
110 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
111 write_MASTER_CTL(iface,
112 read_MASTER_CTL(iface) | RSTART | MDIR);
113 else
114 write_MASTER_CTL(iface,
115 (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
116 }
117 SSYNC();
118 /* Clear status */
119 write_INT_STAT(iface, XMTSERV);
120 SSYNC();
121 }
122 if (twi_int_status & RCVSERV) {
123 if (iface->readNum > 0) {
124 /* Receive next data */
125 *(iface->transPtr) = read_RCV_DATA8(iface);
126 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
127 /* Change combine mode into sub mode after
128 * read first data.
129 */
130 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
131 /* Get read number from first byte in block
132 * combine mode.
133 */
134 if (iface->readNum == 1 && iface->manual_stop)
135 iface->readNum = *iface->transPtr + 1;
136 }
137 iface->transPtr++;
138 iface->readNum--;
139 } else if (iface->manual_stop) {
140 write_MASTER_CTL(iface,
141 read_MASTER_CTL(iface) | STOP);
142 SSYNC();
143 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
144 iface->cur_msg + 1 < iface->msg_num) {
145 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
146 write_MASTER_CTL(iface,
147 read_MASTER_CTL(iface) | RSTART | MDIR);
148 else
149 write_MASTER_CTL(iface,
150 (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
151 SSYNC();
152 }
153 /* Clear interrupt source */
154 write_INT_STAT(iface, RCVSERV);
155 SSYNC();
156 }
157 if (twi_int_status & MERR) {
158 write_INT_STAT(iface, MERR);
159 write_INT_MASK(iface, 0);
160 write_MASTER_STAT(iface, 0x3e);
161 write_MASTER_CTL(iface, 0);
162 SSYNC();
163 iface->result = -EIO;
164 /* if both err and complete int stats are set, return proper
165 * results.
166 */
167 if (twi_int_status & MCOMP) {
168 write_INT_STAT(iface, MCOMP);
169 write_INT_MASK(iface, 0);
170 write_MASTER_CTL(iface, 0);
171 SSYNC();
172 /* If it is a quick transfer, only address bug no data,
173 * not an err, return 1.
174 */
175 if (iface->writeNum == 0 && (mast_stat & BUFRDERR))
176 iface->result = 1;
177 /* If address not acknowledged return -1,
178 * else return 0.
179 */
180 else if (!(mast_stat & ANAK))
181 iface->result = 0;
182 }
183 complete(&iface->complete);
184 return;
185 }
186 if (twi_int_status & MCOMP) {
187 write_INT_STAT(iface, MCOMP);
188 SSYNC();
189 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
190 if (iface->readNum == 0) {
191 /* set the read number to 1 and ask for manual
192 * stop in block combine mode
193 */
194 iface->readNum = 1;
195 iface->manual_stop = 1;
196 write_MASTER_CTL(iface,
197 read_MASTER_CTL(iface) | (0xff << 6));
198 } else {
199 /* set the readd number in other
200 * combine mode.
201 */
202 write_MASTER_CTL(iface,
203 (read_MASTER_CTL(iface) &
204 (~(0xff << 6))) |
205 (iface->readNum << 6));
206 }
207 /* remove restart bit and enable master receive */
208 write_MASTER_CTL(iface,
209 read_MASTER_CTL(iface) & ~RSTART);
210 SSYNC();
211 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
212 iface->cur_msg+1 < iface->msg_num) {
213 iface->cur_msg++;
214 iface->transPtr = iface->pmsg[iface->cur_msg].buf;
215 iface->writeNum = iface->readNum =
216 iface->pmsg[iface->cur_msg].len;
217 /* Set Transmit device address */
218 write_MASTER_ADDR(iface,
219 iface->pmsg[iface->cur_msg].addr);
220 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
221 iface->read_write = I2C_SMBUS_READ;
222 else {
223 iface->read_write = I2C_SMBUS_WRITE;
224 /* Transmit first data */
225 if (iface->writeNum > 0) {
226 write_XMT_DATA8(iface,
227 *(iface->transPtr++));
228 iface->writeNum--;
229 SSYNC();
230 }
231 }
232
233 if (iface->pmsg[iface->cur_msg].len <= 255)
234 write_MASTER_CTL(iface,
235 (read_MASTER_CTL(iface) &
236 (~(0xff << 6))) |
237 (iface->pmsg[iface->cur_msg].len << 6));
238 else {
239 write_MASTER_CTL(iface,
240 (read_MASTER_CTL(iface) |
241 (0xff << 6)));
242 iface->manual_stop = 1;
243 }
244 /* remove restart bit and enable master receive */
245 write_MASTER_CTL(iface,
246 read_MASTER_CTL(iface) & ~RSTART);
247 SSYNC();
248 } else {
249 iface->result = 1;
250 write_INT_MASK(iface, 0);
251 write_MASTER_CTL(iface, 0);
252 SSYNC();
253 complete(&iface->complete);
254 }
255 }
256 }
257
258 /* Interrupt handler */
259 static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
260 {
261 struct bfin_twi_iface *iface = dev_id;
262 unsigned long flags;
263
264 spin_lock_irqsave(&iface->lock, flags);
265 del_timer(&iface->timeout_timer);
266 bfin_twi_handle_interrupt(iface);
267 spin_unlock_irqrestore(&iface->lock, flags);
268 return IRQ_HANDLED;
269 }
270
271 static void bfin_twi_timeout(unsigned long data)
272 {
273 struct bfin_twi_iface *iface = (struct bfin_twi_iface *)data;
274 unsigned long flags;
275
276 spin_lock_irqsave(&iface->lock, flags);
277 bfin_twi_handle_interrupt(iface);
278 if (iface->result == 0) {
279 iface->timeout_count--;
280 if (iface->timeout_count > 0) {
281 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
282 add_timer(&iface->timeout_timer);
283 } else {
284 iface->result = -1;
285 complete(&iface->complete);
286 }
287 }
288 spin_unlock_irqrestore(&iface->lock, flags);
289 }
290
291 /*
292 * Generic i2c master transfer entrypoint
293 */
294 static int bfin_twi_master_xfer(struct i2c_adapter *adap,
295 struct i2c_msg *msgs, int num)
296 {
297 struct bfin_twi_iface *iface = adap->algo_data;
298 struct i2c_msg *pmsg;
299 int rc = 0;
300
301 if (!(read_CONTROL(iface) & TWI_ENA))
302 return -ENXIO;
303
304 while (read_MASTER_STAT(iface) & BUSBUSY)
305 yield();
306
307 iface->pmsg = msgs;
308 iface->msg_num = num;
309 iface->cur_msg = 0;
310
311 pmsg = &msgs[0];
312 if (pmsg->flags & I2C_M_TEN) {
313 dev_err(&adap->dev, "10 bits addr not supported!\n");
314 return -EINVAL;
315 }
316
317 iface->cur_mode = TWI_I2C_MODE_REPEAT;
318 iface->manual_stop = 0;
319 iface->transPtr = pmsg->buf;
320 iface->writeNum = iface->readNum = pmsg->len;
321 iface->result = 0;
322 iface->timeout_count = 10;
323 init_completion(&(iface->complete));
324 /* Set Transmit device address */
325 write_MASTER_ADDR(iface, pmsg->addr);
326
327 /* FIFO Initiation. Data in FIFO should be
328 * discarded before start a new operation.
329 */
330 write_FIFO_CTL(iface, 0x3);
331 SSYNC();
332 write_FIFO_CTL(iface, 0);
333 SSYNC();
334
335 if (pmsg->flags & I2C_M_RD)
336 iface->read_write = I2C_SMBUS_READ;
337 else {
338 iface->read_write = I2C_SMBUS_WRITE;
339 /* Transmit first data */
340 if (iface->writeNum > 0) {
341 write_XMT_DATA8(iface, *(iface->transPtr++));
342 iface->writeNum--;
343 SSYNC();
344 }
345 }
346
347 /* clear int stat */
348 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
349
350 /* Interrupt mask . Enable XMT, RCV interrupt */
351 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
352 SSYNC();
353
354 if (pmsg->len <= 255)
355 write_MASTER_CTL(iface, pmsg->len << 6);
356 else {
357 write_MASTER_CTL(iface, 0xff << 6);
358 iface->manual_stop = 1;
359 }
360
361 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
362 add_timer(&iface->timeout_timer);
363
364 /* Master enable */
365 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
366 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
367 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
368 SSYNC();
369
370 wait_for_completion(&iface->complete);
371
372 rc = iface->result;
373
374 if (rc == 1)
375 return num;
376 else
377 return rc;
378 }
379
380 /*
381 * SMBus type transfer entrypoint
382 */
383
384 int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
385 unsigned short flags, char read_write,
386 u8 command, int size, union i2c_smbus_data *data)
387 {
388 struct bfin_twi_iface *iface = adap->algo_data;
389 int rc = 0;
390
391 if (!(read_CONTROL(iface) & TWI_ENA))
392 return -ENXIO;
393
394 while (read_MASTER_STAT(iface) & BUSBUSY)
395 yield();
396
397 iface->writeNum = 0;
398 iface->readNum = 0;
399
400 /* Prepare datas & select mode */
401 switch (size) {
402 case I2C_SMBUS_QUICK:
403 iface->transPtr = NULL;
404 iface->cur_mode = TWI_I2C_MODE_STANDARD;
405 break;
406 case I2C_SMBUS_BYTE:
407 if (data == NULL)
408 iface->transPtr = NULL;
409 else {
410 if (read_write == I2C_SMBUS_READ)
411 iface->readNum = 1;
412 else
413 iface->writeNum = 1;
414 iface->transPtr = &data->byte;
415 }
416 iface->cur_mode = TWI_I2C_MODE_STANDARD;
417 break;
418 case I2C_SMBUS_BYTE_DATA:
419 if (read_write == I2C_SMBUS_READ) {
420 iface->readNum = 1;
421 iface->cur_mode = TWI_I2C_MODE_COMBINED;
422 } else {
423 iface->writeNum = 1;
424 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
425 }
426 iface->transPtr = &data->byte;
427 break;
428 case I2C_SMBUS_WORD_DATA:
429 if (read_write == I2C_SMBUS_READ) {
430 iface->readNum = 2;
431 iface->cur_mode = TWI_I2C_MODE_COMBINED;
432 } else {
433 iface->writeNum = 2;
434 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
435 }
436 iface->transPtr = (u8 *)&data->word;
437 break;
438 case I2C_SMBUS_PROC_CALL:
439 iface->writeNum = 2;
440 iface->readNum = 2;
441 iface->cur_mode = TWI_I2C_MODE_COMBINED;
442 iface->transPtr = (u8 *)&data->word;
443 break;
444 case I2C_SMBUS_BLOCK_DATA:
445 if (read_write == I2C_SMBUS_READ) {
446 iface->readNum = 0;
447 iface->cur_mode = TWI_I2C_MODE_COMBINED;
448 } else {
449 iface->writeNum = data->block[0] + 1;
450 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
451 }
452 iface->transPtr = data->block;
453 break;
454 case I2C_SMBUS_I2C_BLOCK_DATA:
455 if (read_write == I2C_SMBUS_READ) {
456 iface->readNum = data->block[0];
457 iface->cur_mode = TWI_I2C_MODE_COMBINED;
458 } else {
459 iface->writeNum = data->block[0];
460 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
461 }
462 iface->transPtr = (u8 *)&data->block[1];
463 break;
464 default:
465 return -1;
466 }
467
468 iface->result = 0;
469 iface->manual_stop = 0;
470 iface->read_write = read_write;
471 iface->command = command;
472 iface->timeout_count = 10;
473 init_completion(&(iface->complete));
474
475 /* FIFO Initiation. Data in FIFO should be discarded before
476 * start a new operation.
477 */
478 write_FIFO_CTL(iface, 0x3);
479 SSYNC();
480 write_FIFO_CTL(iface, 0);
481
482 /* clear int stat */
483 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
484
485 /* Set Transmit device address */
486 write_MASTER_ADDR(iface, addr);
487 SSYNC();
488
489 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
490 add_timer(&iface->timeout_timer);
491
492 switch (iface->cur_mode) {
493 case TWI_I2C_MODE_STANDARDSUB:
494 write_XMT_DATA8(iface, iface->command);
495 write_INT_MASK(iface, MCOMP | MERR |
496 ((iface->read_write == I2C_SMBUS_READ) ?
497 RCVSERV : XMTSERV));
498 SSYNC();
499
500 if (iface->writeNum + 1 <= 255)
501 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
502 else {
503 write_MASTER_CTL(iface, 0xff << 6);
504 iface->manual_stop = 1;
505 }
506 /* Master enable */
507 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
508 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
509 break;
510 case TWI_I2C_MODE_COMBINED:
511 write_XMT_DATA8(iface, iface->command);
512 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
513 SSYNC();
514
515 if (iface->writeNum > 0)
516 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
517 else
518 write_MASTER_CTL(iface, 0x1 << 6);
519 /* Master enable */
520 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
521 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
522 break;
523 default:
524 write_MASTER_CTL(iface, 0);
525 if (size != I2C_SMBUS_QUICK) {
526 /* Don't access xmit data register when this is a
527 * read operation.
528 */
529 if (iface->read_write != I2C_SMBUS_READ) {
530 if (iface->writeNum > 0) {
531 write_XMT_DATA8(iface,
532 *(iface->transPtr++));
533 if (iface->writeNum <= 255)
534 write_MASTER_CTL(iface,
535 iface->writeNum << 6);
536 else {
537 write_MASTER_CTL(iface,
538 0xff << 6);
539 iface->manual_stop = 1;
540 }
541 iface->writeNum--;
542 } else {
543 write_XMT_DATA8(iface, iface->command);
544 write_MASTER_CTL(iface, 1 << 6);
545 }
546 } else {
547 if (iface->readNum > 0 && iface->readNum <= 255)
548 write_MASTER_CTL(iface,
549 iface->readNum << 6);
550 else if (iface->readNum > 255) {
551 write_MASTER_CTL(iface, 0xff << 6);
552 iface->manual_stop = 1;
553 } else {
554 del_timer(&iface->timeout_timer);
555 break;
556 }
557 }
558 }
559 write_INT_MASK(iface, MCOMP | MERR |
560 ((iface->read_write == I2C_SMBUS_READ) ?
561 RCVSERV : XMTSERV));
562 SSYNC();
563
564 /* Master enable */
565 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
566 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
567 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
568 break;
569 }
570 SSYNC();
571
572 wait_for_completion(&iface->complete);
573
574 rc = (iface->result >= 0) ? 0 : -1;
575
576 return rc;
577 }
578
579 /*
580 * Return what the adapter supports
581 */
582 static u32 bfin_twi_functionality(struct i2c_adapter *adap)
583 {
584 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
585 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
586 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
587 I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
588 }
589
590 static struct i2c_algorithm bfin_twi_algorithm = {
591 .master_xfer = bfin_twi_master_xfer,
592 .smbus_xfer = bfin_twi_smbus_xfer,
593 .functionality = bfin_twi_functionality,
594 };
595
596 static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state)
597 {
598 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
599
600 iface->saved_clkdiv = read_CLKDIV(iface);
601 iface->saved_control = read_CONTROL(iface);
602
603 free_irq(iface->irq, iface);
604
605 /* Disable TWI */
606 write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
607
608 return 0;
609 }
610
611 static int i2c_bfin_twi_resume(struct platform_device *pdev)
612 {
613 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
614
615 int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
616 IRQF_DISABLED, pdev->name, iface);
617 if (rc) {
618 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
619 return -ENODEV;
620 }
621
622 /* Resume TWI interface clock as specified */
623 write_CLKDIV(iface, iface->saved_clkdiv);
624
625 /* Resume TWI */
626 write_CONTROL(iface, iface->saved_control);
627
628 return 0;
629 }
630
631 static int i2c_bfin_twi_probe(struct platform_device *pdev)
632 {
633 struct bfin_twi_iface *iface;
634 struct i2c_adapter *p_adap;
635 struct resource *res;
636 int rc;
637 unsigned int clkhilow;
638
639 iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
640 if (!iface) {
641 dev_err(&pdev->dev, "Cannot allocate memory\n");
642 rc = -ENOMEM;
643 goto out_error_nomem;
644 }
645
646 spin_lock_init(&(iface->lock));
647
648 /* Find and map our resources */
649 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
650 if (res == NULL) {
651 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
652 rc = -ENOENT;
653 goto out_error_get_res;
654 }
655
656 iface->regs_base = ioremap(res->start, resource_size(res));
657 if (iface->regs_base == NULL) {
658 dev_err(&pdev->dev, "Cannot map IO\n");
659 rc = -ENXIO;
660 goto out_error_ioremap;
661 }
662
663 iface->irq = platform_get_irq(pdev, 0);
664 if (iface->irq < 0) {
665 dev_err(&pdev->dev, "No IRQ specified\n");
666 rc = -ENOENT;
667 goto out_error_no_irq;
668 }
669
670 init_timer(&(iface->timeout_timer));
671 iface->timeout_timer.function = bfin_twi_timeout;
672 iface->timeout_timer.data = (unsigned long)iface;
673
674 p_adap = &iface->adap;
675 p_adap->nr = pdev->id;
676 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
677 p_adap->algo = &bfin_twi_algorithm;
678 p_adap->algo_data = iface;
679 p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
680 p_adap->dev.parent = &pdev->dev;
681
682 rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
683 if (rc) {
684 dev_err(&pdev->dev, "Can't setup pin mux!\n");
685 goto out_error_pin_mux;
686 }
687
688 rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
689 IRQF_DISABLED, pdev->name, iface);
690 if (rc) {
691 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
692 rc = -ENODEV;
693 goto out_error_req_irq;
694 }
695
696 /* Set TWI internal clock as 10MHz */
697 write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
698
699 /*
700 * We will not end up with a CLKDIV=0 because no one will specify
701 * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
702 */
703 clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
704
705 /* Set Twi interface clock as specified */
706 write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
707
708 /* Enable TWI */
709 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
710 SSYNC();
711
712 rc = i2c_add_numbered_adapter(p_adap);
713 if (rc < 0) {
714 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
715 goto out_error_add_adapter;
716 }
717
718 platform_set_drvdata(pdev, iface);
719
720 dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
721 "regs_base@%p\n", iface->regs_base);
722
723 return 0;
724
725 out_error_add_adapter:
726 free_irq(iface->irq, iface);
727 out_error_req_irq:
728 out_error_no_irq:
729 peripheral_free_list(pin_req[pdev->id]);
730 out_error_pin_mux:
731 iounmap(iface->regs_base);
732 out_error_ioremap:
733 out_error_get_res:
734 kfree(iface);
735 out_error_nomem:
736 return rc;
737 }
738
739 static int i2c_bfin_twi_remove(struct platform_device *pdev)
740 {
741 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
742
743 platform_set_drvdata(pdev, NULL);
744
745 i2c_del_adapter(&(iface->adap));
746 free_irq(iface->irq, iface);
747 peripheral_free_list(pin_req[pdev->id]);
748 iounmap(iface->regs_base);
749 kfree(iface);
750
751 return 0;
752 }
753
754 static struct platform_driver i2c_bfin_twi_driver = {
755 .probe = i2c_bfin_twi_probe,
756 .remove = i2c_bfin_twi_remove,
757 .suspend = i2c_bfin_twi_suspend,
758 .resume = i2c_bfin_twi_resume,
759 .driver = {
760 .name = "i2c-bfin-twi",
761 .owner = THIS_MODULE,
762 },
763 };
764
765 static int __init i2c_bfin_twi_init(void)
766 {
767 return platform_driver_register(&i2c_bfin_twi_driver);
768 }
769
770 static void __exit i2c_bfin_twi_exit(void)
771 {
772 platform_driver_unregister(&i2c_bfin_twi_driver);
773 }
774
775 module_init(i2c_bfin_twi_init);
776 module_exit(i2c_bfin_twi_exit);
777
778 MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
779 MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
780 MODULE_LICENSE("GPL");
781 MODULE_ALIAS("platform:i2c-bfin-twi");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree