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ALSA: hda - Add quirk for Dell Vostro 1220
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / ata / sata_mv.c
blob71cc0d42f9e1c015ba90d27d4a457d5e247fddc5
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 *
8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
10 *
11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
28 /*
29 * sata_mv TODO list:
30 *
31 * --> Develop a low-power-consumption strategy, and implement it.
32 *
33 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
34 *
35 * --> [Experiment, Marvell value added] Is it possible to use target
36 * mode to cross-connect two Linux boxes with Marvell cards? If so,
37 * creating LibATA target mode support would be very interesting.
38 *
39 * Target mode, for those without docs, is the ability to directly
40 * connect two SATA ports.
41 */
42
43 /*
44 * 80x1-B2 errata PCI#11:
45 *
46 * Users of the 6041/6081 Rev.B2 chips (current is C0)
47 * should be careful to insert those cards only onto PCI-X bus #0,
48 * and only in device slots 0..7, not higher. The chips may not
49 * work correctly otherwise (note: this is a pretty rare condition).
50 */
51
52 #include <linux/kernel.h>
53 #include <linux/module.h>
54 #include <linux/pci.h>
55 #include <linux/init.h>
56 #include <linux/blkdev.h>
57 #include <linux/delay.h>
58 #include <linux/interrupt.h>
59 #include <linux/dmapool.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/device.h>
62 #include <linux/clk.h>
63 #include <linux/platform_device.h>
64 #include <linux/ata_platform.h>
65 #include <linux/mbus.h>
66 #include <linux/bitops.h>
67 #include <linux/gfp.h>
68 #include <scsi/scsi_host.h>
69 #include <scsi/scsi_cmnd.h>
70 #include <scsi/scsi_device.h>
71 #include <linux/libata.h>
72
73 #define DRV_NAME "sata_mv"
74 #define DRV_VERSION "1.28"
75
76 /*
77 * module options
78 */
79
80 static int msi;
81 #ifdef CONFIG_PCI
82 module_param(msi, int, S_IRUGO);
83 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
84 #endif
85
86 static int irq_coalescing_io_count;
87 module_param(irq_coalescing_io_count, int, S_IRUGO);
88 MODULE_PARM_DESC(irq_coalescing_io_count,
89 "IRQ coalescing I/O count threshold (0..255)");
90
91 static int irq_coalescing_usecs;
92 module_param(irq_coalescing_usecs, int, S_IRUGO);
93 MODULE_PARM_DESC(irq_coalescing_usecs,
94 "IRQ coalescing time threshold in usecs");
95
96 enum {
97 /* BAR's are enumerated in terms of pci_resource_start() terms */
98 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
99 MV_IO_BAR = 2, /* offset 0x18: IO space */
100 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
101
102 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
103 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
104
105 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
106 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
107 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
108 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
109
110 MV_PCI_REG_BASE = 0,
111
112 /*
113 * Per-chip ("all ports") interrupt coalescing feature.
114 * This is only for GEN_II / GEN_IIE hardware.
115 *
116 * Coalescing defers the interrupt until either the IO_THRESHOLD
117 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
118 */
119 COAL_REG_BASE = 0x18000,
120 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
121 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
122
123 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
124 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
125
126 /*
127 * Registers for the (unused here) transaction coalescing feature:
128 */
129 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
130 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
131
132 SATAHC0_REG_BASE = 0x20000,
133 FLASH_CTL = 0x1046c,
134 GPIO_PORT_CTL = 0x104f0,
135 RESET_CFG = 0x180d8,
136
137 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
138 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
139 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
140 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
141
142 MV_MAX_Q_DEPTH = 32,
143 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
144
145 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
146 * CRPB needs alignment on a 256B boundary. Size == 256B
147 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
148 */
149 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
150 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
151 MV_MAX_SG_CT = 256,
152 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
153
154 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
155 MV_PORT_HC_SHIFT = 2,
156 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
157 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
158 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
159
160 /* Host Flags */
161 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
162
163 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
164 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
165
166 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
167
168 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
169 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
170
171 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
172
173 CRQB_FLAG_READ = (1 << 0),
174 CRQB_TAG_SHIFT = 1,
175 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
176 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
177 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
178 CRQB_CMD_ADDR_SHIFT = 8,
179 CRQB_CMD_CS = (0x2 << 11),
180 CRQB_CMD_LAST = (1 << 15),
181
182 CRPB_FLAG_STATUS_SHIFT = 8,
183 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
184 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
185
186 EPRD_FLAG_END_OF_TBL = (1 << 31),
187
188 /* PCI interface registers */
189
190 MV_PCI_COMMAND = 0xc00,
191 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
192 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
193
194 PCI_MAIN_CMD_STS = 0xd30,
195 STOP_PCI_MASTER = (1 << 2),
196 PCI_MASTER_EMPTY = (1 << 3),
197 GLOB_SFT_RST = (1 << 4),
198
199 MV_PCI_MODE = 0xd00,
200 MV_PCI_MODE_MASK = 0x30,
201
202 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
203 MV_PCI_DISC_TIMER = 0xd04,
204 MV_PCI_MSI_TRIGGER = 0xc38,
205 MV_PCI_SERR_MASK = 0xc28,
206 MV_PCI_XBAR_TMOUT = 0x1d04,
207 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
208 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
209 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
210 MV_PCI_ERR_COMMAND = 0x1d50,
211
212 PCI_IRQ_CAUSE = 0x1d58,
213 PCI_IRQ_MASK = 0x1d5c,
214 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
215
216 PCIE_IRQ_CAUSE = 0x1900,
217 PCIE_IRQ_MASK = 0x1910,
218 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
219
220 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
221 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
222 PCI_HC_MAIN_IRQ_MASK = 0x1d64,
223 SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
224 SOC_HC_MAIN_IRQ_MASK = 0x20024,
225 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
226 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
227 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
228 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
229 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
230 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
231 PCI_ERR = (1 << 18),
232 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
233 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
234 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
235 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
236 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
237 GPIO_INT = (1 << 22),
238 SELF_INT = (1 << 23),
239 TWSI_INT = (1 << 24),
240 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
241 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
242 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
243
244 /* SATAHC registers */
245 HC_CFG = 0x00,
246
247 HC_IRQ_CAUSE = 0x14,
248 DMA_IRQ = (1 << 0), /* shift by port # */
249 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
250 DEV_IRQ = (1 << 8), /* shift by port # */
251
252 /*
253 * Per-HC (Host-Controller) interrupt coalescing feature.
254 * This is present on all chip generations.
255 *
256 * Coalescing defers the interrupt until either the IO_THRESHOLD
257 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
258 */
259 HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
260 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
261
262 SOC_LED_CTRL = 0x2c,
263 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
264 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
265 /* with dev activity LED */
266
267 /* Shadow block registers */
268 SHD_BLK = 0x100,
269 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
270
271 /* SATA registers */
272 SATA_STATUS = 0x300, /* ctrl, err regs follow status */
273 SATA_ACTIVE = 0x350,
274 FIS_IRQ_CAUSE = 0x364,
275 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
276
277 LTMODE = 0x30c, /* requires read-after-write */
278 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
279
280 PHY_MODE2 = 0x330,
281 PHY_MODE3 = 0x310,
282
283 PHY_MODE4 = 0x314, /* requires read-after-write */
284 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
285 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
286 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
287 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
288
289 SATA_IFCTL = 0x344,
290 SATA_TESTCTL = 0x348,
291 SATA_IFSTAT = 0x34c,
292 VENDOR_UNIQUE_FIS = 0x35c,
293
294 FISCFG = 0x360,
295 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
296 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
297
298 PHY_MODE9_GEN2 = 0x398,
299 PHY_MODE9_GEN1 = 0x39c,
300 PHYCFG_OFS = 0x3a0, /* only in 65n devices */
301
302 MV5_PHY_MODE = 0x74,
303 MV5_LTMODE = 0x30,
304 MV5_PHY_CTL = 0x0C,
305 SATA_IFCFG = 0x050,
306
307 MV_M2_PREAMP_MASK = 0x7e0,
308
309 /* Port registers */
310 EDMA_CFG = 0,
311 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
312 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
313 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
314 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
315 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
316 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
317 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
318
319 EDMA_ERR_IRQ_CAUSE = 0x8,
320 EDMA_ERR_IRQ_MASK = 0xc,
321 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
322 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
323 EDMA_ERR_DEV = (1 << 2), /* device error */
324 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
325 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
326 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
327 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
328 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
329 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
330 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
331 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
332 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
333 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
334 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
335
336 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
337 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
338 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
339 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
340 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
341
342 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
343
344 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
345 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
346 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
347 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
348 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
349 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
350
351 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
352
353 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
354 EDMA_ERR_OVERRUN_5 = (1 << 5),
355 EDMA_ERR_UNDERRUN_5 = (1 << 6),
356
357 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
358 EDMA_ERR_LNK_CTRL_RX_1 |
359 EDMA_ERR_LNK_CTRL_RX_3 |
360 EDMA_ERR_LNK_CTRL_TX,
361
362 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
363 EDMA_ERR_PRD_PAR |
364 EDMA_ERR_DEV_DCON |
365 EDMA_ERR_DEV_CON |
366 EDMA_ERR_SERR |
367 EDMA_ERR_SELF_DIS |
368 EDMA_ERR_CRQB_PAR |
369 EDMA_ERR_CRPB_PAR |
370 EDMA_ERR_INTRL_PAR |
371 EDMA_ERR_IORDY |
372 EDMA_ERR_LNK_CTRL_RX_2 |
373 EDMA_ERR_LNK_DATA_RX |
374 EDMA_ERR_LNK_DATA_TX |
375 EDMA_ERR_TRANS_PROTO,
376
377 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
378 EDMA_ERR_PRD_PAR |
379 EDMA_ERR_DEV_DCON |
380 EDMA_ERR_DEV_CON |
381 EDMA_ERR_OVERRUN_5 |
382 EDMA_ERR_UNDERRUN_5 |
383 EDMA_ERR_SELF_DIS_5 |
384 EDMA_ERR_CRQB_PAR |
385 EDMA_ERR_CRPB_PAR |
386 EDMA_ERR_INTRL_PAR |
387 EDMA_ERR_IORDY,
388
389 EDMA_REQ_Q_BASE_HI = 0x10,
390 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
391
392 EDMA_REQ_Q_OUT_PTR = 0x18,
393 EDMA_REQ_Q_PTR_SHIFT = 5,
394
395 EDMA_RSP_Q_BASE_HI = 0x1c,
396 EDMA_RSP_Q_IN_PTR = 0x20,
397 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
398 EDMA_RSP_Q_PTR_SHIFT = 3,
399
400 EDMA_CMD = 0x28, /* EDMA command register */
401 EDMA_EN = (1 << 0), /* enable EDMA */
402 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
403 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
404
405 EDMA_STATUS = 0x30, /* EDMA engine status */
406 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
407 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
408
409 EDMA_IORDY_TMOUT = 0x34,
410 EDMA_ARB_CFG = 0x38,
411
412 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
413 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
414
415 BMDMA_CMD = 0x224, /* bmdma command register */
416 BMDMA_STATUS = 0x228, /* bmdma status register */
417 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
418 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
419
420 /* Host private flags (hp_flags) */
421 MV_HP_FLAG_MSI = (1 << 0),
422 MV_HP_ERRATA_50XXB0 = (1 << 1),
423 MV_HP_ERRATA_50XXB2 = (1 << 2),
424 MV_HP_ERRATA_60X1B2 = (1 << 3),
425 MV_HP_ERRATA_60X1C0 = (1 << 4),
426 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
427 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
428 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
429 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
430 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
431 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
432 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
433
434 /* Port private flags (pp_flags) */
435 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
436 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
437 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
438 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
439 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
440 };
441
442 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
443 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
444 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
445 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
446 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
447
448 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
449 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
450
451 enum {
452 /* DMA boundary 0xffff is required by the s/g splitting
453 * we need on /length/ in mv_fill-sg().
454 */
455 MV_DMA_BOUNDARY = 0xffffU,
456
457 /* mask of register bits containing lower 32 bits
458 * of EDMA request queue DMA address
459 */
460 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
461
462 /* ditto, for response queue */
463 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
464 };
465
466 enum chip_type {
467 chip_504x,
468 chip_508x,
469 chip_5080,
470 chip_604x,
471 chip_608x,
472 chip_6042,
473 chip_7042,
474 chip_soc,
475 };
476
477 /* Command ReQuest Block: 32B */
478 struct mv_crqb {
479 __le32 sg_addr;
480 __le32 sg_addr_hi;
481 __le16 ctrl_flags;
482 __le16 ata_cmd[11];
483 };
484
485 struct mv_crqb_iie {
486 __le32 addr;
487 __le32 addr_hi;
488 __le32 flags;
489 __le32 len;
490 __le32 ata_cmd[4];
491 };
492
493 /* Command ResPonse Block: 8B */
494 struct mv_crpb {
495 __le16 id;
496 __le16 flags;
497 __le32 tmstmp;
498 };
499
500 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
501 struct mv_sg {
502 __le32 addr;
503 __le32 flags_size;
504 __le32 addr_hi;
505 __le32 reserved;
506 };
507
508 /*
509 * We keep a local cache of a few frequently accessed port
510 * registers here, to avoid having to read them (very slow)
511 * when switching between EDMA and non-EDMA modes.
512 */
513 struct mv_cached_regs {
514 u32 fiscfg;
515 u32 ltmode;
516 u32 haltcond;
517 u32 unknown_rsvd;
518 };
519
520 struct mv_port_priv {
521 struct mv_crqb *crqb;
522 dma_addr_t crqb_dma;
523 struct mv_crpb *crpb;
524 dma_addr_t crpb_dma;
525 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
526 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
527
528 unsigned int req_idx;
529 unsigned int resp_idx;
530
531 u32 pp_flags;
532 struct mv_cached_regs cached;
533 unsigned int delayed_eh_pmp_map;
534 };
535
536 struct mv_port_signal {
537 u32 amps;
538 u32 pre;
539 };
540
541 struct mv_host_priv {
542 u32 hp_flags;
543 unsigned int board_idx;
544 u32 main_irq_mask;
545 struct mv_port_signal signal[8];
546 const struct mv_hw_ops *ops;
547 int n_ports;
548 void __iomem *base;
549 void __iomem *main_irq_cause_addr;
550 void __iomem *main_irq_mask_addr;
551 u32 irq_cause_offset;
552 u32 irq_mask_offset;
553 u32 unmask_all_irqs;
554
555 #if defined(CONFIG_HAVE_CLK)
556 struct clk *clk;
557 #endif
558 /*
559 * These consistent DMA memory pools give us guaranteed
560 * alignment for hardware-accessed data structures,
561 * and less memory waste in accomplishing the alignment.
562 */
563 struct dma_pool *crqb_pool;
564 struct dma_pool *crpb_pool;
565 struct dma_pool *sg_tbl_pool;
566 };
567
568 struct mv_hw_ops {
569 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
570 unsigned int port);
571 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
572 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
573 void __iomem *mmio);
574 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
575 unsigned int n_hc);
576 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
577 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
578 };
579
580 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
581 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
582 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
583 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
584 static int mv_port_start(struct ata_port *ap);
585 static void mv_port_stop(struct ata_port *ap);
586 static int mv_qc_defer(struct ata_queued_cmd *qc);
587 static void mv_qc_prep(struct ata_queued_cmd *qc);
588 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
589 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
590 static int mv_hardreset(struct ata_link *link, unsigned int *class,
591 unsigned long deadline);
592 static void mv_eh_freeze(struct ata_port *ap);
593 static void mv_eh_thaw(struct ata_port *ap);
594 static void mv6_dev_config(struct ata_device *dev);
595
596 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
597 unsigned int port);
598 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
599 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
600 void __iomem *mmio);
601 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
602 unsigned int n_hc);
603 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
604 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
605
606 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
607 unsigned int port);
608 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
609 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
610 void __iomem *mmio);
611 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
612 unsigned int n_hc);
613 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
614 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
615 void __iomem *mmio);
616 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
617 void __iomem *mmio);
618 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
619 void __iomem *mmio, unsigned int n_hc);
620 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
621 void __iomem *mmio);
622 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
623 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
624 void __iomem *mmio, unsigned int port);
625 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
626 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
627 unsigned int port_no);
628 static int mv_stop_edma(struct ata_port *ap);
629 static int mv_stop_edma_engine(void __iomem *port_mmio);
630 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
631
632 static void mv_pmp_select(struct ata_port *ap, int pmp);
633 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
634 unsigned long deadline);
635 static int mv_softreset(struct ata_link *link, unsigned int *class,
636 unsigned long deadline);
637 static void mv_pmp_error_handler(struct ata_port *ap);
638 static void mv_process_crpb_entries(struct ata_port *ap,
639 struct mv_port_priv *pp);
640
641 static void mv_sff_irq_clear(struct ata_port *ap);
642 static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
643 static void mv_bmdma_setup(struct ata_queued_cmd *qc);
644 static void mv_bmdma_start(struct ata_queued_cmd *qc);
645 static void mv_bmdma_stop(struct ata_queued_cmd *qc);
646 static u8 mv_bmdma_status(struct ata_port *ap);
647 static u8 mv_sff_check_status(struct ata_port *ap);
648
649 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
650 * because we have to allow room for worst case splitting of
651 * PRDs for 64K boundaries in mv_fill_sg().
652 */
653 static struct scsi_host_template mv5_sht = {
654 ATA_BASE_SHT(DRV_NAME),
655 .sg_tablesize = MV_MAX_SG_CT / 2,
656 .dma_boundary = MV_DMA_BOUNDARY,
657 };
658
659 static struct scsi_host_template mv6_sht = {
660 ATA_NCQ_SHT(DRV_NAME),
661 .can_queue = MV_MAX_Q_DEPTH - 1,
662 .sg_tablesize = MV_MAX_SG_CT / 2,
663 .dma_boundary = MV_DMA_BOUNDARY,
664 };
665
666 static struct ata_port_operations mv5_ops = {
667 .inherits = &ata_sff_port_ops,
668
669 .lost_interrupt = ATA_OP_NULL,
670
671 .qc_defer = mv_qc_defer,
672 .qc_prep = mv_qc_prep,
673 .qc_issue = mv_qc_issue,
674
675 .freeze = mv_eh_freeze,
676 .thaw = mv_eh_thaw,
677 .hardreset = mv_hardreset,
678 .error_handler = ata_std_error_handler, /* avoid SFF EH */
679 .post_internal_cmd = ATA_OP_NULL,
680
681 .scr_read = mv5_scr_read,
682 .scr_write = mv5_scr_write,
683
684 .port_start = mv_port_start,
685 .port_stop = mv_port_stop,
686 };
687
688 static struct ata_port_operations mv6_ops = {
689 .inherits = &mv5_ops,
690 .dev_config = mv6_dev_config,
691 .scr_read = mv_scr_read,
692 .scr_write = mv_scr_write,
693
694 .pmp_hardreset = mv_pmp_hardreset,
695 .pmp_softreset = mv_softreset,
696 .softreset = mv_softreset,
697 .error_handler = mv_pmp_error_handler,
698
699 .sff_check_status = mv_sff_check_status,
700 .sff_irq_clear = mv_sff_irq_clear,
701 .check_atapi_dma = mv_check_atapi_dma,
702 .bmdma_setup = mv_bmdma_setup,
703 .bmdma_start = mv_bmdma_start,
704 .bmdma_stop = mv_bmdma_stop,
705 .bmdma_status = mv_bmdma_status,
706 };
707
708 static struct ata_port_operations mv_iie_ops = {
709 .inherits = &mv6_ops,
710 .dev_config = ATA_OP_NULL,
711 .qc_prep = mv_qc_prep_iie,
712 };
713
714 static const struct ata_port_info mv_port_info[] = {
715 { /* chip_504x */
716 .flags = MV_GEN_I_FLAGS,
717 .pio_mask = ATA_PIO4,
718 .udma_mask = ATA_UDMA6,
719 .port_ops = &mv5_ops,
720 },
721 { /* chip_508x */
722 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
723 .pio_mask = ATA_PIO4,
724 .udma_mask = ATA_UDMA6,
725 .port_ops = &mv5_ops,
726 },
727 { /* chip_5080 */
728 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
729 .pio_mask = ATA_PIO4,
730 .udma_mask = ATA_UDMA6,
731 .port_ops = &mv5_ops,
732 },
733 { /* chip_604x */
734 .flags = MV_GEN_II_FLAGS,
735 .pio_mask = ATA_PIO4,
736 .udma_mask = ATA_UDMA6,
737 .port_ops = &mv6_ops,
738 },
739 { /* chip_608x */
740 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
741 .pio_mask = ATA_PIO4,
742 .udma_mask = ATA_UDMA6,
743 .port_ops = &mv6_ops,
744 },
745 { /* chip_6042 */
746 .flags = MV_GEN_IIE_FLAGS,
747 .pio_mask = ATA_PIO4,
748 .udma_mask = ATA_UDMA6,
749 .port_ops = &mv_iie_ops,
750 },
751 { /* chip_7042 */
752 .flags = MV_GEN_IIE_FLAGS,
753 .pio_mask = ATA_PIO4,
754 .udma_mask = ATA_UDMA6,
755 .port_ops = &mv_iie_ops,
756 },
757 { /* chip_soc */
758 .flags = MV_GEN_IIE_FLAGS,
759 .pio_mask = ATA_PIO4,
760 .udma_mask = ATA_UDMA6,
761 .port_ops = &mv_iie_ops,
762 },
763 };
764
765 static const struct pci_device_id mv_pci_tbl[] = {
766 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
767 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
768 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
769 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
770 /* RocketRAID 1720/174x have different identifiers */
771 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
772 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
773 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
774
775 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
776 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
777 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
778 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
779 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
780
781 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
782
783 /* Adaptec 1430SA */
784 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
785
786 /* Marvell 7042 support */
787 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
788
789 /* Highpoint RocketRAID PCIe series */
790 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
791 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
792
793 { } /* terminate list */
794 };
795
796 static const struct mv_hw_ops mv5xxx_ops = {
797 .phy_errata = mv5_phy_errata,
798 .enable_leds = mv5_enable_leds,
799 .read_preamp = mv5_read_preamp,
800 .reset_hc = mv5_reset_hc,
801 .reset_flash = mv5_reset_flash,
802 .reset_bus = mv5_reset_bus,
803 };
804
805 static const struct mv_hw_ops mv6xxx_ops = {
806 .phy_errata = mv6_phy_errata,
807 .enable_leds = mv6_enable_leds,
808 .read_preamp = mv6_read_preamp,
809 .reset_hc = mv6_reset_hc,
810 .reset_flash = mv6_reset_flash,
811 .reset_bus = mv_reset_pci_bus,
812 };
813
814 static const struct mv_hw_ops mv_soc_ops = {
815 .phy_errata = mv6_phy_errata,
816 .enable_leds = mv_soc_enable_leds,
817 .read_preamp = mv_soc_read_preamp,
818 .reset_hc = mv_soc_reset_hc,
819 .reset_flash = mv_soc_reset_flash,
820 .reset_bus = mv_soc_reset_bus,
821 };
822
823 static const struct mv_hw_ops mv_soc_65n_ops = {
824 .phy_errata = mv_soc_65n_phy_errata,
825 .enable_leds = mv_soc_enable_leds,
826 .reset_hc = mv_soc_reset_hc,
827 .reset_flash = mv_soc_reset_flash,
828 .reset_bus = mv_soc_reset_bus,
829 };
830
831 /*
832 * Functions
833 */
834
835 static inline void writelfl(unsigned long data, void __iomem *addr)
836 {
837 writel(data, addr);
838 (void) readl(addr); /* flush to avoid PCI posted write */
839 }
840
841 static inline unsigned int mv_hc_from_port(unsigned int port)
842 {
843 return port >> MV_PORT_HC_SHIFT;
844 }
845
846 static inline unsigned int mv_hardport_from_port(unsigned int port)
847 {
848 return port & MV_PORT_MASK;
849 }
850
851 /*
852 * Consolidate some rather tricky bit shift calculations.
853 * This is hot-path stuff, so not a function.
854 * Simple code, with two return values, so macro rather than inline.
855 *
856 * port is the sole input, in range 0..7.
857 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
858 * hardport is the other output, in range 0..3.
859 *
860 * Note that port and hardport may be the same variable in some cases.
861 */
862 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
863 { \
864 shift = mv_hc_from_port(port) * HC_SHIFT; \
865 hardport = mv_hardport_from_port(port); \
866 shift += hardport * 2; \
867 }
868
869 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
870 {
871 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
872 }
873
874 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
875 unsigned int port)
876 {
877 return mv_hc_base(base, mv_hc_from_port(port));
878 }
879
880 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
881 {
882 return mv_hc_base_from_port(base, port) +
883 MV_SATAHC_ARBTR_REG_SZ +
884 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
885 }
886
887 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
888 {
889 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
890 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
891
892 return hc_mmio + ofs;
893 }
894
895 static inline void __iomem *mv_host_base(struct ata_host *host)
896 {
897 struct mv_host_priv *hpriv = host->private_data;
898 return hpriv->base;
899 }
900
901 static inline void __iomem *mv_ap_base(struct ata_port *ap)
902 {
903 return mv_port_base(mv_host_base(ap->host), ap->port_no);
904 }
905
906 static inline int mv_get_hc_count(unsigned long port_flags)
907 {
908 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
909 }
910
911 /**
912 * mv_save_cached_regs - (re-)initialize cached port registers
913 * @ap: the port whose registers we are caching
914 *
915 * Initialize the local cache of port registers,
916 * so that reading them over and over again can
917 * be avoided on the hotter paths of this driver.
918 * This saves a few microseconds each time we switch
919 * to/from EDMA mode to perform (eg.) a drive cache flush.
920 */
921 static void mv_save_cached_regs(struct ata_port *ap)
922 {
923 void __iomem *port_mmio = mv_ap_base(ap);
924 struct mv_port_priv *pp = ap->private_data;
925
926 pp->cached.fiscfg = readl(port_mmio + FISCFG);
927 pp->cached.ltmode = readl(port_mmio + LTMODE);
928 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
929 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
930 }
931
932 /**
933 * mv_write_cached_reg - write to a cached port register
934 * @addr: hardware address of the register
935 * @old: pointer to cached value of the register
936 * @new: new value for the register
937 *
938 * Write a new value to a cached register,
939 * but only if the value is different from before.
940 */
941 static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
942 {
943 if (new != *old) {
944 unsigned long laddr;
945 *old = new;
946 /*
947 * Workaround for 88SX60x1-B2 FEr SATA#13:
948 * Read-after-write is needed to prevent generating 64-bit
949 * write cycles on the PCI bus for SATA interface registers
950 * at offsets ending in 0x4 or 0xc.
951 *
952 * Looks like a lot of fuss, but it avoids an unnecessary
953 * +1 usec read-after-write delay for unaffected registers.
954 */
955 laddr = (long)addr & 0xffff;
956 if (laddr >= 0x300 && laddr <= 0x33c) {
957 laddr &= 0x000f;
958 if (laddr == 0x4 || laddr == 0xc) {
959 writelfl(new, addr); /* read after write */
960 return;
961 }
962 }
963 writel(new, addr); /* unaffected by the errata */
964 }
965 }
966
967 static void mv_set_edma_ptrs(void __iomem *port_mmio,
968 struct mv_host_priv *hpriv,
969 struct mv_port_priv *pp)
970 {
971 u32 index;
972
973 /*
974 * initialize request queue
975 */
976 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
977 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
978
979 WARN_ON(pp->crqb_dma & 0x3ff);
980 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
981 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
982 port_mmio + EDMA_REQ_Q_IN_PTR);
983 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
984
985 /*
986 * initialize response queue
987 */
988 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
989 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
990
991 WARN_ON(pp->crpb_dma & 0xff);
992 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
993 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
994 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
995 port_mmio + EDMA_RSP_Q_OUT_PTR);
996 }
997
998 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
999 {
1000 /*
1001 * When writing to the main_irq_mask in hardware,
1002 * we must ensure exclusivity between the interrupt coalescing bits
1003 * and the corresponding individual port DONE_IRQ bits.
1004 *
1005 * Note that this register is really an "IRQ enable" register,
1006 * not an "IRQ mask" register as Marvell's naming might suggest.
1007 */
1008 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
1009 mask &= ~DONE_IRQ_0_3;
1010 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
1011 mask &= ~DONE_IRQ_4_7;
1012 writelfl(mask, hpriv->main_irq_mask_addr);
1013 }
1014
1015 static void mv_set_main_irq_mask(struct ata_host *host,
1016 u32 disable_bits, u32 enable_bits)
1017 {
1018 struct mv_host_priv *hpriv = host->private_data;
1019 u32 old_mask, new_mask;
1020
1021 old_mask = hpriv->main_irq_mask;
1022 new_mask = (old_mask & ~disable_bits) | enable_bits;
1023 if (new_mask != old_mask) {
1024 hpriv->main_irq_mask = new_mask;
1025 mv_write_main_irq_mask(new_mask, hpriv);
1026 }
1027 }
1028
1029 static void mv_enable_port_irqs(struct ata_port *ap,
1030 unsigned int port_bits)
1031 {
1032 unsigned int shift, hardport, port = ap->port_no;
1033 u32 disable_bits, enable_bits;
1034
1035 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1036
1037 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
1038 enable_bits = port_bits << shift;
1039 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1040 }
1041
1042 static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
1043 void __iomem *port_mmio,
1044 unsigned int port_irqs)
1045 {
1046 struct mv_host_priv *hpriv = ap->host->private_data;
1047 int hardport = mv_hardport_from_port(ap->port_no);
1048 void __iomem *hc_mmio = mv_hc_base_from_port(
1049 mv_host_base(ap->host), ap->port_no);
1050 u32 hc_irq_cause;
1051
1052 /* clear EDMA event indicators, if any */
1053 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
1054
1055 /* clear pending irq events */
1056 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1057 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
1058
1059 /* clear FIS IRQ Cause */
1060 if (IS_GEN_IIE(hpriv))
1061 writelfl(0, port_mmio + FIS_IRQ_CAUSE);
1062
1063 mv_enable_port_irqs(ap, port_irqs);
1064 }
1065
1066 static void mv_set_irq_coalescing(struct ata_host *host,
1067 unsigned int count, unsigned int usecs)
1068 {
1069 struct mv_host_priv *hpriv = host->private_data;
1070 void __iomem *mmio = hpriv->base, *hc_mmio;
1071 u32 coal_enable = 0;
1072 unsigned long flags;
1073 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
1074 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1075 ALL_PORTS_COAL_DONE;
1076
1077 /* Disable IRQ coalescing if either threshold is zero */
1078 if (!usecs || !count) {
1079 clks = count = 0;
1080 } else {
1081 /* Respect maximum limits of the hardware */
1082 clks = usecs * COAL_CLOCKS_PER_USEC;
1083 if (clks > MAX_COAL_TIME_THRESHOLD)
1084 clks = MAX_COAL_TIME_THRESHOLD;
1085 if (count > MAX_COAL_IO_COUNT)
1086 count = MAX_COAL_IO_COUNT;
1087 }
1088
1089 spin_lock_irqsave(&host->lock, flags);
1090 mv_set_main_irq_mask(host, coal_disable, 0);
1091
1092 if (is_dual_hc && !IS_GEN_I(hpriv)) {
1093 /*
1094 * GEN_II/GEN_IIE with dual host controllers:
1095 * one set of global thresholds for the entire chip.
1096 */
1097 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
1098 writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
1099 /* clear leftover coal IRQ bit */
1100 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
1101 if (count)
1102 coal_enable = ALL_PORTS_COAL_DONE;
1103 clks = count = 0; /* force clearing of regular regs below */
1104 }
1105
1106 /*
1107 * All chips: independent thresholds for each HC on the chip.
1108 */
1109 hc_mmio = mv_hc_base_from_port(mmio, 0);
1110 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1111 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1112 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1113 if (count)
1114 coal_enable |= PORTS_0_3_COAL_DONE;
1115 if (is_dual_hc) {
1116 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
1117 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1118 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1119 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
1120 if (count)
1121 coal_enable |= PORTS_4_7_COAL_DONE;
1122 }
1123
1124 mv_set_main_irq_mask(host, 0, coal_enable);
1125 spin_unlock_irqrestore(&host->lock, flags);
1126 }
1127
1128 /**
1129 * mv_start_edma - Enable eDMA engine
1130 * @base: port base address
1131 * @pp: port private data
1132 *
1133 * Verify the local cache of the eDMA state is accurate with a
1134 * WARN_ON.
1135 *
1136 * LOCKING:
1137 * Inherited from caller.
1138 */
1139 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
1140 struct mv_port_priv *pp, u8 protocol)
1141 {
1142 int want_ncq = (protocol == ATA_PROT_NCQ);
1143
1144 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1145 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1146 if (want_ncq != using_ncq)
1147 mv_stop_edma(ap);
1148 }
1149 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1150 struct mv_host_priv *hpriv = ap->host->private_data;
1151
1152 mv_edma_cfg(ap, want_ncq, 1);
1153
1154 mv_set_edma_ptrs(port_mmio, hpriv, pp);
1155 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
1156
1157 writelfl(EDMA_EN, port_mmio + EDMA_CMD);
1158 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1159 }
1160 }
1161
1162 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1163 {
1164 void __iomem *port_mmio = mv_ap_base(ap);
1165 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1166 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1167 int i;
1168
1169 /*
1170 * Wait for the EDMA engine to finish transactions in progress.
1171 * No idea what a good "timeout" value might be, but measurements
1172 * indicate that it often requires hundreds of microseconds
1173 * with two drives in-use. So we use the 15msec value above
1174 * as a rough guess at what even more drives might require.
1175 */
1176 for (i = 0; i < timeout; ++i) {
1177 u32 edma_stat = readl(port_mmio + EDMA_STATUS);
1178 if ((edma_stat & empty_idle) == empty_idle)
1179 break;
1180 udelay(per_loop);
1181 }
1182 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
1183 }
1184
1185 /**
1186 * mv_stop_edma_engine - Disable eDMA engine
1187 * @port_mmio: io base address
1188 *
1189 * LOCKING:
1190 * Inherited from caller.
1191 */
1192 static int mv_stop_edma_engine(void __iomem *port_mmio)
1193 {
1194 int i;
1195
1196 /* Disable eDMA. The disable bit auto clears. */
1197 writelfl(EDMA_DS, port_mmio + EDMA_CMD);
1198
1199 /* Wait for the chip to confirm eDMA is off. */
1200 for (i = 10000; i > 0; i--) {
1201 u32 reg = readl(port_mmio + EDMA_CMD);
1202 if (!(reg & EDMA_EN))
1203 return 0;
1204 udelay(10);
1205 }
1206 return -EIO;
1207 }
1208
1209 static int mv_stop_edma(struct ata_port *ap)
1210 {
1211 void __iomem *port_mmio = mv_ap_base(ap);
1212 struct mv_port_priv *pp = ap->private_data;
1213 int err = 0;
1214
1215 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1216 return 0;
1217 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1218 mv_wait_for_edma_empty_idle(ap);
1219 if (mv_stop_edma_engine(port_mmio)) {
1220 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
1221 err = -EIO;
1222 }
1223 mv_edma_cfg(ap, 0, 0);
1224 return err;
1225 }
1226
1227 #ifdef ATA_DEBUG
1228 static void mv_dump_mem(void __iomem *start, unsigned bytes)
1229 {
1230 int b, w;
1231 for (b = 0; b < bytes; ) {
1232 DPRINTK("%p: ", start + b);
1233 for (w = 0; b < bytes && w < 4; w++) {
1234 printk("%08x ", readl(start + b));
1235 b += sizeof(u32);
1236 }
1237 printk("\n");
1238 }
1239 }
1240 #endif
1241
1242 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1243 {
1244 #ifdef ATA_DEBUG
1245 int b, w;
1246 u32 dw;
1247 for (b = 0; b < bytes; ) {
1248 DPRINTK("%02x: ", b);
1249 for (w = 0; b < bytes && w < 4; w++) {
1250 (void) pci_read_config_dword(pdev, b, &dw);
1251 printk("%08x ", dw);
1252 b += sizeof(u32);
1253 }
1254 printk("\n");
1255 }
1256 #endif
1257 }
1258 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1259 struct pci_dev *pdev)
1260 {
1261 #ifdef ATA_DEBUG
1262 void __iomem *hc_base = mv_hc_base(mmio_base,
1263 port >> MV_PORT_HC_SHIFT);
1264 void __iomem *port_base;
1265 int start_port, num_ports, p, start_hc, num_hcs, hc;
1266
1267 if (0 > port) {
1268 start_hc = start_port = 0;
1269 num_ports = 8; /* shld be benign for 4 port devs */
1270 num_hcs = 2;
1271 } else {
1272 start_hc = port >> MV_PORT_HC_SHIFT;
1273 start_port = port;
1274 num_ports = num_hcs = 1;
1275 }
1276 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1277 num_ports > 1 ? num_ports - 1 : start_port);
1278
1279 if (NULL != pdev) {
1280 DPRINTK("PCI config space regs:\n");
1281 mv_dump_pci_cfg(pdev, 0x68);
1282 }
1283 DPRINTK("PCI regs:\n");
1284 mv_dump_mem(mmio_base+0xc00, 0x3c);
1285 mv_dump_mem(mmio_base+0xd00, 0x34);
1286 mv_dump_mem(mmio_base+0xf00, 0x4);
1287 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1288 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1289 hc_base = mv_hc_base(mmio_base, hc);
1290 DPRINTK("HC regs (HC %i):\n", hc);
1291 mv_dump_mem(hc_base, 0x1c);
1292 }
1293 for (p = start_port; p < start_port + num_ports; p++) {
1294 port_base = mv_port_base(mmio_base, p);
1295 DPRINTK("EDMA regs (port %i):\n", p);
1296 mv_dump_mem(port_base, 0x54);
1297 DPRINTK("SATA regs (port %i):\n", p);
1298 mv_dump_mem(port_base+0x300, 0x60);
1299 }
1300 #endif
1301 }
1302
1303 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1304 {
1305 unsigned int ofs;
1306
1307 switch (sc_reg_in) {
1308 case SCR_STATUS:
1309 case SCR_CONTROL:
1310 case SCR_ERROR:
1311 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
1312 break;
1313 case SCR_ACTIVE:
1314 ofs = SATA_ACTIVE; /* active is not with the others */
1315 break;
1316 default:
1317 ofs = 0xffffffffU;
1318 break;
1319 }
1320 return ofs;
1321 }
1322
1323 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
1324 {
1325 unsigned int ofs = mv_scr_offset(sc_reg_in);
1326
1327 if (ofs != 0xffffffffU) {
1328 *val = readl(mv_ap_base(link->ap) + ofs);
1329 return 0;
1330 } else
1331 return -EINVAL;
1332 }
1333
1334 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1335 {
1336 unsigned int ofs = mv_scr_offset(sc_reg_in);
1337
1338 if (ofs != 0xffffffffU) {
1339 void __iomem *addr = mv_ap_base(link->ap) + ofs;
1340 if (sc_reg_in == SCR_CONTROL) {
1341 /*
1342 * Workaround for 88SX60x1 FEr SATA#26:
1343 *
1344 * COMRESETs have to take care not to accidently
1345 * put the drive to sleep when writing SCR_CONTROL.
1346 * Setting bits 12..15 prevents this problem.
1347 *
1348 * So if we see an outbound COMMRESET, set those bits.
1349 * Ditto for the followup write that clears the reset.
1350 *
1351 * The proprietary driver does this for
1352 * all chip versions, and so do we.
1353 */
1354 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1355 val |= 0xf000;
1356 }
1357 writelfl(val, addr);
1358 return 0;
1359 } else
1360 return -EINVAL;
1361 }
1362
1363 static void mv6_dev_config(struct ata_device *adev)
1364 {
1365 /*
1366 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1367 *
1368 * Gen-II does not support NCQ over a port multiplier
1369 * (no FIS-based switching).
1370 */
1371 if (adev->flags & ATA_DFLAG_NCQ) {
1372 if (sata_pmp_attached(adev->link->ap)) {
1373 adev->flags &= ~ATA_DFLAG_NCQ;
1374 ata_dev_printk(adev, KERN_INFO,
1375 "NCQ disabled for command-based switching\n");
1376 }
1377 }
1378 }
1379
1380 static int mv_qc_defer(struct ata_queued_cmd *qc)
1381 {
1382 struct ata_link *link = qc->dev->link;
1383 struct ata_port *ap = link->ap;
1384 struct mv_port_priv *pp = ap->private_data;
1385
1386 /*
1387 * Don't allow new commands if we're in a delayed EH state
1388 * for NCQ and/or FIS-based switching.
1389 */
1390 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1391 return ATA_DEFER_PORT;
1392
1393 /* PIO commands need exclusive link: no other commands [DMA or PIO]
1394 * can run concurrently.
1395 * set excl_link when we want to send a PIO command in DMA mode
1396 * or a non-NCQ command in NCQ mode.
1397 * When we receive a command from that link, and there are no
1398 * outstanding commands, mark a flag to clear excl_link and let
1399 * the command go through.
1400 */
1401 if (unlikely(ap->excl_link)) {
1402 if (link == ap->excl_link) {
1403 if (ap->nr_active_links)
1404 return ATA_DEFER_PORT;
1405 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
1406 return 0;
1407 } else
1408 return ATA_DEFER_PORT;
1409 }
1410
1411 /*
1412 * If the port is completely idle, then allow the new qc.
1413 */
1414 if (ap->nr_active_links == 0)
1415 return 0;
1416
1417 /*
1418 * The port is operating in host queuing mode (EDMA) with NCQ
1419 * enabled, allow multiple NCQ commands. EDMA also allows
1420 * queueing multiple DMA commands but libata core currently
1421 * doesn't allow it.
1422 */
1423 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1424 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
1425 if (ata_is_ncq(qc->tf.protocol))
1426 return 0;
1427 else {
1428 ap->excl_link = link;
1429 return ATA_DEFER_PORT;
1430 }
1431 }
1432
1433 return ATA_DEFER_PORT;
1434 }
1435
1436 static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
1437 {
1438 struct mv_port_priv *pp = ap->private_data;
1439 void __iomem *port_mmio;
1440
1441 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1442 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1443 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
1444
1445 ltmode = *old_ltmode & ~LTMODE_BIT8;
1446 haltcond = *old_haltcond | EDMA_ERR_DEV;
1447
1448 if (want_fbs) {
1449 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1450 ltmode = *old_ltmode | LTMODE_BIT8;
1451 if (want_ncq)
1452 haltcond &= ~EDMA_ERR_DEV;
1453 else
1454 fiscfg |= FISCFG_WAIT_DEV_ERR;
1455 } else {
1456 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1457 }
1458
1459 port_mmio = mv_ap_base(ap);
1460 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
1461 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
1462 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
1463 }
1464
1465 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1466 {
1467 struct mv_host_priv *hpriv = ap->host->private_data;
1468 u32 old, new;
1469
1470 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1471 old = readl(hpriv->base + GPIO_PORT_CTL);
1472 if (want_ncq)
1473 new = old | (1 << 22);
1474 else
1475 new = old & ~(1 << 22);
1476 if (new != old)
1477 writel(new, hpriv->base + GPIO_PORT_CTL);
1478 }
1479
1480 /**
1481 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1482 * @ap: Port being initialized
1483 *
1484 * There are two DMA modes on these chips: basic DMA, and EDMA.
1485 *
1486 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1487 * of basic DMA on the GEN_IIE versions of the chips.
1488 *
1489 * This bit survives EDMA resets, and must be set for basic DMA
1490 * to function, and should be cleared when EDMA is active.
1491 */
1492 static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1493 {
1494 struct mv_port_priv *pp = ap->private_data;
1495 u32 new, *old = &pp->cached.unknown_rsvd;
1496
1497 if (enable_bmdma)
1498 new = *old | 1;
1499 else
1500 new = *old & ~1;
1501 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
1502 }
1503
1504 /*
1505 * SOC chips have an issue whereby the HDD LEDs don't always blink
1506 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1507 * of the SOC takes care of it, generating a steady blink rate when
1508 * any drive on the chip is active.
1509 *
1510 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1511 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1512 *
1513 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1514 * LED operation works then, and provides better (more accurate) feedback.
1515 *
1516 * Note that this code assumes that an SOC never has more than one HC onboard.
1517 */
1518 static void mv_soc_led_blink_enable(struct ata_port *ap)
1519 {
1520 struct ata_host *host = ap->host;
1521 struct mv_host_priv *hpriv = host->private_data;
1522 void __iomem *hc_mmio;
1523 u32 led_ctrl;
1524
1525 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1526 return;
1527 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1528 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1529 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1530 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1531 }
1532
1533 static void mv_soc_led_blink_disable(struct ata_port *ap)
1534 {
1535 struct ata_host *host = ap->host;
1536 struct mv_host_priv *hpriv = host->private_data;
1537 void __iomem *hc_mmio;
1538 u32 led_ctrl;
1539 unsigned int port;
1540
1541 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1542 return;
1543
1544 /* disable led-blink only if no ports are using NCQ */
1545 for (port = 0; port < hpriv->n_ports; port++) {
1546 struct ata_port *this_ap = host->ports[port];
1547 struct mv_port_priv *pp = this_ap->private_data;
1548
1549 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1550 return;
1551 }
1552
1553 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1554 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1555 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1556 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
1557 }
1558
1559 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
1560 {
1561 u32 cfg;
1562 struct mv_port_priv *pp = ap->private_data;
1563 struct mv_host_priv *hpriv = ap->host->private_data;
1564 void __iomem *port_mmio = mv_ap_base(ap);
1565
1566 /* set up non-NCQ EDMA configuration */
1567 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1568 pp->pp_flags &=
1569 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
1570
1571 if (IS_GEN_I(hpriv))
1572 cfg |= (1 << 8); /* enab config burst size mask */
1573
1574 else if (IS_GEN_II(hpriv)) {
1575 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1576 mv_60x1_errata_sata25(ap, want_ncq);
1577
1578 } else if (IS_GEN_IIE(hpriv)) {
1579 int want_fbs = sata_pmp_attached(ap);
1580 /*
1581 * Possible future enhancement:
1582 *
1583 * The chip can use FBS with non-NCQ, if we allow it,
1584 * But first we need to have the error handling in place
1585 * for this mode (datasheet section 7.3.15.4.2.3).
1586 * So disallow non-NCQ FBS for now.
1587 */
1588 want_fbs &= want_ncq;
1589
1590 mv_config_fbs(ap, want_ncq, want_fbs);
1591
1592 if (want_fbs) {
1593 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1594 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1595 }
1596
1597 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1598 if (want_edma) {
1599 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1600 if (!IS_SOC(hpriv))
1601 cfg |= (1 << 18); /* enab early completion */
1602 }
1603 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1604 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1605 mv_bmdma_enable_iie(ap, !want_edma);
1606
1607 if (IS_SOC(hpriv)) {
1608 if (want_ncq)
1609 mv_soc_led_blink_enable(ap);
1610 else
1611 mv_soc_led_blink_disable(ap);
1612 }
1613 }
1614
1615 if (want_ncq) {
1616 cfg |= EDMA_CFG_NCQ;
1617 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1618 }
1619
1620 writelfl(cfg, port_mmio + EDMA_CFG);
1621 }
1622
1623 static void mv_port_free_dma_mem(struct ata_port *ap)
1624 {
1625 struct mv_host_priv *hpriv = ap->host->private_data;
1626 struct mv_port_priv *pp = ap->private_data;
1627 int tag;
1628
1629 if (pp->crqb) {
1630 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1631 pp->crqb = NULL;
1632 }
1633 if (pp->crpb) {
1634 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1635 pp->crpb = NULL;
1636 }
1637 /*
1638 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1639 * For later hardware, we have one unique sg_tbl per NCQ tag.
1640 */
1641 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1642 if (pp->sg_tbl[tag]) {
1643 if (tag == 0 || !IS_GEN_I(hpriv))
1644 dma_pool_free(hpriv->sg_tbl_pool,
1645 pp->sg_tbl[tag],
1646 pp->sg_tbl_dma[tag]);
1647 pp->sg_tbl[tag] = NULL;
1648 }
1649 }
1650 }
1651
1652 /**
1653 * mv_port_start - Port specific init/start routine.
1654 * @ap: ATA channel to manipulate
1655 *
1656 * Allocate and point to DMA memory, init port private memory,
1657 * zero indices.
1658 *
1659 * LOCKING:
1660 * Inherited from caller.
1661 */
1662 static int mv_port_start(struct ata_port *ap)
1663 {
1664 struct device *dev = ap->host->dev;
1665 struct mv_host_priv *hpriv = ap->host->private_data;
1666 struct mv_port_priv *pp;
1667 unsigned long flags;
1668 int tag;
1669
1670 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1671 if (!pp)
1672 return -ENOMEM;
1673 ap->private_data = pp;
1674
1675 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1676 if (!pp->crqb)
1677 return -ENOMEM;
1678 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1679
1680 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1681 if (!pp->crpb)
1682 goto out_port_free_dma_mem;
1683 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1684
1685 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1686 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1687 ap->flags |= ATA_FLAG_AN;
1688 /*
1689 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1690 * For later hardware, we need one unique sg_tbl per NCQ tag.
1691 */
1692 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1693 if (tag == 0 || !IS_GEN_I(hpriv)) {
1694 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1695 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1696 if (!pp->sg_tbl[tag])
1697 goto out_port_free_dma_mem;
1698 } else {
1699 pp->sg_tbl[tag] = pp->sg_tbl[0];
1700 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1701 }
1702 }
1703
1704 spin_lock_irqsave(ap->lock, flags);
1705 mv_save_cached_regs(ap);
1706 mv_edma_cfg(ap, 0, 0);
1707 spin_unlock_irqrestore(ap->lock, flags);
1708
1709 return 0;
1710
1711 out_port_free_dma_mem:
1712 mv_port_free_dma_mem(ap);
1713 return -ENOMEM;
1714 }
1715
1716 /**
1717 * mv_port_stop - Port specific cleanup/stop routine.
1718 * @ap: ATA channel to manipulate
1719 *
1720 * Stop DMA, cleanup port memory.
1721 *
1722 * LOCKING:
1723 * This routine uses the host lock to protect the DMA stop.
1724 */
1725 static void mv_port_stop(struct ata_port *ap)
1726 {
1727 unsigned long flags;
1728
1729 spin_lock_irqsave(ap->lock, flags);
1730 mv_stop_edma(ap);
1731 mv_enable_port_irqs(ap, 0);
1732 spin_unlock_irqrestore(ap->lock, flags);
1733 mv_port_free_dma_mem(ap);
1734 }
1735
1736 /**
1737 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1738 * @qc: queued command whose SG list to source from
1739 *
1740 * Populate the SG list and mark the last entry.
1741 *
1742 * LOCKING:
1743 * Inherited from caller.
1744 */
1745 static void mv_fill_sg(struct ata_queued_cmd *qc)
1746 {
1747 struct mv_port_priv *pp = qc->ap->private_data;
1748 struct scatterlist *sg;
1749 struct mv_sg *mv_sg, *last_sg = NULL;
1750 unsigned int si;
1751
1752 mv_sg = pp->sg_tbl[qc->tag];
1753 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1754 dma_addr_t addr = sg_dma_address(sg);
1755 u32 sg_len = sg_dma_len(sg);
1756
1757 while (sg_len) {
1758 u32 offset = addr & 0xffff;
1759 u32 len = sg_len;
1760
1761 if (offset + len > 0x10000)
1762 len = 0x10000 - offset;
1763
1764 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1765 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1766 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1767 mv_sg->reserved = 0;
1768
1769 sg_len -= len;
1770 addr += len;
1771
1772 last_sg = mv_sg;
1773 mv_sg++;
1774 }
1775 }
1776
1777 if (likely(last_sg))
1778 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1779 mb(); /* ensure data structure is visible to the chipset */
1780 }
1781
1782 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1783 {
1784 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1785 (last ? CRQB_CMD_LAST : 0);
1786 *cmdw = cpu_to_le16(tmp);
1787 }
1788
1789 /**
1790 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1791 * @ap: Port associated with this ATA transaction.
1792 *
1793 * We need this only for ATAPI bmdma transactions,
1794 * as otherwise we experience spurious interrupts
1795 * after libata-sff handles the bmdma interrupts.
1796 */
1797 static void mv_sff_irq_clear(struct ata_port *ap)
1798 {
1799 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1800 }
1801
1802 /**
1803 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1804 * @qc: queued command to check for chipset/DMA compatibility.
1805 *
1806 * The bmdma engines cannot handle speculative data sizes
1807 * (bytecount under/over flow). So only allow DMA for
1808 * data transfer commands with known data sizes.
1809 *
1810 * LOCKING:
1811 * Inherited from caller.
1812 */
1813 static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1814 {
1815 struct scsi_cmnd *scmd = qc->scsicmd;
1816
1817 if (scmd) {
1818 switch (scmd->cmnd[0]) {
1819 case READ_6:
1820 case READ_10:
1821 case READ_12:
1822 case WRITE_6:
1823 case WRITE_10:
1824 case WRITE_12:
1825 case GPCMD_READ_CD:
1826 case GPCMD_SEND_DVD_STRUCTURE:
1827 case GPCMD_SEND_CUE_SHEET:
1828 return 0; /* DMA is safe */
1829 }
1830 }
1831 return -EOPNOTSUPP; /* use PIO instead */
1832 }
1833
1834 /**
1835 * mv_bmdma_setup - Set up BMDMA transaction
1836 * @qc: queued command to prepare DMA for.
1837 *
1838 * LOCKING:
1839 * Inherited from caller.
1840 */
1841 static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1842 {
1843 struct ata_port *ap = qc->ap;
1844 void __iomem *port_mmio = mv_ap_base(ap);
1845 struct mv_port_priv *pp = ap->private_data;
1846
1847 mv_fill_sg(qc);
1848
1849 /* clear all DMA cmd bits */
1850 writel(0, port_mmio + BMDMA_CMD);
1851
1852 /* load PRD table addr. */
1853 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1854 port_mmio + BMDMA_PRD_HIGH);
1855 writelfl(pp->sg_tbl_dma[qc->tag],
1856 port_mmio + BMDMA_PRD_LOW);
1857
1858 /* issue r/w command */
1859 ap->ops->sff_exec_command(ap, &qc->tf);
1860 }
1861
1862 /**
1863 * mv_bmdma_start - Start a BMDMA transaction
1864 * @qc: queued command to start DMA on.
1865 *
1866 * LOCKING:
1867 * Inherited from caller.
1868 */
1869 static void mv_bmdma_start(struct ata_queued_cmd *qc)
1870 {
1871 struct ata_port *ap = qc->ap;
1872 void __iomem *port_mmio = mv_ap_base(ap);
1873 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1874 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1875
1876 /* start host DMA transaction */
1877 writelfl(cmd, port_mmio + BMDMA_CMD);
1878 }
1879
1880 /**
1881 * mv_bmdma_stop - Stop BMDMA transfer
1882 * @qc: queued command to stop DMA on.
1883 *
1884 * Clears the ATA_DMA_START flag in the bmdma control register
1885 *
1886 * LOCKING:
1887 * Inherited from caller.
1888 */
1889 static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1890 {
1891 struct ata_port *ap = qc->ap;
1892 void __iomem *port_mmio = mv_ap_base(ap);
1893 u32 cmd;
1894
1895 /* clear start/stop bit */
1896 cmd = readl(port_mmio + BMDMA_CMD);
1897 cmd &= ~ATA_DMA_START;
1898 writelfl(cmd, port_mmio + BMDMA_CMD);
1899
1900 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1901 ata_sff_dma_pause(ap);
1902 }
1903
1904 /**
1905 * mv_bmdma_status - Read BMDMA status
1906 * @ap: port for which to retrieve DMA status.
1907 *
1908 * Read and return equivalent of the sff BMDMA status register.
1909 *
1910 * LOCKING:
1911 * Inherited from caller.
1912 */
1913 static u8 mv_bmdma_status(struct ata_port *ap)
1914 {
1915 void __iomem *port_mmio = mv_ap_base(ap);
1916 u32 reg, status;
1917
1918 /*
1919 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1920 * and the ATA_DMA_INTR bit doesn't exist.
1921 */
1922 reg = readl(port_mmio + BMDMA_STATUS);
1923 if (reg & ATA_DMA_ACTIVE)
1924 status = ATA_DMA_ACTIVE;
1925 else
1926 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1927 return status;
1928 }
1929
1930 static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
1931 {
1932 struct ata_taskfile *tf = &qc->tf;
1933 /*
1934 * Workaround for 88SX60x1 FEr SATA#24.
1935 *
1936 * Chip may corrupt WRITEs if multi_count >= 4kB.
1937 * Note that READs are unaffected.
1938 *
1939 * It's not clear if this errata really means "4K bytes",
1940 * or if it always happens for multi_count > 7
1941 * regardless of device sector_size.
1942 *
1943 * So, for safety, any write with multi_count > 7
1944 * gets converted here into a regular PIO write instead:
1945 */
1946 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
1947 if (qc->dev->multi_count > 7) {
1948 switch (tf->command) {
1949 case ATA_CMD_WRITE_MULTI:
1950 tf->command = ATA_CMD_PIO_WRITE;
1951 break;
1952 case ATA_CMD_WRITE_MULTI_FUA_EXT:
1953 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
1954 /* fall through */
1955 case ATA_CMD_WRITE_MULTI_EXT:
1956 tf->command = ATA_CMD_PIO_WRITE_EXT;
1957 break;
1958 }
1959 }
1960 }
1961 }
1962
1963 /**
1964 * mv_qc_prep - Host specific command preparation.
1965 * @qc: queued command to prepare
1966 *
1967 * This routine simply redirects to the general purpose routine
1968 * if command is not DMA. Else, it handles prep of the CRQB
1969 * (command request block), does some sanity checking, and calls
1970 * the SG load routine.
1971 *
1972 * LOCKING:
1973 * Inherited from caller.
1974 */
1975 static void mv_qc_prep(struct ata_queued_cmd *qc)
1976 {
1977 struct ata_port *ap = qc->ap;
1978 struct mv_port_priv *pp = ap->private_data;
1979 __le16 *cw;
1980 struct ata_taskfile *tf = &qc->tf;
1981 u16 flags = 0;
1982 unsigned in_index;
1983
1984 switch (tf->protocol) {
1985 case ATA_PROT_DMA:
1986 case ATA_PROT_NCQ:
1987 break; /* continue below */
1988 case ATA_PROT_PIO:
1989 mv_rw_multi_errata_sata24(qc);
1990 return;
1991 default:
1992 return;
1993 }
1994
1995 /* Fill in command request block
1996 */
1997 if (!(tf->flags & ATA_TFLAG_WRITE))
1998 flags |= CRQB_FLAG_READ;
1999 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2000 flags |= qc->tag << CRQB_TAG_SHIFT;
2001 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2002
2003 /* get current queue index from software */
2004 in_index = pp->req_idx;
2005
2006 pp->crqb[in_index].sg_addr =
2007 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2008 pp->crqb[in_index].sg_addr_hi =
2009 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2010 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
2011
2012 cw = &pp->crqb[in_index].ata_cmd[0];
2013
2014 /* Sadly, the CRQB cannot accomodate all registers--there are
2015 * only 11 bytes...so we must pick and choose required
2016 * registers based on the command. So, we drop feature and
2017 * hob_feature for [RW] DMA commands, but they are needed for
2018 * NCQ. NCQ will drop hob_nsect, which is not needed there
2019 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
2020 */
2021 switch (tf->command) {
2022 case ATA_CMD_READ:
2023 case ATA_CMD_READ_EXT:
2024 case ATA_CMD_WRITE:
2025 case ATA_CMD_WRITE_EXT:
2026 case ATA_CMD_WRITE_FUA_EXT:
2027 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
2028 break;
2029 case ATA_CMD_FPDMA_READ:
2030 case ATA_CMD_FPDMA_WRITE:
2031 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
2032 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
2033 break;
2034 default:
2035 /* The only other commands EDMA supports in non-queued and
2036 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
2037 * of which are defined/used by Linux. If we get here, this
2038 * driver needs work.
2039 *
2040 * FIXME: modify libata to give qc_prep a return value and
2041 * return error here.
2042 */
2043 BUG_ON(tf->command);
2044 break;
2045 }
2046 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
2047 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
2048 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
2049 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
2050 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
2051 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
2052 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
2053 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
2054 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
2055
2056 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2057 return;
2058 mv_fill_sg(qc);
2059 }
2060
2061 /**
2062 * mv_qc_prep_iie - Host specific command preparation.
2063 * @qc: queued command to prepare
2064 *
2065 * This routine simply redirects to the general purpose routine
2066 * if command is not DMA. Else, it handles prep of the CRQB
2067 * (command request block), does some sanity checking, and calls
2068 * the SG load routine.
2069 *
2070 * LOCKING:
2071 * Inherited from caller.
2072 */
2073 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
2074 {
2075 struct ata_port *ap = qc->ap;
2076 struct mv_port_priv *pp = ap->private_data;
2077 struct mv_crqb_iie *crqb;
2078 struct ata_taskfile *tf = &qc->tf;
2079 unsigned in_index;
2080 u32 flags = 0;
2081
2082 if ((tf->protocol != ATA_PROT_DMA) &&
2083 (tf->protocol != ATA_PROT_NCQ))
2084 return;
2085
2086 /* Fill in Gen IIE command request block */
2087 if (!(tf->flags & ATA_TFLAG_WRITE))
2088 flags |= CRQB_FLAG_READ;
2089
2090 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2091 flags |= qc->tag << CRQB_TAG_SHIFT;
2092 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
2093 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2094
2095 /* get current queue index from software */
2096 in_index = pp->req_idx;
2097
2098 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
2099 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2100 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2101 crqb->flags = cpu_to_le32(flags);
2102
2103 crqb->ata_cmd[0] = cpu_to_le32(
2104 (tf->command << 16) |
2105 (tf->feature << 24)
2106 );
2107 crqb->ata_cmd[1] = cpu_to_le32(
2108 (tf->lbal << 0) |
2109 (tf->lbam << 8) |
2110 (tf->lbah << 16) |
2111 (tf->device << 24)
2112 );
2113 crqb->ata_cmd[2] = cpu_to_le32(
2114 (tf->hob_lbal << 0) |
2115 (tf->hob_lbam << 8) |
2116 (tf->hob_lbah << 16) |
2117 (tf->hob_feature << 24)
2118 );
2119 crqb->ata_cmd[3] = cpu_to_le32(
2120 (tf->nsect << 0) |
2121 (tf->hob_nsect << 8)
2122 );
2123
2124 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2125 return;
2126 mv_fill_sg(qc);
2127 }
2128
2129 /**
2130 * mv_sff_check_status - fetch device status, if valid
2131 * @ap: ATA port to fetch status from
2132 *
2133 * When using command issue via mv_qc_issue_fis(),
2134 * the initial ATA_BUSY state does not show up in the
2135 * ATA status (shadow) register. This can confuse libata!
2136 *
2137 * So we have a hook here to fake ATA_BUSY for that situation,
2138 * until the first time a BUSY, DRQ, or ERR bit is seen.
2139 *
2140 * The rest of the time, it simply returns the ATA status register.
2141 */
2142 static u8 mv_sff_check_status(struct ata_port *ap)
2143 {
2144 u8 stat = ioread8(ap->ioaddr.status_addr);
2145 struct mv_port_priv *pp = ap->private_data;
2146
2147 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2148 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2149 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2150 else
2151 stat = ATA_BUSY;
2152 }
2153 return stat;
2154 }
2155
2156 /**
2157 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2158 * @fis: fis to be sent
2159 * @nwords: number of 32-bit words in the fis
2160 */
2161 static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2162 {
2163 void __iomem *port_mmio = mv_ap_base(ap);
2164 u32 ifctl, old_ifctl, ifstat;
2165 int i, timeout = 200, final_word = nwords - 1;
2166
2167 /* Initiate FIS transmission mode */
2168 old_ifctl = readl(port_mmio + SATA_IFCTL);
2169 ifctl = 0x100 | (old_ifctl & 0xf);
2170 writelfl(ifctl, port_mmio + SATA_IFCTL);
2171
2172 /* Send all words of the FIS except for the final word */
2173 for (i = 0; i < final_word; ++i)
2174 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
2175
2176 /* Flag end-of-transmission, and then send the final word */
2177 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
2178 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
2179
2180 /*
2181 * Wait for FIS transmission to complete.
2182 * This typically takes just a single iteration.
2183 */
2184 do {
2185 ifstat = readl(port_mmio + SATA_IFSTAT);
2186 } while (!(ifstat & 0x1000) && --timeout);
2187
2188 /* Restore original port configuration */
2189 writelfl(old_ifctl, port_mmio + SATA_IFCTL);
2190
2191 /* See if it worked */
2192 if ((ifstat & 0x3000) != 0x1000) {
2193 ata_port_printk(ap, KERN_WARNING,
2194 "%s transmission error, ifstat=%08x\n",
2195 __func__, ifstat);
2196 return AC_ERR_OTHER;
2197 }
2198 return 0;
2199 }
2200
2201 /**
2202 * mv_qc_issue_fis - Issue a command directly as a FIS
2203 * @qc: queued command to start
2204 *
2205 * Note that the ATA shadow registers are not updated
2206 * after command issue, so the device will appear "READY"
2207 * if polled, even while it is BUSY processing the command.
2208 *
2209 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2210 *
2211 * Note: we don't get updated shadow regs on *completion*
2212 * of non-data commands. So avoid sending them via this function,
2213 * as they will appear to have completed immediately.
2214 *
2215 * GEN_IIE has special registers that we could get the result tf from,
2216 * but earlier chipsets do not. For now, we ignore those registers.
2217 */
2218 static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2219 {
2220 struct ata_port *ap = qc->ap;
2221 struct mv_port_priv *pp = ap->private_data;
2222 struct ata_link *link = qc->dev->link;
2223 u32 fis[5];
2224 int err = 0;
2225
2226 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
2227 err = mv_send_fis(ap, fis, ARRAY_SIZE(fis));
2228 if (err)
2229 return err;
2230
2231 switch (qc->tf.protocol) {
2232 case ATAPI_PROT_PIO:
2233 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2234 /* fall through */
2235 case ATAPI_PROT_NODATA:
2236 ap->hsm_task_state = HSM_ST_FIRST;
2237 break;
2238 case ATA_PROT_PIO:
2239 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2240 if (qc->tf.flags & ATA_TFLAG_WRITE)
2241 ap->hsm_task_state = HSM_ST_FIRST;
2242 else
2243 ap->hsm_task_state = HSM_ST;
2244 break;
2245 default:
2246 ap->hsm_task_state = HSM_ST_LAST;
2247 break;
2248 }
2249
2250 if (qc->tf.flags & ATA_TFLAG_POLLING)
2251 ata_pio_queue_task(ap, qc, 0);
2252 return 0;
2253 }
2254
2255 /**
2256 * mv_qc_issue - Initiate a command to the host
2257 * @qc: queued command to start
2258 *
2259 * This routine simply redirects to the general purpose routine
2260 * if command is not DMA. Else, it sanity checks our local
2261 * caches of the request producer/consumer indices then enables
2262 * DMA and bumps the request producer index.
2263 *
2264 * LOCKING:
2265 * Inherited from caller.
2266 */
2267 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
2268 {
2269 static int limit_warnings = 10;
2270 struct ata_port *ap = qc->ap;
2271 void __iomem *port_mmio = mv_ap_base(ap);
2272 struct mv_port_priv *pp = ap->private_data;
2273 u32 in_index;
2274 unsigned int port_irqs;
2275
2276 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2277
2278 switch (qc->tf.protocol) {
2279 case ATA_PROT_DMA:
2280 case ATA_PROT_NCQ:
2281 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2282 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2283 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2284
2285 /* Write the request in pointer to kick the EDMA to life */
2286 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
2287 port_mmio + EDMA_REQ_Q_IN_PTR);
2288 return 0;
2289
2290 case ATA_PROT_PIO:
2291 /*
2292 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2293 *
2294 * Someday, we might implement special polling workarounds
2295 * for these, but it all seems rather unnecessary since we
2296 * normally use only DMA for commands which transfer more
2297 * than a single block of data.
2298 *
2299 * Much of the time, this could just work regardless.
2300 * So for now, just log the incident, and allow the attempt.
2301 */
2302 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
2303 --limit_warnings;
2304 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
2305 ": attempting PIO w/multiple DRQ: "
2306 "this may fail due to h/w errata\n");
2307 }
2308 /* drop through */
2309 case ATA_PROT_NODATA:
2310 case ATAPI_PROT_PIO:
2311 case ATAPI_PROT_NODATA:
2312 if (ap->flags & ATA_FLAG_PIO_POLLING)
2313 qc->tf.flags |= ATA_TFLAG_POLLING;
2314 break;
2315 }
2316
2317 if (qc->tf.flags & ATA_TFLAG_POLLING)
2318 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2319 else
2320 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2321
2322 /*
2323 * We're about to send a non-EDMA capable command to the
2324 * port. Turn off EDMA so there won't be problems accessing
2325 * shadow block, etc registers.
2326 */
2327 mv_stop_edma(ap);
2328 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2329 mv_pmp_select(ap, qc->dev->link->pmp);
2330
2331 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2332 struct mv_host_priv *hpriv = ap->host->private_data;
2333 /*
2334 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
2335 *
2336 * After any NCQ error, the READ_LOG_EXT command
2337 * from libata-eh *must* use mv_qc_issue_fis().
2338 * Otherwise it might fail, due to chip errata.
2339 *
2340 * Rather than special-case it, we'll just *always*
2341 * use this method here for READ_LOG_EXT, making for
2342 * easier testing.
2343 */
2344 if (IS_GEN_II(hpriv))
2345 return mv_qc_issue_fis(qc);
2346 }
2347 return ata_sff_qc_issue(qc);
2348 }
2349
2350 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2351 {
2352 struct mv_port_priv *pp = ap->private_data;
2353 struct ata_queued_cmd *qc;
2354
2355 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2356 return NULL;
2357 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2358 if (qc) {
2359 if (qc->tf.flags & ATA_TFLAG_POLLING)
2360 qc = NULL;
2361 else if (!(qc->flags & ATA_QCFLAG_ACTIVE))
2362 qc = NULL;
2363 }
2364 return qc;
2365 }
2366
2367 static void mv_pmp_error_handler(struct ata_port *ap)
2368 {
2369 unsigned int pmp, pmp_map;
2370 struct mv_port_priv *pp = ap->private_data;
2371
2372 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2373 /*
2374 * Perform NCQ error analysis on failed PMPs
2375 * before we freeze the port entirely.
2376 *
2377 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2378 */
2379 pmp_map = pp->delayed_eh_pmp_map;
2380 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2381 for (pmp = 0; pmp_map != 0; pmp++) {
2382 unsigned int this_pmp = (1 << pmp);
2383 if (pmp_map & this_pmp) {
2384 struct ata_link *link = &ap->pmp_link[pmp];
2385 pmp_map &= ~this_pmp;
2386 ata_eh_analyze_ncq_error(link);
2387 }
2388 }
2389 ata_port_freeze(ap);
2390 }
2391 sata_pmp_error_handler(ap);
2392 }
2393
2394 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2395 {
2396 void __iomem *port_mmio = mv_ap_base(ap);
2397
2398 return readl(port_mmio + SATA_TESTCTL) >> 16;
2399 }
2400
2401 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2402 {
2403 struct ata_eh_info *ehi;
2404 unsigned int pmp;
2405
2406 /*
2407 * Initialize EH info for PMPs which saw device errors
2408 */
2409 ehi = &ap->link.eh_info;
2410 for (pmp = 0; pmp_map != 0; pmp++) {
2411 unsigned int this_pmp = (1 << pmp);
2412 if (pmp_map & this_pmp) {
2413 struct ata_link *link = &ap->pmp_link[pmp];
2414
2415 pmp_map &= ~this_pmp;
2416 ehi = &link->eh_info;
2417 ata_ehi_clear_desc(ehi);
2418 ata_ehi_push_desc(ehi, "dev err");
2419 ehi->err_mask |= AC_ERR_DEV;
2420 ehi->action |= ATA_EH_RESET;
2421 ata_link_abort(link);
2422 }
2423 }
2424 }
2425
2426 static int mv_req_q_empty(struct ata_port *ap)
2427 {
2428 void __iomem *port_mmio = mv_ap_base(ap);
2429 u32 in_ptr, out_ptr;
2430
2431 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
2432 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2433 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
2434 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2435 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2436 }
2437
2438 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2439 {
2440 struct mv_port_priv *pp = ap->private_data;
2441 int failed_links;
2442 unsigned int old_map, new_map;
2443
2444 /*
2445 * Device error during FBS+NCQ operation:
2446 *
2447 * Set a port flag to prevent further I/O being enqueued.
2448 * Leave the EDMA running to drain outstanding commands from this port.
2449 * Perform the post-mortem/EH only when all responses are complete.
2450 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2451 */
2452 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2453 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2454 pp->delayed_eh_pmp_map = 0;
2455 }
2456 old_map = pp->delayed_eh_pmp_map;
2457 new_map = old_map | mv_get_err_pmp_map(ap);
2458
2459 if (old_map != new_map) {
2460 pp->delayed_eh_pmp_map = new_map;
2461 mv_pmp_eh_prep(ap, new_map & ~old_map);
2462 }
2463 failed_links = hweight16(new_map);
2464
2465 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
2466 "failed_links=%d nr_active_links=%d\n",
2467 __func__, pp->delayed_eh_pmp_map,
2468 ap->qc_active, failed_links,
2469 ap->nr_active_links);
2470
2471 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
2472 mv_process_crpb_entries(ap, pp);
2473 mv_stop_edma(ap);
2474 mv_eh_freeze(ap);
2475 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
2476 return 1; /* handled */
2477 }
2478 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
2479 return 1; /* handled */
2480 }
2481
2482 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2483 {
2484 /*
2485 * Possible future enhancement:
2486 *
2487 * FBS+non-NCQ operation is not yet implemented.
2488 * See related notes in mv_edma_cfg().
2489 *
2490 * Device error during FBS+non-NCQ operation:
2491 *
2492 * We need to snapshot the shadow registers for each failed command.
2493 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2494 */
2495 return 0; /* not handled */
2496 }
2497
2498 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2499 {
2500 struct mv_port_priv *pp = ap->private_data;
2501
2502 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2503 return 0; /* EDMA was not active: not handled */
2504 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2505 return 0; /* FBS was not active: not handled */
2506
2507 if (!(edma_err_cause & EDMA_ERR_DEV))
2508 return 0; /* non DEV error: not handled */
2509 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2510 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2511 return 0; /* other problems: not handled */
2512
2513 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2514 /*
2515 * EDMA should NOT have self-disabled for this case.
2516 * If it did, then something is wrong elsewhere,
2517 * and we cannot handle it here.
2518 */
2519 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2520 ata_port_printk(ap, KERN_WARNING,
2521 "%s: err_cause=0x%x pp_flags=0x%x\n",
2522 __func__, edma_err_cause, pp->pp_flags);
2523 return 0; /* not handled */
2524 }
2525 return mv_handle_fbs_ncq_dev_err(ap);
2526 } else {
2527 /*
2528 * EDMA should have self-disabled for this case.
2529 * If it did not, then something is wrong elsewhere,
2530 * and we cannot handle it here.
2531 */
2532 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2533 ata_port_printk(ap, KERN_WARNING,
2534 "%s: err_cause=0x%x pp_flags=0x%x\n",
2535 __func__, edma_err_cause, pp->pp_flags);
2536 return 0; /* not handled */
2537 }
2538 return mv_handle_fbs_non_ncq_dev_err(ap);
2539 }
2540 return 0; /* not handled */
2541 }
2542
2543 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
2544 {
2545 struct ata_eh_info *ehi = &ap->link.eh_info;
2546 char *when = "idle";
2547
2548 ata_ehi_clear_desc(ehi);
2549 if (ap->flags & ATA_FLAG_DISABLED) {
2550 when = "disabled";
2551 } else if (edma_was_enabled) {
2552 when = "EDMA enabled";
2553 } else {
2554 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2555 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
2556 when = "polling";
2557 }
2558 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
2559 ehi->err_mask |= AC_ERR_OTHER;
2560 ehi->action |= ATA_EH_RESET;
2561 ata_port_freeze(ap);
2562 }
2563
2564 /**
2565 * mv_err_intr - Handle error interrupts on the port
2566 * @ap: ATA channel to manipulate
2567 *
2568 * Most cases require a full reset of the chip's state machine,
2569 * which also performs a COMRESET.
2570 * Also, if the port disabled DMA, update our cached copy to match.
2571 *
2572 * LOCKING:
2573 * Inherited from caller.
2574 */
2575 static void mv_err_intr(struct ata_port *ap)
2576 {
2577 void __iomem *port_mmio = mv_ap_base(ap);
2578 u32 edma_err_cause, eh_freeze_mask, serr = 0;
2579 u32 fis_cause = 0;
2580 struct mv_port_priv *pp = ap->private_data;
2581 struct mv_host_priv *hpriv = ap->host->private_data;
2582 unsigned int action = 0, err_mask = 0;
2583 struct ata_eh_info *ehi = &ap->link.eh_info;
2584 struct ata_queued_cmd *qc;
2585 int abort = 0;
2586
2587 /*
2588 * Read and clear the SError and err_cause bits.
2589 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2590 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
2591 */
2592 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2593 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2594
2595 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
2596 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2597 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
2598 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
2599 }
2600 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
2601
2602 if (edma_err_cause & EDMA_ERR_DEV) {
2603 /*
2604 * Device errors during FIS-based switching operation
2605 * require special handling.
2606 */
2607 if (mv_handle_dev_err(ap, edma_err_cause))
2608 return;
2609 }
2610
2611 qc = mv_get_active_qc(ap);
2612 ata_ehi_clear_desc(ehi);
2613 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2614 edma_err_cause, pp->pp_flags);
2615
2616 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2617 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
2618 if (fis_cause & FIS_IRQ_CAUSE_AN) {
2619 u32 ec = edma_err_cause &
2620 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2621 sata_async_notification(ap);
2622 if (!ec)
2623 return; /* Just an AN; no need for the nukes */
2624 ata_ehi_push_desc(ehi, "SDB notify");
2625 }
2626 }
2627 /*
2628 * All generations share these EDMA error cause bits:
2629 */
2630 if (edma_err_cause & EDMA_ERR_DEV) {
2631 err_mask |= AC_ERR_DEV;
2632 action |= ATA_EH_RESET;
2633 ata_ehi_push_desc(ehi, "dev error");
2634 }
2635 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
2636 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
2637 EDMA_ERR_INTRL_PAR)) {
2638 err_mask |= AC_ERR_ATA_BUS;
2639 action |= ATA_EH_RESET;
2640 ata_ehi_push_desc(ehi, "parity error");
2641 }
2642 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2643 ata_ehi_hotplugged(ehi);
2644 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
2645 "dev disconnect" : "dev connect");
2646 action |= ATA_EH_RESET;
2647 }
2648
2649 /*
2650 * Gen-I has a different SELF_DIS bit,
2651 * different FREEZE bits, and no SERR bit:
2652 */
2653 if (IS_GEN_I(hpriv)) {
2654 eh_freeze_mask = EDMA_EH_FREEZE_5;
2655 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
2656 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2657 ata_ehi_push_desc(ehi, "EDMA self-disable");
2658 }
2659 } else {
2660 eh_freeze_mask = EDMA_EH_FREEZE;
2661 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2662 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2663 ata_ehi_push_desc(ehi, "EDMA self-disable");
2664 }
2665 if (edma_err_cause & EDMA_ERR_SERR) {
2666 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2667 err_mask |= AC_ERR_ATA_BUS;
2668 action |= ATA_EH_RESET;
2669 }
2670 }
2671
2672 if (!err_mask) {
2673 err_mask = AC_ERR_OTHER;
2674 action |= ATA_EH_RESET;
2675 }
2676
2677 ehi->serror |= serr;
2678 ehi->action |= action;
2679
2680 if (qc)
2681 qc->err_mask |= err_mask;
2682 else
2683 ehi->err_mask |= err_mask;
2684
2685 if (err_mask == AC_ERR_DEV) {
2686 /*
2687 * Cannot do ata_port_freeze() here,
2688 * because it would kill PIO access,
2689 * which is needed for further diagnosis.
2690 */
2691 mv_eh_freeze(ap);
2692 abort = 1;
2693 } else if (edma_err_cause & eh_freeze_mask) {
2694 /*
2695 * Note to self: ata_port_freeze() calls ata_port_abort()
2696 */
2697 ata_port_freeze(ap);
2698 } else {
2699 abort = 1;
2700 }
2701
2702 if (abort) {
2703 if (qc)
2704 ata_link_abort(qc->dev->link);
2705 else
2706 ata_port_abort(ap);
2707 }
2708 }
2709
2710 static void mv_process_crpb_response(struct ata_port *ap,
2711 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2712 {
2713 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2714
2715 if (qc) {
2716 u8 ata_status;
2717 u16 edma_status = le16_to_cpu(response->flags);
2718 /*
2719 * edma_status from a response queue entry:
2720 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
2721 * MSB is saved ATA status from command completion.
2722 */
2723 if (!ncq_enabled) {
2724 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2725 if (err_cause) {
2726 /*
2727 * Error will be seen/handled by mv_err_intr().
2728 * So do nothing at all here.
2729 */
2730 return;
2731 }
2732 }
2733 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2734 if (!ac_err_mask(ata_status))
2735 ata_qc_complete(qc);
2736 /* else: leave it for mv_err_intr() */
2737 } else {
2738 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2739 __func__, tag);
2740 }
2741 }
2742
2743 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
2744 {
2745 void __iomem *port_mmio = mv_ap_base(ap);
2746 struct mv_host_priv *hpriv = ap->host->private_data;
2747 u32 in_index;
2748 bool work_done = false;
2749 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2750
2751 /* Get the hardware queue position index */
2752 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
2753 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2754
2755 /* Process new responses from since the last time we looked */
2756 while (in_index != pp->resp_idx) {
2757 unsigned int tag;
2758 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2759
2760 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2761
2762 if (IS_GEN_I(hpriv)) {
2763 /* 50xx: no NCQ, only one command active at a time */
2764 tag = ap->link.active_tag;
2765 } else {
2766 /* Gen II/IIE: get command tag from CRPB entry */
2767 tag = le16_to_cpu(response->id) & 0x1f;
2768 }
2769 mv_process_crpb_response(ap, response, tag, ncq_enabled);
2770 work_done = true;
2771 }
2772
2773 /* Update the software queue position index in hardware */
2774 if (work_done)
2775 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2776 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2777 port_mmio + EDMA_RSP_Q_OUT_PTR);
2778 }
2779
2780 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2781 {
2782 struct mv_port_priv *pp;
2783 int edma_was_enabled;
2784
2785 if (ap->flags & ATA_FLAG_DISABLED) {
2786 mv_unexpected_intr(ap, 0);
2787 return;
2788 }
2789 /*
2790 * Grab a snapshot of the EDMA_EN flag setting,
2791 * so that we have a consistent view for this port,
2792 * even if something we call of our routines changes it.
2793 */
2794 pp = ap->private_data;
2795 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2796 /*
2797 * Process completed CRPB response(s) before other events.
2798 */
2799 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2800 mv_process_crpb_entries(ap, pp);
2801 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2802 mv_handle_fbs_ncq_dev_err(ap);
2803 }
2804 /*
2805 * Handle chip-reported errors, or continue on to handle PIO.
2806 */
2807 if (unlikely(port_cause & ERR_IRQ)) {
2808 mv_err_intr(ap);
2809 } else if (!edma_was_enabled) {
2810 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2811 if (qc)
2812 ata_sff_host_intr(ap, qc);
2813 else
2814 mv_unexpected_intr(ap, edma_was_enabled);
2815 }
2816 }
2817
2818 /**
2819 * mv_host_intr - Handle all interrupts on the given host controller
2820 * @host: host specific structure
2821 * @main_irq_cause: Main interrupt cause register for the chip.
2822 *
2823 * LOCKING:
2824 * Inherited from caller.
2825 */
2826 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2827 {
2828 struct mv_host_priv *hpriv = host->private_data;
2829 void __iomem *mmio = hpriv->base, *hc_mmio;
2830 unsigned int handled = 0, port;
2831
2832 /* If asserted, clear the "all ports" IRQ coalescing bit */
2833 if (main_irq_cause & ALL_PORTS_COAL_DONE)
2834 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
2835
2836 for (port = 0; port < hpriv->n_ports; port++) {
2837 struct ata_port *ap = host->ports[port];
2838 unsigned int p, shift, hardport, port_cause;
2839
2840 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2841 /*
2842 * Each hc within the host has its own hc_irq_cause register,
2843 * where the interrupting ports bits get ack'd.
2844 */
2845 if (hardport == 0) { /* first port on this hc ? */
2846 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2847 u32 port_mask, ack_irqs;
2848 /*
2849 * Skip this entire hc if nothing pending for any ports
2850 */
2851 if (!hc_cause) {
2852 port += MV_PORTS_PER_HC - 1;
2853 continue;
2854 }
2855 /*
2856 * We don't need/want to read the hc_irq_cause register,
2857 * because doing so hurts performance, and
2858 * main_irq_cause already gives us everything we need.
2859 *
2860 * But we do have to *write* to the hc_irq_cause to ack
2861 * the ports that we are handling this time through.
2862 *
2863 * This requires that we create a bitmap for those
2864 * ports which interrupted us, and use that bitmap
2865 * to ack (only) those ports via hc_irq_cause.
2866 */
2867 ack_irqs = 0;
2868 if (hc_cause & PORTS_0_3_COAL_DONE)
2869 ack_irqs = HC_COAL_IRQ;
2870 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2871 if ((port + p) >= hpriv->n_ports)
2872 break;
2873 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2874 if (hc_cause & port_mask)
2875 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2876 }
2877 hc_mmio = mv_hc_base_from_port(mmio, port);
2878 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
2879 handled = 1;
2880 }
2881 /*
2882 * Handle interrupts signalled for this port:
2883 */
2884 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2885 if (port_cause)
2886 mv_port_intr(ap, port_cause);
2887 }
2888 return handled;
2889 }
2890
2891 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2892 {
2893 struct mv_host_priv *hpriv = host->private_data;
2894 struct ata_port *ap;
2895 struct ata_queued_cmd *qc;
2896 struct ata_eh_info *ehi;
2897 unsigned int i, err_mask, printed = 0;
2898 u32 err_cause;
2899
2900 err_cause = readl(mmio + hpriv->irq_cause_offset);
2901
2902 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2903 err_cause);
2904
2905 DPRINTK("All regs @ PCI error\n");
2906 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2907
2908 writelfl(0, mmio + hpriv->irq_cause_offset);
2909
2910 for (i = 0; i < host->n_ports; i++) {
2911 ap = host->ports[i];
2912 if (!ata_link_offline(&ap->link)) {
2913 ehi = &ap->link.eh_info;
2914 ata_ehi_clear_desc(ehi);
2915 if (!printed++)
2916 ata_ehi_push_desc(ehi,
2917 "PCI err cause 0x%08x", err_cause);
2918 err_mask = AC_ERR_HOST_BUS;
2919 ehi->action = ATA_EH_RESET;
2920 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2921 if (qc)
2922 qc->err_mask |= err_mask;
2923 else
2924 ehi->err_mask |= err_mask;
2925
2926 ata_port_freeze(ap);
2927 }
2928 }
2929 return 1; /* handled */
2930 }
2931
2932 /**
2933 * mv_interrupt - Main interrupt event handler
2934 * @irq: unused
2935 * @dev_instance: private data; in this case the host structure
2936 *
2937 * Read the read only register to determine if any host
2938 * controllers have pending interrupts. If so, call lower level
2939 * routine to handle. Also check for PCI errors which are only
2940 * reported here.
2941 *
2942 * LOCKING:
2943 * This routine holds the host lock while processing pending
2944 * interrupts.
2945 */
2946 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2947 {
2948 struct ata_host *host = dev_instance;
2949 struct mv_host_priv *hpriv = host->private_data;
2950 unsigned int handled = 0;
2951 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
2952 u32 main_irq_cause, pending_irqs;
2953
2954 spin_lock(&host->lock);
2955
2956 /* for MSI: block new interrupts while in here */
2957 if (using_msi)
2958 mv_write_main_irq_mask(0, hpriv);
2959
2960 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2961 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
2962 /*
2963 * Deal with cases where we either have nothing pending, or have read
2964 * a bogus register value which can indicate HW removal or PCI fault.
2965 */
2966 if (pending_irqs && main_irq_cause != 0xffffffffU) {
2967 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
2968 handled = mv_pci_error(host, hpriv->base);
2969 else
2970 handled = mv_host_intr(host, pending_irqs);
2971 }
2972
2973 /* for MSI: unmask; interrupt cause bits will retrigger now */
2974 if (using_msi)
2975 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
2976
2977 spin_unlock(&host->lock);
2978
2979 return IRQ_RETVAL(handled);
2980 }
2981
2982 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2983 {
2984 unsigned int ofs;
2985
2986 switch (sc_reg_in) {
2987 case SCR_STATUS:
2988 case SCR_ERROR:
2989 case SCR_CONTROL:
2990 ofs = sc_reg_in * sizeof(u32);
2991 break;
2992 default:
2993 ofs = 0xffffffffU;
2994 break;
2995 }
2996 return ofs;
2997 }
2998
2999 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
3000 {
3001 struct mv_host_priv *hpriv = link->ap->host->private_data;
3002 void __iomem *mmio = hpriv->base;
3003 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
3004 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3005
3006 if (ofs != 0xffffffffU) {
3007 *val = readl(addr + ofs);
3008 return 0;
3009 } else
3010 return -EINVAL;
3011 }
3012
3013 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
3014 {
3015 struct mv_host_priv *hpriv = link->ap->host->private_data;
3016 void __iomem *mmio = hpriv->base;
3017 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
3018 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3019
3020 if (ofs != 0xffffffffU) {
3021 writelfl(val, addr + ofs);
3022 return 0;
3023 } else
3024 return -EINVAL;
3025 }
3026
3027 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
3028 {
3029 struct pci_dev *pdev = to_pci_dev(host->dev);
3030 int early_5080;
3031
3032 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
3033
3034 if (!early_5080) {
3035 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3036 tmp |= (1 << 0);
3037 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3038 }
3039
3040 mv_reset_pci_bus(host, mmio);
3041 }
3042
3043 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3044 {
3045 writel(0x0fcfffff, mmio + FLASH_CTL);
3046 }
3047
3048 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
3049 void __iomem *mmio)
3050 {
3051 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
3052 u32 tmp;
3053
3054 tmp = readl(phy_mmio + MV5_PHY_MODE);
3055
3056 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3057 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
3058 }
3059
3060 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3061 {
3062 u32 tmp;
3063
3064 writel(0, mmio + GPIO_PORT_CTL);
3065
3066 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
3067
3068 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3069 tmp |= ~(1 << 0);
3070 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3071 }
3072
3073 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3074 unsigned int port)
3075 {
3076 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3077 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
3078 u32 tmp;
3079 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3080
3081 if (fix_apm_sq) {
3082 tmp = readl(phy_mmio + MV5_LTMODE);
3083 tmp |= (1 << 19);
3084 writel(tmp, phy_mmio + MV5_LTMODE);
3085
3086 tmp = readl(phy_mmio + MV5_PHY_CTL);
3087 tmp &= ~0x3;
3088 tmp |= 0x1;
3089 writel(tmp, phy_mmio + MV5_PHY_CTL);
3090 }
3091
3092 tmp = readl(phy_mmio + MV5_PHY_MODE);
3093 tmp &= ~mask;
3094 tmp |= hpriv->signal[port].pre;
3095 tmp |= hpriv->signal[port].amps;
3096 writel(tmp, phy_mmio + MV5_PHY_MODE);
3097 }
3098
3099
3100 #undef ZERO
3101 #define ZERO(reg) writel(0, port_mmio + (reg))
3102 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3103 unsigned int port)
3104 {
3105 void __iomem *port_mmio = mv_port_base(mmio, port);
3106
3107 mv_reset_channel(hpriv, mmio, port);
3108
3109 ZERO(0x028); /* command */
3110 writel(0x11f, port_mmio + EDMA_CFG);
3111 ZERO(0x004); /* timer */
3112 ZERO(0x008); /* irq err cause */
3113 ZERO(0x00c); /* irq err mask */
3114 ZERO(0x010); /* rq bah */
3115 ZERO(0x014); /* rq inp */
3116 ZERO(0x018); /* rq outp */
3117 ZERO(0x01c); /* respq bah */
3118 ZERO(0x024); /* respq outp */
3119 ZERO(0x020); /* respq inp */
3120 ZERO(0x02c); /* test control */
3121 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
3122 }
3123 #undef ZERO
3124
3125 #define ZERO(reg) writel(0, hc_mmio + (reg))
3126 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3127 unsigned int hc)
3128 {
3129 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3130 u32 tmp;
3131
3132 ZERO(0x00c);
3133 ZERO(0x010);
3134 ZERO(0x014);
3135 ZERO(0x018);
3136
3137 tmp = readl(hc_mmio + 0x20);
3138 tmp &= 0x1c1c1c1c;
3139 tmp |= 0x03030303;
3140 writel(tmp, hc_mmio + 0x20);
3141 }
3142 #undef ZERO
3143
3144 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3145 unsigned int n_hc)
3146 {
3147 unsigned int hc, port;
3148
3149 for (hc = 0; hc < n_hc; hc++) {
3150 for (port = 0; port < MV_PORTS_PER_HC; port++)
3151 mv5_reset_hc_port(hpriv, mmio,
3152 (hc * MV_PORTS_PER_HC) + port);
3153
3154 mv5_reset_one_hc(hpriv, mmio, hc);
3155 }
3156
3157 return 0;
3158 }
3159
3160 #undef ZERO
3161 #define ZERO(reg) writel(0, mmio + (reg))
3162 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
3163 {
3164 struct mv_host_priv *hpriv = host->private_data;
3165 u32 tmp;
3166
3167 tmp = readl(mmio + MV_PCI_MODE);
3168 tmp &= 0xff00ffff;
3169 writel(tmp, mmio + MV_PCI_MODE);
3170
3171 ZERO(MV_PCI_DISC_TIMER);
3172 ZERO(MV_PCI_MSI_TRIGGER);
3173 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
3174 ZERO(MV_PCI_SERR_MASK);
3175 ZERO(hpriv->irq_cause_offset);
3176 ZERO(hpriv->irq_mask_offset);
3177 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3178 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3179 ZERO(MV_PCI_ERR_ATTRIBUTE);
3180 ZERO(MV_PCI_ERR_COMMAND);
3181 }
3182 #undef ZERO
3183
3184 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3185 {
3186 u32 tmp;
3187
3188 mv5_reset_flash(hpriv, mmio);
3189
3190 tmp = readl(mmio + GPIO_PORT_CTL);
3191 tmp &= 0x3;
3192 tmp |= (1 << 5) | (1 << 6);
3193 writel(tmp, mmio + GPIO_PORT_CTL);
3194 }
3195
3196 /**
3197 * mv6_reset_hc - Perform the 6xxx global soft reset
3198 * @mmio: base address of the HBA
3199 *
3200 * This routine only applies to 6xxx parts.
3201 *
3202 * LOCKING:
3203 * Inherited from caller.
3204 */
3205 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3206 unsigned int n_hc)
3207 {
3208 void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
3209 int i, rc = 0;
3210 u32 t;
3211
3212 /* Following procedure defined in PCI "main command and status
3213 * register" table.
3214 */
3215 t = readl(reg);
3216 writel(t | STOP_PCI_MASTER, reg);
3217
3218 for (i = 0; i < 1000; i++) {
3219 udelay(1);
3220 t = readl(reg);
3221 if (PCI_MASTER_EMPTY & t)
3222 break;
3223 }
3224 if (!(PCI_MASTER_EMPTY & t)) {
3225 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3226 rc = 1;
3227 goto done;
3228 }
3229
3230 /* set reset */
3231 i = 5;
3232 do {
3233 writel(t | GLOB_SFT_RST, reg);
3234 t = readl(reg);
3235 udelay(1);
3236 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3237
3238 if (!(GLOB_SFT_RST & t)) {
3239 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3240 rc = 1;
3241 goto done;
3242 }
3243
3244 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3245 i = 5;
3246 do {
3247 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3248 t = readl(reg);
3249 udelay(1);
3250 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3251
3252 if (GLOB_SFT_RST & t) {
3253 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3254 rc = 1;
3255 }
3256 done:
3257 return rc;
3258 }
3259
3260 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
3261 void __iomem *mmio)
3262 {
3263 void __iomem *port_mmio;
3264 u32 tmp;
3265
3266 tmp = readl(mmio + RESET_CFG);
3267 if ((tmp & (1 << 0)) == 0) {
3268 hpriv->signal[idx].amps = 0x7 << 8;
3269 hpriv->signal[idx].pre = 0x1 << 5;
3270 return;
3271 }
3272
3273 port_mmio = mv_port_base(mmio, idx);
3274 tmp = readl(port_mmio + PHY_MODE2);
3275
3276 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3277 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3278 }
3279
3280 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3281 {
3282 writel(0x00000060, mmio + GPIO_PORT_CTL);
3283 }
3284
3285 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3286 unsigned int port)
3287 {
3288 void __iomem *port_mmio = mv_port_base(mmio, port);
3289
3290 u32 hp_flags = hpriv->hp_flags;
3291 int fix_phy_mode2 =
3292 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3293 int fix_phy_mode4 =
3294 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3295 u32 m2, m3;
3296
3297 if (fix_phy_mode2) {
3298 m2 = readl(port_mmio + PHY_MODE2);
3299 m2 &= ~(1 << 16);
3300 m2 |= (1 << 31);
3301 writel(m2, port_mmio + PHY_MODE2);
3302
3303 udelay(200);
3304
3305 m2 = readl(port_mmio + PHY_MODE2);
3306 m2 &= ~((1 << 16) | (1 << 31));
3307 writel(m2, port_mmio + PHY_MODE2);
3308
3309 udelay(200);
3310 }
3311
3312 /*
3313 * Gen-II/IIe PHY_MODE3 errata RM#2:
3314 * Achieves better receiver noise performance than the h/w default:
3315 */
3316 m3 = readl(port_mmio + PHY_MODE3);
3317 m3 = (m3 & 0x1f) | (0x5555601 << 5);
3318
3319 /* Guideline 88F5182 (GL# SATA-S11) */
3320 if (IS_SOC(hpriv))
3321 m3 &= ~0x1c;
3322
3323 if (fix_phy_mode4) {
3324 u32 m4 = readl(port_mmio + PHY_MODE4);
3325 /*
3326 * Enforce reserved-bit restrictions on GenIIe devices only.
3327 * For earlier chipsets, force only the internal config field
3328 * (workaround for errata FEr SATA#10 part 1).
3329 */
3330 if (IS_GEN_IIE(hpriv))
3331 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3332 else
3333 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
3334 writel(m4, port_mmio + PHY_MODE4);
3335 }
3336 /*
3337 * Workaround for 60x1-B2 errata SATA#13:
3338 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3339 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
3340 * Or ensure we use writelfl() when writing PHY_MODE4.
3341 */
3342 writel(m3, port_mmio + PHY_MODE3);
3343
3344 /* Revert values of pre-emphasis and signal amps to the saved ones */
3345 m2 = readl(port_mmio + PHY_MODE2);
3346
3347 m2 &= ~MV_M2_PREAMP_MASK;
3348 m2 |= hpriv->signal[port].amps;
3349 m2 |= hpriv->signal[port].pre;
3350 m2 &= ~(1 << 16);
3351
3352 /* according to mvSata 3.6.1, some IIE values are fixed */
3353 if (IS_GEN_IIE(hpriv)) {
3354 m2 &= ~0xC30FF01F;
3355 m2 |= 0x0000900F;
3356 }
3357
3358 writel(m2, port_mmio + PHY_MODE2);
3359 }
3360
3361 /* TODO: use the generic LED interface to configure the SATA Presence */
3362 /* & Acitivy LEDs on the board */
3363 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3364 void __iomem *mmio)
3365 {
3366 return;
3367 }
3368
3369 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3370 void __iomem *mmio)
3371 {
3372 void __iomem *port_mmio;
3373 u32 tmp;
3374
3375 port_mmio = mv_port_base(mmio, idx);
3376 tmp = readl(port_mmio + PHY_MODE2);
3377
3378 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3379 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3380 }
3381
3382 #undef ZERO
3383 #define ZERO(reg) writel(0, port_mmio + (reg))
3384 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3385 void __iomem *mmio, unsigned int port)
3386 {
3387 void __iomem *port_mmio = mv_port_base(mmio, port);
3388
3389 mv_reset_channel(hpriv, mmio, port);
3390
3391 ZERO(0x028); /* command */
3392 writel(0x101f, port_mmio + EDMA_CFG);
3393 ZERO(0x004); /* timer */
3394 ZERO(0x008); /* irq err cause */
3395 ZERO(0x00c); /* irq err mask */
3396 ZERO(0x010); /* rq bah */
3397 ZERO(0x014); /* rq inp */
3398 ZERO(0x018); /* rq outp */
3399 ZERO(0x01c); /* respq bah */
3400 ZERO(0x024); /* respq outp */
3401 ZERO(0x020); /* respq inp */
3402 ZERO(0x02c); /* test control */
3403 writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
3404 }
3405
3406 #undef ZERO
3407
3408 #define ZERO(reg) writel(0, hc_mmio + (reg))
3409 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3410 void __iomem *mmio)
3411 {
3412 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3413
3414 ZERO(0x00c);
3415 ZERO(0x010);
3416 ZERO(0x014);
3417
3418 }
3419
3420 #undef ZERO
3421
3422 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3423 void __iomem *mmio, unsigned int n_hc)
3424 {
3425 unsigned int port;
3426
3427 for (port = 0; port < hpriv->n_ports; port++)
3428 mv_soc_reset_hc_port(hpriv, mmio, port);
3429
3430 mv_soc_reset_one_hc(hpriv, mmio);
3431
3432 return 0;
3433 }
3434
3435 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3436 void __iomem *mmio)
3437 {
3438 return;
3439 }
3440
3441 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3442 {
3443 return;
3444 }
3445
3446 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3447 void __iomem *mmio, unsigned int port)
3448 {
3449 void __iomem *port_mmio = mv_port_base(mmio, port);
3450 u32 reg;
3451
3452 reg = readl(port_mmio + PHY_MODE3);
3453 reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
3454 reg |= (0x1 << 27);
3455 reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
3456 reg |= (0x1 << 29);
3457 writel(reg, port_mmio + PHY_MODE3);
3458
3459 reg = readl(port_mmio + PHY_MODE4);
3460 reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
3461 reg |= (0x1 << 16);
3462 writel(reg, port_mmio + PHY_MODE4);
3463
3464 reg = readl(port_mmio + PHY_MODE9_GEN2);
3465 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3466 reg |= 0x8;
3467 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3468 writel(reg, port_mmio + PHY_MODE9_GEN2);
3469
3470 reg = readl(port_mmio + PHY_MODE9_GEN1);
3471 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3472 reg |= 0x8;
3473 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3474 writel(reg, port_mmio + PHY_MODE9_GEN1);
3475 }
3476
3477 /**
3478 * soc_is_65 - check if the soc is 65 nano device
3479 *
3480 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
3481 * register, this register should contain non-zero value and it exists only
3482 * in the 65 nano devices, when reading it from older devices we get 0.
3483 */
3484 static bool soc_is_65n(struct mv_host_priv *hpriv)
3485 {
3486 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3487
3488 if (readl(port0_mmio + PHYCFG_OFS))
3489 return true;
3490 return false;
3491 }
3492
3493 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
3494 {
3495 u32 ifcfg = readl(port_mmio + SATA_IFCFG);
3496
3497 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
3498 if (want_gen2i)
3499 ifcfg |= (1 << 7); /* enable gen2i speed */
3500 writelfl(ifcfg, port_mmio + SATA_IFCFG);
3501 }
3502
3503 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
3504 unsigned int port_no)
3505 {
3506 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3507
3508 /*
3509 * The datasheet warns against setting EDMA_RESET when EDMA is active
3510 * (but doesn't say what the problem might be). So we first try
3511 * to disable the EDMA engine before doing the EDMA_RESET operation.
3512 */
3513 mv_stop_edma_engine(port_mmio);
3514 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3515
3516 if (!IS_GEN_I(hpriv)) {
3517 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3518 mv_setup_ifcfg(port_mmio, 1);
3519 }
3520 /*
3521 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
3522 * link, and physical layers. It resets all SATA interface registers
3523 * (except for SATA_IFCFG), and issues a COMRESET to the dev.
3524 */
3525 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
3526 udelay(25); /* allow reset propagation */
3527 writelfl(0, port_mmio + EDMA_CMD);
3528
3529 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3530
3531 if (IS_GEN_I(hpriv))
3532 mdelay(1);
3533 }
3534
3535 static void mv_pmp_select(struct ata_port *ap, int pmp)
3536 {
3537 if (sata_pmp_supported(ap)) {
3538 void __iomem *port_mmio = mv_ap_base(ap);
3539 u32 reg = readl(port_mmio + SATA_IFCTL);
3540 int old = reg & 0xf;
3541
3542 if (old != pmp) {
3543 reg = (reg & ~0xf) | pmp;
3544 writelfl(reg, port_mmio + SATA_IFCTL);
3545 }
3546 }
3547 }
3548
3549 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3550 unsigned long deadline)
3551 {
3552 mv_pmp_select(link->ap, sata_srst_pmp(link));
3553 return sata_std_hardreset(link, class, deadline);
3554 }
3555
3556 static int mv_softreset(struct ata_link *link, unsigned int *class,
3557 unsigned long deadline)
3558 {
3559 mv_pmp_select(link->ap, sata_srst_pmp(link));
3560 return ata_sff_softreset(link, class, deadline);
3561 }
3562
3563 static int mv_hardreset(struct ata_link *link, unsigned int *class,
3564 unsigned long deadline)
3565 {
3566 struct ata_port *ap = link->ap;
3567 struct mv_host_priv *hpriv = ap->host->private_data;
3568 struct mv_port_priv *pp = ap->private_data;
3569 void __iomem *mmio = hpriv->base;
3570 int rc, attempts = 0, extra = 0;
3571 u32 sstatus;
3572 bool online;
3573
3574 mv_reset_channel(hpriv, mmio, ap->port_no);
3575 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
3576 pp->pp_flags &=
3577 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
3578
3579 /* Workaround for errata FEr SATA#10 (part 2) */
3580 do {
3581 const unsigned long *timing =
3582 sata_ehc_deb_timing(&link->eh_context);
3583
3584 rc = sata_link_hardreset(link, timing, deadline + extra,
3585 &online, NULL);
3586 rc = online ? -EAGAIN : rc;
3587 if (rc)
3588 return rc;
3589 sata_scr_read(link, SCR_STATUS, &sstatus);
3590 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3591 /* Force 1.5gb/s link speed and try again */
3592 mv_setup_ifcfg(mv_ap_base(ap), 0);
3593 if (time_after(jiffies + HZ, deadline))
3594 extra = HZ; /* only extend it once, max */
3595 }
3596 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
3597 mv_save_cached_regs(ap);
3598 mv_edma_cfg(ap, 0, 0);
3599
3600 return rc;
3601 }
3602
3603 static void mv_eh_freeze(struct ata_port *ap)
3604 {
3605 mv_stop_edma(ap);
3606 mv_enable_port_irqs(ap, 0);
3607 }
3608
3609 static void mv_eh_thaw(struct ata_port *ap)
3610 {
3611 struct mv_host_priv *hpriv = ap->host->private_data;
3612 unsigned int port = ap->port_no;
3613 unsigned int hardport = mv_hardport_from_port(port);
3614 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3615 void __iomem *port_mmio = mv_ap_base(ap);
3616 u32 hc_irq_cause;
3617
3618 /* clear EDMA errors on this port */
3619 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3620
3621 /* clear pending irq events */
3622 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
3623 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
3624
3625 mv_enable_port_irqs(ap, ERR_IRQ);
3626 }
3627
3628 /**
3629 * mv_port_init - Perform some early initialization on a single port.
3630 * @port: libata data structure storing shadow register addresses
3631 * @port_mmio: base address of the port
3632 *
3633 * Initialize shadow register mmio addresses, clear outstanding
3634 * interrupts on the port, and unmask interrupts for the future
3635 * start of the port.
3636 *
3637 * LOCKING:
3638 * Inherited from caller.
3639 */
3640 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3641 {
3642 void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
3643
3644 /* PIO related setup
3645 */
3646 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
3647 port->error_addr =
3648 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3649 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3650 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3651 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3652 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3653 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
3654 port->status_addr =
3655 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3656 /* special case: control/altstatus doesn't have ATA_REG_ address */
3657 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
3658
3659 /* unused: */
3660 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
3661
3662 /* Clear any currently outstanding port interrupt conditions */
3663 serr = port_mmio + mv_scr_offset(SCR_ERROR);
3664 writelfl(readl(serr), serr);
3665 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
3666
3667 /* unmask all non-transient EDMA error interrupts */
3668 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
3669
3670 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
3671 readl(port_mmio + EDMA_CFG),
3672 readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
3673 readl(port_mmio + EDMA_ERR_IRQ_MASK));
3674 }
3675
3676 static unsigned int mv_in_pcix_mode(struct ata_host *host)
3677 {
3678 struct mv_host_priv *hpriv = host->private_data;
3679 void __iomem *mmio = hpriv->base;
3680 u32 reg;
3681
3682 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
3683 return 0; /* not PCI-X capable */
3684 reg = readl(mmio + MV_PCI_MODE);
3685 if ((reg & MV_PCI_MODE_MASK) == 0)
3686 return 0; /* conventional PCI mode */
3687 return 1; /* chip is in PCI-X mode */
3688 }
3689
3690 static int mv_pci_cut_through_okay(struct ata_host *host)
3691 {
3692 struct mv_host_priv *hpriv = host->private_data;
3693 void __iomem *mmio = hpriv->base;
3694 u32 reg;
3695
3696 if (!mv_in_pcix_mode(host)) {
3697 reg = readl(mmio + MV_PCI_COMMAND);
3698 if (reg & MV_PCI_COMMAND_MRDTRIG)
3699 return 0; /* not okay */
3700 }
3701 return 1; /* okay */
3702 }
3703
3704 static void mv_60x1b2_errata_pci7(struct ata_host *host)
3705 {
3706 struct mv_host_priv *hpriv = host->private_data;
3707 void __iomem *mmio = hpriv->base;
3708
3709 /* workaround for 60x1-B2 errata PCI#7 */
3710 if (mv_in_pcix_mode(host)) {
3711 u32 reg = readl(mmio + MV_PCI_COMMAND);
3712 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
3713 }
3714 }
3715
3716 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3717 {
3718 struct pci_dev *pdev = to_pci_dev(host->dev);
3719 struct mv_host_priv *hpriv = host->private_data;
3720 u32 hp_flags = hpriv->hp_flags;
3721
3722 switch (board_idx) {
3723 case chip_5080:
3724 hpriv->ops = &mv5xxx_ops;
3725 hp_flags |= MV_HP_GEN_I;
3726
3727 switch (pdev->revision) {
3728 case 0x1:
3729 hp_flags |= MV_HP_ERRATA_50XXB0;
3730 break;
3731 case 0x3:
3732 hp_flags |= MV_HP_ERRATA_50XXB2;
3733 break;
3734 default:
3735 dev_printk(KERN_WARNING, &pdev->dev,
3736 "Applying 50XXB2 workarounds to unknown rev\n");
3737 hp_flags |= MV_HP_ERRATA_50XXB2;
3738 break;
3739 }
3740 break;
3741
3742 case chip_504x:
3743 case chip_508x:
3744 hpriv->ops = &mv5xxx_ops;
3745 hp_flags |= MV_HP_GEN_I;
3746
3747 switch (pdev->revision) {
3748 case 0x0:
3749 hp_flags |= MV_HP_ERRATA_50XXB0;
3750 break;
3751 case 0x3:
3752 hp_flags |= MV_HP_ERRATA_50XXB2;
3753 break;
3754 default:
3755 dev_printk(KERN_WARNING, &pdev->dev,
3756 "Applying B2 workarounds to unknown rev\n");
3757 hp_flags |= MV_HP_ERRATA_50XXB2;
3758 break;
3759 }
3760 break;
3761
3762 case chip_604x:
3763 case chip_608x:
3764 hpriv->ops = &mv6xxx_ops;
3765 hp_flags |= MV_HP_GEN_II;
3766
3767 switch (pdev->revision) {
3768 case 0x7:
3769 mv_60x1b2_errata_pci7(host);
3770 hp_flags |= MV_HP_ERRATA_60X1B2;
3771 break;
3772 case 0x9:
3773 hp_flags |= MV_HP_ERRATA_60X1C0;
3774 break;
3775 default:
3776 dev_printk(KERN_WARNING, &pdev->dev,
3777 "Applying B2 workarounds to unknown rev\n");
3778 hp_flags |= MV_HP_ERRATA_60X1B2;
3779 break;
3780 }
3781 break;
3782
3783 case chip_7042:
3784 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
3785 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3786 (pdev->device == 0x2300 || pdev->device == 0x2310))
3787 {
3788 /*
3789 * Highpoint RocketRAID PCIe 23xx series cards:
3790 *
3791 * Unconfigured drives are treated as "Legacy"
3792 * by the BIOS, and it overwrites sector 8 with
3793 * a "Lgcy" metadata block prior to Linux boot.
3794 *
3795 * Configured drives (RAID or JBOD) leave sector 8
3796 * alone, but instead overwrite a high numbered
3797 * sector for the RAID metadata. This sector can
3798 * be determined exactly, by truncating the physical
3799 * drive capacity to a nice even GB value.
3800 *
3801 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3802 *
3803 * Warn the user, lest they think we're just buggy.
3804 */
3805 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3806 " BIOS CORRUPTS DATA on all attached drives,"
3807 " regardless of if/how they are configured."
3808 " BEWARE!\n");
3809 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3810 " use sectors 8-9 on \"Legacy\" drives,"
3811 " and avoid the final two gigabytes on"
3812 " all RocketRAID BIOS initialized drives.\n");
3813 }
3814 /* drop through */
3815 case chip_6042:
3816 hpriv->ops = &mv6xxx_ops;
3817 hp_flags |= MV_HP_GEN_IIE;
3818 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3819 hp_flags |= MV_HP_CUT_THROUGH;
3820
3821 switch (pdev->revision) {
3822 case 0x2: /* Rev.B0: the first/only public release */
3823 hp_flags |= MV_HP_ERRATA_60X1C0;
3824 break;
3825 default:
3826 dev_printk(KERN_WARNING, &pdev->dev,
3827 "Applying 60X1C0 workarounds to unknown rev\n");
3828 hp_flags |= MV_HP_ERRATA_60X1C0;
3829 break;
3830 }
3831 break;
3832 case chip_soc:
3833 if (soc_is_65n(hpriv))
3834 hpriv->ops = &mv_soc_65n_ops;
3835 else
3836 hpriv->ops = &mv_soc_ops;
3837 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3838 MV_HP_ERRATA_60X1C0;
3839 break;
3840
3841 default:
3842 dev_printk(KERN_ERR, host->dev,
3843 "BUG: invalid board index %u\n", board_idx);
3844 return 1;
3845 }
3846
3847 hpriv->hp_flags = hp_flags;
3848 if (hp_flags & MV_HP_PCIE) {
3849 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3850 hpriv->irq_mask_offset = PCIE_IRQ_MASK;
3851 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3852 } else {
3853 hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3854 hpriv->irq_mask_offset = PCI_IRQ_MASK;
3855 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3856 }
3857
3858 return 0;
3859 }
3860
3861 /**
3862 * mv_init_host - Perform some early initialization of the host.
3863 * @host: ATA host to initialize
3864 *
3865 * If possible, do an early global reset of the host. Then do
3866 * our port init and clear/unmask all/relevant host interrupts.
3867 *
3868 * LOCKING:
3869 * Inherited from caller.
3870 */
3871 static int mv_init_host(struct ata_host *host)
3872 {
3873 int rc = 0, n_hc, port, hc;
3874 struct mv_host_priv *hpriv = host->private_data;
3875 void __iomem *mmio = hpriv->base;
3876
3877 rc = mv_chip_id(host, hpriv->board_idx);
3878 if (rc)
3879 goto done;
3880
3881 if (IS_SOC(hpriv)) {
3882 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3883 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
3884 } else {
3885 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3886 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
3887 }
3888
3889 /* initialize shadow irq mask with register's value */
3890 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3891
3892 /* global interrupt mask: 0 == mask everything */
3893 mv_set_main_irq_mask(host, ~0, 0);
3894
3895 n_hc = mv_get_hc_count(host->ports[0]->flags);
3896
3897 for (port = 0; port < host->n_ports; port++)
3898 if (hpriv->ops->read_preamp)
3899 hpriv->ops->read_preamp(hpriv, port, mmio);
3900
3901 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3902 if (rc)
3903 goto done;
3904
3905 hpriv->ops->reset_flash(hpriv, mmio);
3906 hpriv->ops->reset_bus(host, mmio);
3907 hpriv->ops->enable_leds(hpriv, mmio);
3908
3909 for (port = 0; port < host->n_ports; port++) {
3910 struct ata_port *ap = host->ports[port];
3911 void __iomem *port_mmio = mv_port_base(mmio, port);
3912
3913 mv_port_init(&ap->ioaddr, port_mmio);
3914 }
3915
3916 for (hc = 0; hc < n_hc; hc++) {
3917 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3918
3919 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3920 "(before clear)=0x%08x\n", hc,
3921 readl(hc_mmio + HC_CFG),
3922 readl(hc_mmio + HC_IRQ_CAUSE));
3923
3924 /* Clear any currently outstanding hc interrupt conditions */
3925 writelfl(0, hc_mmio + HC_IRQ_CAUSE);
3926 }
3927
3928 if (!IS_SOC(hpriv)) {
3929 /* Clear any currently outstanding host interrupt conditions */
3930 writelfl(0, mmio + hpriv->irq_cause_offset);
3931
3932 /* and unmask interrupt generation for host regs */
3933 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
3934 }
3935
3936 /*
3937 * enable only global host interrupts for now.
3938 * The per-port interrupts get done later as ports are set up.
3939 */
3940 mv_set_main_irq_mask(host, 0, PCI_ERR);
3941 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3942 irq_coalescing_usecs);
3943 done:
3944 return rc;
3945 }
3946
3947 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3948 {
3949 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3950 MV_CRQB_Q_SZ, 0);
3951 if (!hpriv->crqb_pool)
3952 return -ENOMEM;
3953
3954 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3955 MV_CRPB_Q_SZ, 0);
3956 if (!hpriv->crpb_pool)
3957 return -ENOMEM;
3958
3959 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3960 MV_SG_TBL_SZ, 0);
3961 if (!hpriv->sg_tbl_pool)
3962 return -ENOMEM;
3963
3964 return 0;
3965 }
3966
3967 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3968 struct mbus_dram_target_info *dram)
3969 {
3970 int i;
3971
3972 for (i = 0; i < 4; i++) {
3973 writel(0, hpriv->base + WINDOW_CTRL(i));
3974 writel(0, hpriv->base + WINDOW_BASE(i));
3975 }
3976
3977 for (i = 0; i < dram->num_cs; i++) {
3978 struct mbus_dram_window *cs = dram->cs + i;
3979
3980 writel(((cs->size - 1) & 0xffff0000) |
3981 (cs->mbus_attr << 8) |
3982 (dram->mbus_dram_target_id << 4) | 1,
3983 hpriv->base + WINDOW_CTRL(i));
3984 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3985 }
3986 }
3987
3988 /**
3989 * mv_platform_probe - handle a positive probe of an soc Marvell
3990 * host
3991 * @pdev: platform device found
3992 *
3993 * LOCKING:
3994 * Inherited from caller.
3995 */
3996 static int mv_platform_probe(struct platform_device *pdev)
3997 {
3998 static int printed_version;
3999 const struct mv_sata_platform_data *mv_platform_data;
4000 const struct ata_port_info *ppi[] =
4001 { &mv_port_info[chip_soc], NULL };
4002 struct ata_host *host;
4003 struct mv_host_priv *hpriv;
4004 struct resource *res;
4005 int n_ports, rc;
4006
4007 if (!printed_version++)
4008 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
4009
4010 /*
4011 * Simple resource validation ..
4012 */
4013 if (unlikely(pdev->num_resources != 2)) {
4014 dev_err(&pdev->dev, "invalid number of resources\n");
4015 return -EINVAL;
4016 }
4017
4018 /*
4019 * Get the register base first
4020 */
4021 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4022 if (res == NULL)
4023 return -EINVAL;
4024
4025 /* allocate host */
4026 mv_platform_data = pdev->dev.platform_data;
4027 n_ports = mv_platform_data->n_ports;
4028
4029 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4030 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4031
4032 if (!host || !hpriv)
4033 return -ENOMEM;
4034 host->private_data = hpriv;
4035 hpriv->n_ports = n_ports;
4036 hpriv->board_idx = chip_soc;
4037
4038 host->iomap = NULL;
4039 hpriv->base = devm_ioremap(&pdev->dev, res->start,
4040 resource_size(res));
4041 hpriv->base -= SATAHC0_REG_BASE;
4042
4043 #if defined(CONFIG_HAVE_CLK)
4044 hpriv->clk = clk_get(&pdev->dev, NULL);
4045 if (IS_ERR(hpriv->clk))
4046 dev_notice(&pdev->dev, "cannot get clkdev\n");
4047 else
4048 clk_enable(hpriv->clk);
4049 #endif
4050
4051 /*
4052 * (Re-)program MBUS remapping windows if we are asked to.
4053 */
4054 if (mv_platform_data->dram != NULL)
4055 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
4056
4057 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4058 if (rc)
4059 goto err;
4060
4061 /* initialize adapter */
4062 rc = mv_init_host(host);
4063 if (rc)
4064 goto err;
4065
4066 dev_printk(KERN_INFO, &pdev->dev,
4067 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
4068 host->n_ports);
4069
4070 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
4071 IRQF_SHARED, &mv6_sht);
4072 err:
4073 #if defined(CONFIG_HAVE_CLK)
4074 if (!IS_ERR(hpriv->clk)) {
4075 clk_disable(hpriv->clk);
4076 clk_put(hpriv->clk);
4077 }
4078 #endif
4079
4080 return rc;
4081 }
4082
4083 /*
4084 *
4085 * mv_platform_remove - unplug a platform interface
4086 * @pdev: platform device
4087 *
4088 * A platform bus SATA device has been unplugged. Perform the needed
4089 * cleanup. Also called on module unload for any active devices.
4090 */
4091 static int __devexit mv_platform_remove(struct platform_device *pdev)
4092 {
4093 struct device *dev = &pdev->dev;
4094 struct ata_host *host = dev_get_drvdata(dev);
4095 #if defined(CONFIG_HAVE_CLK)
4096 struct mv_host_priv *hpriv = host->private_data;
4097 #endif
4098 ata_host_detach(host);
4099
4100 #if defined(CONFIG_HAVE_CLK)
4101 if (!IS_ERR(hpriv->clk)) {
4102 clk_disable(hpriv->clk);
4103 clk_put(hpriv->clk);
4104 }
4105 #endif
4106 return 0;
4107 }
4108
4109 #ifdef CONFIG_PM
4110 static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)
4111 {
4112 struct ata_host *host = dev_get_drvdata(&pdev->dev);
4113 if (host)
4114 return ata_host_suspend(host, state);
4115 else
4116 return 0;
4117 }
4118
4119 static int mv_platform_resume(struct platform_device *pdev)
4120 {
4121 struct ata_host *host = dev_get_drvdata(&pdev->dev);
4122 int ret;
4123
4124 if (host) {
4125 struct mv_host_priv *hpriv = host->private_data;
4126 const struct mv_sata_platform_data *mv_platform_data = \
4127 pdev->dev.platform_data;
4128 /*
4129 * (Re-)program MBUS remapping windows if we are asked to.
4130 */
4131 if (mv_platform_data->dram != NULL)
4132 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
4133
4134 /* initialize adapter */
4135 ret = mv_init_host(host);
4136 if (ret) {
4137 printk(KERN_ERR DRV_NAME ": Error during HW init\n");
4138 return ret;
4139 }
4140 ata_host_resume(host);
4141 }
4142
4143 return 0;
4144 }
4145 #else
4146 #define mv_platform_suspend NULL
4147 #define mv_platform_resume NULL
4148 #endif
4149
4150 static struct platform_driver mv_platform_driver = {
4151 .probe = mv_platform_probe,
4152 .remove = __devexit_p(mv_platform_remove),
4153 .suspend = mv_platform_suspend,
4154 .resume = mv_platform_resume,
4155 .driver = {
4156 .name = DRV_NAME,
4157 .owner = THIS_MODULE,
4158 },
4159 };
4160
4161
4162 #ifdef CONFIG_PCI
4163 static int mv_pci_init_one(struct pci_dev *pdev,
4164 const struct pci_device_id *ent);
4165 #ifdef CONFIG_PM
4166 static int mv_pci_device_resume(struct pci_dev *pdev);
4167 #endif
4168
4169
4170 static struct pci_driver mv_pci_driver = {
4171 .name = DRV_NAME,
4172 .id_table = mv_pci_tbl,
4173 .probe = mv_pci_init_one,
4174 .remove = ata_pci_remove_one,
4175 #ifdef CONFIG_PM
4176 .suspend = ata_pci_device_suspend,
4177 .resume = mv_pci_device_resume,
4178 #endif
4179
4180 };
4181
4182 /* move to PCI layer or libata core? */
4183 static int pci_go_64(struct pci_dev *pdev)
4184 {
4185 int rc;
4186
4187 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4188 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4189 if (rc) {
4190 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4191 if (rc) {
4192 dev_printk(KERN_ERR, &pdev->dev,
4193 "64-bit DMA enable failed\n");
4194 return rc;
4195 }
4196 }
4197 } else {
4198 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4199 if (rc) {
4200 dev_printk(KERN_ERR, &pdev->dev,
4201 "32-bit DMA enable failed\n");
4202 return rc;
4203 }
4204 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4205 if (rc) {
4206 dev_printk(KERN_ERR, &pdev->dev,
4207 "32-bit consistent DMA enable failed\n");
4208 return rc;
4209 }
4210 }
4211
4212 return rc;
4213 }
4214
4215 /**
4216 * mv_print_info - Dump key info to kernel log for perusal.
4217 * @host: ATA host to print info about
4218 *
4219 * FIXME: complete this.
4220 *
4221 * LOCKING:
4222 * Inherited from caller.
4223 */
4224 static void mv_print_info(struct ata_host *host)
4225 {
4226 struct pci_dev *pdev = to_pci_dev(host->dev);
4227 struct mv_host_priv *hpriv = host->private_data;
4228 u8 scc;
4229 const char *scc_s, *gen;
4230
4231 /* Use this to determine the HW stepping of the chip so we know
4232 * what errata to workaround
4233 */
4234 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
4235 if (scc == 0)
4236 scc_s = "SCSI";
4237 else if (scc == 0x01)
4238 scc_s = "RAID";
4239 else
4240 scc_s = "?";
4241
4242 if (IS_GEN_I(hpriv))
4243 gen = "I";
4244 else if (IS_GEN_II(hpriv))
4245 gen = "II";
4246 else if (IS_GEN_IIE(hpriv))
4247 gen = "IIE";
4248 else
4249 gen = "?";
4250
4251 dev_printk(KERN_INFO, &pdev->dev,
4252 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4253 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
4254 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
4255 }
4256
4257 /**
4258 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
4259 * @pdev: PCI device found
4260 * @ent: PCI device ID entry for the matched host
4261 *
4262 * LOCKING:
4263 * Inherited from caller.
4264 */
4265 static int mv_pci_init_one(struct pci_dev *pdev,
4266 const struct pci_device_id *ent)
4267 {
4268 static int printed_version;
4269 unsigned int board_idx = (unsigned int)ent->driver_data;
4270 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4271 struct ata_host *host;
4272 struct mv_host_priv *hpriv;
4273 int n_ports, port, rc;
4274
4275 if (!printed_version++)
4276 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
4277
4278 /* allocate host */
4279 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4280
4281 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4282 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4283 if (!host || !hpriv)
4284 return -ENOMEM;
4285 host->private_data = hpriv;
4286 hpriv->n_ports = n_ports;
4287 hpriv->board_idx = board_idx;
4288
4289 /* acquire resources */
4290 rc = pcim_enable_device(pdev);
4291 if (rc)
4292 return rc;
4293
4294 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4295 if (rc == -EBUSY)
4296 pcim_pin_device(pdev);
4297 if (rc)
4298 return rc;
4299 host->iomap = pcim_iomap_table(pdev);
4300 hpriv->base = host->iomap[MV_PRIMARY_BAR];
4301
4302 rc = pci_go_64(pdev);
4303 if (rc)
4304 return rc;
4305
4306 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4307 if (rc)
4308 return rc;
4309
4310 for (port = 0; port < host->n_ports; port++) {
4311 struct ata_port *ap = host->ports[port];
4312 void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4313 unsigned int offset = port_mmio - hpriv->base;
4314
4315 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
4316 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
4317 }
4318
4319 /* initialize adapter */
4320 rc = mv_init_host(host);
4321 if (rc)
4322 return rc;
4323
4324 /* Enable message-switched interrupts, if requested */
4325 if (msi && pci_enable_msi(pdev) == 0)
4326 hpriv->hp_flags |= MV_HP_FLAG_MSI;
4327
4328 mv_dump_pci_cfg(pdev, 0x68);
4329 mv_print_info(host);
4330
4331 pci_set_master(pdev);
4332 pci_try_set_mwi(pdev);
4333 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
4334 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
4335 }
4336
4337 #ifdef CONFIG_PM
4338 static int mv_pci_device_resume(struct pci_dev *pdev)
4339 {
4340 struct ata_host *host = dev_get_drvdata(&pdev->dev);
4341 int rc;
4342
4343 rc = ata_pci_device_do_resume(pdev);
4344 if (rc)
4345 return rc;
4346
4347 /* initialize adapter */
4348 rc = mv_init_host(host);
4349 if (rc)
4350 return rc;
4351
4352 ata_host_resume(host);
4353
4354 return 0;
4355 }
4356 #endif
4357 #endif
4358
4359 static int mv_platform_probe(struct platform_device *pdev);
4360 static int __devexit mv_platform_remove(struct platform_device *pdev);
4361
4362 static int __init mv_init(void)
4363 {
4364 int rc = -ENODEV;
4365 #ifdef CONFIG_PCI
4366 rc = pci_register_driver(&mv_pci_driver);
4367 if (rc < 0)
4368 return rc;
4369 #endif
4370 rc = platform_driver_register(&mv_platform_driver);
4371
4372 #ifdef CONFIG_PCI
4373 if (rc < 0)
4374 pci_unregister_driver(&mv_pci_driver);
4375 #endif
4376 return rc;
4377 }
4378
4379 static void __exit mv_exit(void)
4380 {
4381 #ifdef CONFIG_PCI
4382 pci_unregister_driver(&mv_pci_driver);
4383 #endif
4384 platform_driver_unregister(&mv_platform_driver);
4385 }
4386
4387 MODULE_AUTHOR("Brett Russ");
4388 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4389 MODULE_LICENSE("GPL");
4390 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4391 MODULE_VERSION(DRV_VERSION);
4392 MODULE_ALIAS("platform:" DRV_NAME);
4393
4394 module_init(mv_init);
4395 module_exit(mv_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree