?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
USB: usbsevseg: fix max length
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / media / video / em28xx / em28xx-core.c
blob804a4ab47ac636405579d4d6a8003dcffafa04f0
1 /*
2 em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
3
4 Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
5 Markus Rechberger <mrechberger@gmail.com>
6 Mauro Carvalho Chehab <mchehab@infradead.org>
7 Sascha Sommer <saschasommer@freenet.de>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24 #include <linux/init.h>
25 #include <linux/list.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
28 #include <linux/usb.h>
29 #include <linux/vmalloc.h>
30 #include <media/v4l2-common.h>
31
32 #include "em28xx.h"
33
34 /* #define ENABLE_DEBUG_ISOC_FRAMES */
35
36 static unsigned int core_debug;
37 module_param(core_debug, int, 0644);
38 MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
39
40 #define em28xx_coredbg(fmt, arg...) do {\
41 if (core_debug) \
42 printk(KERN_INFO "%s %s :"fmt, \
43 dev->name, __func__ , ##arg); } while (0)
44
45 static unsigned int reg_debug;
46 module_param(reg_debug, int, 0644);
47 MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
48
49 #define em28xx_regdbg(fmt, arg...) do {\
50 if (reg_debug) \
51 printk(KERN_INFO "%s %s :"fmt, \
52 dev->name, __func__ , ##arg); } while (0)
53
54 static int alt;
55 module_param(alt, int, 0644);
56 MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
57
58 static unsigned int disable_vbi;
59 module_param(disable_vbi, int, 0644);
60 MODULE_PARM_DESC(disable_vbi, "disable vbi support");
61
62 /* FIXME */
63 #define em28xx_isocdbg(fmt, arg...) do {\
64 if (core_debug) \
65 printk(KERN_INFO "%s %s :"fmt, \
66 dev->name, __func__ , ##arg); } while (0)
67
68 /*
69 * em28xx_read_reg_req()
70 * reads data from the usb device specifying bRequest
71 */
72 int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
73 char *buf, int len)
74 {
75 int ret;
76 int pipe = usb_rcvctrlpipe(dev->udev, 0);
77
78 if (dev->state & DEV_DISCONNECTED)
79 return -ENODEV;
80
81 if (len > URB_MAX_CTRL_SIZE)
82 return -EINVAL;
83
84 if (reg_debug) {
85 printk(KERN_DEBUG "(pipe 0x%08x): "
86 "IN: %02x %02x %02x %02x %02x %02x %02x %02x ",
87 pipe,
88 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
89 req, 0, 0,
90 reg & 0xff, reg >> 8,
91 len & 0xff, len >> 8);
92 }
93
94 mutex_lock(&dev->ctrl_urb_lock);
95 ret = usb_control_msg(dev->udev, pipe, req,
96 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
97 0x0000, reg, dev->urb_buf, len, HZ);
98 if (ret < 0) {
99 if (reg_debug)
100 printk(" failed!\n");
101 mutex_unlock(&dev->ctrl_urb_lock);
102 return ret;
103 }
104
105 if (len)
106 memcpy(buf, dev->urb_buf, len);
107
108 mutex_unlock(&dev->ctrl_urb_lock);
109
110 if (reg_debug) {
111 int byte;
112
113 printk("<<<");
114 for (byte = 0; byte < len; byte++)
115 printk(" %02x", (unsigned char)buf[byte]);
116 printk("\n");
117 }
118
119 return ret;
120 }
121
122 /*
123 * em28xx_read_reg_req()
124 * reads data from the usb device specifying bRequest
125 */
126 int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
127 {
128 int ret;
129 u8 val;
130
131 ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1);
132 if (ret < 0)
133 return ret;
134
135 return val;
136 }
137
138 int em28xx_read_reg(struct em28xx *dev, u16 reg)
139 {
140 return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
141 }
142
143 /*
144 * em28xx_write_regs_req()
145 * sends data to the usb device, specifying bRequest
146 */
147 int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
148 int len)
149 {
150 int ret;
151 int pipe = usb_sndctrlpipe(dev->udev, 0);
152
153 if (dev->state & DEV_DISCONNECTED)
154 return -ENODEV;
155
156 if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
157 return -EINVAL;
158
159 if (reg_debug) {
160 int byte;
161
162 printk(KERN_DEBUG "(pipe 0x%08x): "
163 "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
164 pipe,
165 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
166 req, 0, 0,
167 reg & 0xff, reg >> 8,
168 len & 0xff, len >> 8);
169
170 for (byte = 0; byte < len; byte++)
171 printk(" %02x", (unsigned char)buf[byte]);
172 printk("\n");
173 }
174
175 mutex_lock(&dev->ctrl_urb_lock);
176 memcpy(dev->urb_buf, buf, len);
177 ret = usb_control_msg(dev->udev, pipe, req,
178 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
179 0x0000, reg, dev->urb_buf, len, HZ);
180 mutex_unlock(&dev->ctrl_urb_lock);
181
182 if (dev->wait_after_write)
183 msleep(dev->wait_after_write);
184
185 return ret;
186 }
187
188 int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
189 {
190 int rc;
191
192 rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
193
194 /* Stores GPO/GPIO values at the cache, if changed
195 Only write values should be stored, since input on a GPIO
196 register will return the input bits.
197 Not sure what happens on reading GPO register.
198 */
199 if (rc >= 0) {
200 if (reg == dev->reg_gpo_num)
201 dev->reg_gpo = buf[0];
202 else if (reg == dev->reg_gpio_num)
203 dev->reg_gpio = buf[0];
204 }
205
206 return rc;
207 }
208
209 /* Write a single register */
210 int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
211 {
212 return em28xx_write_regs(dev, reg, &val, 1);
213 }
214 EXPORT_SYMBOL_GPL(em28xx_write_reg);
215
216 /*
217 * em28xx_write_reg_bits()
218 * sets only some bits (specified by bitmask) of a register, by first reading
219 * the actual value
220 */
221 int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
222 u8 bitmask)
223 {
224 int oldval;
225 u8 newval;
226
227 /* Uses cache for gpo/gpio registers */
228 if (reg == dev->reg_gpo_num)
229 oldval = dev->reg_gpo;
230 else if (reg == dev->reg_gpio_num)
231 oldval = dev->reg_gpio;
232 else
233 oldval = em28xx_read_reg(dev, reg);
234
235 if (oldval < 0)
236 return oldval;
237
238 newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
239
240 return em28xx_write_regs(dev, reg, &newval, 1);
241 }
242
243 /*
244 * em28xx_is_ac97_ready()
245 * Checks if ac97 is ready
246 */
247 static int em28xx_is_ac97_ready(struct em28xx *dev)
248 {
249 int ret, i;
250
251 /* Wait up to 50 ms for AC97 command to complete */
252 for (i = 0; i < 10; i++, msleep(5)) {
253 ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
254 if (ret < 0)
255 return ret;
256
257 if (!(ret & 0x01))
258 return 0;
259 }
260
261 em28xx_warn("AC97 command still being executed: not handled properly!\n");
262 return -EBUSY;
263 }
264
265 /*
266 * em28xx_read_ac97()
267 * write a 16 bit value to the specified AC97 address (LSB first!)
268 */
269 int em28xx_read_ac97(struct em28xx *dev, u8 reg)
270 {
271 int ret;
272 u8 addr = (reg & 0x7f) | 0x80;
273 u16 val;
274
275 ret = em28xx_is_ac97_ready(dev);
276 if (ret < 0)
277 return ret;
278
279 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
280 if (ret < 0)
281 return ret;
282
283 ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
284 (u8 *)&val, sizeof(val));
285
286 if (ret < 0)
287 return ret;
288 return le16_to_cpu(val);
289 }
290 EXPORT_SYMBOL_GPL(em28xx_read_ac97);
291
292 /*
293 * em28xx_write_ac97()
294 * write a 16 bit value to the specified AC97 address (LSB first!)
295 */
296 int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
297 {
298 int ret;
299 u8 addr = reg & 0x7f;
300 __le16 value;
301
302 value = cpu_to_le16(val);
303
304 ret = em28xx_is_ac97_ready(dev);
305 if (ret < 0)
306 return ret;
307
308 ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
309 if (ret < 0)
310 return ret;
311
312 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
313 if (ret < 0)
314 return ret;
315
316 return 0;
317 }
318 EXPORT_SYMBOL_GPL(em28xx_write_ac97);
319
320 struct em28xx_vol_itable {
321 enum em28xx_amux mux;
322 u8 reg;
323 };
324
325 static struct em28xx_vol_itable inputs[] = {
326 { EM28XX_AMUX_VIDEO, AC97_VIDEO_VOL },
327 { EM28XX_AMUX_LINE_IN, AC97_LINEIN_VOL },
328 { EM28XX_AMUX_PHONE, AC97_PHONE_VOL },
329 { EM28XX_AMUX_MIC, AC97_MIC_VOL },
330 { EM28XX_AMUX_CD, AC97_CD_VOL },
331 { EM28XX_AMUX_AUX, AC97_AUX_VOL },
332 { EM28XX_AMUX_PCM_OUT, AC97_PCM_OUT_VOL },
333 };
334
335 static int set_ac97_input(struct em28xx *dev)
336 {
337 int ret, i;
338 enum em28xx_amux amux = dev->ctl_ainput;
339
340 /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
341 em28xx should point to LINE IN, while AC97 should use VIDEO
342 */
343 if (amux == EM28XX_AMUX_VIDEO2)
344 amux = EM28XX_AMUX_VIDEO;
345
346 /* Mute all entres but the one that were selected */
347 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
348 if (amux == inputs[i].mux)
349 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
350 else
351 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
352
353 if (ret < 0)
354 em28xx_warn("couldn't setup AC97 register %d\n",
355 inputs[i].reg);
356 }
357 return 0;
358 }
359
360 static int em28xx_set_audio_source(struct em28xx *dev)
361 {
362 int ret;
363 u8 input;
364
365 if (dev->board.is_em2800) {
366 if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
367 input = EM2800_AUDIO_SRC_TUNER;
368 else
369 input = EM2800_AUDIO_SRC_LINE;
370
371 ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
372 if (ret < 0)
373 return ret;
374 }
375
376 if (dev->board.has_msp34xx)
377 input = EM28XX_AUDIO_SRC_TUNER;
378 else {
379 switch (dev->ctl_ainput) {
380 case EM28XX_AMUX_VIDEO:
381 input = EM28XX_AUDIO_SRC_TUNER;
382 break;
383 default:
384 input = EM28XX_AUDIO_SRC_LINE;
385 break;
386 }
387 }
388
389 if (dev->board.mute_gpio && dev->mute)
390 em28xx_gpio_set(dev, dev->board.mute_gpio);
391 else
392 em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
393
394 ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
395 if (ret < 0)
396 return ret;
397 msleep(5);
398
399 switch (dev->audio_mode.ac97) {
400 case EM28XX_NO_AC97:
401 break;
402 default:
403 ret = set_ac97_input(dev);
404 }
405
406 return ret;
407 }
408
409 struct em28xx_vol_otable {
410 enum em28xx_aout mux;
411 u8 reg;
412 };
413
414 static const struct em28xx_vol_otable outputs[] = {
415 { EM28XX_AOUT_MASTER, AC97_MASTER_VOL },
416 { EM28XX_AOUT_LINE, AC97_LINE_LEVEL_VOL },
417 { EM28XX_AOUT_MONO, AC97_MASTER_MONO_VOL },
418 { EM28XX_AOUT_LFE, AC97_LFE_MASTER_VOL },
419 { EM28XX_AOUT_SURR, AC97_SURR_MASTER_VOL },
420 };
421
422 int em28xx_audio_analog_set(struct em28xx *dev)
423 {
424 int ret, i;
425 u8 xclk;
426
427 if (!dev->audio_mode.has_audio)
428 return 0;
429
430 /* It is assumed that all devices use master volume for output.
431 It would be possible to use also line output.
432 */
433 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
434 /* Mute all outputs */
435 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
436 ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
437 if (ret < 0)
438 em28xx_warn("couldn't setup AC97 register %d\n",
439 outputs[i].reg);
440 }
441 }
442
443 xclk = dev->board.xclk & 0x7f;
444 if (!dev->mute)
445 xclk |= EM28XX_XCLK_AUDIO_UNMUTE;
446
447 ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
448 if (ret < 0)
449 return ret;
450 msleep(10);
451
452 /* Selects the proper audio input */
453 ret = em28xx_set_audio_source(dev);
454
455 /* Sets volume */
456 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
457 int vol;
458
459 em28xx_write_ac97(dev, AC97_POWER_DOWN_CTRL, 0x4200);
460 em28xx_write_ac97(dev, AC97_EXT_AUD_CTRL, 0x0031);
461 em28xx_write_ac97(dev, AC97_PCM_IN_SRATE, 0xbb80);
462
463 /* LSB: left channel - both channels with the same level */
464 vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
465
466 /* Mute device, if needed */
467 if (dev->mute)
468 vol |= 0x8000;
469
470 /* Sets volume */
471 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
472 if (dev->ctl_aoutput & outputs[i].mux)
473 ret = em28xx_write_ac97(dev, outputs[i].reg,
474 vol);
475 if (ret < 0)
476 em28xx_warn("couldn't setup AC97 register %d\n",
477 outputs[i].reg);
478 }
479
480 if (dev->ctl_aoutput & EM28XX_AOUT_PCM_IN) {
481 int sel = ac97_return_record_select(dev->ctl_aoutput);
482
483 /* Use the same input for both left and right
484 channels */
485 sel |= (sel << 8);
486
487 em28xx_write_ac97(dev, AC97_RECORD_SELECT, sel);
488 }
489 }
490
491 return ret;
492 }
493 EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
494
495 int em28xx_audio_setup(struct em28xx *dev)
496 {
497 int vid1, vid2, feat, cfg;
498 u32 vid;
499
500 if (dev->chip_id == CHIP_ID_EM2870 || dev->chip_id == CHIP_ID_EM2874
501 || dev->chip_id == CHIP_ID_EM28174) {
502 /* Digital only device - don't load any alsa module */
503 dev->audio_mode.has_audio = false;
504 dev->has_audio_class = false;
505 dev->has_alsa_audio = false;
506 return 0;
507 }
508
509 dev->audio_mode.has_audio = true;
510
511 /* See how this device is configured */
512 cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
513 em28xx_info("Config register raw data: 0x%02x\n", cfg);
514 if (cfg < 0) {
515 /* Register read error? */
516 cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
517 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) == 0x00) {
518 /* The device doesn't have vendor audio at all */
519 dev->has_alsa_audio = false;
520 dev->audio_mode.has_audio = false;
521 return 0;
522 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
523 EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
524 em28xx_info("I2S Audio (3 sample rates)\n");
525 dev->audio_mode.i2s_3rates = 1;
526 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
527 EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
528 em28xx_info("I2S Audio (5 sample rates)\n");
529 dev->audio_mode.i2s_5rates = 1;
530 }
531
532 if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) != EM28XX_CHIPCFG_AC97) {
533 /* Skip the code that does AC97 vendor detection */
534 dev->audio_mode.ac97 = EM28XX_NO_AC97;
535 goto init_audio;
536 }
537
538 dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
539
540 vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
541 if (vid1 < 0) {
542 /*
543 * Device likely doesn't support AC97
544 * Note: (some) em2800 devices without eeprom reports 0x91 on
545 * CHIPCFG register, even not having an AC97 chip
546 */
547 em28xx_warn("AC97 chip type couldn't be determined\n");
548 dev->audio_mode.ac97 = EM28XX_NO_AC97;
549 dev->has_alsa_audio = false;
550 dev->audio_mode.has_audio = false;
551 goto init_audio;
552 }
553
554 vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
555 if (vid2 < 0)
556 goto init_audio;
557
558 vid = vid1 << 16 | vid2;
559
560 dev->audio_mode.ac97_vendor_id = vid;
561 em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
562
563 feat = em28xx_read_ac97(dev, AC97_RESET);
564 if (feat < 0)
565 goto init_audio;
566
567 dev->audio_mode.ac97_feat = feat;
568 em28xx_warn("AC97 features = 0x%04x\n", feat);
569
570 /* Try to identify what audio processor we have */
571 if ((vid == 0xffffffff) && (feat == 0x6a90))
572 dev->audio_mode.ac97 = EM28XX_AC97_EM202;
573 else if ((vid >> 8) == 0x838476)
574 dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
575
576 init_audio:
577 /* Reports detected AC97 processor */
578 switch (dev->audio_mode.ac97) {
579 case EM28XX_NO_AC97:
580 em28xx_info("No AC97 audio processor\n");
581 break;
582 case EM28XX_AC97_EM202:
583 em28xx_info("Empia 202 AC97 audio processor detected\n");
584 break;
585 case EM28XX_AC97_SIGMATEL:
586 em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n",
587 dev->audio_mode.ac97_vendor_id & 0xff);
588 break;
589 case EM28XX_AC97_OTHER:
590 em28xx_warn("Unknown AC97 audio processor detected!\n");
591 break;
592 default:
593 break;
594 }
595
596 return em28xx_audio_analog_set(dev);
597 }
598 EXPORT_SYMBOL_GPL(em28xx_audio_setup);
599
600 int em28xx_colorlevels_set_default(struct em28xx *dev)
601 {
602 em28xx_write_reg(dev, EM28XX_R20_YGAIN, 0x10); /* contrast */
603 em28xx_write_reg(dev, EM28XX_R21_YOFFSET, 0x00); /* brightness */
604 em28xx_write_reg(dev, EM28XX_R22_UVGAIN, 0x10); /* saturation */
605 em28xx_write_reg(dev, EM28XX_R23_UOFFSET, 0x00);
606 em28xx_write_reg(dev, EM28XX_R24_VOFFSET, 0x00);
607 em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, 0x00);
608
609 em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20);
610 em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20);
611 em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20);
612 em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20);
613 em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00);
614 em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00);
615 return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00);
616 }
617
618 int em28xx_capture_start(struct em28xx *dev, int start)
619 {
620 int rc;
621
622 if (dev->chip_id == CHIP_ID_EM2874 ||
623 dev->chip_id == CHIP_ID_EM2884 ||
624 dev->chip_id == CHIP_ID_EM28174) {
625 /* The Transport Stream Enable Register moved in em2874 */
626 if (!start) {
627 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
628 0x00,
629 EM2874_TS1_CAPTURE_ENABLE);
630 return rc;
631 }
632
633 /* Enable Transport Stream */
634 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
635 EM2874_TS1_CAPTURE_ENABLE,
636 EM2874_TS1_CAPTURE_ENABLE);
637 return rc;
638 }
639
640
641 /* FIXME: which is the best order? */
642 /* video registers are sampled by VREF */
643 rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
644 start ? 0x10 : 0x00, 0x10);
645 if (rc < 0)
646 return rc;
647
648 if (!start) {
649 /* disable video capture */
650 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
651 return rc;
652 }
653
654 if (dev->board.is_webcam)
655 rc = em28xx_write_reg(dev, 0x13, 0x0c);
656
657 /* enable video capture */
658 rc = em28xx_write_reg(dev, 0x48, 0x00);
659
660 if (dev->mode == EM28XX_ANALOG_MODE)
661 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
662 else
663 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
664
665 msleep(6);
666
667 return rc;
668 }
669
670 int em28xx_vbi_supported(struct em28xx *dev)
671 {
672 /* Modprobe option to manually disable */
673 if (disable_vbi == 1)
674 return 0;
675
676 if (dev->chip_id == CHIP_ID_EM2860 ||
677 dev->chip_id == CHIP_ID_EM2883)
678 return 1;
679
680 /* Version of em28xx that does not support VBI */
681 return 0;
682 }
683
684 int em28xx_set_outfmt(struct em28xx *dev)
685 {
686 int ret;
687 u8 vinctrl;
688
689 ret = em28xx_write_reg_bits(dev, EM28XX_R27_OUTFMT,
690 dev->format->reg | 0x20, 0xff);
691 if (ret < 0)
692 return ret;
693
694 ret = em28xx_write_reg(dev, EM28XX_R10_VINMODE, dev->vinmode);
695 if (ret < 0)
696 return ret;
697
698 vinctrl = dev->vinctl;
699 if (em28xx_vbi_supported(dev) == 1) {
700 vinctrl |= EM28XX_VINCTRL_VBI_RAW;
701 em28xx_write_reg(dev, EM28XX_R34_VBI_START_H, 0x00);
702 em28xx_write_reg(dev, EM28XX_R36_VBI_WIDTH, dev->vbi_width/4);
703 em28xx_write_reg(dev, EM28XX_R37_VBI_HEIGHT, dev->vbi_height);
704 if (dev->norm & V4L2_STD_525_60) {
705 /* NTSC */
706 em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x09);
707 } else if (dev->norm & V4L2_STD_625_50) {
708 /* PAL */
709 em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x07);
710 }
711 }
712
713 return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, vinctrl);
714 }
715
716 static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
717 u8 ymin, u8 ymax)
718 {
719 em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
720 xmin, ymin, xmax, ymax);
721
722 em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
723 em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
724 em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
725 return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
726 }
727
728 static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
729 u16 width, u16 height)
730 {
731 u8 cwidth = width;
732 u8 cheight = height;
733 u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
734
735 em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
736 (width | (overflow & 2) << 7),
737 (height | (overflow & 1) << 8));
738
739 em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
740 em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
741 em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
742 em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
743 return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
744 }
745
746 static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
747 {
748 u8 mode;
749 /* the em2800 scaler only supports scaling down to 50% */
750
751 if (dev->board.is_em2800) {
752 mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
753 } else {
754 u8 buf[2];
755
756 buf[0] = h;
757 buf[1] = h >> 8;
758 em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
759
760 buf[0] = v;
761 buf[1] = v >> 8;
762 em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
763 /* it seems that both H and V scalers must be active
764 to work correctly */
765 mode = (h || v) ? 0x30 : 0x00;
766 }
767 return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
768 }
769
770 /* FIXME: this only function read values from dev */
771 int em28xx_resolution_set(struct em28xx *dev)
772 {
773 int width, height;
774 width = norm_maxw(dev);
775 height = norm_maxh(dev);
776
777 /* Properly setup VBI */
778 dev->vbi_width = 720;
779 if (dev->norm & V4L2_STD_525_60)
780 dev->vbi_height = 12;
781 else
782 dev->vbi_height = 18;
783
784 if (!dev->progressive)
785 height >>= norm_maxh(dev);
786
787 em28xx_set_outfmt(dev);
788
789
790 em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
791
792 /* If we don't set the start position to 2 in VBI mode, we end up
793 with line 20/21 being YUYV encoded instead of being in 8-bit
794 greyscale. The core of the issue is that line 21 (and line 23 for
795 PAL WSS) are inside of active video region, and as a result they
796 get the pixelformatting associated with that area. So by cropping
797 it out, we end up with the same format as the rest of the VBI
798 region */
799 if (em28xx_vbi_supported(dev) == 1)
800 em28xx_capture_area_set(dev, 0, 2, width >> 2, height >> 2);
801 else
802 em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
803
804 return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
805 }
806
807 int em28xx_set_alternate(struct em28xx *dev)
808 {
809 int errCode, prev_alt = dev->alt;
810 int i;
811 unsigned int min_pkt_size = dev->width * 2 + 4;
812
813 /*
814 * alt = 0 is used only for control messages, so, only values
815 * greater than 0 can be used for streaming.
816 */
817 if (alt && alt < dev->num_alt) {
818 em28xx_coredbg("alternate forced to %d\n", dev->alt);
819 dev->alt = alt;
820 goto set_alt;
821 }
822
823 /* When image size is bigger than a certain value,
824 the frame size should be increased, otherwise, only
825 green screen will be received.
826 */
827 if (dev->width * 2 * dev->height > 720 * 240 * 2)
828 min_pkt_size *= 2;
829
830 for (i = 0; i < dev->num_alt; i++) {
831 /* stop when the selected alt setting offers enough bandwidth */
832 if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
833 dev->alt = i;
834 break;
835 /* otherwise make sure that we end up with the maximum bandwidth
836 because the min_pkt_size equation might be wrong...
837 */
838 } else if (dev->alt_max_pkt_size[i] >
839 dev->alt_max_pkt_size[dev->alt])
840 dev->alt = i;
841 }
842
843 set_alt:
844 if (dev->alt != prev_alt) {
845 em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
846 min_pkt_size, dev->alt);
847 dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
848 em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
849 dev->alt, dev->max_pkt_size);
850 errCode = usb_set_interface(dev->udev, 0, dev->alt);
851 if (errCode < 0) {
852 em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
853 dev->alt, errCode);
854 return errCode;
855 }
856 }
857 return 0;
858 }
859
860 int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
861 {
862 int rc = 0;
863
864 if (!gpio)
865 return rc;
866
867 if (dev->mode != EM28XX_SUSPEND) {
868 em28xx_write_reg(dev, 0x48, 0x00);
869 if (dev->mode == EM28XX_ANALOG_MODE)
870 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
871 else
872 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
873 msleep(6);
874 }
875
876 /* Send GPIO reset sequences specified at board entry */
877 while (gpio->sleep >= 0) {
878 if (gpio->reg >= 0) {
879 rc = em28xx_write_reg_bits(dev,
880 gpio->reg,
881 gpio->val,
882 gpio->mask);
883 if (rc < 0)
884 return rc;
885 }
886 if (gpio->sleep > 0)
887 msleep(gpio->sleep);
888
889 gpio++;
890 }
891 return rc;
892 }
893 EXPORT_SYMBOL_GPL(em28xx_gpio_set);
894
895 int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
896 {
897 if (dev->mode == set_mode)
898 return 0;
899
900 if (set_mode == EM28XX_SUSPEND) {
901 dev->mode = set_mode;
902
903 /* FIXME: add suspend support for ac97 */
904
905 return em28xx_gpio_set(dev, dev->board.suspend_gpio);
906 }
907
908 dev->mode = set_mode;
909
910 if (dev->mode == EM28XX_DIGITAL_MODE)
911 return em28xx_gpio_set(dev, dev->board.dvb_gpio);
912 else
913 return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
914 }
915 EXPORT_SYMBOL_GPL(em28xx_set_mode);
916
917 /* ------------------------------------------------------------------
918 URB control
919 ------------------------------------------------------------------*/
920
921 /*
922 * IRQ callback, called by URB callback
923 */
924 static void em28xx_irq_callback(struct urb *urb)
925 {
926 struct em28xx *dev = urb->context;
927 int i;
928
929 switch (urb->status) {
930 case 0: /* success */
931 case -ETIMEDOUT: /* NAK */
932 break;
933 case -ECONNRESET: /* kill */
934 case -ENOENT:
935 case -ESHUTDOWN:
936 return;
937 default: /* error */
938 em28xx_isocdbg("urb completition error %d.\n", urb->status);
939 break;
940 }
941
942 /* Copy data from URB */
943 spin_lock(&dev->slock);
944 dev->isoc_ctl.isoc_copy(dev, urb);
945 spin_unlock(&dev->slock);
946
947 /* Reset urb buffers */
948 for (i = 0; i < urb->number_of_packets; i++) {
949 urb->iso_frame_desc[i].status = 0;
950 urb->iso_frame_desc[i].actual_length = 0;
951 }
952 urb->status = 0;
953
954 urb->status = usb_submit_urb(urb, GFP_ATOMIC);
955 if (urb->status) {
956 em28xx_isocdbg("urb resubmit failed (error=%i)\n",
957 urb->status);
958 }
959 }
960
961 /*
962 * Stop and Deallocate URBs
963 */
964 void em28xx_uninit_isoc(struct em28xx *dev)
965 {
966 struct urb *urb;
967 int i;
968
969 em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n");
970
971 dev->isoc_ctl.nfields = -1;
972 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
973 urb = dev->isoc_ctl.urb[i];
974 if (urb) {
975 if (!irqs_disabled())
976 usb_kill_urb(urb);
977 else
978 usb_unlink_urb(urb);
979
980 if (dev->isoc_ctl.transfer_buffer[i]) {
981 usb_free_coherent(dev->udev,
982 urb->transfer_buffer_length,
983 dev->isoc_ctl.transfer_buffer[i],
984 urb->transfer_dma);
985 }
986 usb_free_urb(urb);
987 dev->isoc_ctl.urb[i] = NULL;
988 }
989 dev->isoc_ctl.transfer_buffer[i] = NULL;
990 }
991
992 kfree(dev->isoc_ctl.urb);
993 kfree(dev->isoc_ctl.transfer_buffer);
994
995 dev->isoc_ctl.urb = NULL;
996 dev->isoc_ctl.transfer_buffer = NULL;
997 dev->isoc_ctl.num_bufs = 0;
998
999 em28xx_capture_start(dev, 0);
1000 }
1001 EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
1002
1003 /*
1004 * Allocate URBs and start IRQ
1005 */
1006 int em28xx_init_isoc(struct em28xx *dev, int max_packets,
1007 int num_bufs, int max_pkt_size,
1008 int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
1009 {
1010 struct em28xx_dmaqueue *dma_q = &dev->vidq;
1011 struct em28xx_dmaqueue *vbi_dma_q = &dev->vbiq;
1012 int i;
1013 int sb_size, pipe;
1014 struct urb *urb;
1015 int j, k;
1016 int rc;
1017
1018 em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n");
1019
1020 /* De-allocates all pending stuff */
1021 em28xx_uninit_isoc(dev);
1022
1023 dev->isoc_ctl.isoc_copy = isoc_copy;
1024 dev->isoc_ctl.num_bufs = num_bufs;
1025
1026 dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
1027 if (!dev->isoc_ctl.urb) {
1028 em28xx_errdev("cannot alloc memory for usb buffers\n");
1029 return -ENOMEM;
1030 }
1031
1032 dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
1033 GFP_KERNEL);
1034 if (!dev->isoc_ctl.transfer_buffer) {
1035 em28xx_errdev("cannot allocate memory for usb transfer\n");
1036 kfree(dev->isoc_ctl.urb);
1037 return -ENOMEM;
1038 }
1039
1040 dev->isoc_ctl.max_pkt_size = max_pkt_size;
1041 dev->isoc_ctl.vid_buf = NULL;
1042 dev->isoc_ctl.vbi_buf = NULL;
1043
1044 sb_size = max_packets * dev->isoc_ctl.max_pkt_size;
1045
1046 /* allocate urbs and transfer buffers */
1047 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
1048 urb = usb_alloc_urb(max_packets, GFP_KERNEL);
1049 if (!urb) {
1050 em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
1051 em28xx_uninit_isoc(dev);
1052 return -ENOMEM;
1053 }
1054 dev->isoc_ctl.urb[i] = urb;
1055
1056 dev->isoc_ctl.transfer_buffer[i] = usb_alloc_coherent(dev->udev,
1057 sb_size, GFP_KERNEL, &urb->transfer_dma);
1058 if (!dev->isoc_ctl.transfer_buffer[i]) {
1059 em28xx_err("unable to allocate %i bytes for transfer"
1060 " buffer %i%s\n",
1061 sb_size, i,
1062 in_interrupt() ? " while in int" : "");
1063 em28xx_uninit_isoc(dev);
1064 return -ENOMEM;
1065 }
1066 memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
1067
1068 /* FIXME: this is a hack - should be
1069 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
1070 should also be using 'desc.bInterval'
1071 */
1072 pipe = usb_rcvisocpipe(dev->udev,
1073 dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84);
1074
1075 usb_fill_int_urb(urb, dev->udev, pipe,
1076 dev->isoc_ctl.transfer_buffer[i], sb_size,
1077 em28xx_irq_callback, dev, 1);
1078
1079 urb->number_of_packets = max_packets;
1080 urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP;
1081
1082 k = 0;
1083 for (j = 0; j < max_packets; j++) {
1084 urb->iso_frame_desc[j].offset = k;
1085 urb->iso_frame_desc[j].length =
1086 dev->isoc_ctl.max_pkt_size;
1087 k += dev->isoc_ctl.max_pkt_size;
1088 }
1089 }
1090
1091 init_waitqueue_head(&dma_q->wq);
1092 init_waitqueue_head(&vbi_dma_q->wq);
1093
1094 em28xx_capture_start(dev, 1);
1095
1096 /* submit urbs and enables IRQ */
1097 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
1098 rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC);
1099 if (rc) {
1100 em28xx_err("submit of urb %i failed (error=%i)\n", i,
1101 rc);
1102 em28xx_uninit_isoc(dev);
1103 return rc;
1104 }
1105 }
1106
1107 return 0;
1108 }
1109 EXPORT_SYMBOL_GPL(em28xx_init_isoc);
1110
1111 /* Determine the packet size for the DVB stream for the given device
1112 (underlying value programmed into the eeprom) */
1113 int em28xx_isoc_dvb_max_packetsize(struct em28xx *dev)
1114 {
1115 unsigned int chip_cfg2;
1116 unsigned int packet_size;
1117
1118 switch (dev->chip_id) {
1119 case CHIP_ID_EM2710:
1120 case CHIP_ID_EM2750:
1121 case CHIP_ID_EM2800:
1122 case CHIP_ID_EM2820:
1123 case CHIP_ID_EM2840:
1124 case CHIP_ID_EM2860:
1125 /* No DVB support */
1126 return -EINVAL;
1127 case CHIP_ID_EM2870:
1128 case CHIP_ID_EM2883:
1129 /* TS max packet size stored in bits 1-0 of R01 */
1130 chip_cfg2 = em28xx_read_reg(dev, EM28XX_R01_CHIPCFG2);
1131 switch (chip_cfg2 & EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK) {
1132 case EM28XX_CHIPCFG2_TS_PACKETSIZE_188:
1133 packet_size = 188;
1134 break;
1135 case EM28XX_CHIPCFG2_TS_PACKETSIZE_376:
1136 packet_size = 376;
1137 break;
1138 case EM28XX_CHIPCFG2_TS_PACKETSIZE_564:
1139 packet_size = 564;
1140 break;
1141 case EM28XX_CHIPCFG2_TS_PACKETSIZE_752:
1142 packet_size = 752;
1143 break;
1144 }
1145 break;
1146 case CHIP_ID_EM2874:
1147 /*
1148 * FIXME: for now assumes 564 like it was before, but the
1149 * em2874 code should be added to return the proper value
1150 */
1151 packet_size = 564;
1152 break;
1153 case CHIP_ID_EM2884:
1154 case CHIP_ID_EM28174:
1155 default:
1156 /*
1157 * FIXME: same as em2874. 564 was enough for 22 Mbit DVB-T
1158 * but not enough for 44 Mbit DVB-C.
1159 */
1160 packet_size = 752;
1161 }
1162
1163 return packet_size;
1164 }
1165 EXPORT_SYMBOL_GPL(em28xx_isoc_dvb_max_packetsize);
1166
1167 /*
1168 * em28xx_wake_i2c()
1169 * configure i2c attached devices
1170 */
1171 void em28xx_wake_i2c(struct em28xx *dev)
1172 {
1173 v4l2_device_call_all(&dev->v4l2_dev, 0, core, reset, 0);
1174 v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_routing,
1175 INPUT(dev->ctl_input)->vmux, 0, 0);
1176 v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_stream, 0);
1177 }
1178
1179 /*
1180 * Device control list
1181 */
1182
1183 static LIST_HEAD(em28xx_devlist);
1184 static DEFINE_MUTEX(em28xx_devlist_mutex);
1185
1186 /*
1187 * Extension interface
1188 */
1189
1190 static LIST_HEAD(em28xx_extension_devlist);
1191
1192 int em28xx_register_extension(struct em28xx_ops *ops)
1193 {
1194 struct em28xx *dev = NULL;
1195
1196 mutex_lock(&em28xx_devlist_mutex);
1197 list_add_tail(&ops->next, &em28xx_extension_devlist);
1198 list_for_each_entry(dev, &em28xx_devlist, devlist) {
1199 ops->init(dev);
1200 }
1201 mutex_unlock(&em28xx_devlist_mutex);
1202 printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name);
1203 return 0;
1204 }
1205 EXPORT_SYMBOL(em28xx_register_extension);
1206
1207 void em28xx_unregister_extension(struct em28xx_ops *ops)
1208 {
1209 struct em28xx *dev = NULL;
1210
1211 mutex_lock(&em28xx_devlist_mutex);
1212 list_for_each_entry(dev, &em28xx_devlist, devlist) {
1213 ops->fini(dev);
1214 }
1215 list_del(&ops->next);
1216 mutex_unlock(&em28xx_devlist_mutex);
1217 printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name);
1218 }
1219 EXPORT_SYMBOL(em28xx_unregister_extension);
1220
1221 void em28xx_init_extension(struct em28xx *dev)
1222 {
1223 const struct em28xx_ops *ops = NULL;
1224
1225 mutex_lock(&em28xx_devlist_mutex);
1226 list_add_tail(&dev->devlist, &em28xx_devlist);
1227 list_for_each_entry(ops, &em28xx_extension_devlist, next) {
1228 if (ops->init)
1229 ops->init(dev);
1230 }
1231 mutex_unlock(&em28xx_devlist_mutex);
1232 }
1233
1234 void em28xx_close_extension(struct em28xx *dev)
1235 {
1236 const struct em28xx_ops *ops = NULL;
1237
1238 mutex_lock(&em28xx_devlist_mutex);
1239 list_for_each_entry(ops, &em28xx_extension_devlist, next) {
1240 if (ops->fini)
1241 ops->fini(dev);
1242 }
1243 list_del(&dev->devlist);
1244 mutex_unlock(&em28xx_devlist_mutex);
1245 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree