drivers/iommu/amd_iommu_types.h

   1 /*
   2  * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
   3  * Author: Joerg Roedel <joerg.roedel@amd.com>
   4  *         Leo Duran <leo.duran@amd.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
  21 #define _ASM_X86_AMD_IOMMU_TYPES_H
  22
  23 #include <linux/types.h>
  24 #include <linux/mutex.h>
  25 #include <linux/list.h>
  26 #include <linux/spinlock.h>
  27
  28 /*
  29  * Maximum number of IOMMUs supported
  30  */
  31 #define MAX_IOMMUS      32
  32
  33 /*
  34  * some size calculation constants
  35  */
  36 #define DEV_TABLE_ENTRY_SIZE            32
  37 #define ALIAS_TABLE_ENTRY_SIZE          2
  38 #define RLOOKUP_TABLE_ENTRY_SIZE        (sizeof(void *))
  39
  40 /* Length of the MMIO region for the AMD IOMMU */
  41 #define MMIO_REGION_LENGTH       0x4000
  42
  43 /* Capability offsets used by the driver */
  44 #define MMIO_CAP_HDR_OFFSET     0x00
  45 #define MMIO_RANGE_OFFSET       0x0c
  46 #define MMIO_MISC_OFFSET        0x10
  47
  48 /* Masks, shifts and macros to parse the device range capability */
  49 #define MMIO_RANGE_LD_MASK      0xff000000
  50 #define MMIO_RANGE_FD_MASK      0x00ff0000
  51 #define MMIO_RANGE_BUS_MASK     0x0000ff00
  52 #define MMIO_RANGE_LD_SHIFT     24
  53 #define MMIO_RANGE_FD_SHIFT     16
  54 #define MMIO_RANGE_BUS_SHIFT    8
  55 #define MMIO_GET_LD(x)  (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
  56 #define MMIO_GET_FD(x)  (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
  57 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
  58 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
  59
  60 /* Flag masks for the AMD IOMMU exclusion range */
  61 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
  62 #define MMIO_EXCL_ALLOW_MASK  0x02ULL
  63
  64 /* Used offsets into the MMIO space */
  65 #define MMIO_DEV_TABLE_OFFSET   0x0000
  66 #define MMIO_CMD_BUF_OFFSET     0x0008
  67 #define MMIO_EVT_BUF_OFFSET     0x0010
  68 #define MMIO_CONTROL_OFFSET     0x0018
  69 #define MMIO_EXCL_BASE_OFFSET   0x0020
  70 #define MMIO_EXCL_LIMIT_OFFSET  0x0028
  71 #define MMIO_EXT_FEATURES       0x0030
  72 #define MMIO_CMD_HEAD_OFFSET    0x2000
  73 #define MMIO_CMD_TAIL_OFFSET    0x2008
  74 #define MMIO_EVT_HEAD_OFFSET    0x2010
  75 #define MMIO_EVT_TAIL_OFFSET    0x2018
  76 #define MMIO_STATUS_OFFSET      0x2020
  77
  78
  79 /* Extended Feature Bits */
  80 #define FEATURE_PREFETCH        (1ULL<<0)
  81 #define FEATURE_PPR             (1ULL<<1)
  82 #define FEATURE_X2APIC          (1ULL<<2)
  83 #define FEATURE_NX              (1ULL<<3)
  84 #define FEATURE_GT              (1ULL<<4)
  85 #define FEATURE_IA              (1ULL<<6)
  86 #define FEATURE_GA              (1ULL<<7)
  87 #define FEATURE_HE              (1ULL<<8)
  88 #define FEATURE_PC              (1ULL<<9)
  89
  90 /* MMIO status bits */
  91 #define MMIO_STATUS_COM_WAIT_INT_MASK   0x04
  92
  93 /* event logging constants */
  94 #define EVENT_ENTRY_SIZE        0x10
  95 #define EVENT_TYPE_SHIFT        28
  96 #define EVENT_TYPE_MASK         0xf
  97 #define EVENT_TYPE_ILL_DEV      0x1
  98 #define EVENT_TYPE_IO_FAULT     0x2
  99 #define EVENT_TYPE_DEV_TAB_ERR  0x3
 100 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
 101 #define EVENT_TYPE_ILL_CMD      0x5
 102 #define EVENT_TYPE_CMD_HARD_ERR 0x6
 103 #define EVENT_TYPE_IOTLB_INV_TO 0x7
 104 #define EVENT_TYPE_INV_DEV_REQ  0x8
 105 #define EVENT_DEVID_MASK        0xffff
 106 #define EVENT_DEVID_SHIFT       0
 107 #define EVENT_DOMID_MASK        0xffff
 108 #define EVENT_DOMID_SHIFT       0
 109 #define EVENT_FLAGS_MASK        0xfff
 110 #define EVENT_FLAGS_SHIFT       0x10
 111
 112 /* feature control bits */
 113 #define CONTROL_IOMMU_EN        0x00ULL
 114 #define CONTROL_HT_TUN_EN       0x01ULL
 115 #define CONTROL_EVT_LOG_EN      0x02ULL
 116 #define CONTROL_EVT_INT_EN      0x03ULL
 117 #define CONTROL_COMWAIT_EN      0x04ULL
 118 #define CONTROL_PASSPW_EN       0x08ULL
 119 #define CONTROL_RESPASSPW_EN    0x09ULL
 120 #define CONTROL_COHERENT_EN     0x0aULL
 121 #define CONTROL_ISOC_EN         0x0bULL
 122 #define CONTROL_CMDBUF_EN       0x0cULL
 123 #define CONTROL_PPFLOG_EN       0x0dULL
 124 #define CONTROL_PPFINT_EN       0x0eULL
 125
 126 /* command specific defines */
 127 #define CMD_COMPL_WAIT          0x01
 128 #define CMD_INV_DEV_ENTRY       0x02
 129 #define CMD_INV_IOMMU_PAGES     0x03
 130 #define CMD_INV_IOTLB_PAGES     0x04
 131 #define CMD_INV_ALL             0x08
 132
 133 #define CMD_COMPL_WAIT_STORE_MASK       0x01
 134 #define CMD_COMPL_WAIT_INT_MASK         0x02
 135 #define CMD_INV_IOMMU_PAGES_SIZE_MASK   0x01
 136 #define CMD_INV_IOMMU_PAGES_PDE_MASK    0x02
 137
 138 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
 139
 140 /* macros and definitions for device table entries */
 141 #define DEV_ENTRY_VALID         0x00
 142 #define DEV_ENTRY_TRANSLATION   0x01
 143 #define DEV_ENTRY_IR            0x3d
 144 #define DEV_ENTRY_IW            0x3e
 145 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
 146 #define DEV_ENTRY_EX            0x67
 147 #define DEV_ENTRY_SYSMGT1       0x68
 148 #define DEV_ENTRY_SYSMGT2       0x69
 149 #define DEV_ENTRY_INIT_PASS     0xb8
 150 #define DEV_ENTRY_EINT_PASS     0xb9
 151 #define DEV_ENTRY_NMI_PASS      0xba
 152 #define DEV_ENTRY_LINT0_PASS    0xbe
 153 #define DEV_ENTRY_LINT1_PASS    0xbf
 154 #define DEV_ENTRY_MODE_MASK     0x07
 155 #define DEV_ENTRY_MODE_SHIFT    0x09
 156
 157 /* constants to configure the command buffer */
 158 #define CMD_BUFFER_SIZE    8192
 159 #define CMD_BUFFER_UNINITIALIZED 1
 160 #define CMD_BUFFER_ENTRIES 512
 161 #define MMIO_CMD_SIZE_SHIFT 56
 162 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
 163
 164 /* constants for event buffer handling */
 165 #define EVT_BUFFER_SIZE         8192 /* 512 entries */
 166 #define EVT_LEN_MASK            (0x9ULL << 56)
 167
 168 #define PAGE_MODE_NONE    0x00
 169 #define PAGE_MODE_1_LEVEL 0x01
 170 #define PAGE_MODE_2_LEVEL 0x02
 171 #define PAGE_MODE_3_LEVEL 0x03
 172 #define PAGE_MODE_4_LEVEL 0x04
 173 #define PAGE_MODE_5_LEVEL 0x05
 174 #define PAGE_MODE_6_LEVEL 0x06
 175
 176 #define PM_LEVEL_SHIFT(x)       (12 + ((x) * 9))
 177 #define PM_LEVEL_SIZE(x)        (((x) < 6) ? \
 178                                   ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
 179                                    (0xffffffffffffffffULL))
 180 #define PM_LEVEL_INDEX(x, a)    (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
 181 #define PM_LEVEL_ENC(x)         (((x) << 9) & 0xe00ULL)
 182 #define PM_LEVEL_PDE(x, a)      ((a) | PM_LEVEL_ENC((x)) | \
 183                                  IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
 184 #define PM_PTE_LEVEL(pte)       (((pte) >> 9) & 0x7ULL)
 185
 186 #define PM_MAP_4k               0
 187 #define PM_ADDR_MASK            0x000ffffffffff000ULL
 188 #define PM_MAP_MASK(lvl)        (PM_ADDR_MASK & \
 189                                 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
 190 #define PM_ALIGNED(lvl, addr)   ((PM_MAP_MASK(lvl) & (addr)) == (addr))
 191
 192 /*
 193  * Returns the page table level to use for a given page size
 194  * Pagesize is expected to be a power-of-two
 195  */
 196 #define PAGE_SIZE_LEVEL(pagesize) \
 197                 ((__ffs(pagesize) - 12) / 9)
 198 /*
 199  * Returns the number of ptes to use for a given page size
 200  * Pagesize is expected to be a power-of-two
 201  */
 202 #define PAGE_SIZE_PTE_COUNT(pagesize) \
 203                 (1ULL << ((__ffs(pagesize) - 12) % 9))
 204
 205 /*
 206  * Aligns a given io-virtual address to a given page size
 207  * Pagesize is expected to be a power-of-two
 208  */
 209 #define PAGE_SIZE_ALIGN(address, pagesize) \
 210                 ((address) & ~((pagesize) - 1))
 211 /*
 212  * Creates an IOMMU PTE for an address an a given pagesize
 213  * The PTE has no permission bits set
 214  * Pagesize is expected to be a power-of-two larger than 4096
 215  */
 216 #define PAGE_SIZE_PTE(address, pagesize)                \
 217                 (((address) | ((pagesize) - 1)) &       \
 218                  (~(pagesize >> 1)) & PM_ADDR_MASK)
 219
 220 /*
 221  * Takes a PTE value with mode=0x07 and returns the page size it maps
 222  */
 223 #define PTE_PAGE_SIZE(pte) \
 224         (1ULL << (1 + ffz(((pte) | 0xfffULL))))
 225
 226 #define IOMMU_PTE_P  (1ULL << 0)
 227 #define IOMMU_PTE_TV (1ULL << 1)
 228 #define IOMMU_PTE_U  (1ULL << 59)
 229 #define IOMMU_PTE_FC (1ULL << 60)
 230 #define IOMMU_PTE_IR (1ULL << 61)
 231 #define IOMMU_PTE_IW (1ULL << 62)
 232
 233 #define DTE_FLAG_IOTLB  0x01
 234
 235 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
 236 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
 237 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
 238 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
 239
 240 #define IOMMU_PROT_MASK 0x03
 241 #define IOMMU_PROT_IR 0x01
 242 #define IOMMU_PROT_IW 0x02
 243
 244 /* IOMMU capabilities */
 245 #define IOMMU_CAP_IOTLB   24
 246 #define IOMMU_CAP_NPCACHE 26
 247 #define IOMMU_CAP_EFR     27
 248
 249 #define MAX_DOMAIN_ID 65536
 250
 251 /* FIXME: move this macro to <linux/pci.h> */
 252 #define PCI_BUS(x) (((x) >> 8) & 0xff)
 253
 254 /* Protection domain flags */
 255 #define PD_DMA_OPS_MASK         (1UL << 0) /* domain used for dma_ops */
 256 #define PD_DEFAULT_MASK         (1UL << 1) /* domain is a default dma_ops
 257                                               domain for an IOMMU */
 258 #define PD_PASSTHROUGH_MASK     (1UL << 2) /* domain has no page
 259                                               translation */
 260
 261 extern bool amd_iommu_dump;
 262 #define DUMP_printk(format, arg...)                                     \
 263         do {                                                            \
 264                 if (amd_iommu_dump)                                             \
 265                         printk(KERN_INFO "AMD-Vi: " format, ## arg);    \
 266         } while(0);
 267
 268 /* global flag if IOMMUs cache non-present entries */
 269 extern bool amd_iommu_np_cache;
 270 /* Only true if all IOMMUs support device IOTLBs */
 271 extern bool amd_iommu_iotlb_sup;
 272
 273 /*
 274  * Make iterating over all IOMMUs easier
 275  */
 276 #define for_each_iommu(iommu) \
 277         list_for_each_entry((iommu), &amd_iommu_list, list)
 278 #define for_each_iommu_safe(iommu, next) \
 279         list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
 280
 281 #define APERTURE_RANGE_SHIFT    27      /* 128 MB */
 282 #define APERTURE_RANGE_SIZE     (1ULL << APERTURE_RANGE_SHIFT)
 283 #define APERTURE_RANGE_PAGES    (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
 284 #define APERTURE_MAX_RANGES     32      /* allows 4GB of DMA address space */
 285 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
 286 #define APERTURE_PAGE_INDEX(a)  (((a) >> 21) & 0x3fULL)
 287
 288 /*
 289  * This structure contains generic data for  IOMMU protection domains
 290  * independent of their use.
 291  */
 292 struct protection_domain {
 293         struct list_head list;  /* for list of all protection domains */
 294         struct list_head dev_list; /* List of all devices in this domain */
 295         spinlock_t lock;        /* mostly used to lock the page table*/
 296         struct mutex api_lock;  /* protect page tables in the iommu-api path */
 297         u16 id;                 /* the domain id written to the device table */
 298         int mode;               /* paging mode (0-6 levels) */
 299         u64 *pt_root;           /* page table root pointer */
 300         unsigned long flags;    /* flags to find out type of domain */
 301         bool updated;           /* complete domain flush required */
 302         unsigned dev_cnt;       /* devices assigned to this domain */
 303         unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
 304         void *priv;             /* private data */
 305
 306 };
 307
 308 /*
 309  * This struct contains device specific data for the IOMMU
 310  */
 311 struct iommu_dev_data {
 312         struct list_head list;            /* For domain->dev_list */
 313         struct list_head dev_data_list;   /* For global dev_data_list */
 314         struct iommu_dev_data *alias_data;/* The alias dev_data */
 315         struct protection_domain *domain; /* Domain the device is bound to */
 316         atomic_t bind;                    /* Domain attach reverent count */
 317         u16 devid;                        /* PCI Device ID */
 318         struct {
 319                 bool enabled;
 320                 int qdep;
 321         } ats;                            /* ATS state */
 322 };
 323
 324 /*
 325  * For dynamic growth the aperture size is split into ranges of 128MB of
 326  * DMA address space each. This struct represents one such range.
 327  */
 328 struct aperture_range {
 329
 330         /* address allocation bitmap */
 331         unsigned long *bitmap;
 332
 333         /*
 334          * Array of PTE pages for the aperture. In this array we save all the
 335          * leaf pages of the domain page table used for the aperture. This way
 336          * we don't need to walk the page table to find a specific PTE. We can
 337          * just calculate its address in constant time.
 338          */
 339         u64 *pte_pages[64];
 340
 341         unsigned long offset;
 342 };
 343
 344 /*
 345  * Data container for a dma_ops specific protection domain
 346  */
 347 struct dma_ops_domain {
 348         struct list_head list;
 349
 350         /* generic protection domain information */
 351         struct protection_domain domain;
 352
 353         /* size of the aperture for the mappings */
 354         unsigned long aperture_size;
 355
 356         /* address we start to search for free addresses */
 357         unsigned long next_address;
 358
 359         /* address space relevant data */
 360         struct aperture_range *aperture[APERTURE_MAX_RANGES];
 361
 362         /* This will be set to true when TLB needs to be flushed */
 363         bool need_flush;
 364
 365         /*
 366          * if this is a preallocated domain, keep the device for which it was
 367          * preallocated in this variable
 368          */
 369         u16 target_dev;
 370 };
 371
 372 /*
 373  * Structure where we save information about one hardware AMD IOMMU in the
 374  * system.
 375  */
 376 struct amd_iommu {
 377         struct list_head list;
 378
 379         /* Index within the IOMMU array */
 380         int index;
 381
 382         /* locks the accesses to the hardware */
 383         spinlock_t lock;
 384
 385         /* Pointer to PCI device of this IOMMU */
 386         struct pci_dev *dev;
 387
 388         /* physical address of MMIO space */
 389         u64 mmio_phys;
 390         /* virtual address of MMIO space */
 391         u8 *mmio_base;
 392
 393         /* capabilities of that IOMMU read from ACPI */
 394         u32 cap;
 395
 396         /* flags read from acpi table */
 397         u8 acpi_flags;
 398
 399         /* Extended features */
 400         u64 features;
 401
 402         /*
 403          * Capability pointer. There could be more than one IOMMU per PCI
 404          * device function if there are more than one AMD IOMMU capability
 405          * pointers.
 406          */
 407         u16 cap_ptr;
 408
 409         /* pci domain of this IOMMU */
 410         u16 pci_seg;
 411
 412         /* first device this IOMMU handles. read from PCI */
 413         u16 first_device;
 414         /* last device this IOMMU handles. read from PCI */
 415         u16 last_device;
 416
 417         /* start of exclusion range of that IOMMU */
 418         u64 exclusion_start;
 419         /* length of exclusion range of that IOMMU */
 420         u64 exclusion_length;
 421
 422         /* command buffer virtual address */
 423         u8 *cmd_buf;
 424         /* size of command buffer */
 425         u32 cmd_buf_size;
 426
 427         /* size of event buffer */
 428         u32 evt_buf_size;
 429         /* event buffer virtual address */
 430         u8 *evt_buf;
 431         /* MSI number for event interrupt */
 432         u16 evt_msi_num;
 433
 434         /* true if interrupts for this IOMMU are already enabled */
 435         bool int_enabled;
 436
 437         /* if one, we need to send a completion wait command */
 438         bool need_sync;
 439
 440         /* default dma_ops domain for that IOMMU */
 441         struct dma_ops_domain *default_dom;
 442
 443         /*
 444          * We can't rely on the BIOS to restore all values on reinit, so we
 445          * need to stash them
 446          */
 447
 448         /* The iommu BAR */
 449         u32 stored_addr_lo;
 450         u32 stored_addr_hi;
 451
 452         /*
 453          * Each iommu has 6 l1s, each of which is documented as having 0x12
 454          * registers
 455          */
 456         u32 stored_l1[6][0x12];
 457
 458         /* The l2 indirect registers */
 459         u32 stored_l2[0x83];
 460 };
 461
 462 /*
 463  * List with all IOMMUs in the system. This list is not locked because it is
 464  * only written and read at driver initialization or suspend time
 465  */
 466 extern struct list_head amd_iommu_list;
 467
 468 /*
 469  * Array with pointers to each IOMMU struct
 470  * The indices are referenced in the protection domains
 471  */
 472 extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
 473
 474 /* Number of IOMMUs present in the system */
 475 extern int amd_iommus_present;
 476
 477 /*
 478  * Declarations for the global list of all protection domains
 479  */
 480 extern spinlock_t amd_iommu_pd_lock;
 481 extern struct list_head amd_iommu_pd_list;
 482
 483 /*
 484  * Structure defining one entry in the device table
 485  */
 486 struct dev_table_entry {
 487         u32 data[8];
 488 };
 489
 490 /*
 491  * One entry for unity mappings parsed out of the ACPI table.
 492  */
 493 struct unity_map_entry {
 494         struct list_head list;
 495
 496         /* starting device id this entry is used for (including) */
 497         u16 devid_start;
 498         /* end device id this entry is used for (including) */
 499         u16 devid_end;
 500
 501         /* start address to unity map (including) */
 502         u64 address_start;
 503         /* end address to unity map (including) */
 504         u64 address_end;
 505
 506         /* required protection */
 507         int prot;
 508 };
 509
 510 /*
 511  * List of all unity mappings. It is not locked because as runtime it is only
 512  * read. It is created at ACPI table parsing time.
 513  */
 514 extern struct list_head amd_iommu_unity_map;
 515
 516 /*
 517  * Data structures for device handling
 518  */
 519
 520 /*
 521  * Device table used by hardware. Read and write accesses by software are
 522  * locked with the amd_iommu_pd_table lock.
 523  */
 524 extern struct dev_table_entry *amd_iommu_dev_table;
 525
 526 /*
 527  * Alias table to find requestor ids to device ids. Not locked because only
 528  * read on runtime.
 529  */
 530 extern u16 *amd_iommu_alias_table;
 531
 532 /*
 533  * Reverse lookup table to find the IOMMU which translates a specific device.
 534  */
 535 extern struct amd_iommu **amd_iommu_rlookup_table;
 536
 537 /* size of the dma_ops aperture as power of 2 */
 538 extern unsigned amd_iommu_aperture_order;
 539
 540 /* largest PCI device id we expect translation requests for */
 541 extern u16 amd_iommu_last_bdf;
 542
 543 /* allocation bitmap for domain ids */
 544 extern unsigned long *amd_iommu_pd_alloc_bitmap;
 545
 546 /*
 547  * If true, the addresses will be flushed on unmap time, not when
 548  * they are reused
 549  */
 550 extern bool amd_iommu_unmap_flush;
 551
 552 /* takes bus and device/function and returns the device id
 553  * FIXME: should that be in generic PCI code? */
 554 static inline u16 calc_devid(u8 bus, u8 devfn)
 555 {
 556         return (((u16)bus) << 8) | devfn;
 557 }
 558
 559 #ifdef CONFIG_AMD_IOMMU_STATS
 560
 561 struct __iommu_counter {
 562         char *name;
 563         struct dentry *dent;
 564         u64 value;
 565 };
 566
 567 #define DECLARE_STATS_COUNTER(nm) \
 568         static struct __iommu_counter nm = {    \
 569                 .name = #nm,                    \
 570         }
 571
 572 #define INC_STATS_COUNTER(name)         name.value += 1
 573 #define ADD_STATS_COUNTER(name, x)      name.value += (x)
 574 #define SUB_STATS_COUNTER(name, x)      name.value -= (x)
 575
 576 #else /* CONFIG_AMD_IOMMU_STATS */
 577
 578 #define DECLARE_STATS_COUNTER(name)
 579 #define INC_STATS_COUNTER(name)
 580 #define ADD_STATS_COUNTER(name, x)
 581 #define SUB_STATS_COUNTER(name, x)
 582
 583 #endif /* CONFIG_AMD_IOMMU_STATS */
 584
 585 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */