3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
11 *------------------------------------------------------------------------------
13 * et1310_mac.c - All code and routines pertaining to the MAC
15 *------------------------------------------------------------------------------
19 * This software is provided subject to the following terms and conditions,
20 * which you should read carefully before using the software. Using this
21 * software indicates your acceptance of these terms and conditions. If you do
22 * not agree with these terms and conditions, do not use the software.
24 * Copyright © 2005 Agere Systems Inc.
25 * All rights reserved.
27 * Redistribution and use in source or binary forms, with or without
28 * modifications, are permitted provided that the following conditions are met:
30 * . Redistributions of source code must retain the above copyright notice, this
31 * list of conditions and the following Disclaimer as comments in the code as
32 * well as in the documentation and/or other materials provided with the
35 * . Redistributions in binary form must reproduce the above copyright notice,
36 * this list of conditions and the following Disclaimer in the documentation
37 * and/or other materials provided with the distribution.
39 * . Neither the name of Agere Systems Inc. nor the names of the contributors
40 * may be used to endorse or promote products derived from this software
41 * without specific prior written permission.
45 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
46 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
48 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
49 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
50 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
51 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
52 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
53 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
55 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
60 #include "et131x_defs.h"
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/types.h>
65 #include <linux/kernel.h>
67 #include <linux/sched.h>
68 #include <linux/ptrace.h>
69 #include <linux/ctype.h>
70 #include <linux/string.h>
71 #include <linux/timer.h>
72 #include <linux/interrupt.h>
74 #include <linux/delay.h>
76 #include <linux/bitops.h>
77 #include <linux/pci.h>
78 #include <asm/system.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/if_arp.h>
84 #include <linux/ioport.h>
85 #include <linux/crc32.h>
86 #include <linux/phy.h>
88 #include "et1310_phy.h"
89 #include "et131x_adapter.h"
93 #define COUNTER_WRAP_28_BIT 0x10000000
94 #define COUNTER_WRAP_22_BIT 0x400000
95 #define COUNTER_WRAP_16_BIT 0x10000
96 #define COUNTER_WRAP_12_BIT 0x1000
98 #define COUNTER_MASK_28_BIT (COUNTER_WRAP_28_BIT - 1)
99 #define COUNTER_MASK_22_BIT (COUNTER_WRAP_22_BIT - 1)
100 #define COUNTER_MASK_16_BIT (COUNTER_WRAP_16_BIT - 1)
101 #define COUNTER_MASK_12_BIT (COUNTER_WRAP_12_BIT - 1)
104 * et1310_config_mac_regs1 - Initialize the first part of MAC regs
105 * @adapter: pointer to our adapter structure
107 void et1310_config_mac_regs1(struct et131x_adapter
*adapter
)
109 struct mac_regs __iomem
*macregs
= &adapter
->regs
->mac
;
114 /* First we need to reset everything. Write to MAC configuration
115 * register 1 to perform reset.
117 writel(0xC00F0000, ¯egs
->cfg1
);
119 /* Next lets configure the MAC Inter-packet gap register */
120 ipg
= 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
121 ipg
|= 0x50 << 8; /* ifg enforce 0x50 */
122 writel(ipg
, ¯egs
->ipg
);
124 /* Next lets configure the MAC Half Duplex register */
125 /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
126 writel(0x00A1F037, ¯egs
->hfdp
);
128 /* Next lets configure the MAC Interface Control register */
129 writel(0, ¯egs
->if_ctrl
);
131 /* Let's move on to setting up the mii management configuration */
132 writel(0x07, ¯egs
->mii_mgmt_cfg
); /* Clock reset 0x7 */
134 /* Next lets configure the MAC Station Address register. These
135 * values are read from the EEPROM during initialization and stored
136 * in the adapter structure. We write what is stored in the adapter
137 * structure to the MAC Station Address registers high and low. This
138 * station address is used for generating and checking pause control
141 station2
= (adapter
->addr
[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT
) |
142 (adapter
->addr
[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT
);
143 station1
= (adapter
->addr
[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT
) |
144 (adapter
->addr
[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT
) |
145 (adapter
->addr
[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT
) |
147 writel(station1
, ¯egs
->station_addr_1
);
148 writel(station2
, ¯egs
->station_addr_2
);
150 /* Max ethernet packet in bytes that will passed by the mac without
151 * being truncated. Allow the MAC to pass 4 more than our max packet
152 * size. This is 4 for the Ethernet CRC.
154 * Packets larger than (registry_jumbo_packet) that do not contain a
155 * VLAN ID will be dropped by the Rx function.
157 writel(adapter
->registry_jumbo_packet
+ 4, ¯egs
->max_fm_len
);
159 /* clear out MAC config reset */
160 writel(0, ¯egs
->cfg1
);
164 * et1310_config_mac_regs2 - Initialize the second part of MAC regs
165 * @adapter: pointer to our adapter structure
167 void et1310_config_mac_regs2(struct et131x_adapter
*adapter
)
170 struct mac_regs __iomem
*mac
= &adapter
->regs
->mac
;
171 struct phy_device
*phydev
= adapter
->phydev
;
177 ctl
= readl(&adapter
->regs
->txmac
.ctl
);
178 cfg1
= readl(&mac
->cfg1
);
179 cfg2
= readl(&mac
->cfg2
);
180 ifctrl
= readl(&mac
->if_ctrl
);
182 /* Set up the if mode bits */
184 if (phydev
&& phydev
->speed
== SPEED_1000
) {
187 ifctrl
&= ~(1 << 24);
193 /* We need to enable Rx/Tx */
194 cfg1
|= CFG1_RX_ENABLE
| CFG1_TX_ENABLE
| CFG1_TX_FLOW
;
195 /* Initialize loop back to off */
196 cfg1
&= ~(CFG1_LOOPBACK
| CFG1_RX_FLOW
);
197 if (adapter
->flowcontrol
== FLOW_RXONLY
||
198 adapter
->flowcontrol
== FLOW_BOTH
)
199 cfg1
|= CFG1_RX_FLOW
;
200 writel(cfg1
, &mac
->cfg1
);
202 /* Now we need to initialize the MAC Configuration 2 register */
203 /* preamble 7, check length, huge frame off, pad crc, crc enable
208 /* Turn on duplex if needed */
209 if (phydev
&& phydev
->duplex
== DUPLEX_FULL
)
212 ifctrl
&= ~(1 << 26);
213 if (phydev
&& phydev
->duplex
== DUPLEX_HALF
)
214 ifctrl
|= (1<<26); /* Enable ghd */
216 writel(ifctrl
, &mac
->if_ctrl
);
217 writel(cfg2
, &mac
->cfg2
);
222 cfg1
= readl(&mac
->cfg1
);
223 } while ((cfg1
& CFG1_WAIT
) != CFG1_WAIT
&& delay
< 100);
226 dev_warn(&adapter
->pdev
->dev
,
227 "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
232 ctl
|= 0x09; /* TX mac enable, FC disable */
233 writel(ctl
, &adapter
->regs
->txmac
.ctl
);
235 /* Ready to start the RXDMA/TXDMA engine */
236 if (adapter
->flags
& fMP_ADAPTER_LOWER_POWER
) {
237 et131x_rx_dma_enable(adapter
);
238 et131x_tx_dma_enable(adapter
);
242 void et1310_config_rxmac_regs(struct et131x_adapter
*adapter
)
244 struct rxmac_regs __iomem
*rxmac
= &adapter
->regs
->rxmac
;
245 struct phy_device
*phydev
= adapter
->phydev
;
250 /* Disable the MAC while it is being configured (also disable WOL) */
251 writel(0x8, &rxmac
->ctrl
);
253 /* Initialize WOL to disabled. */
254 writel(0, &rxmac
->crc0
);
255 writel(0, &rxmac
->crc12
);
256 writel(0, &rxmac
->crc34
);
258 /* We need to set the WOL mask0 - mask4 next. We initialize it to
259 * its default Values of 0x00000000 because there are not WOL masks
262 writel(0, &rxmac
->mask0_word0
);
263 writel(0, &rxmac
->mask0_word1
);
264 writel(0, &rxmac
->mask0_word2
);
265 writel(0, &rxmac
->mask0_word3
);
267 writel(0, &rxmac
->mask1_word0
);
268 writel(0, &rxmac
->mask1_word1
);
269 writel(0, &rxmac
->mask1_word2
);
270 writel(0, &rxmac
->mask1_word3
);
272 writel(0, &rxmac
->mask2_word0
);
273 writel(0, &rxmac
->mask2_word1
);
274 writel(0, &rxmac
->mask2_word2
);
275 writel(0, &rxmac
->mask2_word3
);
277 writel(0, &rxmac
->mask3_word0
);
278 writel(0, &rxmac
->mask3_word1
);
279 writel(0, &rxmac
->mask3_word2
);
280 writel(0, &rxmac
->mask3_word3
);
282 writel(0, &rxmac
->mask4_word0
);
283 writel(0, &rxmac
->mask4_word1
);
284 writel(0, &rxmac
->mask4_word2
);
285 writel(0, &rxmac
->mask4_word3
);
287 /* Lets setup the WOL Source Address */
288 sa_lo
= (adapter
->addr
[2] << ET_WOL_LO_SA3_SHIFT
) |
289 (adapter
->addr
[3] << ET_WOL_LO_SA4_SHIFT
) |
290 (adapter
->addr
[4] << ET_WOL_LO_SA5_SHIFT
) |
292 writel(sa_lo
, &rxmac
->sa_lo
);
294 sa_hi
= (u32
) (adapter
->addr
[0] << ET_WOL_HI_SA1_SHIFT
) |
296 writel(sa_hi
, &rxmac
->sa_hi
);
298 /* Disable all Packet Filtering */
299 writel(0, &rxmac
->pf_ctrl
);
301 /* Let's initialize the Unicast Packet filtering address */
302 if (adapter
->packet_filter
& ET131X_PACKET_TYPE_DIRECTED
) {
303 et1310_setup_device_for_unicast(adapter
);
304 pf_ctrl
|= 4; /* Unicast filter */
306 writel(0, &rxmac
->uni_pf_addr1
);
307 writel(0, &rxmac
->uni_pf_addr2
);
308 writel(0, &rxmac
->uni_pf_addr3
);
311 /* Let's initialize the Multicast hash */
312 if (!(adapter
->packet_filter
& ET131X_PACKET_TYPE_ALL_MULTICAST
)) {
313 pf_ctrl
|= 2; /* Multicast filter */
314 et1310_setup_device_for_multicast(adapter
);
317 /* Runt packet filtering. Didn't work in version A silicon. */
318 pf_ctrl
|= (NIC_MIN_PACKET_SIZE
+ 4) << 16;
319 pf_ctrl
|= 8; /* Fragment filter */
321 if (adapter
->registry_jumbo_packet
> 8192)
322 /* In order to transmit jumbo packets greater than 8k, the
323 * FIFO between RxMAC and RxDMA needs to be reduced in size
324 * to (16k - Jumbo packet size). In order to implement this,
325 * we must use "cut through" mode in the RxMAC, which chops
326 * packets down into segments which are (max_size * 16). In
327 * this case we selected 256 bytes, since this is the size of
328 * the PCI-Express TLP's that the 1310 uses.
330 * seg_en on, fc_en off, size 0x10
332 writel(0x41, &rxmac
->mcif_ctrl_max_seg
);
334 writel(0, &rxmac
->mcif_ctrl_max_seg
);
336 /* Initialize the MCIF water marks */
337 writel(0, &rxmac
->mcif_water_mark
);
339 /* Initialize the MIF control */
340 writel(0, &rxmac
->mif_ctrl
);
342 /* Initialize the Space Available Register */
343 writel(0, &rxmac
->space_avail
);
345 /* Initialize the the mif_ctrl register
346 * bit 3: Receive code error. One or more nibbles were signaled as
347 * errors during the reception of the packet. Clear this
348 * bit in Gigabit, set it in 100Mbit. This was derived
349 * experimentally at UNH.
350 * bit 4: Receive CRC error. The packet's CRC did not match the
351 * internally generated CRC.
352 * bit 5: Receive length check error. Indicates that frame length
353 * field value in the packet does not match the actual data
354 * byte length and is not a type field.
355 * bit 16: Receive frame truncated.
356 * bit 17: Drop packet enable
358 if (phydev
&& phydev
->speed
== SPEED_100
)
359 writel(0x30038, &rxmac
->mif_ctrl
);
361 writel(0x30030, &rxmac
->mif_ctrl
);
363 /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
364 * filter is always enabled since it is where the runt packets are
365 * supposed to be dropped. For version A silicon, runt packet
366 * dropping doesn't work, so it is disabled in the pf_ctrl register,
367 * but we still leave the packet filter on.
369 writel(pf_ctrl
, &rxmac
->pf_ctrl
);
370 writel(0x9, &rxmac
->ctrl
);
373 void et1310_config_txmac_regs(struct et131x_adapter
*adapter
)
375 struct txmac_regs
*txmac
= &adapter
->regs
->txmac
;
377 /* We need to update the Control Frame Parameters
378 * cfpt - control frame pause timer set to 64 (0x40)
379 * cfep - control frame extended pause timer set to 0x0
381 if (adapter
->flowcontrol
== FLOW_NONE
)
382 writel(0, &txmac
->cf_param
);
384 writel(0x40, &txmac
->cf_param
);
387 void et1310_config_macstat_regs(struct et131x_adapter
*adapter
)
389 struct macstat_regs __iomem
*macstat
=
390 &adapter
->regs
->macstat
;
392 /* Next we need to initialize all the macstat registers to zero on
395 writel(0, &macstat
->txrx_0_64_byte_frames
);
396 writel(0, &macstat
->txrx_65_127_byte_frames
);
397 writel(0, &macstat
->txrx_128_255_byte_frames
);
398 writel(0, &macstat
->txrx_256_511_byte_frames
);
399 writel(0, &macstat
->txrx_512_1023_byte_frames
);
400 writel(0, &macstat
->txrx_1024_1518_byte_frames
);
401 writel(0, &macstat
->txrx_1519_1522_gvln_frames
);
403 writel(0, &macstat
->rx_bytes
);
404 writel(0, &macstat
->rx_packets
);
405 writel(0, &macstat
->rx_fcs_errs
);
406 writel(0, &macstat
->rx_multicast_packets
);
407 writel(0, &macstat
->rx_broadcast_packets
);
408 writel(0, &macstat
->rx_control_frames
);
409 writel(0, &macstat
->rx_pause_frames
);
410 writel(0, &macstat
->rx_unknown_opcodes
);
411 writel(0, &macstat
->rx_align_errs
);
412 writel(0, &macstat
->rx_frame_len_errs
);
413 writel(0, &macstat
->rx_code_errs
);
414 writel(0, &macstat
->rx_carrier_sense_errs
);
415 writel(0, &macstat
->rx_undersize_packets
);
416 writel(0, &macstat
->rx_oversize_packets
);
417 writel(0, &macstat
->rx_fragment_packets
);
418 writel(0, &macstat
->rx_jabbers
);
419 writel(0, &macstat
->rx_drops
);
421 writel(0, &macstat
->tx_bytes
);
422 writel(0, &macstat
->tx_packets
);
423 writel(0, &macstat
->tx_multicast_packets
);
424 writel(0, &macstat
->tx_broadcast_packets
);
425 writel(0, &macstat
->tx_pause_frames
);
426 writel(0, &macstat
->tx_deferred
);
427 writel(0, &macstat
->tx_excessive_deferred
);
428 writel(0, &macstat
->tx_single_collisions
);
429 writel(0, &macstat
->tx_multiple_collisions
);
430 writel(0, &macstat
->tx_late_collisions
);
431 writel(0, &macstat
->tx_excessive_collisions
);
432 writel(0, &macstat
->tx_total_collisions
);
433 writel(0, &macstat
->tx_pause_honored_frames
);
434 writel(0, &macstat
->tx_drops
);
435 writel(0, &macstat
->tx_jabbers
);
436 writel(0, &macstat
->tx_fcs_errs
);
437 writel(0, &macstat
->tx_control_frames
);
438 writel(0, &macstat
->tx_oversize_frames
);
439 writel(0, &macstat
->tx_undersize_frames
);
440 writel(0, &macstat
->tx_fragments
);
441 writel(0, &macstat
->carry_reg1
);
442 writel(0, &macstat
->carry_reg2
);
444 /* Unmask any counters that we want to track the overflow of.
445 * Initially this will be all counters. It may become clear later
446 * that we do not need to track all counters.
448 writel(0xFFFFBE32, &macstat
->carry_reg1_mask
);
449 writel(0xFFFE7E8B, &macstat
->carry_reg2_mask
);
452 void et1310_config_flow_control(struct et131x_adapter
*adapter
)
454 struct phy_device
*phydev
= adapter
->phydev
;
456 if (phydev
->duplex
== DUPLEX_HALF
) {
457 adapter
->flowcontrol
= FLOW_NONE
;
459 char remote_pause
, remote_async_pause
;
461 et1310_phy_access_mii_bit(adapter
,
462 TRUEPHY_BIT_READ
, 5, 10, &remote_pause
);
463 et1310_phy_access_mii_bit(adapter
,
464 TRUEPHY_BIT_READ
, 5, 11,
465 &remote_async_pause
);
467 if ((remote_pause
== TRUEPHY_BIT_SET
) &&
468 (remote_async_pause
== TRUEPHY_BIT_SET
)) {
469 adapter
->flowcontrol
= adapter
->wanted_flow
;
470 } else if ((remote_pause
== TRUEPHY_BIT_SET
) &&
471 (remote_async_pause
== TRUEPHY_BIT_CLEAR
)) {
472 if (adapter
->wanted_flow
== FLOW_BOTH
)
473 adapter
->flowcontrol
= FLOW_BOTH
;
475 adapter
->flowcontrol
= FLOW_NONE
;
476 } else if ((remote_pause
== TRUEPHY_BIT_CLEAR
) &&
477 (remote_async_pause
== TRUEPHY_BIT_CLEAR
)) {
478 adapter
->flowcontrol
= FLOW_NONE
;
479 } else {/* if (remote_pause == TRUEPHY_CLEAR_BIT &&
480 remote_async_pause == TRUEPHY_SET_BIT) */
481 if (adapter
->wanted_flow
== FLOW_BOTH
)
482 adapter
->flowcontrol
= FLOW_RXONLY
;
484 adapter
->flowcontrol
= FLOW_NONE
;
490 * et1310_update_macstat_host_counters - Update the local copy of the statistics
491 * @adapter: pointer to the adapter structure
493 void et1310_update_macstat_host_counters(struct et131x_adapter
*adapter
)
495 struct ce_stats
*stats
= &adapter
->stats
;
496 struct macstat_regs __iomem
*macstat
=
497 &adapter
->regs
->macstat
;
499 stats
->tx_collisions
+= readl(&macstat
->tx_total_collisions
);
500 stats
->tx_first_collisions
+= readl(&macstat
->tx_single_collisions
);
501 stats
->tx_deferred
+= readl(&macstat
->tx_deferred
);
502 stats
->tx_excessive_collisions
+=
503 readl(&macstat
->tx_multiple_collisions
);
504 stats
->tx_late_collisions
+= readl(&macstat
->tx_late_collisions
);
505 stats
->tx_underflows
+= readl(&macstat
->tx_undersize_frames
);
506 stats
->tx_max_pkt_errs
+= readl(&macstat
->tx_oversize_frames
);
508 stats
->rx_align_errs
+= readl(&macstat
->rx_align_errs
);
509 stats
->rx_crc_errs
+= readl(&macstat
->rx_code_errs
);
510 stats
->rcvd_pkts_dropped
+= readl(&macstat
->rx_drops
);
511 stats
->rx_overflows
+= readl(&macstat
->rx_oversize_packets
);
512 stats
->rx_code_violations
+= readl(&macstat
->rx_fcs_errs
);
513 stats
->rx_length_errs
+= readl(&macstat
->rx_frame_len_errs
);
514 stats
->rx_other_errs
+= readl(&macstat
->rx_fragment_packets
);
518 * et1310_handle_macstat_interrupt
519 * @adapter: pointer to the adapter structure
521 * One of the MACSTAT counters has wrapped. Update the local copy of
522 * the statistics held in the adapter structure, checking the "wrap"
523 * bit for each counter.
525 void et1310_handle_macstat_interrupt(struct et131x_adapter
*adapter
)
530 /* Read the interrupt bits from the register(s). These are Clear On
533 carry_reg1
= readl(&adapter
->regs
->macstat
.carry_reg1
);
534 carry_reg2
= readl(&adapter
->regs
->macstat
.carry_reg2
);
536 writel(carry_reg1
, &adapter
->regs
->macstat
.carry_reg1
);
537 writel(carry_reg2
, &adapter
->regs
->macstat
.carry_reg2
);
539 /* We need to do update the host copy of all the MAC_STAT counters.
540 * For each counter, check it's overflow bit. If the overflow bit is
541 * set, then increment the host version of the count by one complete
542 * revolution of the counter. This routine is called when the counter
543 * block indicates that one of the counters has wrapped.
545 if (carry_reg1
& (1 << 14))
546 adapter
->stats
.rx_code_violations
+= COUNTER_WRAP_16_BIT
;
547 if (carry_reg1
& (1 << 8))
548 adapter
->stats
.rx_align_errs
+= COUNTER_WRAP_12_BIT
;
549 if (carry_reg1
& (1 << 7))
550 adapter
->stats
.rx_length_errs
+= COUNTER_WRAP_16_BIT
;
551 if (carry_reg1
& (1 << 2))
552 adapter
->stats
.rx_other_errs
+= COUNTER_WRAP_16_BIT
;
553 if (carry_reg1
& (1 << 6))
554 adapter
->stats
.rx_crc_errs
+= COUNTER_WRAP_16_BIT
;
555 if (carry_reg1
& (1 << 3))
556 adapter
->stats
.rx_overflows
+= COUNTER_WRAP_16_BIT
;
557 if (carry_reg1
& (1 << 0))
558 adapter
->stats
.rcvd_pkts_dropped
+= COUNTER_WRAP_16_BIT
;
559 if (carry_reg2
& (1 << 16))
560 adapter
->stats
.tx_max_pkt_errs
+= COUNTER_WRAP_12_BIT
;
561 if (carry_reg2
& (1 << 15))
562 adapter
->stats
.tx_underflows
+= COUNTER_WRAP_12_BIT
;
563 if (carry_reg2
& (1 << 6))
564 adapter
->stats
.tx_first_collisions
+= COUNTER_WRAP_12_BIT
;
565 if (carry_reg2
& (1 << 8))
566 adapter
->stats
.tx_deferred
+= COUNTER_WRAP_12_BIT
;
567 if (carry_reg2
& (1 << 5))
568 adapter
->stats
.tx_excessive_collisions
+= COUNTER_WRAP_12_BIT
;
569 if (carry_reg2
& (1 << 4))
570 adapter
->stats
.tx_late_collisions
+= COUNTER_WRAP_12_BIT
;
571 if (carry_reg2
& (1 << 2))
572 adapter
->stats
.tx_collisions
+= COUNTER_WRAP_12_BIT
;
575 void et1310_setup_device_for_multicast(struct et131x_adapter
*adapter
)
577 struct rxmac_regs __iomem
*rxmac
= &adapter
->regs
->rxmac
;
586 /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
587 * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
588 * specified) then we should pass NO multi-cast addresses to the
591 if (adapter
->packet_filter
& ET131X_PACKET_TYPE_MULTICAST
) {
592 /* Loop through our multicast array and set up the device */
593 for (nIndex
= 0; nIndex
< adapter
->multicast_addr_count
;
595 result
= ether_crc(6, adapter
->multicast_list
[nIndex
]);
597 result
= (result
& 0x3F800000) >> 23;
600 hash1
|= (1 << result
);
601 } else if ((31 < result
) && (result
< 64)) {
603 hash2
|= (1 << result
);
604 } else if ((63 < result
) && (result
< 96)) {
606 hash3
|= (1 << result
);
609 hash4
|= (1 << result
);
614 /* Write out the new hash to the device */
615 pm_csr
= readl(&adapter
->regs
->global
.pm_csr
);
616 if (!et1310_in_phy_coma(adapter
)) {
617 writel(hash1
, &rxmac
->multi_hash1
);
618 writel(hash2
, &rxmac
->multi_hash2
);
619 writel(hash3
, &rxmac
->multi_hash3
);
620 writel(hash4
, &rxmac
->multi_hash4
);
624 void et1310_setup_device_for_unicast(struct et131x_adapter
*adapter
)
626 struct rxmac_regs __iomem
*rxmac
= &adapter
->regs
->rxmac
;
632 /* Set up unicast packet filter reg 3 to be the first two octets of
633 * the MAC address for both address
635 * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
636 * MAC address for second address
638 * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
639 * MAC address for first address
641 uni_pf3
= (adapter
->addr
[0] << ET_UNI_PF_ADDR2_1_SHIFT
) |
642 (adapter
->addr
[1] << ET_UNI_PF_ADDR2_2_SHIFT
) |
643 (adapter
->addr
[0] << ET_UNI_PF_ADDR1_1_SHIFT
) |
646 uni_pf2
= (adapter
->addr
[2] << ET_UNI_PF_ADDR2_3_SHIFT
) |
647 (adapter
->addr
[3] << ET_UNI_PF_ADDR2_4_SHIFT
) |
648 (adapter
->addr
[4] << ET_UNI_PF_ADDR2_5_SHIFT
) |
651 uni_pf1
= (adapter
->addr
[2] << ET_UNI_PF_ADDR1_3_SHIFT
) |
652 (adapter
->addr
[3] << ET_UNI_PF_ADDR1_4_SHIFT
) |
653 (adapter
->addr
[4] << ET_UNI_PF_ADDR1_5_SHIFT
) |
656 pm_csr
= readl(&adapter
->regs
->global
.pm_csr
);
657 if (!et1310_in_phy_coma(adapter
)) {
658 writel(uni_pf1
, &rxmac
->uni_pf_addr1
);
659 writel(uni_pf2
, &rxmac
->uni_pf_addr2
);
660 writel(uni_pf3
, &rxmac
->uni_pf_addr3
);