4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Daniel Vetter <daniel@ffwll.ch>
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
29 #include <linux/seq_file.h>
35 #include "intel_drv.h"
37 /* Limits for overlay size. According to intel doc, the real limits are:
38 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
39 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
40 * the mininum of both. */
41 #define IMAGE_MAX_WIDTH 2048
42 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
43 /* on 830 and 845 these large limits result in the card hanging */
44 #define IMAGE_MAX_WIDTH_LEGACY 1024
45 #define IMAGE_MAX_HEIGHT_LEGACY 1088
47 /* overlay register definitions */
49 #define OCMD_TILED_SURFACE (0x1<<19)
50 #define OCMD_MIRROR_MASK (0x3<<17)
51 #define OCMD_MIRROR_MODE (0x3<<17)
52 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
53 #define OCMD_MIRROR_VERTICAL (0x2<<17)
54 #define OCMD_MIRROR_BOTH (0x3<<17)
55 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
56 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
57 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
58 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
59 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
60 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
61 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
62 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
63 #define OCMD_YUV_422_PACKED (0x8<<10)
64 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
65 #define OCMD_YUV_420_PLANAR (0xc<<10)
66 #define OCMD_YUV_422_PLANAR (0xd<<10)
67 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
68 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
69 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
70 #define OCMD_BUF_TYPE_MASK (0x1<<5)
71 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
72 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
73 #define OCMD_TEST_MODE (0x1<<4)
74 #define OCMD_BUFFER_SELECT (0x3<<2)
75 #define OCMD_BUFFER0 (0x0<<2)
76 #define OCMD_BUFFER1 (0x1<<2)
77 #define OCMD_FIELD_SELECT (0x1<<2)
78 #define OCMD_FIELD0 (0x0<<1)
79 #define OCMD_FIELD1 (0x1<<1)
80 #define OCMD_ENABLE (0x1<<0)
82 /* OCONFIG register */
83 #define OCONF_PIPE_MASK (0x1<<18)
84 #define OCONF_PIPE_A (0x0<<18)
85 #define OCONF_PIPE_B (0x1<<18)
86 #define OCONF_GAMMA2_ENABLE (0x1<<16)
87 #define OCONF_CSC_MODE_BT601 (0x0<<5)
88 #define OCONF_CSC_MODE_BT709 (0x1<<5)
89 #define OCONF_CSC_BYPASS (0x1<<4)
90 #define OCONF_CC_OUT_8BIT (0x1<<3)
91 #define OCONF_TEST_MODE (0x1<<2)
92 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
93 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
95 /* DCLRKM (dst-key) register */
96 #define DST_KEY_ENABLE (0x1<<31)
97 #define CLK_RGB24_MASK 0x0
98 #define CLK_RGB16_MASK 0x070307
99 #define CLK_RGB15_MASK 0x070707
100 #define CLK_RGB8I_MASK 0xffffff
102 #define RGB16_TO_COLORKEY(c) \
103 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
104 #define RGB15_TO_COLORKEY(c) \
105 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
107 /* overlay flip addr flag */
108 #define OFC_UPDATE 0x1
110 /* polyphase filter coefficients */
111 #define N_HORIZ_Y_TAPS 5
112 #define N_VERT_Y_TAPS 3
113 #define N_HORIZ_UV_TAPS 3
114 #define N_VERT_UV_TAPS 3
118 /* memory bufferd overlay registers */
119 struct overlay_registers
{
147 u32 RESERVED1
; /* 0x6C */
160 u32 FASTHSCALE
; /* 0xA0 */
161 u32 UVSCALEV
; /* 0xA4 */
162 u32 RESERVEDC
[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
163 u16 Y_VCOEFS
[N_VERT_Y_TAPS
* N_PHASES
]; /* 0x200 */
164 u16 RESERVEDD
[0x100 / 2 - N_VERT_Y_TAPS
* N_PHASES
];
165 u16 Y_HCOEFS
[N_HORIZ_Y_TAPS
* N_PHASES
]; /* 0x300 */
166 u16 RESERVEDE
[0x200 / 2 - N_HORIZ_Y_TAPS
* N_PHASES
];
167 u16 UV_VCOEFS
[N_VERT_UV_TAPS
* N_PHASES
]; /* 0x500 */
168 u16 RESERVEDF
[0x100 / 2 - N_VERT_UV_TAPS
* N_PHASES
];
169 u16 UV_HCOEFS
[N_HORIZ_UV_TAPS
* N_PHASES
]; /* 0x600 */
170 u16 RESERVEDG
[0x100 / 2 - N_HORIZ_UV_TAPS
* N_PHASES
];
173 static struct overlay_registers
*
174 intel_overlay_map_regs_atomic(struct intel_overlay
*overlay
,
177 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
178 struct overlay_registers
*regs
;
180 /* no recursive mappings */
181 BUG_ON(overlay
->virt_addr
);
183 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
)) {
184 regs
= overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
186 regs
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
187 overlay
->reg_bo
->gtt_offset
,
191 DRM_ERROR("failed to map overlay regs in GTT\n");
196 return overlay
->virt_addr
= regs
;
199 static void intel_overlay_unmap_regs_atomic(struct intel_overlay
*overlay
,
202 if (!OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
203 io_mapping_unmap_atomic(overlay
->virt_addr
, slot
);
205 overlay
->virt_addr
= NULL
;
210 static struct overlay_registers
*
211 intel_overlay_map_regs(struct intel_overlay
*overlay
)
213 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
214 struct overlay_registers
*regs
;
216 /* no recursive mappings */
217 BUG_ON(overlay
->virt_addr
);
219 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
)) {
220 regs
= overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
222 regs
= io_mapping_map_wc(dev_priv
->mm
.gtt_mapping
,
223 overlay
->reg_bo
->gtt_offset
);
226 DRM_ERROR("failed to map overlay regs in GTT\n");
231 return overlay
->virt_addr
= regs
;
234 static void intel_overlay_unmap_regs(struct intel_overlay
*overlay
)
236 if (!OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
237 io_mapping_unmap(overlay
->virt_addr
);
239 overlay
->virt_addr
= NULL
;
244 static int intel_overlay_do_wait_request(struct intel_overlay
*overlay
,
248 struct drm_device
*dev
= overlay
->dev
;
249 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
252 overlay
->last_flip_req
=
253 i915_add_request(dev
, NULL
, &dev_priv
->render_ring
);
254 if (overlay
->last_flip_req
== 0)
257 overlay
->hw_wedged
= stage
;
258 ret
= i915_do_wait_request(dev
,
259 overlay
->last_flip_req
, true,
260 &dev_priv
->render_ring
);
264 overlay
->hw_wedged
= 0;
265 overlay
->last_flip_req
= 0;
269 /* overlay needs to be disable in OCMD reg */
270 static int intel_overlay_on(struct intel_overlay
*overlay
)
272 struct drm_device
*dev
= overlay
->dev
;
274 BUG_ON(overlay
->active
);
279 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_ON
);
280 OUT_RING(overlay
->flip_addr
| OFC_UPDATE
);
281 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
285 return intel_overlay_do_wait_request(overlay
, true,
286 NEEDS_WAIT_FOR_FLIP
);
289 /* overlay needs to be enabled in OCMD reg */
290 static void intel_overlay_continue(struct intel_overlay
*overlay
,
291 bool load_polyphase_filter
)
293 struct drm_device
*dev
= overlay
->dev
;
294 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
295 u32 flip_addr
= overlay
->flip_addr
;
298 BUG_ON(!overlay
->active
);
300 if (load_polyphase_filter
)
301 flip_addr
|= OFC_UPDATE
;
303 /* check for underruns */
304 tmp
= I915_READ(DOVSTA
);
306 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp
);
309 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
313 overlay
->last_flip_req
=
314 i915_add_request(dev
, NULL
, &dev_priv
->render_ring
);
317 static int intel_overlay_wait_flip(struct intel_overlay
*overlay
)
319 struct drm_device
*dev
= overlay
->dev
;
320 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
324 if (overlay
->last_flip_req
!= 0) {
325 ret
= i915_do_wait_request(dev
,
326 overlay
->last_flip_req
, true,
327 &dev_priv
->render_ring
);
329 overlay
->last_flip_req
= 0;
331 tmp
= I915_READ(ISR
);
333 if (!(tmp
& I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT
))
338 /* synchronous slowpath */
340 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
344 return intel_overlay_do_wait_request(overlay
, true, RELEASE_OLD_VID
);
347 /* overlay needs to be disabled in OCMD reg */
348 static int intel_overlay_off(struct intel_overlay
*overlay
)
350 u32 flip_addr
= overlay
->flip_addr
;
351 struct drm_device
*dev
= overlay
->dev
;
354 BUG_ON(!overlay
->active
);
356 /* According to intel docs the overlay hw may hang (when switching
357 * off) without loading the filter coeffs. It is however unclear whether
358 * this applies to the disabling of the overlay or to the switching off
359 * of the hw. Do it in both cases */
360 flip_addr
|= OFC_UPDATE
;
362 /* wait for overlay to go idle */
364 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
366 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
370 ret
= intel_overlay_do_wait_request(overlay
, true,
375 /* turn overlay off */
377 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_OFF
);
379 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
383 return intel_overlay_do_wait_request(overlay
, true,
387 static void intel_overlay_off_tail(struct intel_overlay
*overlay
)
389 struct drm_gem_object
*obj
;
391 /* never have the overlay hw on without showing a frame */
392 BUG_ON(!overlay
->vid_bo
);
393 obj
= &overlay
->vid_bo
->base
;
395 i915_gem_object_unpin(obj
);
396 drm_gem_object_unreference(obj
);
397 overlay
->vid_bo
= NULL
;
399 overlay
->crtc
->overlay
= NULL
;
400 overlay
->crtc
= NULL
;
404 /* recover from an interruption due to a signal
405 * We have to be careful not to repeat work forever an make forward progess. */
406 int intel_overlay_recover_from_interrupt(struct intel_overlay
*overlay
,
409 struct drm_device
*dev
= overlay
->dev
;
410 struct drm_gem_object
*obj
;
411 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
415 if (overlay
->hw_wedged
== HW_WEDGED
)
418 ret
= i915_do_wait_request(dev
, overlay
->last_flip_req
,
419 interruptible
, &dev_priv
->render_ring
);
423 switch (overlay
->hw_wedged
) {
424 case RELEASE_OLD_VID
:
425 obj
= &overlay
->old_vid_bo
->base
;
426 i915_gem_object_unpin(obj
);
427 drm_gem_object_unreference(obj
);
428 overlay
->old_vid_bo
= NULL
;
431 case SWITCH_OFF_STAGE_1
:
432 flip_addr
= overlay
->flip_addr
;
433 flip_addr
|= OFC_UPDATE
;
436 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_OFF
);
438 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
442 ret
= intel_overlay_do_wait_request(overlay
, interruptible
,
447 case SWITCH_OFF_STAGE_2
:
448 intel_overlay_off_tail(overlay
);
451 BUG_ON(overlay
->hw_wedged
!= NEEDS_WAIT_FOR_FLIP
);
454 overlay
->hw_wedged
= 0;
455 overlay
->last_flip_req
= 0;
459 /* Wait for pending overlay flip and release old frame.
460 * Needs to be called before the overlay register are changed
461 * via intel_overlay_(un)map_regs
463 static int intel_overlay_release_old_vid(struct intel_overlay
*overlay
)
466 struct drm_gem_object
*obj
;
468 /* only wait if there is actually an old frame to release to
469 * guarantee forward progress */
470 if (!overlay
->old_vid_bo
)
473 ret
= intel_overlay_wait_flip(overlay
);
477 obj
= &overlay
->old_vid_bo
->base
;
478 i915_gem_object_unpin(obj
);
479 drm_gem_object_unreference(obj
);
480 overlay
->old_vid_bo
= NULL
;
485 struct put_image_params
{
502 static int packed_depth_bytes(u32 format
)
504 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
505 case I915_OVERLAY_YUV422
:
507 case I915_OVERLAY_YUV411
:
508 /* return 6; not implemented */
514 static int packed_width_bytes(u32 format
, short width
)
516 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
517 case I915_OVERLAY_YUV422
:
524 static int uv_hsubsampling(u32 format
)
526 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
527 case I915_OVERLAY_YUV422
:
528 case I915_OVERLAY_YUV420
:
530 case I915_OVERLAY_YUV411
:
531 case I915_OVERLAY_YUV410
:
538 static int uv_vsubsampling(u32 format
)
540 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
541 case I915_OVERLAY_YUV420
:
542 case I915_OVERLAY_YUV410
:
544 case I915_OVERLAY_YUV422
:
545 case I915_OVERLAY_YUV411
:
552 static u32
calc_swidthsw(struct drm_device
*dev
, u32 offset
, u32 width
)
554 u32 mask
, shift
, ret
;
562 ret
= ((offset
+ width
+ mask
) >> shift
) - (offset
>> shift
);
569 static const u16 y_static_hcoeffs
[N_HORIZ_Y_TAPS
* N_PHASES
] = {
570 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
571 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
572 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
573 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
574 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
575 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
576 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
577 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
578 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
579 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
580 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
581 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
582 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
583 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
584 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
585 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
586 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
589 static const u16 uv_static_hcoeffs
[N_HORIZ_UV_TAPS
* N_PHASES
] = {
590 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
591 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
592 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
593 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
594 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
595 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
596 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
597 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
598 0x3000, 0x0800, 0x3000
601 static void update_polyphase_filter(struct overlay_registers
*regs
)
603 memcpy(regs
->Y_HCOEFS
, y_static_hcoeffs
, sizeof(y_static_hcoeffs
));
604 memcpy(regs
->UV_HCOEFS
, uv_static_hcoeffs
, sizeof(uv_static_hcoeffs
));
607 static bool update_scaling_factors(struct intel_overlay
*overlay
,
608 struct overlay_registers
*regs
,
609 struct put_image_params
*params
)
611 /* fixed point with a 12 bit shift */
612 u32 xscale
, yscale
, xscale_UV
, yscale_UV
;
614 #define FRACT_MASK 0xfff
615 bool scale_changed
= false;
616 int uv_hscale
= uv_hsubsampling(params
->format
);
617 int uv_vscale
= uv_vsubsampling(params
->format
);
619 if (params
->dst_w
> 1)
620 xscale
= ((params
->src_scan_w
- 1) << FP_SHIFT
)
623 xscale
= 1 << FP_SHIFT
;
625 if (params
->dst_h
> 1)
626 yscale
= ((params
->src_scan_h
- 1) << FP_SHIFT
)
629 yscale
= 1 << FP_SHIFT
;
631 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
632 xscale_UV
= xscale
/uv_hscale
;
633 yscale_UV
= yscale
/uv_vscale
;
634 /* make the Y scale to UV scale ratio an exact multiply */
635 xscale
= xscale_UV
* uv_hscale
;
636 yscale
= yscale_UV
* uv_vscale
;
642 if (xscale
!= overlay
->old_xscale
|| yscale
!= overlay
->old_yscale
)
643 scale_changed
= true;
644 overlay
->old_xscale
= xscale
;
645 overlay
->old_yscale
= yscale
;
647 regs
->YRGBSCALE
= (((yscale
& FRACT_MASK
) << 20) |
648 ((xscale
>> FP_SHIFT
) << 16) |
649 ((xscale
& FRACT_MASK
) << 3));
651 regs
->UVSCALE
= (((yscale_UV
& FRACT_MASK
) << 20) |
652 ((xscale_UV
>> FP_SHIFT
) << 16) |
653 ((xscale_UV
& FRACT_MASK
) << 3));
655 regs
->UVSCALEV
= ((((yscale
>> FP_SHIFT
) << 16) |
656 ((yscale_UV
>> FP_SHIFT
) << 0)));
659 update_polyphase_filter(regs
);
661 return scale_changed
;
664 static void update_colorkey(struct intel_overlay
*overlay
,
665 struct overlay_registers
*regs
)
667 u32 key
= overlay
->color_key
;
669 switch (overlay
->crtc
->base
.fb
->bits_per_pixel
) {
672 regs
->DCLRKM
= CLK_RGB8I_MASK
| DST_KEY_ENABLE
;
676 if (overlay
->crtc
->base
.fb
->depth
== 15) {
677 regs
->DCLRKV
= RGB15_TO_COLORKEY(key
);
678 regs
->DCLRKM
= CLK_RGB15_MASK
| DST_KEY_ENABLE
;
680 regs
->DCLRKV
= RGB16_TO_COLORKEY(key
);
681 regs
->DCLRKM
= CLK_RGB16_MASK
| DST_KEY_ENABLE
;
688 regs
->DCLRKM
= CLK_RGB24_MASK
| DST_KEY_ENABLE
;
693 static u32
overlay_cmd_reg(struct put_image_params
*params
)
695 u32 cmd
= OCMD_ENABLE
| OCMD_BUF_TYPE_FRAME
| OCMD_BUFFER0
;
697 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
698 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
699 case I915_OVERLAY_YUV422
:
700 cmd
|= OCMD_YUV_422_PLANAR
;
702 case I915_OVERLAY_YUV420
:
703 cmd
|= OCMD_YUV_420_PLANAR
;
705 case I915_OVERLAY_YUV411
:
706 case I915_OVERLAY_YUV410
:
707 cmd
|= OCMD_YUV_410_PLANAR
;
710 } else { /* YUV packed */
711 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
712 case I915_OVERLAY_YUV422
:
713 cmd
|= OCMD_YUV_422_PACKED
;
715 case I915_OVERLAY_YUV411
:
716 cmd
|= OCMD_YUV_411_PACKED
;
720 switch (params
->format
& I915_OVERLAY_SWAP_MASK
) {
721 case I915_OVERLAY_NO_SWAP
:
723 case I915_OVERLAY_UV_SWAP
:
726 case I915_OVERLAY_Y_SWAP
:
729 case I915_OVERLAY_Y_AND_UV_SWAP
:
730 cmd
|= OCMD_Y_AND_UV_SWAP
;
738 int intel_overlay_do_put_image(struct intel_overlay
*overlay
,
739 struct drm_gem_object
*new_bo
,
740 struct put_image_params
*params
)
743 struct overlay_registers
*regs
;
744 bool scale_changed
= false;
745 struct drm_i915_gem_object
*bo_priv
= to_intel_bo(new_bo
);
746 struct drm_device
*dev
= overlay
->dev
;
748 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
749 BUG_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
752 ret
= intel_overlay_release_old_vid(overlay
);
756 ret
= i915_gem_object_pin(new_bo
, PAGE_SIZE
);
760 ret
= i915_gem_object_set_to_gtt_domain(new_bo
, 0);
764 if (!overlay
->active
) {
765 regs
= intel_overlay_map_regs(overlay
);
770 regs
->OCONFIG
= OCONF_CC_OUT_8BIT
;
771 if (IS_I965GM(overlay
->dev
))
772 regs
->OCONFIG
|= OCONF_CSC_MODE_BT709
;
773 regs
->OCONFIG
|= overlay
->crtc
->pipe
== 0 ?
774 OCONF_PIPE_A
: OCONF_PIPE_B
;
775 intel_overlay_unmap_regs(overlay
);
777 ret
= intel_overlay_on(overlay
);
782 regs
= intel_overlay_map_regs(overlay
);
788 regs
->DWINPOS
= (params
->dst_y
<< 16) | params
->dst_x
;
789 regs
->DWINSZ
= (params
->dst_h
<< 16) | params
->dst_w
;
791 if (params
->format
& I915_OVERLAY_YUV_PACKED
)
792 tmp_width
= packed_width_bytes(params
->format
, params
->src_w
);
794 tmp_width
= params
->src_w
;
796 regs
->SWIDTH
= params
->src_w
;
797 regs
->SWIDTHSW
= calc_swidthsw(overlay
->dev
,
798 params
->offset_Y
, tmp_width
);
799 regs
->SHEIGHT
= params
->src_h
;
800 regs
->OBUF_0Y
= bo_priv
->gtt_offset
+ params
-> offset_Y
;
801 regs
->OSTRIDE
= params
->stride_Y
;
803 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
804 int uv_hscale
= uv_hsubsampling(params
->format
);
805 int uv_vscale
= uv_vsubsampling(params
->format
);
807 regs
->SWIDTH
|= (params
->src_w
/uv_hscale
) << 16;
808 tmp_U
= calc_swidthsw(overlay
->dev
, params
->offset_U
,
809 params
->src_w
/uv_hscale
);
810 tmp_V
= calc_swidthsw(overlay
->dev
, params
->offset_V
,
811 params
->src_w
/uv_hscale
);
812 regs
->SWIDTHSW
|= max_t(u32
, tmp_U
, tmp_V
) << 16;
813 regs
->SHEIGHT
|= (params
->src_h
/uv_vscale
) << 16;
814 regs
->OBUF_0U
= bo_priv
->gtt_offset
+ params
->offset_U
;
815 regs
->OBUF_0V
= bo_priv
->gtt_offset
+ params
->offset_V
;
816 regs
->OSTRIDE
|= params
->stride_UV
<< 16;
819 scale_changed
= update_scaling_factors(overlay
, regs
, params
);
821 update_colorkey(overlay
, regs
);
823 regs
->OCMD
= overlay_cmd_reg(params
);
825 intel_overlay_unmap_regs(overlay
);
827 intel_overlay_continue(overlay
, scale_changed
);
829 overlay
->old_vid_bo
= overlay
->vid_bo
;
830 overlay
->vid_bo
= to_intel_bo(new_bo
);
835 i915_gem_object_unpin(new_bo
);
839 int intel_overlay_switch_off(struct intel_overlay
*overlay
)
842 struct overlay_registers
*regs
;
843 struct drm_device
*dev
= overlay
->dev
;
845 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
846 BUG_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
848 if (overlay
->hw_wedged
) {
849 ret
= intel_overlay_recover_from_interrupt(overlay
, 1);
854 if (!overlay
->active
)
857 ret
= intel_overlay_release_old_vid(overlay
);
861 regs
= intel_overlay_map_regs(overlay
);
863 intel_overlay_unmap_regs(overlay
);
865 ret
= intel_overlay_off(overlay
);
869 intel_overlay_off_tail(overlay
);
874 static int check_overlay_possible_on_crtc(struct intel_overlay
*overlay
,
875 struct intel_crtc
*crtc
)
877 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
879 int pipeconf_reg
= (crtc
->pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
881 if (!crtc
->base
.enabled
|| crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
)
884 pipeconf
= I915_READ(pipeconf_reg
);
886 /* can't use the overlay with double wide pipe */
887 if (!IS_I965G(overlay
->dev
) && pipeconf
& PIPEACONF_DOUBLE_WIDE
)
893 static void update_pfit_vscale_ratio(struct intel_overlay
*overlay
)
895 struct drm_device
*dev
= overlay
->dev
;
896 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
897 u32 pfit_control
= I915_READ(PFIT_CONTROL
);
900 /* XXX: This is not the same logic as in the xorg driver, but more in
901 * line with the intel documentation for the i965
903 if (!IS_I965G(dev
)) {
904 if (pfit_control
& VERT_AUTO_SCALE
)
905 ratio
= I915_READ(PFIT_AUTO_RATIOS
);
907 ratio
= I915_READ(PFIT_PGM_RATIOS
);
908 ratio
>>= PFIT_VERT_SCALE_SHIFT
;
909 } else { /* on i965 use the PGM reg to read out the autoscaler values */
910 ratio
= I915_READ(PFIT_PGM_RATIOS
) >> PFIT_VERT_SCALE_SHIFT_965
;
913 overlay
->pfit_vscale_ratio
= ratio
;
916 static int check_overlay_dst(struct intel_overlay
*overlay
,
917 struct drm_intel_overlay_put_image
*rec
)
919 struct drm_display_mode
*mode
= &overlay
->crtc
->base
.mode
;
921 if (rec
->dst_x
< mode
->crtc_hdisplay
&&
922 rec
->dst_x
+ rec
->dst_width
<= mode
->crtc_hdisplay
&&
923 rec
->dst_y
< mode
->crtc_vdisplay
&&
924 rec
->dst_y
+ rec
->dst_height
<= mode
->crtc_vdisplay
)
930 static int check_overlay_scaling(struct put_image_params
*rec
)
934 /* downscaling limit is 8.0 */
935 tmp
= ((rec
->src_scan_h
<< 16) / rec
->dst_h
) >> 16;
938 tmp
= ((rec
->src_scan_w
<< 16) / rec
->dst_w
) >> 16;
945 static int check_overlay_src(struct drm_device
*dev
,
946 struct drm_intel_overlay_put_image
*rec
,
947 struct drm_gem_object
*new_bo
)
949 int uv_hscale
= uv_hsubsampling(rec
->flags
);
950 int uv_vscale
= uv_vsubsampling(rec
->flags
);
951 u32 stride_mask
, depth
, tmp
;
953 /* check src dimensions */
954 if (IS_845G(dev
) || IS_I830(dev
)) {
955 if (rec
->src_height
> IMAGE_MAX_HEIGHT_LEGACY
||
956 rec
->src_width
> IMAGE_MAX_WIDTH_LEGACY
)
959 if (rec
->src_height
> IMAGE_MAX_HEIGHT
||
960 rec
->src_width
> IMAGE_MAX_WIDTH
)
964 /* better safe than sorry, use 4 as the maximal subsampling ratio */
965 if (rec
->src_height
< N_VERT_Y_TAPS
*4 ||
966 rec
->src_width
< N_HORIZ_Y_TAPS
*4)
969 /* check alignment constraints */
970 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
971 case I915_OVERLAY_RGB
:
972 /* not implemented */
975 case I915_OVERLAY_YUV_PACKED
:
979 depth
= packed_depth_bytes(rec
->flags
);
983 /* ignore UV planes */
987 /* check pixel alignment */
988 if (rec
->offset_Y
% depth
)
992 case I915_OVERLAY_YUV_PLANAR
:
993 if (uv_vscale
< 0 || uv_hscale
< 0)
995 /* no offset restrictions for planar formats */
1002 if (rec
->src_width
% uv_hscale
)
1005 /* stride checking */
1006 if (IS_I830(dev
) || IS_845G(dev
))
1011 if (rec
->stride_Y
& stride_mask
|| rec
->stride_UV
& stride_mask
)
1013 if (IS_I965G(dev
) && rec
->stride_Y
< 512)
1016 tmp
= (rec
->flags
& I915_OVERLAY_TYPE_MASK
) == I915_OVERLAY_YUV_PLANAR
?
1018 if (rec
->stride_Y
> tmp
|| rec
->stride_UV
> 2*1024)
1021 /* check buffer dimensions */
1022 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
1023 case I915_OVERLAY_RGB
:
1024 case I915_OVERLAY_YUV_PACKED
:
1025 /* always 4 Y values per depth pixels */
1026 if (packed_width_bytes(rec
->flags
, rec
->src_width
) > rec
->stride_Y
)
1029 tmp
= rec
->stride_Y
*rec
->src_height
;
1030 if (rec
->offset_Y
+ tmp
> new_bo
->size
)
1034 case I915_OVERLAY_YUV_PLANAR
:
1035 if (rec
->src_width
> rec
->stride_Y
)
1037 if (rec
->src_width
/uv_hscale
> rec
->stride_UV
)
1040 tmp
= rec
->stride_Y
* rec
->src_height
;
1041 if (rec
->offset_Y
+ tmp
> new_bo
->size
)
1044 tmp
= rec
->stride_UV
* (rec
->src_height
/ uv_vscale
);
1045 if (rec
->offset_U
+ tmp
> new_bo
->size
||
1046 rec
->offset_V
+ tmp
> new_bo
->size
)
1054 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
1055 struct drm_file
*file_priv
)
1057 struct drm_intel_overlay_put_image
*put_image_rec
= data
;
1058 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1059 struct intel_overlay
*overlay
;
1060 struct drm_mode_object
*drmmode_obj
;
1061 struct intel_crtc
*crtc
;
1062 struct drm_gem_object
*new_bo
;
1063 struct put_image_params
*params
;
1067 DRM_ERROR("called with no initialization\n");
1071 overlay
= dev_priv
->overlay
;
1073 DRM_DEBUG("userspace bug: no overlay\n");
1077 if (!(put_image_rec
->flags
& I915_OVERLAY_ENABLE
)) {
1078 mutex_lock(&dev
->mode_config
.mutex
);
1079 mutex_lock(&dev
->struct_mutex
);
1081 ret
= intel_overlay_switch_off(overlay
);
1083 mutex_unlock(&dev
->struct_mutex
);
1084 mutex_unlock(&dev
->mode_config
.mutex
);
1089 params
= kmalloc(sizeof(struct put_image_params
), GFP_KERNEL
);
1093 drmmode_obj
= drm_mode_object_find(dev
, put_image_rec
->crtc_id
,
1094 DRM_MODE_OBJECT_CRTC
);
1099 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
1101 new_bo
= drm_gem_object_lookup(dev
, file_priv
,
1102 put_image_rec
->bo_handle
);
1108 mutex_lock(&dev
->mode_config
.mutex
);
1109 mutex_lock(&dev
->struct_mutex
);
1111 if (overlay
->hw_wedged
) {
1112 ret
= intel_overlay_recover_from_interrupt(overlay
, 1);
1117 if (overlay
->crtc
!= crtc
) {
1118 struct drm_display_mode
*mode
= &crtc
->base
.mode
;
1119 ret
= intel_overlay_switch_off(overlay
);
1123 ret
= check_overlay_possible_on_crtc(overlay
, crtc
);
1127 overlay
->crtc
= crtc
;
1128 crtc
->overlay
= overlay
;
1130 if (intel_panel_fitter_pipe(dev
) == crtc
->pipe
1131 /* and line to wide, i.e. one-line-mode */
1132 && mode
->hdisplay
> 1024) {
1133 overlay
->pfit_active
= 1;
1134 update_pfit_vscale_ratio(overlay
);
1136 overlay
->pfit_active
= 0;
1139 ret
= check_overlay_dst(overlay
, put_image_rec
);
1143 if (overlay
->pfit_active
) {
1144 params
->dst_y
= ((((u32
)put_image_rec
->dst_y
) << 12) /
1145 overlay
->pfit_vscale_ratio
);
1146 /* shifting right rounds downwards, so add 1 */
1147 params
->dst_h
= ((((u32
)put_image_rec
->dst_height
) << 12) /
1148 overlay
->pfit_vscale_ratio
) + 1;
1150 params
->dst_y
= put_image_rec
->dst_y
;
1151 params
->dst_h
= put_image_rec
->dst_height
;
1153 params
->dst_x
= put_image_rec
->dst_x
;
1154 params
->dst_w
= put_image_rec
->dst_width
;
1156 params
->src_w
= put_image_rec
->src_width
;
1157 params
->src_h
= put_image_rec
->src_height
;
1158 params
->src_scan_w
= put_image_rec
->src_scan_width
;
1159 params
->src_scan_h
= put_image_rec
->src_scan_height
;
1160 if (params
->src_scan_h
> params
->src_h
||
1161 params
->src_scan_w
> params
->src_w
) {
1166 ret
= check_overlay_src(dev
, put_image_rec
, new_bo
);
1169 params
->format
= put_image_rec
->flags
& ~I915_OVERLAY_FLAGS_MASK
;
1170 params
->stride_Y
= put_image_rec
->stride_Y
;
1171 params
->stride_UV
= put_image_rec
->stride_UV
;
1172 params
->offset_Y
= put_image_rec
->offset_Y
;
1173 params
->offset_U
= put_image_rec
->offset_U
;
1174 params
->offset_V
= put_image_rec
->offset_V
;
1176 /* Check scaling after src size to prevent a divide-by-zero. */
1177 ret
= check_overlay_scaling(params
);
1181 ret
= intel_overlay_do_put_image(overlay
, new_bo
, params
);
1185 mutex_unlock(&dev
->struct_mutex
);
1186 mutex_unlock(&dev
->mode_config
.mutex
);
1193 mutex_unlock(&dev
->struct_mutex
);
1194 mutex_unlock(&dev
->mode_config
.mutex
);
1195 drm_gem_object_unreference_unlocked(new_bo
);
1202 static void update_reg_attrs(struct intel_overlay
*overlay
,
1203 struct overlay_registers
*regs
)
1205 regs
->OCLRC0
= (overlay
->contrast
<< 18) | (overlay
->brightness
& 0xff);
1206 regs
->OCLRC1
= overlay
->saturation
;
1209 static bool check_gamma_bounds(u32 gamma1
, u32 gamma2
)
1213 if (gamma1
& 0xff000000 || gamma2
& 0xff000000)
1216 for (i
= 0; i
< 3; i
++) {
1217 if (((gamma1
>> i
*8) & 0xff) >= ((gamma2
>> i
*8) & 0xff))
1224 static bool check_gamma5_errata(u32 gamma5
)
1228 for (i
= 0; i
< 3; i
++) {
1229 if (((gamma5
>> i
*8) & 0xff) == 0x80)
1236 static int check_gamma(struct drm_intel_overlay_attrs
*attrs
)
1238 if (!check_gamma_bounds(0, attrs
->gamma0
) ||
1239 !check_gamma_bounds(attrs
->gamma0
, attrs
->gamma1
) ||
1240 !check_gamma_bounds(attrs
->gamma1
, attrs
->gamma2
) ||
1241 !check_gamma_bounds(attrs
->gamma2
, attrs
->gamma3
) ||
1242 !check_gamma_bounds(attrs
->gamma3
, attrs
->gamma4
) ||
1243 !check_gamma_bounds(attrs
->gamma4
, attrs
->gamma5
) ||
1244 !check_gamma_bounds(attrs
->gamma5
, 0x00ffffff))
1247 if (!check_gamma5_errata(attrs
->gamma5
))
1253 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
1254 struct drm_file
*file_priv
)
1256 struct drm_intel_overlay_attrs
*attrs
= data
;
1257 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1258 struct intel_overlay
*overlay
;
1259 struct overlay_registers
*regs
;
1263 DRM_ERROR("called with no initialization\n");
1267 overlay
= dev_priv
->overlay
;
1269 DRM_DEBUG("userspace bug: no overlay\n");
1273 mutex_lock(&dev
->mode_config
.mutex
);
1274 mutex_lock(&dev
->struct_mutex
);
1277 if (!(attrs
->flags
& I915_OVERLAY_UPDATE_ATTRS
)) {
1278 attrs
->color_key
= overlay
->color_key
;
1279 attrs
->brightness
= overlay
->brightness
;
1280 attrs
->contrast
= overlay
->contrast
;
1281 attrs
->saturation
= overlay
->saturation
;
1284 attrs
->gamma0
= I915_READ(OGAMC0
);
1285 attrs
->gamma1
= I915_READ(OGAMC1
);
1286 attrs
->gamma2
= I915_READ(OGAMC2
);
1287 attrs
->gamma3
= I915_READ(OGAMC3
);
1288 attrs
->gamma4
= I915_READ(OGAMC4
);
1289 attrs
->gamma5
= I915_READ(OGAMC5
);
1292 if (attrs
->brightness
< -128 || attrs
->brightness
> 127)
1294 if (attrs
->contrast
> 255)
1296 if (attrs
->saturation
> 1023)
1299 overlay
->color_key
= attrs
->color_key
;
1300 overlay
->brightness
= attrs
->brightness
;
1301 overlay
->contrast
= attrs
->contrast
;
1302 overlay
->saturation
= attrs
->saturation
;
1304 regs
= intel_overlay_map_regs(overlay
);
1310 update_reg_attrs(overlay
, regs
);
1312 intel_overlay_unmap_regs(overlay
);
1314 if (attrs
->flags
& I915_OVERLAY_UPDATE_GAMMA
) {
1318 if (overlay
->active
) {
1323 ret
= check_gamma(attrs
);
1327 I915_WRITE(OGAMC0
, attrs
->gamma0
);
1328 I915_WRITE(OGAMC1
, attrs
->gamma1
);
1329 I915_WRITE(OGAMC2
, attrs
->gamma2
);
1330 I915_WRITE(OGAMC3
, attrs
->gamma3
);
1331 I915_WRITE(OGAMC4
, attrs
->gamma4
);
1332 I915_WRITE(OGAMC5
, attrs
->gamma5
);
1338 mutex_unlock(&dev
->struct_mutex
);
1339 mutex_unlock(&dev
->mode_config
.mutex
);
1344 void intel_setup_overlay(struct drm_device
*dev
)
1346 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1347 struct intel_overlay
*overlay
;
1348 struct drm_gem_object
*reg_bo
;
1349 struct overlay_registers
*regs
;
1352 if (!HAS_OVERLAY(dev
))
1355 overlay
= kzalloc(sizeof(struct intel_overlay
), GFP_KERNEL
);
1360 reg_bo
= i915_gem_alloc_object(dev
, PAGE_SIZE
);
1363 overlay
->reg_bo
= to_intel_bo(reg_bo
);
1365 if (OVERLAY_NEEDS_PHYSICAL(dev
)) {
1366 ret
= i915_gem_attach_phys_object(dev
, reg_bo
,
1367 I915_GEM_PHYS_OVERLAY_REGS
,
1370 DRM_ERROR("failed to attach phys overlay regs\n");
1373 overlay
->flip_addr
= overlay
->reg_bo
->phys_obj
->handle
->busaddr
;
1375 ret
= i915_gem_object_pin(reg_bo
, PAGE_SIZE
);
1377 DRM_ERROR("failed to pin overlay register bo\n");
1380 overlay
->flip_addr
= overlay
->reg_bo
->gtt_offset
;
1382 ret
= i915_gem_object_set_to_gtt_domain(reg_bo
, true);
1384 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1389 /* init all values */
1390 overlay
->color_key
= 0x0101fe;
1391 overlay
->brightness
= -19;
1392 overlay
->contrast
= 75;
1393 overlay
->saturation
= 146;
1395 regs
= intel_overlay_map_regs(overlay
);
1399 memset(regs
, 0, sizeof(struct overlay_registers
));
1400 update_polyphase_filter(regs
);
1402 update_reg_attrs(overlay
, regs
);
1404 intel_overlay_unmap_regs(overlay
);
1406 dev_priv
->overlay
= overlay
;
1407 DRM_INFO("initialized overlay support\n");
1411 i915_gem_object_unpin(reg_bo
);
1413 drm_gem_object_unreference(reg_bo
);
1419 void intel_cleanup_overlay(struct drm_device
*dev
)
1421 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1423 if (!dev_priv
->overlay
)
1426 /* The bo's should be free'd by the generic code already.
1427 * Furthermore modesetting teardown happens beforehand so the
1428 * hardware should be off already */
1429 BUG_ON(dev_priv
->overlay
->active
);
1431 drm_gem_object_unreference_unlocked(&dev_priv
->overlay
->reg_bo
->base
);
1432 kfree(dev_priv
->overlay
);
1435 struct intel_overlay_error_state
{
1436 struct overlay_registers regs
;
1442 struct intel_overlay_error_state
*
1443 intel_overlay_capture_error_state(struct drm_device
*dev
)
1445 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1446 struct intel_overlay
*overlay
= dev_priv
->overlay
;
1447 struct intel_overlay_error_state
*error
;
1448 struct overlay_registers __iomem
*regs
;
1450 if (!overlay
|| !overlay
->active
)
1453 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
1457 error
->dovsta
= I915_READ(DOVSTA
);
1458 error
->isr
= I915_READ(ISR
);
1459 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
1460 error
->base
= (long) overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
1462 error
->base
= (long) overlay
->reg_bo
->gtt_offset
;
1464 regs
= intel_overlay_map_regs_atomic(overlay
, KM_IRQ0
);
1468 memcpy_fromio(&error
->regs
, regs
, sizeof(struct overlay_registers
));
1469 intel_overlay_unmap_regs_atomic(overlay
, KM_IRQ0
);
1479 intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
)
1481 seq_printf(m
, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1482 error
->dovsta
, error
->isr
);
1483 seq_printf(m
, " Register file at 0x%08lx:\n",
1486 #define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)