2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 static void ath9k_hw_set_txq_interrupts(struct ath_hw
*ah
,
21 struct ath9k_tx_queue_info
*qi
)
23 ath_dbg(ath9k_hw_common(ah
), ATH_DBG_INTERRUPT
,
24 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
25 ah
->txok_interrupt_mask
, ah
->txerr_interrupt_mask
,
26 ah
->txdesc_interrupt_mask
, ah
->txeol_interrupt_mask
,
27 ah
->txurn_interrupt_mask
);
29 ENABLE_REGWRITE_BUFFER(ah
);
31 REG_WRITE(ah
, AR_IMR_S0
,
32 SM(ah
->txok_interrupt_mask
, AR_IMR_S0_QCU_TXOK
)
33 | SM(ah
->txdesc_interrupt_mask
, AR_IMR_S0_QCU_TXDESC
));
34 REG_WRITE(ah
, AR_IMR_S1
,
35 SM(ah
->txerr_interrupt_mask
, AR_IMR_S1_QCU_TXERR
)
36 | SM(ah
->txeol_interrupt_mask
, AR_IMR_S1_QCU_TXEOL
));
38 ah
->imrs2_reg
&= ~AR_IMR_S2_QCU_TXURN
;
39 ah
->imrs2_reg
|= (ah
->txurn_interrupt_mask
& AR_IMR_S2_QCU_TXURN
);
40 REG_WRITE(ah
, AR_IMR_S2
, ah
->imrs2_reg
);
42 REGWRITE_BUFFER_FLUSH(ah
);
45 u32
ath9k_hw_gettxbuf(struct ath_hw
*ah
, u32 q
)
47 return REG_READ(ah
, AR_QTXDP(q
));
49 EXPORT_SYMBOL(ath9k_hw_gettxbuf
);
51 void ath9k_hw_puttxbuf(struct ath_hw
*ah
, u32 q
, u32 txdp
)
53 REG_WRITE(ah
, AR_QTXDP(q
), txdp
);
55 EXPORT_SYMBOL(ath9k_hw_puttxbuf
);
57 void ath9k_hw_txstart(struct ath_hw
*ah
, u32 q
)
59 ath_dbg(ath9k_hw_common(ah
), ATH_DBG_QUEUE
,
60 "Enable TXE on queue: %u\n", q
);
61 REG_WRITE(ah
, AR_Q_TXE
, 1 << q
);
63 EXPORT_SYMBOL(ath9k_hw_txstart
);
65 void ath9k_hw_cleartxdesc(struct ath_hw
*ah
, void *ds
)
67 struct ar5416_desc
*ads
= AR5416DESC(ds
);
69 ads
->ds_txstatus0
= ads
->ds_txstatus1
= 0;
70 ads
->ds_txstatus2
= ads
->ds_txstatus3
= 0;
71 ads
->ds_txstatus4
= ads
->ds_txstatus5
= 0;
72 ads
->ds_txstatus6
= ads
->ds_txstatus7
= 0;
73 ads
->ds_txstatus8
= ads
->ds_txstatus9
= 0;
75 EXPORT_SYMBOL(ath9k_hw_cleartxdesc
);
77 u32
ath9k_hw_numtxpending(struct ath_hw
*ah
, u32 q
)
81 npend
= REG_READ(ah
, AR_QSTS(q
)) & AR_Q_STS_PEND_FR_CNT
;
84 if (REG_READ(ah
, AR_Q_TXE
) & (1 << q
))
90 EXPORT_SYMBOL(ath9k_hw_numtxpending
);
93 * ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
95 * @ah: atheros hardware struct
96 * @bIncTrigLevel: whether or not the frame trigger level should be updated
98 * The frame trigger level specifies the minimum number of bytes,
99 * in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO
100 * before the PCU will initiate sending the frame on the air. This can
101 * mean we initiate transmit before a full frame is on the PCU TX FIFO.
102 * Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs
105 * Caution must be taken to ensure to set the frame trigger level based
106 * on the DMA request size. For example if the DMA request size is set to
107 * 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because
108 * there need to be enough space in the tx FIFO for the requested transfer
109 * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set
110 * the threshold to a value beyond 6, then the transmit will hang.
112 * Current dual stream devices have a PCU TX FIFO size of 8 KB.
113 * Current single stream devices have a PCU TX FIFO size of 4 KB, however,
114 * there is a hardware issue which forces us to use 2 KB instead so the
115 * frame trigger level must not exceed 2 KB for these chipsets.
117 bool ath9k_hw_updatetxtriglevel(struct ath_hw
*ah
, bool bIncTrigLevel
)
119 u32 txcfg
, curLevel
, newLevel
;
121 if (ah
->tx_trig_level
>= ah
->config
.max_txtrig_level
)
124 ath9k_hw_disable_interrupts(ah
);
126 txcfg
= REG_READ(ah
, AR_TXCFG
);
127 curLevel
= MS(txcfg
, AR_FTRIG
);
130 if (curLevel
< ah
->config
.max_txtrig_level
)
132 } else if (curLevel
> MIN_TX_FIFO_THRESHOLD
)
134 if (newLevel
!= curLevel
)
135 REG_WRITE(ah
, AR_TXCFG
,
136 (txcfg
& ~AR_FTRIG
) | SM(newLevel
, AR_FTRIG
));
138 ath9k_hw_enable_interrupts(ah
);
140 ah
->tx_trig_level
= newLevel
;
142 return newLevel
!= curLevel
;
144 EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel
);
146 void ath9k_hw_abort_tx_dma(struct ath_hw
*ah
)
150 REG_WRITE(ah
, AR_Q_TXD
, AR_Q_TXD_M
);
152 REG_SET_BIT(ah
, AR_PCU_MISC
, AR_PCU_FORCE_QUIET_COLL
| AR_PCU_CLEAR_VMF
);
153 REG_SET_BIT(ah
, AR_DIAG_SW
, AR_DIAG_FORCE_CH_IDLE_HIGH
);
154 REG_SET_BIT(ah
, AR_D_GBL_IFS_MISC
, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF
);
156 for (q
= 0; q
< AR_NUM_QCU
; q
++) {
157 for (i
= 0; i
< 1000; i
++) {
161 if (!ath9k_hw_numtxpending(ah
, q
))
166 REG_CLR_BIT(ah
, AR_PCU_MISC
, AR_PCU_FORCE_QUIET_COLL
| AR_PCU_CLEAR_VMF
);
167 REG_CLR_BIT(ah
, AR_DIAG_SW
, AR_DIAG_FORCE_CH_IDLE_HIGH
);
168 REG_CLR_BIT(ah
, AR_D_GBL_IFS_MISC
, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF
);
170 REG_WRITE(ah
, AR_Q_TXD
, 0);
172 EXPORT_SYMBOL(ath9k_hw_abort_tx_dma
);
174 bool ath9k_hw_stop_dma_queue(struct ath_hw
*ah
, u32 q
)
176 #define ATH9K_TX_STOP_DMA_TIMEOUT 1000 /* usec */
177 #define ATH9K_TIME_QUANTUM 100 /* usec */
178 int wait_time
= ATH9K_TX_STOP_DMA_TIMEOUT
/ ATH9K_TIME_QUANTUM
;
181 REG_WRITE(ah
, AR_Q_TXD
, 1 << q
);
183 for (wait
= wait_time
; wait
!= 0; wait
--) {
184 if (wait
!= wait_time
)
185 udelay(ATH9K_TIME_QUANTUM
);
187 if (ath9k_hw_numtxpending(ah
, q
) == 0)
191 REG_WRITE(ah
, AR_Q_TXD
, 0);
195 #undef ATH9K_TX_STOP_DMA_TIMEOUT
196 #undef ATH9K_TIME_QUANTUM
198 EXPORT_SYMBOL(ath9k_hw_stop_dma_queue
);
200 void ath9k_hw_gettxintrtxqs(struct ath_hw
*ah
, u32
*txqs
)
202 *txqs
&= ah
->intr_txqs
;
203 ah
->intr_txqs
&= ~(*txqs
);
205 EXPORT_SYMBOL(ath9k_hw_gettxintrtxqs
);
207 bool ath9k_hw_set_txq_props(struct ath_hw
*ah
, int q
,
208 const struct ath9k_tx_queue_info
*qinfo
)
211 struct ath_common
*common
= ath9k_hw_common(ah
);
212 struct ath9k_tx_queue_info
*qi
;
215 if (qi
->tqi_type
== ATH9K_TX_QUEUE_INACTIVE
) {
216 ath_dbg(common
, ATH_DBG_QUEUE
,
217 "Set TXQ properties, inactive queue: %u\n", q
);
221 ath_dbg(common
, ATH_DBG_QUEUE
, "Set queue properties for: %u\n", q
);
223 qi
->tqi_ver
= qinfo
->tqi_ver
;
224 qi
->tqi_subtype
= qinfo
->tqi_subtype
;
225 qi
->tqi_qflags
= qinfo
->tqi_qflags
;
226 qi
->tqi_priority
= qinfo
->tqi_priority
;
227 if (qinfo
->tqi_aifs
!= ATH9K_TXQ_USEDEFAULT
)
228 qi
->tqi_aifs
= min(qinfo
->tqi_aifs
, 255U);
230 qi
->tqi_aifs
= INIT_AIFS
;
231 if (qinfo
->tqi_cwmin
!= ATH9K_TXQ_USEDEFAULT
) {
232 cw
= min(qinfo
->tqi_cwmin
, 1024U);
234 while (qi
->tqi_cwmin
< cw
)
235 qi
->tqi_cwmin
= (qi
->tqi_cwmin
<< 1) | 1;
237 qi
->tqi_cwmin
= qinfo
->tqi_cwmin
;
238 if (qinfo
->tqi_cwmax
!= ATH9K_TXQ_USEDEFAULT
) {
239 cw
= min(qinfo
->tqi_cwmax
, 1024U);
241 while (qi
->tqi_cwmax
< cw
)
242 qi
->tqi_cwmax
= (qi
->tqi_cwmax
<< 1) | 1;
244 qi
->tqi_cwmax
= INIT_CWMAX
;
246 if (qinfo
->tqi_shretry
!= 0)
247 qi
->tqi_shretry
= min((u32
) qinfo
->tqi_shretry
, 15U);
249 qi
->tqi_shretry
= INIT_SH_RETRY
;
250 if (qinfo
->tqi_lgretry
!= 0)
251 qi
->tqi_lgretry
= min((u32
) qinfo
->tqi_lgretry
, 15U);
253 qi
->tqi_lgretry
= INIT_LG_RETRY
;
254 qi
->tqi_cbrPeriod
= qinfo
->tqi_cbrPeriod
;
255 qi
->tqi_cbrOverflowLimit
= qinfo
->tqi_cbrOverflowLimit
;
256 qi
->tqi_burstTime
= qinfo
->tqi_burstTime
;
257 qi
->tqi_readyTime
= qinfo
->tqi_readyTime
;
259 switch (qinfo
->tqi_subtype
) {
261 if (qi
->tqi_type
== ATH9K_TX_QUEUE_DATA
)
262 qi
->tqi_intFlags
= ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS
;
270 EXPORT_SYMBOL(ath9k_hw_set_txq_props
);
272 bool ath9k_hw_get_txq_props(struct ath_hw
*ah
, int q
,
273 struct ath9k_tx_queue_info
*qinfo
)
275 struct ath_common
*common
= ath9k_hw_common(ah
);
276 struct ath9k_tx_queue_info
*qi
;
279 if (qi
->tqi_type
== ATH9K_TX_QUEUE_INACTIVE
) {
280 ath_dbg(common
, ATH_DBG_QUEUE
,
281 "Get TXQ properties, inactive queue: %u\n", q
);
285 qinfo
->tqi_qflags
= qi
->tqi_qflags
;
286 qinfo
->tqi_ver
= qi
->tqi_ver
;
287 qinfo
->tqi_subtype
= qi
->tqi_subtype
;
288 qinfo
->tqi_qflags
= qi
->tqi_qflags
;
289 qinfo
->tqi_priority
= qi
->tqi_priority
;
290 qinfo
->tqi_aifs
= qi
->tqi_aifs
;
291 qinfo
->tqi_cwmin
= qi
->tqi_cwmin
;
292 qinfo
->tqi_cwmax
= qi
->tqi_cwmax
;
293 qinfo
->tqi_shretry
= qi
->tqi_shretry
;
294 qinfo
->tqi_lgretry
= qi
->tqi_lgretry
;
295 qinfo
->tqi_cbrPeriod
= qi
->tqi_cbrPeriod
;
296 qinfo
->tqi_cbrOverflowLimit
= qi
->tqi_cbrOverflowLimit
;
297 qinfo
->tqi_burstTime
= qi
->tqi_burstTime
;
298 qinfo
->tqi_readyTime
= qi
->tqi_readyTime
;
302 EXPORT_SYMBOL(ath9k_hw_get_txq_props
);
304 int ath9k_hw_setuptxqueue(struct ath_hw
*ah
, enum ath9k_tx_queue type
,
305 const struct ath9k_tx_queue_info
*qinfo
)
307 struct ath_common
*common
= ath9k_hw_common(ah
);
308 struct ath9k_tx_queue_info
*qi
;
312 case ATH9K_TX_QUEUE_BEACON
:
313 q
= ATH9K_NUM_TX_QUEUES
- 1;
315 case ATH9K_TX_QUEUE_CAB
:
316 q
= ATH9K_NUM_TX_QUEUES
- 2;
318 case ATH9K_TX_QUEUE_PSPOLL
:
321 case ATH9K_TX_QUEUE_UAPSD
:
322 q
= ATH9K_NUM_TX_QUEUES
- 3;
324 case ATH9K_TX_QUEUE_DATA
:
325 for (q
= 0; q
< ATH9K_NUM_TX_QUEUES
; q
++)
326 if (ah
->txq
[q
].tqi_type
==
327 ATH9K_TX_QUEUE_INACTIVE
)
329 if (q
== ATH9K_NUM_TX_QUEUES
) {
330 ath_err(common
, "No available TX queue\n");
335 ath_err(common
, "Invalid TX queue type: %u\n", type
);
339 ath_dbg(common
, ATH_DBG_QUEUE
, "Setup TX queue: %u\n", q
);
342 if (qi
->tqi_type
!= ATH9K_TX_QUEUE_INACTIVE
) {
343 ath_err(common
, "TX queue: %u already active\n", q
);
346 memset(qi
, 0, sizeof(struct ath9k_tx_queue_info
));
350 TXQ_FLAG_TXOKINT_ENABLE
351 | TXQ_FLAG_TXERRINT_ENABLE
352 | TXQ_FLAG_TXDESCINT_ENABLE
| TXQ_FLAG_TXURNINT_ENABLE
;
353 qi
->tqi_aifs
= INIT_AIFS
;
354 qi
->tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
355 qi
->tqi_cwmax
= INIT_CWMAX
;
356 qi
->tqi_shretry
= INIT_SH_RETRY
;
357 qi
->tqi_lgretry
= INIT_LG_RETRY
;
358 qi
->tqi_physCompBuf
= 0;
360 qi
->tqi_physCompBuf
= qinfo
->tqi_physCompBuf
;
361 (void) ath9k_hw_set_txq_props(ah
, q
, qinfo
);
366 EXPORT_SYMBOL(ath9k_hw_setuptxqueue
);
368 bool ath9k_hw_releasetxqueue(struct ath_hw
*ah
, u32 q
)
370 struct ath_common
*common
= ath9k_hw_common(ah
);
371 struct ath9k_tx_queue_info
*qi
;
374 if (qi
->tqi_type
== ATH9K_TX_QUEUE_INACTIVE
) {
375 ath_dbg(common
, ATH_DBG_QUEUE
,
376 "Release TXQ, inactive queue: %u\n", q
);
380 ath_dbg(common
, ATH_DBG_QUEUE
, "Release TX queue: %u\n", q
);
382 qi
->tqi_type
= ATH9K_TX_QUEUE_INACTIVE
;
383 ah
->txok_interrupt_mask
&= ~(1 << q
);
384 ah
->txerr_interrupt_mask
&= ~(1 << q
);
385 ah
->txdesc_interrupt_mask
&= ~(1 << q
);
386 ah
->txeol_interrupt_mask
&= ~(1 << q
);
387 ah
->txurn_interrupt_mask
&= ~(1 << q
);
388 ath9k_hw_set_txq_interrupts(ah
, qi
);
392 EXPORT_SYMBOL(ath9k_hw_releasetxqueue
);
394 bool ath9k_hw_resettxqueue(struct ath_hw
*ah
, u32 q
)
396 struct ath_common
*common
= ath9k_hw_common(ah
);
397 struct ath9k_channel
*chan
= ah
->curchan
;
398 struct ath9k_tx_queue_info
*qi
;
399 u32 cwMin
, chanCwMin
, value
;
402 if (qi
->tqi_type
== ATH9K_TX_QUEUE_INACTIVE
) {
403 ath_dbg(common
, ATH_DBG_QUEUE
,
404 "Reset TXQ, inactive queue: %u\n", q
);
408 ath_dbg(common
, ATH_DBG_QUEUE
, "Reset TX queue: %u\n", q
);
410 if (qi
->tqi_cwmin
== ATH9K_TXQ_USEDEFAULT
) {
411 if (chan
&& IS_CHAN_B(chan
))
412 chanCwMin
= INIT_CWMIN_11B
;
414 chanCwMin
= INIT_CWMIN
;
416 for (cwMin
= 1; cwMin
< chanCwMin
; cwMin
= (cwMin
<< 1) | 1);
418 cwMin
= qi
->tqi_cwmin
;
420 ENABLE_REGWRITE_BUFFER(ah
);
422 REG_WRITE(ah
, AR_DLCL_IFS(q
),
423 SM(cwMin
, AR_D_LCL_IFS_CWMIN
) |
424 SM(qi
->tqi_cwmax
, AR_D_LCL_IFS_CWMAX
) |
425 SM(qi
->tqi_aifs
, AR_D_LCL_IFS_AIFS
));
427 REG_WRITE(ah
, AR_DRETRY_LIMIT(q
),
428 SM(INIT_SSH_RETRY
, AR_D_RETRY_LIMIT_STA_SH
) |
429 SM(INIT_SLG_RETRY
, AR_D_RETRY_LIMIT_STA_LG
) |
430 SM(qi
->tqi_shretry
, AR_D_RETRY_LIMIT_FR_SH
));
432 REG_WRITE(ah
, AR_QMISC(q
), AR_Q_MISC_DCU_EARLY_TERM_REQ
);
433 REG_WRITE(ah
, AR_DMISC(q
),
434 AR_D_MISC_CW_BKOFF_EN
| AR_D_MISC_FRAG_WAIT_EN
| 0x2);
436 if (qi
->tqi_cbrPeriod
) {
437 REG_WRITE(ah
, AR_QCBRCFG(q
),
438 SM(qi
->tqi_cbrPeriod
, AR_Q_CBRCFG_INTERVAL
) |
439 SM(qi
->tqi_cbrOverflowLimit
, AR_Q_CBRCFG_OVF_THRESH
));
440 REG_SET_BIT(ah
, AR_QMISC(q
), AR_Q_MISC_FSP_CBR
|
441 (qi
->tqi_cbrOverflowLimit
?
442 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN
: 0));
444 if (qi
->tqi_readyTime
&& (qi
->tqi_type
!= ATH9K_TX_QUEUE_CAB
)) {
445 REG_WRITE(ah
, AR_QRDYTIMECFG(q
),
446 SM(qi
->tqi_readyTime
, AR_Q_RDYTIMECFG_DURATION
) |
450 REG_WRITE(ah
, AR_DCHNTIME(q
),
451 SM(qi
->tqi_burstTime
, AR_D_CHNTIME_DUR
) |
452 (qi
->tqi_burstTime
? AR_D_CHNTIME_EN
: 0));
454 if (qi
->tqi_burstTime
455 && (qi
->tqi_qflags
& TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE
))
456 REG_SET_BIT(ah
, AR_QMISC(q
), AR_Q_MISC_RDYTIME_EXP_POLICY
);
458 if (qi
->tqi_qflags
& TXQ_FLAG_BACKOFF_DISABLE
)
459 REG_SET_BIT(ah
, AR_DMISC(q
), AR_D_MISC_POST_FR_BKOFF_DIS
);
461 REGWRITE_BUFFER_FLUSH(ah
);
463 if (qi
->tqi_qflags
& TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE
)
464 REG_SET_BIT(ah
, AR_DMISC(q
), AR_D_MISC_FRAG_BKOFF_EN
);
466 switch (qi
->tqi_type
) {
467 case ATH9K_TX_QUEUE_BEACON
:
468 ENABLE_REGWRITE_BUFFER(ah
);
470 REG_SET_BIT(ah
, AR_QMISC(q
),
471 AR_Q_MISC_FSP_DBA_GATED
472 | AR_Q_MISC_BEACON_USE
473 | AR_Q_MISC_CBR_INCR_DIS1
);
475 REG_SET_BIT(ah
, AR_DMISC(q
),
476 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL
<<
477 AR_D_MISC_ARB_LOCKOUT_CNTRL_S
)
478 | AR_D_MISC_BEACON_USE
479 | AR_D_MISC_POST_FR_BKOFF_DIS
);
481 REGWRITE_BUFFER_FLUSH(ah
);
484 * cwmin and cwmax should be 0 for beacon queue
485 * but not for IBSS as we would create an imbalance
486 * on beaconing fairness for participating nodes.
488 if (AR_SREV_9300_20_OR_LATER(ah
) &&
489 ah
->opmode
!= NL80211_IFTYPE_ADHOC
) {
490 REG_WRITE(ah
, AR_DLCL_IFS(q
), SM(0, AR_D_LCL_IFS_CWMIN
)
491 | SM(0, AR_D_LCL_IFS_CWMAX
)
492 | SM(qi
->tqi_aifs
, AR_D_LCL_IFS_AIFS
));
495 case ATH9K_TX_QUEUE_CAB
:
496 ENABLE_REGWRITE_BUFFER(ah
);
498 REG_SET_BIT(ah
, AR_QMISC(q
),
499 AR_Q_MISC_FSP_DBA_GATED
500 | AR_Q_MISC_CBR_INCR_DIS1
501 | AR_Q_MISC_CBR_INCR_DIS0
);
502 value
= (qi
->tqi_readyTime
-
503 (ah
->config
.sw_beacon_response_time
-
504 ah
->config
.dma_beacon_response_time
) -
505 ah
->config
.additional_swba_backoff
) * 1024;
506 REG_WRITE(ah
, AR_QRDYTIMECFG(q
),
507 value
| AR_Q_RDYTIMECFG_EN
);
508 REG_SET_BIT(ah
, AR_DMISC(q
),
509 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL
<<
510 AR_D_MISC_ARB_LOCKOUT_CNTRL_S
));
512 REGWRITE_BUFFER_FLUSH(ah
);
515 case ATH9K_TX_QUEUE_PSPOLL
:
516 REG_SET_BIT(ah
, AR_QMISC(q
), AR_Q_MISC_CBR_INCR_DIS1
);
518 case ATH9K_TX_QUEUE_UAPSD
:
519 REG_SET_BIT(ah
, AR_DMISC(q
), AR_D_MISC_POST_FR_BKOFF_DIS
);
525 if (qi
->tqi_intFlags
& ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS
) {
526 REG_SET_BIT(ah
, AR_DMISC(q
),
527 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL
,
528 AR_D_MISC_ARB_LOCKOUT_CNTRL
) |
529 AR_D_MISC_POST_FR_BKOFF_DIS
);
532 if (AR_SREV_9300_20_OR_LATER(ah
))
533 REG_WRITE(ah
, AR_Q_DESC_CRCCHK
, AR_Q_DESC_CRCCHK_EN
);
535 if (qi
->tqi_qflags
& TXQ_FLAG_TXOKINT_ENABLE
)
536 ah
->txok_interrupt_mask
|= 1 << q
;
538 ah
->txok_interrupt_mask
&= ~(1 << q
);
539 if (qi
->tqi_qflags
& TXQ_FLAG_TXERRINT_ENABLE
)
540 ah
->txerr_interrupt_mask
|= 1 << q
;
542 ah
->txerr_interrupt_mask
&= ~(1 << q
);
543 if (qi
->tqi_qflags
& TXQ_FLAG_TXDESCINT_ENABLE
)
544 ah
->txdesc_interrupt_mask
|= 1 << q
;
546 ah
->txdesc_interrupt_mask
&= ~(1 << q
);
547 if (qi
->tqi_qflags
& TXQ_FLAG_TXEOLINT_ENABLE
)
548 ah
->txeol_interrupt_mask
|= 1 << q
;
550 ah
->txeol_interrupt_mask
&= ~(1 << q
);
551 if (qi
->tqi_qflags
& TXQ_FLAG_TXURNINT_ENABLE
)
552 ah
->txurn_interrupt_mask
|= 1 << q
;
554 ah
->txurn_interrupt_mask
&= ~(1 << q
);
555 ath9k_hw_set_txq_interrupts(ah
, qi
);
559 EXPORT_SYMBOL(ath9k_hw_resettxqueue
);
561 int ath9k_hw_rxprocdesc(struct ath_hw
*ah
, struct ath_desc
*ds
,
562 struct ath_rx_status
*rs
, u64 tsf
)
564 struct ar5416_desc ads
;
565 struct ar5416_desc
*adsp
= AR5416DESC(ds
);
568 if ((adsp
->ds_rxstatus8
& AR_RxDone
) == 0)
571 ads
.u
.rx
= adsp
->u
.rx
;
576 rs
->rs_datalen
= ads
.ds_rxstatus1
& AR_DataLen
;
577 rs
->rs_tstamp
= ads
.AR_RcvTimestamp
;
579 if (ads
.ds_rxstatus8
& AR_PostDelimCRCErr
) {
580 rs
->rs_rssi
= ATH9K_RSSI_BAD
;
581 rs
->rs_rssi_ctl0
= ATH9K_RSSI_BAD
;
582 rs
->rs_rssi_ctl1
= ATH9K_RSSI_BAD
;
583 rs
->rs_rssi_ctl2
= ATH9K_RSSI_BAD
;
584 rs
->rs_rssi_ext0
= ATH9K_RSSI_BAD
;
585 rs
->rs_rssi_ext1
= ATH9K_RSSI_BAD
;
586 rs
->rs_rssi_ext2
= ATH9K_RSSI_BAD
;
588 rs
->rs_rssi
= MS(ads
.ds_rxstatus4
, AR_RxRSSICombined
);
589 rs
->rs_rssi_ctl0
= MS(ads
.ds_rxstatus0
,
591 rs
->rs_rssi_ctl1
= MS(ads
.ds_rxstatus0
,
593 rs
->rs_rssi_ctl2
= MS(ads
.ds_rxstatus0
,
595 rs
->rs_rssi_ext0
= MS(ads
.ds_rxstatus4
,
597 rs
->rs_rssi_ext1
= MS(ads
.ds_rxstatus4
,
599 rs
->rs_rssi_ext2
= MS(ads
.ds_rxstatus4
,
602 if (ads
.ds_rxstatus8
& AR_RxKeyIdxValid
)
603 rs
->rs_keyix
= MS(ads
.ds_rxstatus8
, AR_KeyIdx
);
605 rs
->rs_keyix
= ATH9K_RXKEYIX_INVALID
;
607 rs
->rs_rate
= RXSTATUS_RATE(ah
, (&ads
));
608 rs
->rs_more
= (ads
.ds_rxstatus1
& AR_RxMore
) ? 1 : 0;
610 rs
->rs_isaggr
= (ads
.ds_rxstatus8
& AR_RxAggr
) ? 1 : 0;
612 (ads
.ds_rxstatus8
& AR_RxMoreAggr
) ? 1 : 0;
613 rs
->rs_antenna
= MS(ads
.ds_rxstatus3
, AR_RxAntenna
);
615 (ads
.ds_rxstatus3
& AR_GI
) ? ATH9K_RX_GI
: 0;
617 (ads
.ds_rxstatus3
& AR_2040
) ? ATH9K_RX_2040
: 0;
619 if (ads
.ds_rxstatus8
& AR_PreDelimCRCErr
)
620 rs
->rs_flags
|= ATH9K_RX_DELIM_CRC_PRE
;
621 if (ads
.ds_rxstatus8
& AR_PostDelimCRCErr
)
622 rs
->rs_flags
|= ATH9K_RX_DELIM_CRC_POST
;
623 if (ads
.ds_rxstatus8
& AR_DecryptBusyErr
)
624 rs
->rs_flags
|= ATH9K_RX_DECRYPT_BUSY
;
626 if ((ads
.ds_rxstatus8
& AR_RxFrameOK
) == 0) {
628 * Treat these errors as mutually exclusive to avoid spurious
629 * extra error reports from the hardware. If a CRC error is
630 * reported, then decryption and MIC errors are irrelevant,
631 * the frame is going to be dropped either way
633 if (ads
.ds_rxstatus8
& AR_CRCErr
)
634 rs
->rs_status
|= ATH9K_RXERR_CRC
;
635 else if (ads
.ds_rxstatus8
& AR_PHYErr
) {
636 rs
->rs_status
|= ATH9K_RXERR_PHY
;
637 phyerr
= MS(ads
.ds_rxstatus8
, AR_PHYErrCode
);
638 rs
->rs_phyerr
= phyerr
;
639 } else if (ads
.ds_rxstatus8
& AR_DecryptCRCErr
)
640 rs
->rs_status
|= ATH9K_RXERR_DECRYPT
;
641 else if (ads
.ds_rxstatus8
& AR_MichaelErr
)
642 rs
->rs_status
|= ATH9K_RXERR_MIC
;
644 if (ads
.ds_rxstatus8
& AR_KeyMiss
)
645 rs
->rs_status
|= ATH9K_RXERR_DECRYPT
;
650 EXPORT_SYMBOL(ath9k_hw_rxprocdesc
);
653 * This can stop or re-enables RX.
655 * If bool is set this will kill any frame which is currently being
656 * transferred between the MAC and baseband and also prevent any new
657 * frames from getting started.
659 bool ath9k_hw_setrxabort(struct ath_hw
*ah
, bool set
)
664 REG_SET_BIT(ah
, AR_DIAG_SW
,
665 (AR_DIAG_RX_DIS
| AR_DIAG_RX_ABORT
));
667 if (!ath9k_hw_wait(ah
, AR_OBS_BUS_1
, AR_OBS_BUS_1_RX_STATE
,
668 0, AH_WAIT_TIMEOUT
)) {
669 REG_CLR_BIT(ah
, AR_DIAG_SW
,
673 reg
= REG_READ(ah
, AR_OBS_BUS_1
);
674 ath_err(ath9k_hw_common(ah
),
675 "RX failed to go idle in 10 ms RXSM=0x%x\n",
681 REG_CLR_BIT(ah
, AR_DIAG_SW
,
682 (AR_DIAG_RX_DIS
| AR_DIAG_RX_ABORT
));
687 EXPORT_SYMBOL(ath9k_hw_setrxabort
);
689 void ath9k_hw_putrxbuf(struct ath_hw
*ah
, u32 rxdp
)
691 REG_WRITE(ah
, AR_RXDP
, rxdp
);
693 EXPORT_SYMBOL(ath9k_hw_putrxbuf
);
695 void ath9k_hw_startpcureceive(struct ath_hw
*ah
, bool is_scanning
)
697 ath9k_enable_mib_counters(ah
);
699 ath9k_ani_reset(ah
, is_scanning
);
701 REG_CLR_BIT(ah
, AR_DIAG_SW
, (AR_DIAG_RX_DIS
| AR_DIAG_RX_ABORT
));
703 EXPORT_SYMBOL(ath9k_hw_startpcureceive
);
705 void ath9k_hw_abortpcurecv(struct ath_hw
*ah
)
707 REG_SET_BIT(ah
, AR_DIAG_SW
, AR_DIAG_RX_ABORT
| AR_DIAG_RX_DIS
);
709 ath9k_hw_disable_mib_counters(ah
);
711 EXPORT_SYMBOL(ath9k_hw_abortpcurecv
);
713 bool ath9k_hw_stopdmarecv(struct ath_hw
*ah
)
715 #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
716 struct ath_common
*common
= ath9k_hw_common(ah
);
719 REG_WRITE(ah
, AR_CR
, AR_CR_RXD
);
721 /* Wait for rx enable bit to go low */
722 for (i
= AH_RX_STOP_DMA_TIMEOUT
/ AH_TIME_QUANTUM
; i
!= 0; i
--) {
723 if ((REG_READ(ah
, AR_CR
) & AR_CR_RXE
) == 0)
725 udelay(AH_TIME_QUANTUM
);
730 "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
731 AH_RX_STOP_DMA_TIMEOUT
/ 1000,
733 REG_READ(ah
, AR_DIAG_SW
));
739 #undef AH_RX_STOP_DMA_TIMEOUT
741 EXPORT_SYMBOL(ath9k_hw_stopdmarecv
);
743 int ath9k_hw_beaconq_setup(struct ath_hw
*ah
)
745 struct ath9k_tx_queue_info qi
;
747 memset(&qi
, 0, sizeof(qi
));
751 /* NB: don't enable any interrupts */
752 return ath9k_hw_setuptxqueue(ah
, ATH9K_TX_QUEUE_BEACON
, &qi
);
754 EXPORT_SYMBOL(ath9k_hw_beaconq_setup
);
756 bool ath9k_hw_intrpend(struct ath_hw
*ah
)
760 if (AR_SREV_9100(ah
))
763 host_isr
= REG_READ(ah
, AR_INTR_ASYNC_CAUSE
);
764 if ((host_isr
& AR_INTR_MAC_IRQ
) && (host_isr
!= AR_INTR_SPURIOUS
))
767 host_isr
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
768 if ((host_isr
& AR_INTR_SYNC_DEFAULT
)
769 && (host_isr
!= AR_INTR_SPURIOUS
))
774 EXPORT_SYMBOL(ath9k_hw_intrpend
);
776 void ath9k_hw_disable_interrupts(struct ath_hw
*ah
)
778 struct ath_common
*common
= ath9k_hw_common(ah
);
780 ath_dbg(common
, ATH_DBG_INTERRUPT
, "disable IER\n");
781 REG_WRITE(ah
, AR_IER
, AR_IER_DISABLE
);
782 (void) REG_READ(ah
, AR_IER
);
783 if (!AR_SREV_9100(ah
)) {
784 REG_WRITE(ah
, AR_INTR_ASYNC_ENABLE
, 0);
785 (void) REG_READ(ah
, AR_INTR_ASYNC_ENABLE
);
787 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
788 (void) REG_READ(ah
, AR_INTR_SYNC_ENABLE
);
791 EXPORT_SYMBOL(ath9k_hw_disable_interrupts
);
793 void ath9k_hw_enable_interrupts(struct ath_hw
*ah
)
795 struct ath_common
*common
= ath9k_hw_common(ah
);
797 if (!(ah
->imask
& ATH9K_INT_GLOBAL
))
800 ath_dbg(common
, ATH_DBG_INTERRUPT
, "enable IER\n");
801 REG_WRITE(ah
, AR_IER
, AR_IER_ENABLE
);
802 if (!AR_SREV_9100(ah
)) {
803 REG_WRITE(ah
, AR_INTR_ASYNC_ENABLE
,
805 REG_WRITE(ah
, AR_INTR_ASYNC_MASK
, AR_INTR_MAC_IRQ
);
808 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
,
809 AR_INTR_SYNC_DEFAULT
);
810 REG_WRITE(ah
, AR_INTR_SYNC_MASK
,
811 AR_INTR_SYNC_DEFAULT
);
813 ath_dbg(common
, ATH_DBG_INTERRUPT
, "AR_IMR 0x%x IER 0x%x\n",
814 REG_READ(ah
, AR_IMR
), REG_READ(ah
, AR_IER
));
816 EXPORT_SYMBOL(ath9k_hw_enable_interrupts
);
818 void ath9k_hw_set_interrupts(struct ath_hw
*ah
, enum ath9k_int ints
)
820 enum ath9k_int omask
= ah
->imask
;
822 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
823 struct ath_common
*common
= ath9k_hw_common(ah
);
825 if (!(ints
& ATH9K_INT_GLOBAL
))
826 ath9k_hw_disable_interrupts(ah
);
828 ath_dbg(common
, ATH_DBG_INTERRUPT
, "0x%x => 0x%x\n", omask
, ints
);
830 /* TODO: global int Ref count */
831 mask
= ints
& ATH9K_INT_COMMON
;
834 if (ints
& ATH9K_INT_TX
) {
835 if (ah
->config
.tx_intr_mitigation
)
836 mask
|= AR_IMR_TXMINTR
| AR_IMR_TXINTM
;
838 if (ah
->txok_interrupt_mask
)
840 if (ah
->txdesc_interrupt_mask
)
841 mask
|= AR_IMR_TXDESC
;
843 if (ah
->txerr_interrupt_mask
)
844 mask
|= AR_IMR_TXERR
;
845 if (ah
->txeol_interrupt_mask
)
846 mask
|= AR_IMR_TXEOL
;
848 if (ints
& ATH9K_INT_RX
) {
849 if (AR_SREV_9300_20_OR_LATER(ah
)) {
850 mask
|= AR_IMR_RXERR
| AR_IMR_RXOK_HP
;
851 if (ah
->config
.rx_intr_mitigation
) {
852 mask
&= ~AR_IMR_RXOK_LP
;
853 mask
|= AR_IMR_RXMINTR
| AR_IMR_RXINTM
;
855 mask
|= AR_IMR_RXOK_LP
;
858 if (ah
->config
.rx_intr_mitigation
)
859 mask
|= AR_IMR_RXMINTR
| AR_IMR_RXINTM
;
861 mask
|= AR_IMR_RXOK
| AR_IMR_RXDESC
;
863 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
))
864 mask
|= AR_IMR_GENTMR
;
867 if (ints
& (ATH9K_INT_BMISC
)) {
868 mask
|= AR_IMR_BCNMISC
;
869 if (ints
& ATH9K_INT_TIM
)
870 mask2
|= AR_IMR_S2_TIM
;
871 if (ints
& ATH9K_INT_DTIM
)
872 mask2
|= AR_IMR_S2_DTIM
;
873 if (ints
& ATH9K_INT_DTIMSYNC
)
874 mask2
|= AR_IMR_S2_DTIMSYNC
;
875 if (ints
& ATH9K_INT_CABEND
)
876 mask2
|= AR_IMR_S2_CABEND
;
877 if (ints
& ATH9K_INT_TSFOOR
)
878 mask2
|= AR_IMR_S2_TSFOOR
;
881 if (ints
& (ATH9K_INT_GTT
| ATH9K_INT_CST
)) {
882 mask
|= AR_IMR_BCNMISC
;
883 if (ints
& ATH9K_INT_GTT
)
884 mask2
|= AR_IMR_S2_GTT
;
885 if (ints
& ATH9K_INT_CST
)
886 mask2
|= AR_IMR_S2_CST
;
889 ath_dbg(common
, ATH_DBG_INTERRUPT
, "new IMR 0x%x\n", mask
);
890 REG_WRITE(ah
, AR_IMR
, mask
);
891 ah
->imrs2_reg
&= ~(AR_IMR_S2_TIM
| AR_IMR_S2_DTIM
| AR_IMR_S2_DTIMSYNC
|
892 AR_IMR_S2_CABEND
| AR_IMR_S2_CABTO
|
893 AR_IMR_S2_TSFOOR
| AR_IMR_S2_GTT
| AR_IMR_S2_CST
);
894 ah
->imrs2_reg
|= mask2
;
895 REG_WRITE(ah
, AR_IMR_S2
, ah
->imrs2_reg
);
897 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
898 if (ints
& ATH9K_INT_TIM_TIMER
)
899 REG_SET_BIT(ah
, AR_IMR_S5
, AR_IMR_S5_TIM_TIMER
);
901 REG_CLR_BIT(ah
, AR_IMR_S5
, AR_IMR_S5_TIM_TIMER
);
904 if (ints
& ATH9K_INT_GLOBAL
)
905 ath9k_hw_enable_interrupts(ah
);
909 EXPORT_SYMBOL(ath9k_hw_set_interrupts
);