?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
gma500: The MID devices have the register offset different
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / spi / spi_bfin5xx.c
blobf706dba165cf6812fc364271d3086424ce12aa36
1 /*
2 * Blackfin On-Chip SPI Driver
3 *
4 * Copyright 2004-2010 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
16 #include <linux/io.h>
17 #include <linux/ioport.h>
18 #include <linux/irq.h>
19 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi.h>
24 #include <linux/workqueue.h>
25
26 #include <asm/dma.h>
27 #include <asm/portmux.h>
28 #include <asm/bfin5xx_spi.h>
29 #include <asm/cacheflush.h>
30
31 #define DRV_NAME "bfin-spi"
32 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
33 #define DRV_DESC "Blackfin on-chip SPI Controller Driver"
34 #define DRV_VERSION "1.0"
35
36 MODULE_AUTHOR(DRV_AUTHOR);
37 MODULE_DESCRIPTION(DRV_DESC);
38 MODULE_LICENSE("GPL");
39
40 #define START_STATE ((void *)0)
41 #define RUNNING_STATE ((void *)1)
42 #define DONE_STATE ((void *)2)
43 #define ERROR_STATE ((void *)-1)
44
45 struct bfin_spi_master_data;
46
47 struct bfin_spi_transfer_ops {
48 void (*write) (struct bfin_spi_master_data *);
49 void (*read) (struct bfin_spi_master_data *);
50 void (*duplex) (struct bfin_spi_master_data *);
51 };
52
53 struct bfin_spi_master_data {
54 /* Driver model hookup */
55 struct platform_device *pdev;
56
57 /* SPI framework hookup */
58 struct spi_master *master;
59
60 /* Regs base of SPI controller */
61 void __iomem *regs_base;
62
63 /* Pin request list */
64 u16 *pin_req;
65
66 /* BFIN hookup */
67 struct bfin5xx_spi_master *master_info;
68
69 /* Driver message queue */
70 struct workqueue_struct *workqueue;
71 struct work_struct pump_messages;
72 spinlock_t lock;
73 struct list_head queue;
74 int busy;
75 bool running;
76
77 /* Message Transfer pump */
78 struct tasklet_struct pump_transfers;
79
80 /* Current message transfer state info */
81 struct spi_message *cur_msg;
82 struct spi_transfer *cur_transfer;
83 struct bfin_spi_slave_data *cur_chip;
84 size_t len_in_bytes;
85 size_t len;
86 void *tx;
87 void *tx_end;
88 void *rx;
89 void *rx_end;
90
91 /* DMA stuffs */
92 int dma_channel;
93 int dma_mapped;
94 int dma_requested;
95 dma_addr_t rx_dma;
96 dma_addr_t tx_dma;
97
98 int irq_requested;
99 int spi_irq;
100
101 size_t rx_map_len;
102 size_t tx_map_len;
103 u8 n_bytes;
104 u16 ctrl_reg;
105 u16 flag_reg;
106
107 int cs_change;
108 const struct bfin_spi_transfer_ops *ops;
109 };
110
111 struct bfin_spi_slave_data {
112 u16 ctl_reg;
113 u16 baud;
114 u16 flag;
115
116 u8 chip_select_num;
117 u8 enable_dma;
118 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
119 u32 cs_gpio;
120 u16 idle_tx_val;
121 u8 pio_interrupt; /* use spi data irq */
122 const struct bfin_spi_transfer_ops *ops;
123 };
124
125 #define DEFINE_SPI_REG(reg, off) \
126 static inline u16 read_##reg(struct bfin_spi_master_data *drv_data) \
127 { return bfin_read16(drv_data->regs_base + off); } \
128 static inline void write_##reg(struct bfin_spi_master_data *drv_data, u16 v) \
129 { bfin_write16(drv_data->regs_base + off, v); }
130
131 DEFINE_SPI_REG(CTRL, 0x00)
132 DEFINE_SPI_REG(FLAG, 0x04)
133 DEFINE_SPI_REG(STAT, 0x08)
134 DEFINE_SPI_REG(TDBR, 0x0C)
135 DEFINE_SPI_REG(RDBR, 0x10)
136 DEFINE_SPI_REG(BAUD, 0x14)
137 DEFINE_SPI_REG(SHAW, 0x18)
138
139 static void bfin_spi_enable(struct bfin_spi_master_data *drv_data)
140 {
141 u16 cr;
142
143 cr = read_CTRL(drv_data);
144 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
145 }
146
147 static void bfin_spi_disable(struct bfin_spi_master_data *drv_data)
148 {
149 u16 cr;
150
151 cr = read_CTRL(drv_data);
152 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
153 }
154
155 /* Caculate the SPI_BAUD register value based on input HZ */
156 static u16 hz_to_spi_baud(u32 speed_hz)
157 {
158 u_long sclk = get_sclk();
159 u16 spi_baud = (sclk / (2 * speed_hz));
160
161 if ((sclk % (2 * speed_hz)) > 0)
162 spi_baud++;
163
164 if (spi_baud < MIN_SPI_BAUD_VAL)
165 spi_baud = MIN_SPI_BAUD_VAL;
166
167 return spi_baud;
168 }
169
170 static int bfin_spi_flush(struct bfin_spi_master_data *drv_data)
171 {
172 unsigned long limit = loops_per_jiffy << 1;
173
174 /* wait for stop and clear stat */
175 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit)
176 cpu_relax();
177
178 write_STAT(drv_data, BIT_STAT_CLR);
179
180 return limit;
181 }
182
183 /* Chip select operation functions for cs_change flag */
184 static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip)
185 {
186 if (likely(chip->chip_select_num < MAX_CTRL_CS)) {
187 u16 flag = read_FLAG(drv_data);
188
189 flag &= ~chip->flag;
190
191 write_FLAG(drv_data, flag);
192 } else {
193 gpio_set_value(chip->cs_gpio, 0);
194 }
195 }
196
197 static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data,
198 struct bfin_spi_slave_data *chip)
199 {
200 if (likely(chip->chip_select_num < MAX_CTRL_CS)) {
201 u16 flag = read_FLAG(drv_data);
202
203 flag |= chip->flag;
204
205 write_FLAG(drv_data, flag);
206 } else {
207 gpio_set_value(chip->cs_gpio, 1);
208 }
209
210 /* Move delay here for consistency */
211 if (chip->cs_chg_udelay)
212 udelay(chip->cs_chg_udelay);
213 }
214
215 /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
216 static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data,
217 struct bfin_spi_slave_data *chip)
218 {
219 if (chip->chip_select_num < MAX_CTRL_CS) {
220 u16 flag = read_FLAG(drv_data);
221
222 flag |= (chip->flag >> 8);
223
224 write_FLAG(drv_data, flag);
225 }
226 }
227
228 static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data,
229 struct bfin_spi_slave_data *chip)
230 {
231 if (chip->chip_select_num < MAX_CTRL_CS) {
232 u16 flag = read_FLAG(drv_data);
233
234 flag &= ~(chip->flag >> 8);
235
236 write_FLAG(drv_data, flag);
237 }
238 }
239
240 /* stop controller and re-config current chip*/
241 static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data)
242 {
243 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
244
245 /* Clear status and disable clock */
246 write_STAT(drv_data, BIT_STAT_CLR);
247 bfin_spi_disable(drv_data);
248 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
249
250 SSYNC();
251
252 /* Load the registers */
253 write_CTRL(drv_data, chip->ctl_reg);
254 write_BAUD(drv_data, chip->baud);
255
256 bfin_spi_enable(drv_data);
257 bfin_spi_cs_active(drv_data, chip);
258 }
259
260 /* used to kick off transfer in rx mode and read unwanted RX data */
261 static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data)
262 {
263 (void) read_RDBR(drv_data);
264 }
265
266 static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data)
267 {
268 /* clear RXS (we check for RXS inside the loop) */
269 bfin_spi_dummy_read(drv_data);
270
271 while (drv_data->tx < drv_data->tx_end) {
272 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
273 /* wait until transfer finished.
274 checking SPIF or TXS may not guarantee transfer completion */
275 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
276 cpu_relax();
277 /* discard RX data and clear RXS */
278 bfin_spi_dummy_read(drv_data);
279 }
280 }
281
282 static void bfin_spi_u8_reader(struct bfin_spi_master_data *drv_data)
283 {
284 u16 tx_val = drv_data->cur_chip->idle_tx_val;
285
286 /* discard old RX data and clear RXS */
287 bfin_spi_dummy_read(drv_data);
288
289 while (drv_data->rx < drv_data->rx_end) {
290 write_TDBR(drv_data, tx_val);
291 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
292 cpu_relax();
293 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
294 }
295 }
296
297 static void bfin_spi_u8_duplex(struct bfin_spi_master_data *drv_data)
298 {
299 /* discard old RX data and clear RXS */
300 bfin_spi_dummy_read(drv_data);
301
302 while (drv_data->rx < drv_data->rx_end) {
303 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
304 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
305 cpu_relax();
306 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
307 }
308 }
309
310 static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = {
311 .write = bfin_spi_u8_writer,
312 .read = bfin_spi_u8_reader,
313 .duplex = bfin_spi_u8_duplex,
314 };
315
316 static void bfin_spi_u16_writer(struct bfin_spi_master_data *drv_data)
317 {
318 /* clear RXS (we check for RXS inside the loop) */
319 bfin_spi_dummy_read(drv_data);
320
321 while (drv_data->tx < drv_data->tx_end) {
322 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
323 drv_data->tx += 2;
324 /* wait until transfer finished.
325 checking SPIF or TXS may not guarantee transfer completion */
326 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
327 cpu_relax();
328 /* discard RX data and clear RXS */
329 bfin_spi_dummy_read(drv_data);
330 }
331 }
332
333 static void bfin_spi_u16_reader(struct bfin_spi_master_data *drv_data)
334 {
335 u16 tx_val = drv_data->cur_chip->idle_tx_val;
336
337 /* discard old RX data and clear RXS */
338 bfin_spi_dummy_read(drv_data);
339
340 while (drv_data->rx < drv_data->rx_end) {
341 write_TDBR(drv_data, tx_val);
342 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
343 cpu_relax();
344 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
345 drv_data->rx += 2;
346 }
347 }
348
349 static void bfin_spi_u16_duplex(struct bfin_spi_master_data *drv_data)
350 {
351 /* discard old RX data and clear RXS */
352 bfin_spi_dummy_read(drv_data);
353
354 while (drv_data->rx < drv_data->rx_end) {
355 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
356 drv_data->tx += 2;
357 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
358 cpu_relax();
359 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
360 drv_data->rx += 2;
361 }
362 }
363
364 static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = {
365 .write = bfin_spi_u16_writer,
366 .read = bfin_spi_u16_reader,
367 .duplex = bfin_spi_u16_duplex,
368 };
369
370 /* test if there is more transfer to be done */
371 static void *bfin_spi_next_transfer(struct bfin_spi_master_data *drv_data)
372 {
373 struct spi_message *msg = drv_data->cur_msg;
374 struct spi_transfer *trans = drv_data->cur_transfer;
375
376 /* Move to next transfer */
377 if (trans->transfer_list.next != &msg->transfers) {
378 drv_data->cur_transfer =
379 list_entry(trans->transfer_list.next,
380 struct spi_transfer, transfer_list);
381 return RUNNING_STATE;
382 } else
383 return DONE_STATE;
384 }
385
386 /*
387 * caller already set message->status;
388 * dma and pio irqs are blocked give finished message back
389 */
390 static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data)
391 {
392 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
393 struct spi_transfer *last_transfer;
394 unsigned long flags;
395 struct spi_message *msg;
396
397 spin_lock_irqsave(&drv_data->lock, flags);
398 msg = drv_data->cur_msg;
399 drv_data->cur_msg = NULL;
400 drv_data->cur_transfer = NULL;
401 drv_data->cur_chip = NULL;
402 queue_work(drv_data->workqueue, &drv_data->pump_messages);
403 spin_unlock_irqrestore(&drv_data->lock, flags);
404
405 last_transfer = list_entry(msg->transfers.prev,
406 struct spi_transfer, transfer_list);
407
408 msg->state = NULL;
409
410 if (!drv_data->cs_change)
411 bfin_spi_cs_deactive(drv_data, chip);
412
413 /* Not stop spi in autobuffer mode */
414 if (drv_data->tx_dma != 0xFFFF)
415 bfin_spi_disable(drv_data);
416
417 if (msg->complete)
418 msg->complete(msg->context);
419 }
420
421 /* spi data irq handler */
422 static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
423 {
424 struct bfin_spi_master_data *drv_data = dev_id;
425 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
426 struct spi_message *msg = drv_data->cur_msg;
427 int n_bytes = drv_data->n_bytes;
428 int loop = 0;
429
430 /* wait until transfer finished. */
431 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
432 cpu_relax();
433
434 if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
435 (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
436 /* last read */
437 if (drv_data->rx) {
438 dev_dbg(&drv_data->pdev->dev, "last read\n");
439 if (n_bytes % 2) {
440 u16 *buf = (u16 *)drv_data->rx;
441 for (loop = 0; loop < n_bytes / 2; loop++)
442 *buf++ = read_RDBR(drv_data);
443 } else {
444 u8 *buf = (u8 *)drv_data->rx;
445 for (loop = 0; loop < n_bytes; loop++)
446 *buf++ = read_RDBR(drv_data);
447 }
448 drv_data->rx += n_bytes;
449 }
450
451 msg->actual_length += drv_data->len_in_bytes;
452 if (drv_data->cs_change)
453 bfin_spi_cs_deactive(drv_data, chip);
454 /* Move to next transfer */
455 msg->state = bfin_spi_next_transfer(drv_data);
456
457 disable_irq_nosync(drv_data->spi_irq);
458
459 /* Schedule transfer tasklet */
460 tasklet_schedule(&drv_data->pump_transfers);
461 return IRQ_HANDLED;
462 }
463
464 if (drv_data->rx && drv_data->tx) {
465 /* duplex */
466 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
467 if (n_bytes % 2) {
468 u16 *buf = (u16 *)drv_data->rx;
469 u16 *buf2 = (u16 *)drv_data->tx;
470 for (loop = 0; loop < n_bytes / 2; loop++) {
471 *buf++ = read_RDBR(drv_data);
472 write_TDBR(drv_data, *buf2++);
473 }
474 } else {
475 u8 *buf = (u8 *)drv_data->rx;
476 u8 *buf2 = (u8 *)drv_data->tx;
477 for (loop = 0; loop < n_bytes; loop++) {
478 *buf++ = read_RDBR(drv_data);
479 write_TDBR(drv_data, *buf2++);
480 }
481 }
482 } else if (drv_data->rx) {
483 /* read */
484 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
485 if (n_bytes % 2) {
486 u16 *buf = (u16 *)drv_data->rx;
487 for (loop = 0; loop < n_bytes / 2; loop++) {
488 *buf++ = read_RDBR(drv_data);
489 write_TDBR(drv_data, chip->idle_tx_val);
490 }
491 } else {
492 u8 *buf = (u8 *)drv_data->rx;
493 for (loop = 0; loop < n_bytes; loop++) {
494 *buf++ = read_RDBR(drv_data);
495 write_TDBR(drv_data, chip->idle_tx_val);
496 }
497 }
498 } else if (drv_data->tx) {
499 /* write */
500 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
501 if (n_bytes % 2) {
502 u16 *buf = (u16 *)drv_data->tx;
503 for (loop = 0; loop < n_bytes / 2; loop++) {
504 read_RDBR(drv_data);
505 write_TDBR(drv_data, *buf++);
506 }
507 } else {
508 u8 *buf = (u8 *)drv_data->tx;
509 for (loop = 0; loop < n_bytes; loop++) {
510 read_RDBR(drv_data);
511 write_TDBR(drv_data, *buf++);
512 }
513 }
514 }
515
516 if (drv_data->tx)
517 drv_data->tx += n_bytes;
518 if (drv_data->rx)
519 drv_data->rx += n_bytes;
520
521 return IRQ_HANDLED;
522 }
523
524 static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
525 {
526 struct bfin_spi_master_data *drv_data = dev_id;
527 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
528 struct spi_message *msg = drv_data->cur_msg;
529 unsigned long timeout;
530 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
531 u16 spistat = read_STAT(drv_data);
532
533 dev_dbg(&drv_data->pdev->dev,
534 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
535 dmastat, spistat);
536
537 if (drv_data->rx != NULL) {
538 u16 cr = read_CTRL(drv_data);
539 /* discard old RX data and clear RXS */
540 bfin_spi_dummy_read(drv_data);
541 write_CTRL(drv_data, cr & ~BIT_CTL_ENABLE); /* Disable SPI */
542 write_CTRL(drv_data, cr & ~BIT_CTL_TIMOD); /* Restore State */
543 write_STAT(drv_data, BIT_STAT_CLR); /* Clear Status */
544 }
545
546 clear_dma_irqstat(drv_data->dma_channel);
547
548 /*
549 * wait for the last transaction shifted out. HRM states:
550 * at this point there may still be data in the SPI DMA FIFO waiting
551 * to be transmitted ... software needs to poll TXS in the SPI_STAT
552 * register until it goes low for 2 successive reads
553 */
554 if (drv_data->tx != NULL) {
555 while ((read_STAT(drv_data) & BIT_STAT_TXS) ||
556 (read_STAT(drv_data) & BIT_STAT_TXS))
557 cpu_relax();
558 }
559
560 dev_dbg(&drv_data->pdev->dev,
561 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
562 dmastat, read_STAT(drv_data));
563
564 timeout = jiffies + HZ;
565 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
566 if (!time_before(jiffies, timeout)) {
567 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
568 break;
569 } else
570 cpu_relax();
571
572 if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) {
573 msg->state = ERROR_STATE;
574 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
575 } else {
576 msg->actual_length += drv_data->len_in_bytes;
577
578 if (drv_data->cs_change)
579 bfin_spi_cs_deactive(drv_data, chip);
580
581 /* Move to next transfer */
582 msg->state = bfin_spi_next_transfer(drv_data);
583 }
584
585 /* Schedule transfer tasklet */
586 tasklet_schedule(&drv_data->pump_transfers);
587
588 /* free the irq handler before next transfer */
589 dev_dbg(&drv_data->pdev->dev,
590 "disable dma channel irq%d\n",
591 drv_data->dma_channel);
592 dma_disable_irq_nosync(drv_data->dma_channel);
593
594 return IRQ_HANDLED;
595 }
596
597 static void bfin_spi_pump_transfers(unsigned long data)
598 {
599 struct bfin_spi_master_data *drv_data = (struct bfin_spi_master_data *)data;
600 struct spi_message *message = NULL;
601 struct spi_transfer *transfer = NULL;
602 struct spi_transfer *previous = NULL;
603 struct bfin_spi_slave_data *chip = NULL;
604 unsigned int bits_per_word;
605 u16 cr, cr_width, dma_width, dma_config;
606 u32 tranf_success = 1;
607 u8 full_duplex = 0;
608
609 /* Get current state information */
610 message = drv_data->cur_msg;
611 transfer = drv_data->cur_transfer;
612 chip = drv_data->cur_chip;
613
614 /*
615 * if msg is error or done, report it back using complete() callback
616 */
617
618 /* Handle for abort */
619 if (message->state == ERROR_STATE) {
620 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
621 message->status = -EIO;
622 bfin_spi_giveback(drv_data);
623 return;
624 }
625
626 /* Handle end of message */
627 if (message->state == DONE_STATE) {
628 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
629 message->status = 0;
630 bfin_spi_giveback(drv_data);
631 return;
632 }
633
634 /* Delay if requested at end of transfer */
635 if (message->state == RUNNING_STATE) {
636 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
637 previous = list_entry(transfer->transfer_list.prev,
638 struct spi_transfer, transfer_list);
639 if (previous->delay_usecs)
640 udelay(previous->delay_usecs);
641 }
642
643 /* Flush any existing transfers that may be sitting in the hardware */
644 if (bfin_spi_flush(drv_data) == 0) {
645 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
646 message->status = -EIO;
647 bfin_spi_giveback(drv_data);
648 return;
649 }
650
651 if (transfer->len == 0) {
652 /* Move to next transfer of this msg */
653 message->state = bfin_spi_next_transfer(drv_data);
654 /* Schedule next transfer tasklet */
655 tasklet_schedule(&drv_data->pump_transfers);
656 return;
657 }
658
659 if (transfer->tx_buf != NULL) {
660 drv_data->tx = (void *)transfer->tx_buf;
661 drv_data->tx_end = drv_data->tx + transfer->len;
662 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
663 transfer->tx_buf, drv_data->tx_end);
664 } else {
665 drv_data->tx = NULL;
666 }
667
668 if (transfer->rx_buf != NULL) {
669 full_duplex = transfer->tx_buf != NULL;
670 drv_data->rx = transfer->rx_buf;
671 drv_data->rx_end = drv_data->rx + transfer->len;
672 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
673 transfer->rx_buf, drv_data->rx_end);
674 } else {
675 drv_data->rx = NULL;
676 }
677
678 drv_data->rx_dma = transfer->rx_dma;
679 drv_data->tx_dma = transfer->tx_dma;
680 drv_data->len_in_bytes = transfer->len;
681 drv_data->cs_change = transfer->cs_change;
682
683 /* Bits per word setup */
684 bits_per_word = transfer->bits_per_word ? : message->spi->bits_per_word;
685 if ((bits_per_word > 0) && (bits_per_word % 16 == 0)) {
686 drv_data->n_bytes = bits_per_word/8;
687 drv_data->len = (transfer->len) >> 1;
688 cr_width = BIT_CTL_WORDSIZE;
689 drv_data->ops = &bfin_bfin_spi_transfer_ops_u16;
690 } else if ((bits_per_word > 0) && (bits_per_word % 8 == 0)) {
691 drv_data->n_bytes = bits_per_word/8;
692 drv_data->len = transfer->len;
693 cr_width = 0;
694 drv_data->ops = &bfin_bfin_spi_transfer_ops_u8;
695 } else {
696 dev_err(&drv_data->pdev->dev, "transfer: unsupported bits_per_word\n");
697 message->status = -EINVAL;
698 bfin_spi_giveback(drv_data);
699 return;
700 }
701 cr = read_CTRL(drv_data) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
702 cr |= cr_width;
703 write_CTRL(drv_data, cr);
704
705 dev_dbg(&drv_data->pdev->dev,
706 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
707 drv_data->ops, chip->ops, &bfin_bfin_spi_transfer_ops_u8);
708
709 message->state = RUNNING_STATE;
710 dma_config = 0;
711
712 /* Speed setup (surely valid because already checked) */
713 if (transfer->speed_hz)
714 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
715 else
716 write_BAUD(drv_data, chip->baud);
717
718 write_STAT(drv_data, BIT_STAT_CLR);
719 bfin_spi_cs_active(drv_data, chip);
720
721 dev_dbg(&drv_data->pdev->dev,
722 "now pumping a transfer: width is %d, len is %d\n",
723 cr_width, transfer->len);
724
725 /*
726 * Try to map dma buffer and do a dma transfer. If successful use,
727 * different way to r/w according to the enable_dma settings and if
728 * we are not doing a full duplex transfer (since the hardware does
729 * not support full duplex DMA transfers).
730 */
731 if (!full_duplex && drv_data->cur_chip->enable_dma
732 && drv_data->len > 6) {
733
734 unsigned long dma_start_addr, flags;
735
736 disable_dma(drv_data->dma_channel);
737 clear_dma_irqstat(drv_data->dma_channel);
738
739 /* config dma channel */
740 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
741 set_dma_x_count(drv_data->dma_channel, drv_data->len);
742 if (cr_width == BIT_CTL_WORDSIZE) {
743 set_dma_x_modify(drv_data->dma_channel, 2);
744 dma_width = WDSIZE_16;
745 } else {
746 set_dma_x_modify(drv_data->dma_channel, 1);
747 dma_width = WDSIZE_8;
748 }
749
750 /* poll for SPI completion before start */
751 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
752 cpu_relax();
753
754 /* dirty hack for autobuffer DMA mode */
755 if (drv_data->tx_dma == 0xFFFF) {
756 dev_dbg(&drv_data->pdev->dev,
757 "doing autobuffer DMA out.\n");
758
759 /* no irq in autobuffer mode */
760 dma_config =
761 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
762 set_dma_config(drv_data->dma_channel, dma_config);
763 set_dma_start_addr(drv_data->dma_channel,
764 (unsigned long)drv_data->tx);
765 enable_dma(drv_data->dma_channel);
766
767 /* start SPI transfer */
768 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
769
770 /* just return here, there can only be one transfer
771 * in this mode
772 */
773 message->status = 0;
774 bfin_spi_giveback(drv_data);
775 return;
776 }
777
778 /* In dma mode, rx or tx must be NULL in one transfer */
779 dma_config = (RESTART | dma_width | DI_EN);
780 if (drv_data->rx != NULL) {
781 /* set transfer mode, and enable SPI */
782 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
783 drv_data->rx, drv_data->len_in_bytes);
784
785 /* invalidate caches, if needed */
786 if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
787 invalidate_dcache_range((unsigned long) drv_data->rx,
788 (unsigned long) (drv_data->rx +
789 drv_data->len_in_bytes));
790
791 dma_config |= WNR;
792 dma_start_addr = (unsigned long)drv_data->rx;
793 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
794
795 } else if (drv_data->tx != NULL) {
796 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
797
798 /* flush caches, if needed */
799 if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
800 flush_dcache_range((unsigned long) drv_data->tx,
801 (unsigned long) (drv_data->tx +
802 drv_data->len_in_bytes));
803
804 dma_start_addr = (unsigned long)drv_data->tx;
805 cr |= BIT_CTL_TIMOD_DMA_TX;
806
807 } else
808 BUG();
809
810 /* oh man, here there be monsters ... and i dont mean the
811 * fluffy cute ones from pixar, i mean the kind that'll eat
812 * your data, kick your dog, and love it all. do *not* try
813 * and change these lines unless you (1) heavily test DMA
814 * with SPI flashes on a loaded system (e.g. ping floods),
815 * (2) know just how broken the DMA engine interaction with
816 * the SPI peripheral is, and (3) have someone else to blame
817 * when you screw it all up anyways.
818 */
819 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
820 set_dma_config(drv_data->dma_channel, dma_config);
821 local_irq_save(flags);
822 SSYNC();
823 write_CTRL(drv_data, cr);
824 enable_dma(drv_data->dma_channel);
825 dma_enable_irq(drv_data->dma_channel);
826 local_irq_restore(flags);
827
828 return;
829 }
830
831 /*
832 * We always use SPI_WRITE mode (transfer starts with TDBR write).
833 * SPI_READ mode (transfer starts with RDBR read) seems to have
834 * problems with setting up the output value in TDBR prior to the
835 * start of the transfer.
836 */
837 write_CTRL(drv_data, cr | BIT_CTL_TXMOD);
838
839 if (chip->pio_interrupt) {
840 /* SPI irq should have been disabled by now */
841
842 /* discard old RX data and clear RXS */
843 bfin_spi_dummy_read(drv_data);
844
845 /* start transfer */
846 if (drv_data->tx == NULL)
847 write_TDBR(drv_data, chip->idle_tx_val);
848 else {
849 int loop;
850 if (bits_per_word % 16 == 0) {
851 u16 *buf = (u16 *)drv_data->tx;
852 for (loop = 0; loop < bits_per_word / 16;
853 loop++) {
854 write_TDBR(drv_data, *buf++);
855 }
856 } else if (bits_per_word % 8 == 0) {
857 u8 *buf = (u8 *)drv_data->tx;
858 for (loop = 0; loop < bits_per_word / 8; loop++)
859 write_TDBR(drv_data, *buf++);
860 }
861
862 drv_data->tx += drv_data->n_bytes;
863 }
864
865 /* once TDBR is empty, interrupt is triggered */
866 enable_irq(drv_data->spi_irq);
867 return;
868 }
869
870 /* IO mode */
871 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
872
873 if (full_duplex) {
874 /* full duplex mode */
875 BUG_ON((drv_data->tx_end - drv_data->tx) !=
876 (drv_data->rx_end - drv_data->rx));
877 dev_dbg(&drv_data->pdev->dev,
878 "IO duplex: cr is 0x%x\n", cr);
879
880 drv_data->ops->duplex(drv_data);
881
882 if (drv_data->tx != drv_data->tx_end)
883 tranf_success = 0;
884 } else if (drv_data->tx != NULL) {
885 /* write only half duplex */
886 dev_dbg(&drv_data->pdev->dev,
887 "IO write: cr is 0x%x\n", cr);
888
889 drv_data->ops->write(drv_data);
890
891 if (drv_data->tx != drv_data->tx_end)
892 tranf_success = 0;
893 } else if (drv_data->rx != NULL) {
894 /* read only half duplex */
895 dev_dbg(&drv_data->pdev->dev,
896 "IO read: cr is 0x%x\n", cr);
897
898 drv_data->ops->read(drv_data);
899 if (drv_data->rx != drv_data->rx_end)
900 tranf_success = 0;
901 }
902
903 if (!tranf_success) {
904 dev_dbg(&drv_data->pdev->dev,
905 "IO write error!\n");
906 message->state = ERROR_STATE;
907 } else {
908 /* Update total byte transferred */
909 message->actual_length += drv_data->len_in_bytes;
910 /* Move to next transfer of this msg */
911 message->state = bfin_spi_next_transfer(drv_data);
912 if (drv_data->cs_change)
913 bfin_spi_cs_deactive(drv_data, chip);
914 }
915
916 /* Schedule next transfer tasklet */
917 tasklet_schedule(&drv_data->pump_transfers);
918 }
919
920 /* pop a msg from queue and kick off real transfer */
921 static void bfin_spi_pump_messages(struct work_struct *work)
922 {
923 struct bfin_spi_master_data *drv_data;
924 unsigned long flags;
925
926 drv_data = container_of(work, struct bfin_spi_master_data, pump_messages);
927
928 /* Lock queue and check for queue work */
929 spin_lock_irqsave(&drv_data->lock, flags);
930 if (list_empty(&drv_data->queue) || !drv_data->running) {
931 /* pumper kicked off but no work to do */
932 drv_data->busy = 0;
933 spin_unlock_irqrestore(&drv_data->lock, flags);
934 return;
935 }
936
937 /* Make sure we are not already running a message */
938 if (drv_data->cur_msg) {
939 spin_unlock_irqrestore(&drv_data->lock, flags);
940 return;
941 }
942
943 /* Extract head of queue */
944 drv_data->cur_msg = list_entry(drv_data->queue.next,
945 struct spi_message, queue);
946
947 /* Setup the SSP using the per chip configuration */
948 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
949 bfin_spi_restore_state(drv_data);
950
951 list_del_init(&drv_data->cur_msg->queue);
952
953 /* Initial message state */
954 drv_data->cur_msg->state = START_STATE;
955 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
956 struct spi_transfer, transfer_list);
957
958 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
959 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
960 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
961 drv_data->cur_chip->ctl_reg);
962
963 dev_dbg(&drv_data->pdev->dev,
964 "the first transfer len is %d\n",
965 drv_data->cur_transfer->len);
966
967 /* Mark as busy and launch transfers */
968 tasklet_schedule(&drv_data->pump_transfers);
969
970 drv_data->busy = 1;
971 spin_unlock_irqrestore(&drv_data->lock, flags);
972 }
973
974 /*
975 * got a msg to transfer, queue it in drv_data->queue.
976 * And kick off message pumper
977 */
978 static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
979 {
980 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
981 unsigned long flags;
982
983 spin_lock_irqsave(&drv_data->lock, flags);
984
985 if (!drv_data->running) {
986 spin_unlock_irqrestore(&drv_data->lock, flags);
987 return -ESHUTDOWN;
988 }
989
990 msg->actual_length = 0;
991 msg->status = -EINPROGRESS;
992 msg->state = START_STATE;
993
994 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
995 list_add_tail(&msg->queue, &drv_data->queue);
996
997 if (drv_data->running && !drv_data->busy)
998 queue_work(drv_data->workqueue, &drv_data->pump_messages);
999
1000 spin_unlock_irqrestore(&drv_data->lock, flags);
1001
1002 return 0;
1003 }
1004
1005 #define MAX_SPI_SSEL 7
1006
1007 static u16 ssel[][MAX_SPI_SSEL] = {
1008 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1009 P_SPI0_SSEL4, P_SPI0_SSEL5,
1010 P_SPI0_SSEL6, P_SPI0_SSEL7},
1011
1012 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1013 P_SPI1_SSEL4, P_SPI1_SSEL5,
1014 P_SPI1_SSEL6, P_SPI1_SSEL7},
1015
1016 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1017 P_SPI2_SSEL4, P_SPI2_SSEL5,
1018 P_SPI2_SSEL6, P_SPI2_SSEL7},
1019 };
1020
1021 /* setup for devices (may be called multiple times -- not just first setup) */
1022 static int bfin_spi_setup(struct spi_device *spi)
1023 {
1024 struct bfin5xx_spi_chip *chip_info;
1025 struct bfin_spi_slave_data *chip = NULL;
1026 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
1027 u16 bfin_ctl_reg;
1028 int ret = -EINVAL;
1029
1030 /* Only alloc (or use chip_info) on first setup */
1031 chip_info = NULL;
1032 chip = spi_get_ctldata(spi);
1033 if (chip == NULL) {
1034 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1035 if (!chip) {
1036 dev_err(&spi->dev, "cannot allocate chip data\n");
1037 ret = -ENOMEM;
1038 goto error;
1039 }
1040
1041 chip->enable_dma = 0;
1042 chip_info = spi->controller_data;
1043 }
1044
1045 /* Let people set non-standard bits directly */
1046 bfin_ctl_reg = BIT_CTL_OPENDRAIN | BIT_CTL_EMISO |
1047 BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ;
1048
1049 /* chip_info isn't always needed */
1050 if (chip_info) {
1051 /* Make sure people stop trying to set fields via ctl_reg
1052 * when they should actually be using common SPI framework.
1053 * Currently we let through: WOM EMISO PSSE GM SZ.
1054 * Not sure if a user actually needs/uses any of these,
1055 * but let's assume (for now) they do.
1056 */
1057 if (chip_info->ctl_reg & ~bfin_ctl_reg) {
1058 dev_err(&spi->dev, "do not set bits in ctl_reg "
1059 "that the SPI framework manages\n");
1060 goto error;
1061 }
1062 chip->enable_dma = chip_info->enable_dma != 0
1063 && drv_data->master_info->enable_dma;
1064 chip->ctl_reg = chip_info->ctl_reg;
1065 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1066 chip->idle_tx_val = chip_info->idle_tx_val;
1067 chip->pio_interrupt = chip_info->pio_interrupt;
1068 spi->bits_per_word = chip_info->bits_per_word;
1069 } else {
1070 /* force a default base state */
1071 chip->ctl_reg &= bfin_ctl_reg;
1072 }
1073
1074 if (spi->bits_per_word % 8) {
1075 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1076 spi->bits_per_word);
1077 goto error;
1078 }
1079
1080 /* translate common spi framework into our register */
1081 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1082 dev_err(&spi->dev, "unsupported spi modes detected\n");
1083 goto error;
1084 }
1085 if (spi->mode & SPI_CPOL)
1086 chip->ctl_reg |= BIT_CTL_CPOL;
1087 if (spi->mode & SPI_CPHA)
1088 chip->ctl_reg |= BIT_CTL_CPHA;
1089 if (spi->mode & SPI_LSB_FIRST)
1090 chip->ctl_reg |= BIT_CTL_LSBF;
1091 /* we dont support running in slave mode (yet?) */
1092 chip->ctl_reg |= BIT_CTL_MASTER;
1093
1094 /*
1095 * Notice: for blackfin, the speed_hz is the value of register
1096 * SPI_BAUD, not the real baudrate
1097 */
1098 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1099 chip->chip_select_num = spi->chip_select;
1100 if (chip->chip_select_num < MAX_CTRL_CS) {
1101 if (!(spi->mode & SPI_CPHA))
1102 dev_warn(&spi->dev, "Warning: SPI CPHA not set:"
1103 " Slave Select not under software control!\n"
1104 " See Documentation/blackfin/bfin-spi-notes.txt");
1105
1106 chip->flag = (1 << spi->chip_select) << 8;
1107 } else
1108 chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS;
1109
1110 if (chip->enable_dma && chip->pio_interrupt) {
1111 dev_err(&spi->dev, "enable_dma is set, "
1112 "do not set pio_interrupt\n");
1113 goto error;
1114 }
1115 /*
1116 * if any one SPI chip is registered and wants DMA, request the
1117 * DMA channel for it
1118 */
1119 if (chip->enable_dma && !drv_data->dma_requested) {
1120 /* register dma irq handler */
1121 ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
1122 if (ret) {
1123 dev_err(&spi->dev,
1124 "Unable to request BlackFin SPI DMA channel\n");
1125 goto error;
1126 }
1127 drv_data->dma_requested = 1;
1128
1129 ret = set_dma_callback(drv_data->dma_channel,
1130 bfin_spi_dma_irq_handler, drv_data);
1131 if (ret) {
1132 dev_err(&spi->dev, "Unable to set dma callback\n");
1133 goto error;
1134 }
1135 dma_disable_irq(drv_data->dma_channel);
1136 }
1137
1138 if (chip->pio_interrupt && !drv_data->irq_requested) {
1139 ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
1140 IRQF_DISABLED, "BFIN_SPI", drv_data);
1141 if (ret) {
1142 dev_err(&spi->dev, "Unable to register spi IRQ\n");
1143 goto error;
1144 }
1145 drv_data->irq_requested = 1;
1146 /* we use write mode, spi irq has to be disabled here */
1147 disable_irq(drv_data->spi_irq);
1148 }
1149
1150 if (chip->chip_select_num >= MAX_CTRL_CS) {
1151 /* Only request on first setup */
1152 if (spi_get_ctldata(spi) == NULL) {
1153 ret = gpio_request(chip->cs_gpio, spi->modalias);
1154 if (ret) {
1155 dev_err(&spi->dev, "gpio_request() error\n");
1156 goto pin_error;
1157 }
1158 gpio_direction_output(chip->cs_gpio, 1);
1159 }
1160 }
1161
1162 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1163 spi->modalias, spi->bits_per_word, chip->enable_dma);
1164 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1165 chip->ctl_reg, chip->flag);
1166
1167 spi_set_ctldata(spi, chip);
1168
1169 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1170 if (chip->chip_select_num < MAX_CTRL_CS) {
1171 ret = peripheral_request(ssel[spi->master->bus_num]
1172 [chip->chip_select_num-1], spi->modalias);
1173 if (ret) {
1174 dev_err(&spi->dev, "peripheral_request() error\n");
1175 goto pin_error;
1176 }
1177 }
1178
1179 bfin_spi_cs_enable(drv_data, chip);
1180 bfin_spi_cs_deactive(drv_data, chip);
1181
1182 return 0;
1183
1184 pin_error:
1185 if (chip->chip_select_num >= MAX_CTRL_CS)
1186 gpio_free(chip->cs_gpio);
1187 else
1188 peripheral_free(ssel[spi->master->bus_num]
1189 [chip->chip_select_num - 1]);
1190 error:
1191 if (chip) {
1192 if (drv_data->dma_requested)
1193 free_dma(drv_data->dma_channel);
1194 drv_data->dma_requested = 0;
1195
1196 kfree(chip);
1197 /* prevent free 'chip' twice */
1198 spi_set_ctldata(spi, NULL);
1199 }
1200
1201 return ret;
1202 }
1203
1204 /*
1205 * callback for spi framework.
1206 * clean driver specific data
1207 */
1208 static void bfin_spi_cleanup(struct spi_device *spi)
1209 {
1210 struct bfin_spi_slave_data *chip = spi_get_ctldata(spi);
1211 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
1212
1213 if (!chip)
1214 return;
1215
1216 if (chip->chip_select_num < MAX_CTRL_CS) {
1217 peripheral_free(ssel[spi->master->bus_num]
1218 [chip->chip_select_num-1]);
1219 bfin_spi_cs_disable(drv_data, chip);
1220 } else
1221 gpio_free(chip->cs_gpio);
1222
1223 kfree(chip);
1224 /* prevent free 'chip' twice */
1225 spi_set_ctldata(spi, NULL);
1226 }
1227
1228 static inline int bfin_spi_init_queue(struct bfin_spi_master_data *drv_data)
1229 {
1230 INIT_LIST_HEAD(&drv_data->queue);
1231 spin_lock_init(&drv_data->lock);
1232
1233 drv_data->running = false;
1234 drv_data->busy = 0;
1235
1236 /* init transfer tasklet */
1237 tasklet_init(&drv_data->pump_transfers,
1238 bfin_spi_pump_transfers, (unsigned long)drv_data);
1239
1240 /* init messages workqueue */
1241 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1242 drv_data->workqueue = create_singlethread_workqueue(
1243 dev_name(drv_data->master->dev.parent));
1244 if (drv_data->workqueue == NULL)
1245 return -EBUSY;
1246
1247 return 0;
1248 }
1249
1250 static inline int bfin_spi_start_queue(struct bfin_spi_master_data *drv_data)
1251 {
1252 unsigned long flags;
1253
1254 spin_lock_irqsave(&drv_data->lock, flags);
1255
1256 if (drv_data->running || drv_data->busy) {
1257 spin_unlock_irqrestore(&drv_data->lock, flags);
1258 return -EBUSY;
1259 }
1260
1261 drv_data->running = true;
1262 drv_data->cur_msg = NULL;
1263 drv_data->cur_transfer = NULL;
1264 drv_data->cur_chip = NULL;
1265 spin_unlock_irqrestore(&drv_data->lock, flags);
1266
1267 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1268
1269 return 0;
1270 }
1271
1272 static inline int bfin_spi_stop_queue(struct bfin_spi_master_data *drv_data)
1273 {
1274 unsigned long flags;
1275 unsigned limit = 500;
1276 int status = 0;
1277
1278 spin_lock_irqsave(&drv_data->lock, flags);
1279
1280 /*
1281 * This is a bit lame, but is optimized for the common execution path.
1282 * A wait_queue on the drv_data->busy could be used, but then the common
1283 * execution path (pump_messages) would be required to call wake_up or
1284 * friends on every SPI message. Do this instead
1285 */
1286 drv_data->running = false;
1287 while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) {
1288 spin_unlock_irqrestore(&drv_data->lock, flags);
1289 msleep(10);
1290 spin_lock_irqsave(&drv_data->lock, flags);
1291 }
1292
1293 if (!list_empty(&drv_data->queue) || drv_data->busy)
1294 status = -EBUSY;
1295
1296 spin_unlock_irqrestore(&drv_data->lock, flags);
1297
1298 return status;
1299 }
1300
1301 static inline int bfin_spi_destroy_queue(struct bfin_spi_master_data *drv_data)
1302 {
1303 int status;
1304
1305 status = bfin_spi_stop_queue(drv_data);
1306 if (status != 0)
1307 return status;
1308
1309 destroy_workqueue(drv_data->workqueue);
1310
1311 return 0;
1312 }
1313
1314 static int __init bfin_spi_probe(struct platform_device *pdev)
1315 {
1316 struct device *dev = &pdev->dev;
1317 struct bfin5xx_spi_master *platform_info;
1318 struct spi_master *master;
1319 struct bfin_spi_master_data *drv_data;
1320 struct resource *res;
1321 int status = 0;
1322
1323 platform_info = dev->platform_data;
1324
1325 /* Allocate master with space for drv_data */
1326 master = spi_alloc_master(dev, sizeof(*drv_data));
1327 if (!master) {
1328 dev_err(&pdev->dev, "can not alloc spi_master\n");
1329 return -ENOMEM;
1330 }
1331
1332 drv_data = spi_master_get_devdata(master);
1333 drv_data->master = master;
1334 drv_data->master_info = platform_info;
1335 drv_data->pdev = pdev;
1336 drv_data->pin_req = platform_info->pin_req;
1337
1338 /* the spi->mode bits supported by this driver: */
1339 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1340
1341 master->bus_num = pdev->id;
1342 master->num_chipselect = platform_info->num_chipselect;
1343 master->cleanup = bfin_spi_cleanup;
1344 master->setup = bfin_spi_setup;
1345 master->transfer = bfin_spi_transfer;
1346
1347 /* Find and map our resources */
1348 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1349 if (res == NULL) {
1350 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1351 status = -ENOENT;
1352 goto out_error_get_res;
1353 }
1354
1355 drv_data->regs_base = ioremap(res->start, resource_size(res));
1356 if (drv_data->regs_base == NULL) {
1357 dev_err(dev, "Cannot map IO\n");
1358 status = -ENXIO;
1359 goto out_error_ioremap;
1360 }
1361
1362 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1363 if (res == NULL) {
1364 dev_err(dev, "No DMA channel specified\n");
1365 status = -ENOENT;
1366 goto out_error_free_io;
1367 }
1368 drv_data->dma_channel = res->start;
1369
1370 drv_data->spi_irq = platform_get_irq(pdev, 0);
1371 if (drv_data->spi_irq < 0) {
1372 dev_err(dev, "No spi pio irq specified\n");
1373 status = -ENOENT;
1374 goto out_error_free_io;
1375 }
1376
1377 /* Initial and start queue */
1378 status = bfin_spi_init_queue(drv_data);
1379 if (status != 0) {
1380 dev_err(dev, "problem initializing queue\n");
1381 goto out_error_queue_alloc;
1382 }
1383
1384 status = bfin_spi_start_queue(drv_data);
1385 if (status != 0) {
1386 dev_err(dev, "problem starting queue\n");
1387 goto out_error_queue_alloc;
1388 }
1389
1390 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1391 if (status != 0) {
1392 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1393 goto out_error_queue_alloc;
1394 }
1395
1396 /* Reset SPI registers. If these registers were used by the boot loader,
1397 * the sky may fall on your head if you enable the dma controller.
1398 */
1399 write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER);
1400 write_FLAG(drv_data, 0xFF00);
1401
1402 /* Register with the SPI framework */
1403 platform_set_drvdata(pdev, drv_data);
1404 status = spi_register_master(master);
1405 if (status != 0) {
1406 dev_err(dev, "problem registering spi master\n");
1407 goto out_error_queue_alloc;
1408 }
1409
1410 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1411 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1412 drv_data->dma_channel);
1413 return status;
1414
1415 out_error_queue_alloc:
1416 bfin_spi_destroy_queue(drv_data);
1417 out_error_free_io:
1418 iounmap((void *) drv_data->regs_base);
1419 out_error_ioremap:
1420 out_error_get_res:
1421 spi_master_put(master);
1422
1423 return status;
1424 }
1425
1426 /* stop hardware and remove the driver */
1427 static int __devexit bfin_spi_remove(struct platform_device *pdev)
1428 {
1429 struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1430 int status = 0;
1431
1432 if (!drv_data)
1433 return 0;
1434
1435 /* Remove the queue */
1436 status = bfin_spi_destroy_queue(drv_data);
1437 if (status != 0)
1438 return status;
1439
1440 /* Disable the SSP at the peripheral and SOC level */
1441 bfin_spi_disable(drv_data);
1442
1443 /* Release DMA */
1444 if (drv_data->master_info->enable_dma) {
1445 if (dma_channel_active(drv_data->dma_channel))
1446 free_dma(drv_data->dma_channel);
1447 }
1448
1449 if (drv_data->irq_requested) {
1450 free_irq(drv_data->spi_irq, drv_data);
1451 drv_data->irq_requested = 0;
1452 }
1453
1454 /* Disconnect from the SPI framework */
1455 spi_unregister_master(drv_data->master);
1456
1457 peripheral_free_list(drv_data->pin_req);
1458
1459 /* Prevent double remove */
1460 platform_set_drvdata(pdev, NULL);
1461
1462 return 0;
1463 }
1464
1465 #ifdef CONFIG_PM
1466 static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
1467 {
1468 struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1469 int status = 0;
1470
1471 status = bfin_spi_stop_queue(drv_data);
1472 if (status != 0)
1473 return status;
1474
1475 drv_data->ctrl_reg = read_CTRL(drv_data);
1476 drv_data->flag_reg = read_FLAG(drv_data);
1477
1478 /*
1479 * reset SPI_CTL and SPI_FLG registers
1480 */
1481 write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER);
1482 write_FLAG(drv_data, 0xFF00);
1483
1484 return 0;
1485 }
1486
1487 static int bfin_spi_resume(struct platform_device *pdev)
1488 {
1489 struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1490 int status = 0;
1491
1492 write_CTRL(drv_data, drv_data->ctrl_reg);
1493 write_FLAG(drv_data, drv_data->flag_reg);
1494
1495 /* Start the queue running */
1496 status = bfin_spi_start_queue(drv_data);
1497 if (status != 0) {
1498 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1499 return status;
1500 }
1501
1502 return 0;
1503 }
1504 #else
1505 #define bfin_spi_suspend NULL
1506 #define bfin_spi_resume NULL
1507 #endif /* CONFIG_PM */
1508
1509 MODULE_ALIAS("platform:bfin-spi");
1510 static struct platform_driver bfin_spi_driver = {
1511 .driver = {
1512 .name = DRV_NAME,
1513 .owner = THIS_MODULE,
1514 },
1515 .suspend = bfin_spi_suspend,
1516 .resume = bfin_spi_resume,
1517 .remove = __devexit_p(bfin_spi_remove),
1518 };
1519
1520 static int __init bfin_spi_init(void)
1521 {
1522 return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
1523 }
1524 subsys_initcall(bfin_spi_init);
1525
1526 static void __exit bfin_spi_exit(void)
1527 {
1528 platform_driver_unregister(&bfin_spi_driver);
1529 }
1530 module_exit(bfin_spi_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree