arch/x86/kernel/cpu/cpufreq/cpufreq-nforce2.c

   1 /*
   2  * (C) 2004-2006  Sebastian Witt <se.witt@gmx.net>
   3  *
   4  *  Licensed under the terms of the GNU GPL License version 2.
   5  *  Based upon reverse engineered information
   6  *
   7  *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/init.h>
  14 #include <linux/cpufreq.h>
  15 #include <linux/pci.h>
  16 #include <linux/delay.h>
  17
  18 #define NFORCE2_XTAL 25
  19 #define NFORCE2_BOOTFSB 0x48
  20 #define NFORCE2_PLLENABLE 0xa8
  21 #define NFORCE2_PLLREG 0xa4
  22 #define NFORCE2_PLLADR 0xa0
  23 #define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div)
  24
  25 #define NFORCE2_MIN_FSB 50
  26 #define NFORCE2_SAFE_DISTANCE 50
  27
  28 /* Delay in ms between FSB changes */
  29 /* #define NFORCE2_DELAY 10 */
  30
  31 /*
  32  * nforce2_chipset:
  33  * FSB is changed using the chipset
  34  */
  35 static struct pci_dev *nforce2_dev;
  36
  37 /* fid:
  38  * multiplier * 10
  39  */
  40 static int fid;
  41
  42 /* min_fsb, max_fsb:
  43  * minimum and maximum FSB (= FSB at boot time)
  44  */
  45 static int min_fsb;
  46 static int max_fsb;
  47
  48 MODULE_AUTHOR("Sebastian Witt <se.witt@gmx.net>");
  49 MODULE_DESCRIPTION("nForce2 FSB changing cpufreq driver");
  50 MODULE_LICENSE("GPL");
  51
  52 module_param(fid, int, 0444);
  53 module_param(min_fsb, int, 0444);
  54
  55 MODULE_PARM_DESC(fid, "CPU multiplier to use (11.5 = 115)");
  56 MODULE_PARM_DESC(min_fsb,
  57                 "Minimum FSB to use, if not defined: current FSB - 50");
  58
  59 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
  60                 "cpufreq-nforce2", msg)
  61
  62 /**
  63  * nforce2_calc_fsb - calculate FSB
  64  * @pll: PLL value
  65  *
  66  *   Calculates FSB from PLL value
  67  */
  68 static int nforce2_calc_fsb(int pll)
  69 {
  70         unsigned char mul, div;
  71
  72         mul = (pll >> 8) & 0xff;
  73         div = pll & 0xff;
  74
  75         if (div > 0)
  76                 return NFORCE2_XTAL * mul / div;
  77
  78         return 0;
  79 }
  80
  81 /**
  82  * nforce2_calc_pll - calculate PLL value
  83  * @fsb: FSB
  84  *
  85  *   Calculate PLL value for given FSB
  86  */
  87 static int nforce2_calc_pll(unsigned int fsb)
  88 {
  89         unsigned char xmul, xdiv;
  90         unsigned char mul = 0, div = 0;
  91         int tried = 0;
  92
  93         /* Try to calculate multiplier and divider up to 4 times */
  94         while (((mul == 0) || (div == 0)) && (tried <= 3)) {
  95                 for (xdiv = 2; xdiv <= 0x80; xdiv++)
  96                         for (xmul = 1; xmul <= 0xfe; xmul++)
  97                                 if (nforce2_calc_fsb(NFORCE2_PLL(xmul, xdiv)) ==
  98                                     fsb + tried) {
  99                                         mul = xmul;
 100                                         div = xdiv;
 101                                 }
 102                 tried++;
 103         }
 104
 105         if ((mul == 0) || (div == 0))
 106                 return -1;
 107
 108         return NFORCE2_PLL(mul, div);
 109 }
 110
 111 /**
 112  * nforce2_write_pll - write PLL value to chipset
 113  * @pll: PLL value
 114  *
 115  *   Writes new FSB PLL value to chipset
 116  */
 117 static void nforce2_write_pll(int pll)
 118 {
 119         int temp;
 120
 121         /* Set the pll addr. to 0x00 */
 122         pci_write_config_dword(nforce2_dev, NFORCE2_PLLADR, 0);
 123
 124         /* Now write the value in all 64 registers */
 125         for (temp = 0; temp <= 0x3f; temp++)
 126                 pci_write_config_dword(nforce2_dev, NFORCE2_PLLREG, pll);
 127
 128         return;
 129 }
 130
 131 /**
 132  * nforce2_fsb_read - Read FSB
 133  *
 134  *   Read FSB from chipset
 135  *   If bootfsb != 0, return FSB at boot-time
 136  */
 137 static unsigned int nforce2_fsb_read(int bootfsb)
 138 {
 139         struct pci_dev *nforce2_sub5;
 140         u32 fsb, temp = 0;
 141
 142         /* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
 143         nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA, 0x01EF,
 144                                 PCI_ANY_ID, PCI_ANY_ID, NULL);
 145         if (!nforce2_sub5)
 146                 return 0;
 147
 148         pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb);
 149         fsb /= 1000000;
 150
 151         /* Check if PLL register is already set */
 152         pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
 153
 154         if (bootfsb || !temp)
 155                 return fsb;
 156
 157         /* Use PLL register FSB value */
 158         pci_read_config_dword(nforce2_dev, NFORCE2_PLLREG, &temp);
 159         fsb = nforce2_calc_fsb(temp);
 160
 161         return fsb;
 162 }
 163
 164 /**
 165  * nforce2_set_fsb - set new FSB
 166  * @fsb: New FSB
 167  *
 168  *   Sets new FSB
 169  */
 170 static int nforce2_set_fsb(unsigned int fsb)
 171 {
 172         u32 temp = 0;
 173         unsigned int tfsb;
 174         int diff;
 175         int pll = 0;
 176
 177         if ((fsb > max_fsb) || (fsb < NFORCE2_MIN_FSB)) {
 178                 printk(KERN_ERR "cpufreq: FSB %d is out of range!\n", fsb);
 179                 return -EINVAL;
 180         }
 181
 182         tfsb = nforce2_fsb_read(0);
 183         if (!tfsb) {
 184                 printk(KERN_ERR "cpufreq: Error while reading the FSB\n");
 185                 return -EINVAL;
 186         }
 187
 188         /* First write? Then set actual value */
 189         pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
 190         if (!temp) {
 191                 pll = nforce2_calc_pll(tfsb);
 192
 193                 if (pll < 0)
 194                         return -EINVAL;
 195
 196                 nforce2_write_pll(pll);
 197         }
 198
 199         /* Enable write access */
 200         temp = 0x01;
 201         pci_write_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8)temp);
 202
 203         diff = tfsb - fsb;
 204
 205         if (!diff)
 206                 return 0;
 207
 208         while ((tfsb != fsb) && (tfsb <= max_fsb) && (tfsb >= min_fsb)) {
 209                 if (diff < 0)
 210                         tfsb++;
 211                 else
 212                         tfsb--;
 213
 214                 /* Calculate the PLL reg. value */
 215                 pll = nforce2_calc_pll(tfsb);
 216                 if (pll == -1)
 217                         return -EINVAL;
 218
 219                 nforce2_write_pll(pll);
 220 #ifdef NFORCE2_DELAY
 221                 mdelay(NFORCE2_DELAY);
 222 #endif
 223         }
 224
 225         temp = 0x40;
 226         pci_write_config_byte(nforce2_dev, NFORCE2_PLLADR, (u8)temp);
 227
 228         return 0;
 229 }
 230
 231 /**
 232  * nforce2_get - get the CPU frequency
 233  * @cpu: CPU number
 234  *
 235  * Returns the CPU frequency
 236  */
 237 static unsigned int nforce2_get(unsigned int cpu)
 238 {
 239         if (cpu)
 240                 return 0;
 241         return nforce2_fsb_read(0) * fid * 100;
 242 }
 243
 244 /**
 245  * nforce2_target - set a new CPUFreq policy
 246  * @policy: new policy
 247  * @target_freq: the target frequency
 248  * @relation: how that frequency relates to achieved frequency
 249  *  (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
 250  *
 251  * Sets a new CPUFreq policy.
 252  */
 253 static int nforce2_target(struct cpufreq_policy *policy,
 254                           unsigned int target_freq, unsigned int relation)
 255 {
 256 /*        unsigned long         flags; */
 257         struct cpufreq_freqs freqs;
 258         unsigned int target_fsb;
 259
 260         if ((target_freq > policy->max) || (target_freq < policy->min))
 261                 return -EINVAL;
 262
 263         target_fsb = target_freq / (fid * 100);
 264
 265         freqs.old = nforce2_get(policy->cpu);
 266         freqs.new = target_fsb * fid * 100;
 267         freqs.cpu = 0;          /* Only one CPU on nForce2 platforms */
 268
 269         if (freqs.old == freqs.new)
 270                 return 0;
 271
 272         dprintk("Old CPU frequency %d kHz, new %d kHz\n",
 273                freqs.old, freqs.new);
 274
 275         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 276
 277         /* Disable IRQs */
 278         /* local_irq_save(flags); */
 279
 280         if (nforce2_set_fsb(target_fsb) < 0)
 281                 printk(KERN_ERR "cpufreq: Changing FSB to %d failed\n",
 282                         target_fsb);
 283         else
 284                 dprintk("Changed FSB successfully to %d\n",
 285                         target_fsb);
 286
 287         /* Enable IRQs */
 288         /* local_irq_restore(flags); */
 289
 290         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 291
 292         return 0;
 293 }
 294
 295 /**
 296  * nforce2_verify - verifies a new CPUFreq policy
 297  * @policy: new policy
 298  */
 299 static int nforce2_verify(struct cpufreq_policy *policy)
 300 {
 301         unsigned int fsb_pol_max;
 302
 303         fsb_pol_max = policy->max / (fid * 100);
 304
 305         if (policy->min < (fsb_pol_max * fid * 100))
 306                 policy->max = (fsb_pol_max + 1) * fid * 100;
 307
 308         cpufreq_verify_within_limits(policy,
 309                                      policy->cpuinfo.min_freq,
 310                                      policy->cpuinfo.max_freq);
 311         return 0;
 312 }
 313
 314 static int nforce2_cpu_init(struct cpufreq_policy *policy)
 315 {
 316         unsigned int fsb;
 317         unsigned int rfid;
 318
 319         /* capability check */
 320         if (policy->cpu != 0)
 321                 return -ENODEV;
 322
 323         /* Get current FSB */
 324         fsb = nforce2_fsb_read(0);
 325
 326         if (!fsb)
 327                 return -EIO;
 328
 329         /* FIX: Get FID from CPU */
 330         if (!fid) {
 331                 if (!cpu_khz) {
 332                         printk(KERN_WARNING
 333                                "cpufreq: cpu_khz not set, "
 334                                "can't calculate multiplier!\n");
 335                         return -ENODEV;
 336                 }
 337
 338                 fid = cpu_khz / (fsb * 100);
 339                 rfid = fid % 5;
 340
 341                 if (rfid) {
 342                         if (rfid > 2)
 343                                 fid += 5 - rfid;
 344                         else
 345                                 fid -= rfid;
 346                 }
 347         }
 348
 349         printk(KERN_INFO "cpufreq: FSB currently at %i MHz, FID %d.%d\n", fsb,
 350                fid / 10, fid % 10);
 351
 352         /* Set maximum FSB to FSB at boot time */
 353         max_fsb = nforce2_fsb_read(1);
 354
 355         if (!max_fsb)
 356                 return -EIO;
 357
 358         if (!min_fsb)
 359                 min_fsb = max_fsb - NFORCE2_SAFE_DISTANCE;
 360
 361         if (min_fsb < NFORCE2_MIN_FSB)
 362                 min_fsb = NFORCE2_MIN_FSB;
 363
 364         /* cpuinfo and default policy values */
 365         policy->cpuinfo.min_freq = min_fsb * fid * 100;
 366         policy->cpuinfo.max_freq = max_fsb * fid * 100;
 367         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
 368         policy->cur = nforce2_get(policy->cpu);
 369         policy->min = policy->cpuinfo.min_freq;
 370         policy->max = policy->cpuinfo.max_freq;
 371
 372         return 0;
 373 }
 374
 375 static int nforce2_cpu_exit(struct cpufreq_policy *policy)
 376 {
 377         return 0;
 378 }
 379
 380 static struct cpufreq_driver nforce2_driver = {
 381         .name = "nforce2",
 382         .verify = nforce2_verify,
 383         .target = nforce2_target,
 384         .get = nforce2_get,
 385         .init = nforce2_cpu_init,
 386         .exit = nforce2_cpu_exit,
 387         .owner = THIS_MODULE,
 388 };
 389
 390 /**
 391  * nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic
 392  *
 393  * Detects nForce2 A2 and C1 stepping
 394  *
 395  */
 396 static unsigned int nforce2_detect_chipset(void)
 397 {
 398         nforce2_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
 399                                         PCI_DEVICE_ID_NVIDIA_NFORCE2,
 400                                         PCI_ANY_ID, PCI_ANY_ID, NULL);
 401
 402         if (nforce2_dev == NULL)
 403                 return -ENODEV;
 404
 405         printk(KERN_INFO "cpufreq: Detected nForce2 chipset revision %X\n",
 406                nforce2_dev->revision);
 407         printk(KERN_INFO
 408                "cpufreq: FSB changing is maybe unstable and can lead to "
 409                "crashes and data loss.\n");
 410
 411         return 0;
 412 }
 413
 414 /**
 415  * nforce2_init - initializes the nForce2 CPUFreq driver
 416  *
 417  * Initializes the nForce2 FSB support. Returns -ENODEV on unsupported
 418  * devices, -EINVAL on problems during initiatization, and zero on
 419  * success.
 420  */
 421 static int __init nforce2_init(void)
 422 {
 423         /* TODO: do we need to detect the processor? */
 424
 425         /* detect chipset */
 426         if (nforce2_detect_chipset()) {
 427                 printk(KERN_ERR "cpufreq: No nForce2 chipset.\n");
 428                 return -ENODEV;
 429         }
 430
 431         return cpufreq_register_driver(&nforce2_driver);
 432 }
 433
 434 /**
 435  * nforce2_exit - unregisters cpufreq module
 436  *
 437  *   Unregisters nForce2 FSB change support.
 438  */
 439 static void __exit nforce2_exit(void)
 440 {
 441         cpufreq_unregister_driver(&nforce2_driver);
 442 }
 443
 444 module_init(nforce2_init);
 445 module_exit(nforce2_exit);
 446