1 /*******************************************************************************
4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 The full GNU General Public License is included in this distribution in the
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * Shared functions for accessing and configuring the MAC
35 static int32_t e1000_set_phy_type(struct e1000_hw
*hw
);
36 static void e1000_phy_init_script(struct e1000_hw
*hw
);
37 static int32_t e1000_setup_copper_link(struct e1000_hw
*hw
);
38 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw
*hw
);
39 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw
*hw
);
40 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw
*hw
);
41 static int32_t e1000_config_mac_to_phy(struct e1000_hw
*hw
);
42 static void e1000_raise_mdi_clk(struct e1000_hw
*hw
, uint32_t *ctrl
);
43 static void e1000_lower_mdi_clk(struct e1000_hw
*hw
, uint32_t *ctrl
);
44 static void e1000_shift_out_mdi_bits(struct e1000_hw
*hw
, uint32_t data
,
46 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw
*hw
);
47 static int32_t e1000_phy_reset_dsp(struct e1000_hw
*hw
);
48 static int32_t e1000_write_eeprom_spi(struct e1000_hw
*hw
, uint16_t offset
,
49 uint16_t words
, uint16_t *data
);
50 static int32_t e1000_write_eeprom_microwire(struct e1000_hw
*hw
,
51 uint16_t offset
, uint16_t words
,
53 static int32_t e1000_spi_eeprom_ready(struct e1000_hw
*hw
);
54 static void e1000_raise_ee_clk(struct e1000_hw
*hw
, uint32_t *eecd
);
55 static void e1000_lower_ee_clk(struct e1000_hw
*hw
, uint32_t *eecd
);
56 static void e1000_shift_out_ee_bits(struct e1000_hw
*hw
, uint16_t data
,
58 static int32_t e1000_write_phy_reg_ex(struct e1000_hw
*hw
, uint32_t reg_addr
,
60 static int32_t e1000_read_phy_reg_ex(struct e1000_hw
*hw
,uint32_t reg_addr
,
62 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw
*hw
, uint16_t count
);
63 static int32_t e1000_acquire_eeprom(struct e1000_hw
*hw
);
64 static void e1000_release_eeprom(struct e1000_hw
*hw
);
65 static void e1000_standby_eeprom(struct e1000_hw
*hw
);
66 static int32_t e1000_set_vco_speed(struct e1000_hw
*hw
);
67 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw
*hw
);
68 static int32_t e1000_set_phy_mode(struct e1000_hw
*hw
);
69 static int32_t e1000_host_if_read_cookie(struct e1000_hw
*hw
, uint8_t *buffer
);
70 static uint8_t e1000_calculate_mng_checksum(char *buffer
, uint32_t length
);
71 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw
*hw
);
72 static int32_t e1000_check_downshift(struct e1000_hw
*hw
);
73 static int32_t e1000_check_polarity(struct e1000_hw
*hw
, uint16_t *polarity
);
74 static void e1000_clear_hw_cntrs(struct e1000_hw
*hw
);
75 static void e1000_clear_vfta(struct e1000_hw
*hw
);
76 static int32_t e1000_commit_shadow_ram(struct e1000_hw
*hw
);
77 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw
*hw
,
79 static int32_t e1000_config_fc_after_link_up(struct e1000_hw
*hw
);
80 static int32_t e1000_detect_gig_phy(struct e1000_hw
*hw
);
81 static int32_t e1000_get_auto_rd_done(struct e1000_hw
*hw
);
82 static int32_t e1000_get_cable_length(struct e1000_hw
*hw
,
84 uint16_t *max_length
);
85 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw
*hw
);
86 static int32_t e1000_get_phy_cfg_done(struct e1000_hw
*hw
);
87 static int32_t e1000_id_led_init(struct e1000_hw
* hw
);
88 static void e1000_init_rx_addrs(struct e1000_hw
*hw
);
89 static boolean_t
e1000_is_onboard_nvm_eeprom(struct e1000_hw
*hw
);
90 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw
*hw
, int eerd
);
91 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw
*hw
);
92 static int32_t e1000_read_eeprom_eerd(struct e1000_hw
*hw
, uint16_t offset
,
93 uint16_t words
, uint16_t *data
);
94 static int32_t e1000_set_d0_lplu_state(struct e1000_hw
*hw
, boolean_t active
);
95 static int32_t e1000_set_d3_lplu_state(struct e1000_hw
*hw
, boolean_t active
);
96 static int32_t e1000_wait_autoneg(struct e1000_hw
*hw
);
98 static void e1000_write_reg_io(struct e1000_hw
*hw
, uint32_t offset
,
101 #define E1000_WRITE_REG_IO(a, reg, val) \
102 e1000_write_reg_io((a), E1000_##reg, val)
104 /* IGP cable length table */
106 uint16_t e1000_igp_cable_length_table
[IGP01E1000_AGC_LENGTH_TABLE_SIZE
] =
107 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
108 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
109 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
110 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
111 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
112 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
113 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
114 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
117 uint16_t e1000_igp_2_cable_length_table
[IGP02E1000_AGC_LENGTH_TABLE_SIZE
] =
118 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
119 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
120 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
121 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
122 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
123 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
124 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
125 104, 109, 114, 118, 121, 124};
128 /******************************************************************************
129 * Set the phy type member in the hw struct.
131 * hw - Struct containing variables accessed by shared code
132 *****************************************************************************/
134 e1000_set_phy_type(struct e1000_hw
*hw
)
136 DEBUGFUNC("e1000_set_phy_type");
138 if(hw
->mac_type
== e1000_undefined
)
139 return -E1000_ERR_PHY_TYPE
;
142 case M88E1000_E_PHY_ID
:
143 case M88E1000_I_PHY_ID
:
144 case M88E1011_I_PHY_ID
:
145 case M88E1111_I_PHY_ID
:
146 hw
->phy_type
= e1000_phy_m88
;
148 case IGP01E1000_I_PHY_ID
:
149 if(hw
->mac_type
== e1000_82541
||
150 hw
->mac_type
== e1000_82541_rev_2
||
151 hw
->mac_type
== e1000_82547
||
152 hw
->mac_type
== e1000_82547_rev_2
) {
153 hw
->phy_type
= e1000_phy_igp
;
158 /* Should never have loaded on this device */
159 hw
->phy_type
= e1000_phy_undefined
;
160 return -E1000_ERR_PHY_TYPE
;
163 return E1000_SUCCESS
;
166 /******************************************************************************
167 * IGP phy init script - initializes the GbE PHY
169 * hw - Struct containing variables accessed by shared code
170 *****************************************************************************/
172 e1000_phy_init_script(struct e1000_hw
*hw
)
175 uint16_t phy_saved_data
;
177 DEBUGFUNC("e1000_phy_init_script");
179 if(hw
->phy_init_script
) {
182 /* Save off the current value of register 0x2F5B to be restored at
183 * the end of this routine. */
184 ret_val
= e1000_read_phy_reg(hw
, 0x2F5B, &phy_saved_data
);
186 /* Disabled the PHY transmitter */
187 e1000_write_phy_reg(hw
, 0x2F5B, 0x0003);
191 e1000_write_phy_reg(hw
,0x0000,0x0140);
195 switch(hw
->mac_type
) {
198 e1000_write_phy_reg(hw
, 0x1F95, 0x0001);
200 e1000_write_phy_reg(hw
, 0x1F71, 0xBD21);
202 e1000_write_phy_reg(hw
, 0x1F79, 0x0018);
204 e1000_write_phy_reg(hw
, 0x1F30, 0x1600);
206 e1000_write_phy_reg(hw
, 0x1F31, 0x0014);
208 e1000_write_phy_reg(hw
, 0x1F32, 0x161C);
210 e1000_write_phy_reg(hw
, 0x1F94, 0x0003);
212 e1000_write_phy_reg(hw
, 0x1F96, 0x003F);
214 e1000_write_phy_reg(hw
, 0x2010, 0x0008);
217 case e1000_82541_rev_2
:
218 case e1000_82547_rev_2
:
219 e1000_write_phy_reg(hw
, 0x1F73, 0x0099);
225 e1000_write_phy_reg(hw
, 0x0000, 0x3300);
229 /* Now enable the transmitter */
230 e1000_write_phy_reg(hw
, 0x2F5B, phy_saved_data
);
232 if(hw
->mac_type
== e1000_82547
) {
233 uint16_t fused
, fine
, coarse
;
235 /* Move to analog registers page */
236 e1000_read_phy_reg(hw
, IGP01E1000_ANALOG_SPARE_FUSE_STATUS
, &fused
);
238 if(!(fused
& IGP01E1000_ANALOG_SPARE_FUSE_ENABLED
)) {
239 e1000_read_phy_reg(hw
, IGP01E1000_ANALOG_FUSE_STATUS
, &fused
);
241 fine
= fused
& IGP01E1000_ANALOG_FUSE_FINE_MASK
;
242 coarse
= fused
& IGP01E1000_ANALOG_FUSE_COARSE_MASK
;
244 if(coarse
> IGP01E1000_ANALOG_FUSE_COARSE_THRESH
) {
245 coarse
-= IGP01E1000_ANALOG_FUSE_COARSE_10
;
246 fine
-= IGP01E1000_ANALOG_FUSE_FINE_1
;
247 } else if(coarse
== IGP01E1000_ANALOG_FUSE_COARSE_THRESH
)
248 fine
-= IGP01E1000_ANALOG_FUSE_FINE_10
;
250 fused
= (fused
& IGP01E1000_ANALOG_FUSE_POLY_MASK
) |
251 (fine
& IGP01E1000_ANALOG_FUSE_FINE_MASK
) |
252 (coarse
& IGP01E1000_ANALOG_FUSE_COARSE_MASK
);
254 e1000_write_phy_reg(hw
, IGP01E1000_ANALOG_FUSE_CONTROL
, fused
);
255 e1000_write_phy_reg(hw
, IGP01E1000_ANALOG_FUSE_BYPASS
,
256 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL
);
262 /******************************************************************************
263 * Set the mac type member in the hw struct.
265 * hw - Struct containing variables accessed by shared code
266 *****************************************************************************/
268 e1000_set_mac_type(struct e1000_hw
*hw
)
270 DEBUGFUNC("e1000_set_mac_type");
272 switch (hw
->device_id
) {
273 case E1000_DEV_ID_82542
:
274 switch (hw
->revision_id
) {
275 case E1000_82542_2_0_REV_ID
:
276 hw
->mac_type
= e1000_82542_rev2_0
;
278 case E1000_82542_2_1_REV_ID
:
279 hw
->mac_type
= e1000_82542_rev2_1
;
282 /* Invalid 82542 revision ID */
283 return -E1000_ERR_MAC_TYPE
;
286 case E1000_DEV_ID_82543GC_FIBER
:
287 case E1000_DEV_ID_82543GC_COPPER
:
288 hw
->mac_type
= e1000_82543
;
290 case E1000_DEV_ID_82544EI_COPPER
:
291 case E1000_DEV_ID_82544EI_FIBER
:
292 case E1000_DEV_ID_82544GC_COPPER
:
293 case E1000_DEV_ID_82544GC_LOM
:
294 hw
->mac_type
= e1000_82544
;
296 case E1000_DEV_ID_82540EM
:
297 case E1000_DEV_ID_82540EM_LOM
:
298 case E1000_DEV_ID_82540EP
:
299 case E1000_DEV_ID_82540EP_LOM
:
300 case E1000_DEV_ID_82540EP_LP
:
301 hw
->mac_type
= e1000_82540
;
303 case E1000_DEV_ID_82545EM_COPPER
:
304 case E1000_DEV_ID_82545EM_FIBER
:
305 hw
->mac_type
= e1000_82545
;
307 case E1000_DEV_ID_82545GM_COPPER
:
308 case E1000_DEV_ID_82545GM_FIBER
:
309 case E1000_DEV_ID_82545GM_SERDES
:
310 hw
->mac_type
= e1000_82545_rev_3
;
312 case E1000_DEV_ID_82546EB_COPPER
:
313 case E1000_DEV_ID_82546EB_FIBER
:
314 case E1000_DEV_ID_82546EB_QUAD_COPPER
:
315 hw
->mac_type
= e1000_82546
;
317 case E1000_DEV_ID_82546GB_COPPER
:
318 case E1000_DEV_ID_82546GB_FIBER
:
319 case E1000_DEV_ID_82546GB_SERDES
:
320 case E1000_DEV_ID_82546GB_PCIE
:
321 hw
->mac_type
= e1000_82546_rev_3
;
323 case E1000_DEV_ID_82541EI
:
324 case E1000_DEV_ID_82541EI_MOBILE
:
325 hw
->mac_type
= e1000_82541
;
327 case E1000_DEV_ID_82541ER
:
328 case E1000_DEV_ID_82541GI
:
329 case E1000_DEV_ID_82541GI_LF
:
330 case E1000_DEV_ID_82541GI_MOBILE
:
331 hw
->mac_type
= e1000_82541_rev_2
;
333 case E1000_DEV_ID_82547EI
:
334 hw
->mac_type
= e1000_82547
;
336 case E1000_DEV_ID_82547GI
:
337 hw
->mac_type
= e1000_82547_rev_2
;
339 case E1000_DEV_ID_82571EB_COPPER
:
340 case E1000_DEV_ID_82571EB_FIBER
:
341 case E1000_DEV_ID_82571EB_SERDES
:
342 hw
->mac_type
= e1000_82571
;
344 case E1000_DEV_ID_82572EI_COPPER
:
345 case E1000_DEV_ID_82572EI_FIBER
:
346 case E1000_DEV_ID_82572EI_SERDES
:
347 hw
->mac_type
= e1000_82572
;
349 case E1000_DEV_ID_82573E
:
350 case E1000_DEV_ID_82573E_IAMT
:
351 case E1000_DEV_ID_82573L
:
352 hw
->mac_type
= e1000_82573
;
355 /* Should never have loaded on this device */
356 return -E1000_ERR_MAC_TYPE
;
359 switch(hw
->mac_type
) {
363 hw
->eeprom_semaphore_present
= TRUE
;
367 case e1000_82541_rev_2
:
368 case e1000_82547_rev_2
:
369 hw
->asf_firmware_present
= TRUE
;
375 return E1000_SUCCESS
;
378 /*****************************************************************************
379 * Set media type and TBI compatibility.
381 * hw - Struct containing variables accessed by shared code
382 * **************************************************************************/
384 e1000_set_media_type(struct e1000_hw
*hw
)
388 DEBUGFUNC("e1000_set_media_type");
390 if(hw
->mac_type
!= e1000_82543
) {
391 /* tbi_compatibility is only valid on 82543 */
392 hw
->tbi_compatibility_en
= FALSE
;
395 switch (hw
->device_id
) {
396 case E1000_DEV_ID_82545GM_SERDES
:
397 case E1000_DEV_ID_82546GB_SERDES
:
398 case E1000_DEV_ID_82571EB_SERDES
:
399 case E1000_DEV_ID_82572EI_SERDES
:
400 hw
->media_type
= e1000_media_type_internal_serdes
;
403 switch (hw
->mac_type
) {
404 case e1000_82542_rev2_0
:
405 case e1000_82542_rev2_1
:
406 hw
->media_type
= e1000_media_type_fiber
;
409 /* The STATUS_TBIMODE bit is reserved or reused for the this
412 hw
->media_type
= e1000_media_type_copper
;
415 status
= E1000_READ_REG(hw
, STATUS
);
416 if (status
& E1000_STATUS_TBIMODE
) {
417 hw
->media_type
= e1000_media_type_fiber
;
418 /* tbi_compatibility not valid on fiber */
419 hw
->tbi_compatibility_en
= FALSE
;
421 hw
->media_type
= e1000_media_type_copper
;
428 /******************************************************************************
429 * Reset the transmit and receive units; mask and clear all interrupts.
431 * hw - Struct containing variables accessed by shared code
432 *****************************************************************************/
434 e1000_reset_hw(struct e1000_hw
*hw
)
442 uint32_t extcnf_ctrl
;
445 DEBUGFUNC("e1000_reset_hw");
447 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
448 if(hw
->mac_type
== e1000_82542_rev2_0
) {
449 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
450 e1000_pci_clear_mwi(hw
);
453 if(hw
->bus_type
== e1000_bus_type_pci_express
) {
454 /* Prevent the PCI-E bus from sticking if there is no TLP connection
455 * on the last TLP read/write transaction when MAC is reset.
457 if(e1000_disable_pciex_master(hw
) != E1000_SUCCESS
) {
458 DEBUGOUT("PCI-E Master disable polling has failed.\n");
462 /* Clear interrupt mask to stop board from generating interrupts */
463 DEBUGOUT("Masking off all interrupts\n");
464 E1000_WRITE_REG(hw
, IMC
, 0xffffffff);
466 /* Disable the Transmit and Receive units. Then delay to allow
467 * any pending transactions to complete before we hit the MAC with
470 E1000_WRITE_REG(hw
, RCTL
, 0);
471 E1000_WRITE_REG(hw
, TCTL
, E1000_TCTL_PSP
);
472 E1000_WRITE_FLUSH(hw
);
474 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
475 hw
->tbi_compatibility_on
= FALSE
;
477 /* Delay to allow any outstanding PCI transactions to complete before
478 * resetting the device
482 ctrl
= E1000_READ_REG(hw
, CTRL
);
484 /* Must reset the PHY before resetting the MAC */
485 if((hw
->mac_type
== e1000_82541
) || (hw
->mac_type
== e1000_82547
)) {
486 E1000_WRITE_REG(hw
, CTRL
, (ctrl
| E1000_CTRL_PHY_RST
));
490 /* Must acquire the MDIO ownership before MAC reset.
491 * Ownership defaults to firmware after a reset. */
492 if(hw
->mac_type
== e1000_82573
) {
495 extcnf_ctrl
= E1000_READ_REG(hw
, EXTCNF_CTRL
);
496 extcnf_ctrl
|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
;
499 E1000_WRITE_REG(hw
, EXTCNF_CTRL
, extcnf_ctrl
);
500 extcnf_ctrl
= E1000_READ_REG(hw
, EXTCNF_CTRL
);
502 if(extcnf_ctrl
& E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
)
505 extcnf_ctrl
|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
;
512 /* Issue a global reset to the MAC. This will reset the chip's
513 * transmit, receive, DMA, and link units. It will not effect
514 * the current PCI configuration. The global reset bit is self-
515 * clearing, and should clear within a microsecond.
517 DEBUGOUT("Issuing a global reset to MAC\n");
519 switch(hw
->mac_type
) {
525 case e1000_82541_rev_2
:
526 /* These controllers can't ack the 64-bit write when issuing the
527 * reset, so use IO-mapping as a workaround to issue the reset */
528 E1000_WRITE_REG_IO(hw
, CTRL
, (ctrl
| E1000_CTRL_RST
));
530 case e1000_82545_rev_3
:
531 case e1000_82546_rev_3
:
532 /* Reset is performed on a shadow of the control register */
533 E1000_WRITE_REG(hw
, CTRL_DUP
, (ctrl
| E1000_CTRL_RST
));
536 E1000_WRITE_REG(hw
, CTRL
, (ctrl
| E1000_CTRL_RST
));
540 /* After MAC reset, force reload of EEPROM to restore power-on settings to
541 * device. Later controllers reload the EEPROM automatically, so just wait
542 * for reload to complete.
544 switch(hw
->mac_type
) {
545 case e1000_82542_rev2_0
:
546 case e1000_82542_rev2_1
:
549 /* Wait for reset to complete */
551 ctrl_ext
= E1000_READ_REG(hw
, CTRL_EXT
);
552 ctrl_ext
|= E1000_CTRL_EXT_EE_RST
;
553 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
554 E1000_WRITE_FLUSH(hw
);
555 /* Wait for EEPROM reload */
559 case e1000_82541_rev_2
:
561 case e1000_82547_rev_2
:
562 /* Wait for EEPROM reload */
566 if (e1000_is_onboard_nvm_eeprom(hw
) == FALSE
) {
568 ctrl_ext
= E1000_READ_REG(hw
, CTRL_EXT
);
569 ctrl_ext
|= E1000_CTRL_EXT_EE_RST
;
570 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
571 E1000_WRITE_FLUSH(hw
);
576 ret_val
= e1000_get_auto_rd_done(hw
);
578 /* We don't want to continue accessing MAC registers. */
582 /* Wait for EEPROM reload (it happens automatically) */
587 /* Disable HW ARPs on ASF enabled adapters */
588 if(hw
->mac_type
>= e1000_82540
&& hw
->mac_type
<= e1000_82547_rev_2
) {
589 manc
= E1000_READ_REG(hw
, MANC
);
590 manc
&= ~(E1000_MANC_ARP_EN
);
591 E1000_WRITE_REG(hw
, MANC
, manc
);
594 if((hw
->mac_type
== e1000_82541
) || (hw
->mac_type
== e1000_82547
)) {
595 e1000_phy_init_script(hw
);
597 /* Configure activity LED after PHY reset */
598 led_ctrl
= E1000_READ_REG(hw
, LEDCTL
);
599 led_ctrl
&= IGP_ACTIVITY_LED_MASK
;
600 led_ctrl
|= (IGP_ACTIVITY_LED_ENABLE
| IGP_LED3_MODE
);
601 E1000_WRITE_REG(hw
, LEDCTL
, led_ctrl
);
604 /* Clear interrupt mask to stop board from generating interrupts */
605 DEBUGOUT("Masking off all interrupts\n");
606 E1000_WRITE_REG(hw
, IMC
, 0xffffffff);
608 /* Clear any pending interrupt events. */
609 icr
= E1000_READ_REG(hw
, ICR
);
611 /* If MWI was previously enabled, reenable it. */
612 if(hw
->mac_type
== e1000_82542_rev2_0
) {
613 if(hw
->pci_cmd_word
& CMD_MEM_WRT_INVALIDATE
)
614 e1000_pci_set_mwi(hw
);
617 return E1000_SUCCESS
;
620 /******************************************************************************
621 * Performs basic configuration of the adapter.
623 * hw - Struct containing variables accessed by shared code
625 * Assumes that the controller has previously been reset and is in a
626 * post-reset uninitialized state. Initializes the receive address registers,
627 * multicast table, and VLAN filter table. Calls routines to setup link
628 * configuration and flow control settings. Clears all on-chip counters. Leaves
629 * the transmit and receive units disabled and uninitialized.
630 *****************************************************************************/
632 e1000_init_hw(struct e1000_hw
*hw
)
637 uint16_t pcix_cmd_word
;
638 uint16_t pcix_stat_hi_word
;
643 DEBUGFUNC("e1000_init_hw");
645 /* Initialize Identification LED */
646 ret_val
= e1000_id_led_init(hw
);
648 DEBUGOUT("Error Initializing Identification LED\n");
652 /* Set the media type and TBI compatibility */
653 e1000_set_media_type(hw
);
655 /* Disabling VLAN filtering. */
656 DEBUGOUT("Initializing the IEEE VLAN\n");
657 if (hw
->mac_type
< e1000_82545_rev_3
)
658 E1000_WRITE_REG(hw
, VET
, 0);
659 e1000_clear_vfta(hw
);
661 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
662 if(hw
->mac_type
== e1000_82542_rev2_0
) {
663 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
664 e1000_pci_clear_mwi(hw
);
665 E1000_WRITE_REG(hw
, RCTL
, E1000_RCTL_RST
);
666 E1000_WRITE_FLUSH(hw
);
670 /* Setup the receive address. This involves initializing all of the Receive
671 * Address Registers (RARs 0 - 15).
673 e1000_init_rx_addrs(hw
);
675 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
676 if(hw
->mac_type
== e1000_82542_rev2_0
) {
677 E1000_WRITE_REG(hw
, RCTL
, 0);
678 E1000_WRITE_FLUSH(hw
);
680 if(hw
->pci_cmd_word
& CMD_MEM_WRT_INVALIDATE
)
681 e1000_pci_set_mwi(hw
);
684 /* Zero out the Multicast HASH table */
685 DEBUGOUT("Zeroing the MTA\n");
686 mta_size
= E1000_MC_TBL_SIZE
;
687 for(i
= 0; i
< mta_size
; i
++)
688 E1000_WRITE_REG_ARRAY(hw
, MTA
, i
, 0);
690 /* Set the PCI priority bit correctly in the CTRL register. This
691 * determines if the adapter gives priority to receives, or if it
692 * gives equal priority to transmits and receives. Valid only on
693 * 82542 and 82543 silicon.
695 if(hw
->dma_fairness
&& hw
->mac_type
<= e1000_82543
) {
696 ctrl
= E1000_READ_REG(hw
, CTRL
);
697 E1000_WRITE_REG(hw
, CTRL
, ctrl
| E1000_CTRL_PRIOR
);
700 switch(hw
->mac_type
) {
701 case e1000_82545_rev_3
:
702 case e1000_82546_rev_3
:
705 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
706 if(hw
->bus_type
== e1000_bus_type_pcix
) {
707 e1000_read_pci_cfg(hw
, PCIX_COMMAND_REGISTER
, &pcix_cmd_word
);
708 e1000_read_pci_cfg(hw
, PCIX_STATUS_REGISTER_HI
,
710 cmd_mmrbc
= (pcix_cmd_word
& PCIX_COMMAND_MMRBC_MASK
) >>
711 PCIX_COMMAND_MMRBC_SHIFT
;
712 stat_mmrbc
= (pcix_stat_hi_word
& PCIX_STATUS_HI_MMRBC_MASK
) >>
713 PCIX_STATUS_HI_MMRBC_SHIFT
;
714 if(stat_mmrbc
== PCIX_STATUS_HI_MMRBC_4K
)
715 stat_mmrbc
= PCIX_STATUS_HI_MMRBC_2K
;
716 if(cmd_mmrbc
> stat_mmrbc
) {
717 pcix_cmd_word
&= ~PCIX_COMMAND_MMRBC_MASK
;
718 pcix_cmd_word
|= stat_mmrbc
<< PCIX_COMMAND_MMRBC_SHIFT
;
719 e1000_write_pci_cfg(hw
, PCIX_COMMAND_REGISTER
,
726 /* Call a subroutine to configure the link and setup flow control. */
727 ret_val
= e1000_setup_link(hw
);
729 /* Set the transmit descriptor write-back policy */
730 if(hw
->mac_type
> e1000_82544
) {
731 ctrl
= E1000_READ_REG(hw
, TXDCTL
);
732 ctrl
= (ctrl
& ~E1000_TXDCTL_WTHRESH
) | E1000_TXDCTL_FULL_TX_DESC_WB
;
733 switch (hw
->mac_type
) {
740 ctrl
|= E1000_TXDCTL_COUNT_DESC
;
743 E1000_WRITE_REG(hw
, TXDCTL
, ctrl
);
746 if (hw
->mac_type
== e1000_82573
) {
747 e1000_enable_tx_pkt_filtering(hw
);
750 switch (hw
->mac_type
) {
755 ctrl
= E1000_READ_REG(hw
, TXDCTL1
);
756 ctrl
&= ~E1000_TXDCTL_WTHRESH
;
757 ctrl
|= E1000_TXDCTL_COUNT_DESC
| E1000_TXDCTL_FULL_TX_DESC_WB
;
759 E1000_WRITE_REG(hw
, TXDCTL1
, ctrl
);
765 if (hw
->mac_type
== e1000_82573
) {
766 uint32_t gcr
= E1000_READ_REG(hw
, GCR
);
767 gcr
|= E1000_GCR_L1_ACT_WITHOUT_L0S_RX
;
768 E1000_WRITE_REG(hw
, GCR
, gcr
);
771 /* Clear all of the statistics registers (clear on read). It is
772 * important that we do this after we have tried to establish link
773 * because the symbol error count will increment wildly if there
776 e1000_clear_hw_cntrs(hw
);
781 /******************************************************************************
782 * Adjust SERDES output amplitude based on EEPROM setting.
784 * hw - Struct containing variables accessed by shared code.
785 *****************************************************************************/
787 e1000_adjust_serdes_amplitude(struct e1000_hw
*hw
)
789 uint16_t eeprom_data
;
792 DEBUGFUNC("e1000_adjust_serdes_amplitude");
794 if(hw
->media_type
!= e1000_media_type_internal_serdes
)
795 return E1000_SUCCESS
;
797 switch(hw
->mac_type
) {
798 case e1000_82545_rev_3
:
799 case e1000_82546_rev_3
:
802 return E1000_SUCCESS
;
805 ret_val
= e1000_read_eeprom(hw
, EEPROM_SERDES_AMPLITUDE
, 1, &eeprom_data
);
810 if(eeprom_data
!= EEPROM_RESERVED_WORD
) {
811 /* Adjust SERDES output amplitude only. */
812 eeprom_data
&= EEPROM_SERDES_AMPLITUDE_MASK
;
813 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_EXT_CTRL
, eeprom_data
);
818 return E1000_SUCCESS
;
821 /******************************************************************************
822 * Configures flow control and link settings.
824 * hw - Struct containing variables accessed by shared code
826 * Determines which flow control settings to use. Calls the apropriate media-
827 * specific link configuration function. Configures the flow control settings.
828 * Assuming the adapter has a valid link partner, a valid link should be
829 * established. Assumes the hardware has previously been reset and the
830 * transmitter and receiver are not enabled.
831 *****************************************************************************/
833 e1000_setup_link(struct e1000_hw
*hw
)
837 uint16_t eeprom_data
;
839 DEBUGFUNC("e1000_setup_link");
841 /* Read and store word 0x0F of the EEPROM. This word contains bits
842 * that determine the hardware's default PAUSE (flow control) mode,
843 * a bit that determines whether the HW defaults to enabling or
844 * disabling auto-negotiation, and the direction of the
845 * SW defined pins. If there is no SW over-ride of the flow
846 * control setting, then the variable hw->fc will
847 * be initialized based on a value in the EEPROM.
849 if (hw
->fc
== e1000_fc_default
) {
850 switch (hw
->mac_type
) {
852 hw
->fc
= e1000_fc_full
;
855 ret_val
= e1000_read_eeprom(hw
, EEPROM_INIT_CONTROL2_REG
,
858 DEBUGOUT("EEPROM Read Error\n");
859 return -E1000_ERR_EEPROM
;
861 if ((eeprom_data
& EEPROM_WORD0F_PAUSE_MASK
) == 0)
862 hw
->fc
= e1000_fc_none
;
863 else if ((eeprom_data
& EEPROM_WORD0F_PAUSE_MASK
) ==
864 EEPROM_WORD0F_ASM_DIR
)
865 hw
->fc
= e1000_fc_tx_pause
;
867 hw
->fc
= e1000_fc_full
;
872 /* We want to save off the original Flow Control configuration just
873 * in case we get disconnected and then reconnected into a different
874 * hub or switch with different Flow Control capabilities.
876 if(hw
->mac_type
== e1000_82542_rev2_0
)
877 hw
->fc
&= (~e1000_fc_tx_pause
);
879 if((hw
->mac_type
< e1000_82543
) && (hw
->report_tx_early
== 1))
880 hw
->fc
&= (~e1000_fc_rx_pause
);
882 hw
->original_fc
= hw
->fc
;
884 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw
->fc
);
886 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
887 * polarity value for the SW controlled pins, and setup the
888 * Extended Device Control reg with that info.
889 * This is needed because one of the SW controlled pins is used for
890 * signal detection. So this should be done before e1000_setup_pcs_link()
891 * or e1000_phy_setup() is called.
893 if(hw
->mac_type
== e1000_82543
) {
894 ctrl_ext
= ((eeprom_data
& EEPROM_WORD0F_SWPDIO_EXT
) <<
896 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
899 /* Call the necessary subroutine to configure the link. */
900 ret_val
= (hw
->media_type
== e1000_media_type_copper
) ?
901 e1000_setup_copper_link(hw
) :
902 e1000_setup_fiber_serdes_link(hw
);
904 /* Initialize the flow control address, type, and PAUSE timer
905 * registers to their default values. This is done even if flow
906 * control is disabled, because it does not hurt anything to
907 * initialize these registers.
909 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
911 E1000_WRITE_REG(hw
, FCAL
, FLOW_CONTROL_ADDRESS_LOW
);
912 E1000_WRITE_REG(hw
, FCAH
, FLOW_CONTROL_ADDRESS_HIGH
);
913 E1000_WRITE_REG(hw
, FCT
, FLOW_CONTROL_TYPE
);
915 E1000_WRITE_REG(hw
, FCTTV
, hw
->fc_pause_time
);
917 /* Set the flow control receive threshold registers. Normally,
918 * these registers will be set to a default threshold that may be
919 * adjusted later by the driver's runtime code. However, if the
920 * ability to transmit pause frames in not enabled, then these
921 * registers will be set to 0.
923 if(!(hw
->fc
& e1000_fc_tx_pause
)) {
924 E1000_WRITE_REG(hw
, FCRTL
, 0);
925 E1000_WRITE_REG(hw
, FCRTH
, 0);
927 /* We need to set up the Receive Threshold high and low water marks
928 * as well as (optionally) enabling the transmission of XON frames.
930 if(hw
->fc_send_xon
) {
931 E1000_WRITE_REG(hw
, FCRTL
, (hw
->fc_low_water
| E1000_FCRTL_XONE
));
932 E1000_WRITE_REG(hw
, FCRTH
, hw
->fc_high_water
);
934 E1000_WRITE_REG(hw
, FCRTL
, hw
->fc_low_water
);
935 E1000_WRITE_REG(hw
, FCRTH
, hw
->fc_high_water
);
941 /******************************************************************************
942 * Sets up link for a fiber based or serdes based adapter
944 * hw - Struct containing variables accessed by shared code
946 * Manipulates Physical Coding Sublayer functions in order to configure
947 * link. Assumes the hardware has been previously reset and the transmitter
948 * and receiver are not enabled.
949 *****************************************************************************/
951 e1000_setup_fiber_serdes_link(struct e1000_hw
*hw
)
960 DEBUGFUNC("e1000_setup_fiber_serdes_link");
962 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
963 * until explicitly turned off or a power cycle is performed. A read to
964 * the register does not indicate its status. Therefore, we ensure
965 * loopback mode is disabled during initialization.
967 if (hw
->mac_type
== e1000_82571
|| hw
->mac_type
== e1000_82572
)
968 E1000_WRITE_REG(hw
, SCTL
, E1000_DISABLE_SERDES_LOOPBACK
);
970 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
971 * set when the optics detect a signal. On older adapters, it will be
972 * cleared when there is a signal. This applies to fiber media only.
973 * If we're on serdes media, adjust the output amplitude to value set in
976 ctrl
= E1000_READ_REG(hw
, CTRL
);
977 if(hw
->media_type
== e1000_media_type_fiber
)
978 signal
= (hw
->mac_type
> e1000_82544
) ? E1000_CTRL_SWDPIN1
: 0;
980 ret_val
= e1000_adjust_serdes_amplitude(hw
);
984 /* Take the link out of reset */
985 ctrl
&= ~(E1000_CTRL_LRST
);
987 /* Adjust VCO speed to improve BER performance */
988 ret_val
= e1000_set_vco_speed(hw
);
992 e1000_config_collision_dist(hw
);
994 /* Check for a software override of the flow control settings, and setup
995 * the device accordingly. If auto-negotiation is enabled, then software
996 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
997 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
998 * auto-negotiation is disabled, then software will have to manually
999 * configure the two flow control enable bits in the CTRL register.
1001 * The possible values of the "fc" parameter are:
1002 * 0: Flow control is completely disabled
1003 * 1: Rx flow control is enabled (we can receive pause frames, but
1004 * not send pause frames).
1005 * 2: Tx flow control is enabled (we can send pause frames but we do
1006 * not support receiving pause frames).
1007 * 3: Both Rx and TX flow control (symmetric) are enabled.
1011 /* Flow control is completely disabled by a software over-ride. */
1012 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
);
1014 case e1000_fc_rx_pause
:
1015 /* RX Flow control is enabled and TX Flow control is disabled by a
1016 * software over-ride. Since there really isn't a way to advertise
1017 * that we are capable of RX Pause ONLY, we will advertise that we
1018 * support both symmetric and asymmetric RX PAUSE. Later, we will
1019 * disable the adapter's ability to send PAUSE frames.
1021 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_PAUSE_MASK
);
1023 case e1000_fc_tx_pause
:
1024 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1025 * software over-ride.
1027 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_ASM_DIR
);
1030 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1031 txcw
= (E1000_TXCW_ANE
| E1000_TXCW_FD
| E1000_TXCW_PAUSE_MASK
);
1034 DEBUGOUT("Flow control param set incorrectly\n");
1035 return -E1000_ERR_CONFIG
;
1039 /* Since auto-negotiation is enabled, take the link out of reset (the link
1040 * will be in reset, because we previously reset the chip). This will
1041 * restart auto-negotiation. If auto-neogtiation is successful then the
1042 * link-up status bit will be set and the flow control enable bits (RFCE
1043 * and TFCE) will be set according to their negotiated value.
1045 DEBUGOUT("Auto-negotiation enabled\n");
1047 E1000_WRITE_REG(hw
, TXCW
, txcw
);
1048 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
1049 E1000_WRITE_FLUSH(hw
);
1054 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1055 * indication in the Device Status Register. Time-out if a link isn't
1056 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1057 * less than 500 milliseconds even if the other end is doing it in SW).
1058 * For internal serdes, we just assume a signal is present, then poll.
1060 if(hw
->media_type
== e1000_media_type_internal_serdes
||
1061 (E1000_READ_REG(hw
, CTRL
) & E1000_CTRL_SWDPIN1
) == signal
) {
1062 DEBUGOUT("Looking for Link\n");
1063 for(i
= 0; i
< (LINK_UP_TIMEOUT
/ 10); i
++) {
1065 status
= E1000_READ_REG(hw
, STATUS
);
1066 if(status
& E1000_STATUS_LU
) break;
1068 if(i
== (LINK_UP_TIMEOUT
/ 10)) {
1069 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1070 hw
->autoneg_failed
= 1;
1071 /* AutoNeg failed to achieve a link, so we'll call
1072 * e1000_check_for_link. This routine will force the link up if
1073 * we detect a signal. This will allow us to communicate with
1074 * non-autonegotiating link partners.
1076 ret_val
= e1000_check_for_link(hw
);
1078 DEBUGOUT("Error while checking for link\n");
1081 hw
->autoneg_failed
= 0;
1083 hw
->autoneg_failed
= 0;
1084 DEBUGOUT("Valid Link Found\n");
1087 DEBUGOUT("No Signal Detected\n");
1089 return E1000_SUCCESS
;
1092 /******************************************************************************
1093 * Make sure we have a valid PHY and change PHY mode before link setup.
1095 * hw - Struct containing variables accessed by shared code
1096 ******************************************************************************/
1098 e1000_copper_link_preconfig(struct e1000_hw
*hw
)
1104 DEBUGFUNC("e1000_copper_link_preconfig");
1106 ctrl
= E1000_READ_REG(hw
, CTRL
);
1107 /* With 82543, we need to force speed and duplex on the MAC equal to what
1108 * the PHY speed and duplex configuration is. In addition, we need to
1109 * perform a hardware reset on the PHY to take it out of reset.
1111 if(hw
->mac_type
> e1000_82543
) {
1112 ctrl
|= E1000_CTRL_SLU
;
1113 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1114 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
1116 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
| E1000_CTRL_SLU
);
1117 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
1118 ret_val
= e1000_phy_hw_reset(hw
);
1123 /* Make sure we have a valid PHY */
1124 ret_val
= e1000_detect_gig_phy(hw
);
1126 DEBUGOUT("Error, did not detect valid phy.\n");
1129 DEBUGOUT1("Phy ID = %x \n", hw
->phy_id
);
1131 /* Set PHY to class A mode (if necessary) */
1132 ret_val
= e1000_set_phy_mode(hw
);
1136 if((hw
->mac_type
== e1000_82545_rev_3
) ||
1137 (hw
->mac_type
== e1000_82546_rev_3
)) {
1138 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1139 phy_data
|= 0x00000008;
1140 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1143 if(hw
->mac_type
<= e1000_82543
||
1144 hw
->mac_type
== e1000_82541
|| hw
->mac_type
== e1000_82547
||
1145 hw
->mac_type
== e1000_82541_rev_2
|| hw
->mac_type
== e1000_82547_rev_2
)
1146 hw
->phy_reset_disable
= FALSE
;
1148 return E1000_SUCCESS
;
1152 /********************************************************************
1153 * Copper link setup for e1000_phy_igp series.
1155 * hw - Struct containing variables accessed by shared code
1156 *********************************************************************/
1158 e1000_copper_link_igp_setup(struct e1000_hw
*hw
)
1164 DEBUGFUNC("e1000_copper_link_igp_setup");
1166 if (hw
->phy_reset_disable
)
1167 return E1000_SUCCESS
;
1169 ret_val
= e1000_phy_reset(hw
);
1171 DEBUGOUT("Error Resetting the PHY\n");
1175 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1178 /* Configure activity LED after PHY reset */
1179 led_ctrl
= E1000_READ_REG(hw
, LEDCTL
);
1180 led_ctrl
&= IGP_ACTIVITY_LED_MASK
;
1181 led_ctrl
|= (IGP_ACTIVITY_LED_ENABLE
| IGP_LED3_MODE
);
1182 E1000_WRITE_REG(hw
, LEDCTL
, led_ctrl
);
1184 /* disable lplu d3 during driver init */
1185 ret_val
= e1000_set_d3_lplu_state(hw
, FALSE
);
1187 DEBUGOUT("Error Disabling LPLU D3\n");
1191 /* disable lplu d0 during driver init */
1192 ret_val
= e1000_set_d0_lplu_state(hw
, FALSE
);
1194 DEBUGOUT("Error Disabling LPLU D0\n");
1197 /* Configure mdi-mdix settings */
1198 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, &phy_data
);
1202 if ((hw
->mac_type
== e1000_82541
) || (hw
->mac_type
== e1000_82547
)) {
1203 hw
->dsp_config_state
= e1000_dsp_config_disabled
;
1204 /* Force MDI for earlier revs of the IGP PHY */
1205 phy_data
&= ~(IGP01E1000_PSCR_AUTO_MDIX
| IGP01E1000_PSCR_FORCE_MDI_MDIX
);
1209 hw
->dsp_config_state
= e1000_dsp_config_enabled
;
1210 phy_data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
1214 phy_data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1217 phy_data
|= IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1221 phy_data
|= IGP01E1000_PSCR_AUTO_MDIX
;
1225 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, phy_data
);
1229 /* set auto-master slave resolution settings */
1231 e1000_ms_type phy_ms_setting
= hw
->master_slave
;
1233 if(hw
->ffe_config_state
== e1000_ffe_config_active
)
1234 hw
->ffe_config_state
= e1000_ffe_config_enabled
;
1236 if(hw
->dsp_config_state
== e1000_dsp_config_activated
)
1237 hw
->dsp_config_state
= e1000_dsp_config_enabled
;
1239 /* when autonegotiation advertisment is only 1000Mbps then we
1240 * should disable SmartSpeed and enable Auto MasterSlave
1241 * resolution as hardware default. */
1242 if(hw
->autoneg_advertised
== ADVERTISE_1000_FULL
) {
1243 /* Disable SmartSpeed */
1244 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, &phy_data
);
1247 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1248 ret_val
= e1000_write_phy_reg(hw
,
1249 IGP01E1000_PHY_PORT_CONFIG
,
1253 /* Set auto Master/Slave resolution process */
1254 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_CTRL
, &phy_data
);
1257 phy_data
&= ~CR_1000T_MS_ENABLE
;
1258 ret_val
= e1000_write_phy_reg(hw
, PHY_1000T_CTRL
, phy_data
);
1263 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_CTRL
, &phy_data
);
1267 /* load defaults for future use */
1268 hw
->original_master_slave
= (phy_data
& CR_1000T_MS_ENABLE
) ?
1269 ((phy_data
& CR_1000T_MS_VALUE
) ?
1270 e1000_ms_force_master
:
1271 e1000_ms_force_slave
) :
1274 switch (phy_ms_setting
) {
1275 case e1000_ms_force_master
:
1276 phy_data
|= (CR_1000T_MS_ENABLE
| CR_1000T_MS_VALUE
);
1278 case e1000_ms_force_slave
:
1279 phy_data
|= CR_1000T_MS_ENABLE
;
1280 phy_data
&= ~(CR_1000T_MS_VALUE
);
1283 phy_data
&= ~CR_1000T_MS_ENABLE
;
1287 ret_val
= e1000_write_phy_reg(hw
, PHY_1000T_CTRL
, phy_data
);
1292 return E1000_SUCCESS
;
1296 /********************************************************************
1297 * Copper link setup for e1000_phy_m88 series.
1299 * hw - Struct containing variables accessed by shared code
1300 *********************************************************************/
1302 e1000_copper_link_mgp_setup(struct e1000_hw
*hw
)
1307 DEBUGFUNC("e1000_copper_link_mgp_setup");
1309 if(hw
->phy_reset_disable
)
1310 return E1000_SUCCESS
;
1312 /* Enable CRS on TX. This must be set for half-duplex operation. */
1313 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1317 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
1320 * MDI/MDI-X = 0 (default)
1321 * 0 - Auto for all speeds
1324 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1326 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
1330 phy_data
|= M88E1000_PSCR_MDI_MANUAL_MODE
;
1333 phy_data
|= M88E1000_PSCR_MDIX_MANUAL_MODE
;
1336 phy_data
|= M88E1000_PSCR_AUTO_X_1000T
;
1340 phy_data
|= M88E1000_PSCR_AUTO_X_MODE
;
1345 * disable_polarity_correction = 0 (default)
1346 * Automatic Correction for Reversed Cable Polarity
1350 phy_data
&= ~M88E1000_PSCR_POLARITY_REVERSAL
;
1351 if(hw
->disable_polarity_correction
== 1)
1352 phy_data
|= M88E1000_PSCR_POLARITY_REVERSAL
;
1353 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1357 /* Force TX_CLK in the Extended PHY Specific Control Register
1360 ret_val
= e1000_read_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
1364 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
1366 if (hw
->phy_revision
< M88E1011_I_REV_4
) {
1367 /* Configure Master and Slave downshift values */
1368 phy_data
&= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
|
1369 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK
);
1370 phy_data
|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
|
1371 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X
);
1372 ret_val
= e1000_write_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
1377 /* SW Reset the PHY so all changes take effect */
1378 ret_val
= e1000_phy_reset(hw
);
1380 DEBUGOUT("Error Resetting the PHY\n");
1384 return E1000_SUCCESS
;
1387 /********************************************************************
1388 * Setup auto-negotiation and flow control advertisements,
1389 * and then perform auto-negotiation.
1391 * hw - Struct containing variables accessed by shared code
1392 *********************************************************************/
1394 e1000_copper_link_autoneg(struct e1000_hw
*hw
)
1399 DEBUGFUNC("e1000_copper_link_autoneg");
1401 /* Perform some bounds checking on the hw->autoneg_advertised
1402 * parameter. If this variable is zero, then set it to the default.
1404 hw
->autoneg_advertised
&= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
1406 /* If autoneg_advertised is zero, we assume it was not defaulted
1407 * by the calling code so we set to advertise full capability.
1409 if(hw
->autoneg_advertised
== 0)
1410 hw
->autoneg_advertised
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
1412 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1413 ret_val
= e1000_phy_setup_autoneg(hw
);
1415 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1418 DEBUGOUT("Restarting Auto-Neg\n");
1420 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1421 * the Auto Neg Restart bit in the PHY control register.
1423 ret_val
= e1000_read_phy_reg(hw
, PHY_CTRL
, &phy_data
);
1427 phy_data
|= (MII_CR_AUTO_NEG_EN
| MII_CR_RESTART_AUTO_NEG
);
1428 ret_val
= e1000_write_phy_reg(hw
, PHY_CTRL
, phy_data
);
1432 /* Does the user want to wait for Auto-Neg to complete here, or
1433 * check at a later time (for example, callback routine).
1435 if(hw
->wait_autoneg_complete
) {
1436 ret_val
= e1000_wait_autoneg(hw
);
1438 DEBUGOUT("Error while waiting for autoneg to complete\n");
1443 hw
->get_link_status
= TRUE
;
1445 return E1000_SUCCESS
;
1449 /******************************************************************************
1450 * Config the MAC and the PHY after link is up.
1451 * 1) Set up the MAC to the current PHY speed/duplex
1452 * if we are on 82543. If we
1453 * are on newer silicon, we only need to configure
1454 * collision distance in the Transmit Control Register.
1455 * 2) Set up flow control on the MAC to that established with
1457 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1459 * hw - Struct containing variables accessed by shared code
1460 ******************************************************************************/
1462 e1000_copper_link_postconfig(struct e1000_hw
*hw
)
1465 DEBUGFUNC("e1000_copper_link_postconfig");
1467 if(hw
->mac_type
>= e1000_82544
) {
1468 e1000_config_collision_dist(hw
);
1470 ret_val
= e1000_config_mac_to_phy(hw
);
1472 DEBUGOUT("Error configuring MAC to PHY settings\n");
1476 ret_val
= e1000_config_fc_after_link_up(hw
);
1478 DEBUGOUT("Error Configuring Flow Control\n");
1482 /* Config DSP to improve Giga link quality */
1483 if(hw
->phy_type
== e1000_phy_igp
) {
1484 ret_val
= e1000_config_dsp_after_link_change(hw
, TRUE
);
1486 DEBUGOUT("Error Configuring DSP after link up\n");
1491 return E1000_SUCCESS
;
1494 /******************************************************************************
1495 * Detects which PHY is present and setup the speed and duplex
1497 * hw - Struct containing variables accessed by shared code
1498 ******************************************************************************/
1500 e1000_setup_copper_link(struct e1000_hw
*hw
)
1506 DEBUGFUNC("e1000_setup_copper_link");
1508 /* Check if it is a valid PHY and set PHY mode if necessary. */
1509 ret_val
= e1000_copper_link_preconfig(hw
);
1513 if (hw
->phy_type
== e1000_phy_igp
||
1514 hw
->phy_type
== e1000_phy_igp_2
) {
1515 ret_val
= e1000_copper_link_igp_setup(hw
);
1518 } else if (hw
->phy_type
== e1000_phy_m88
) {
1519 ret_val
= e1000_copper_link_mgp_setup(hw
);
1525 /* Setup autoneg and flow control advertisement
1526 * and perform autonegotiation */
1527 ret_val
= e1000_copper_link_autoneg(hw
);
1531 /* PHY will be set to 10H, 10F, 100H,or 100F
1532 * depending on value from forced_speed_duplex. */
1533 DEBUGOUT("Forcing speed and duplex\n");
1534 ret_val
= e1000_phy_force_speed_duplex(hw
);
1536 DEBUGOUT("Error Forcing Speed and Duplex\n");
1541 /* Check link status. Wait up to 100 microseconds for link to become
1544 for(i
= 0; i
< 10; i
++) {
1545 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
1548 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
1552 if(phy_data
& MII_SR_LINK_STATUS
) {
1553 /* Config the MAC and PHY after link is up */
1554 ret_val
= e1000_copper_link_postconfig(hw
);
1558 DEBUGOUT("Valid link established!!!\n");
1559 return E1000_SUCCESS
;
1564 DEBUGOUT("Unable to establish link!!!\n");
1565 return E1000_SUCCESS
;
1568 /******************************************************************************
1569 * Configures PHY autoneg and flow control advertisement settings
1571 * hw - Struct containing variables accessed by shared code
1572 ******************************************************************************/
1574 e1000_phy_setup_autoneg(struct e1000_hw
*hw
)
1577 uint16_t mii_autoneg_adv_reg
;
1578 uint16_t mii_1000t_ctrl_reg
;
1580 DEBUGFUNC("e1000_phy_setup_autoneg");
1582 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1583 ret_val
= e1000_read_phy_reg(hw
, PHY_AUTONEG_ADV
, &mii_autoneg_adv_reg
);
1587 /* Read the MII 1000Base-T Control Register (Address 9). */
1588 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_CTRL
, &mii_1000t_ctrl_reg
);
1592 /* Need to parse both autoneg_advertised and fc and set up
1593 * the appropriate PHY registers. First we will parse for
1594 * autoneg_advertised software override. Since we can advertise
1595 * a plethora of combinations, we need to check each bit
1599 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1600 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1601 * the 1000Base-T Control Register (Address 9).
1603 mii_autoneg_adv_reg
&= ~REG4_SPEED_MASK
;
1604 mii_1000t_ctrl_reg
&= ~REG9_SPEED_MASK
;
1606 DEBUGOUT1("autoneg_advertised %x\n", hw
->autoneg_advertised
);
1608 /* Do we want to advertise 10 Mb Half Duplex? */
1609 if(hw
->autoneg_advertised
& ADVERTISE_10_HALF
) {
1610 DEBUGOUT("Advertise 10mb Half duplex\n");
1611 mii_autoneg_adv_reg
|= NWAY_AR_10T_HD_CAPS
;
1614 /* Do we want to advertise 10 Mb Full Duplex? */
1615 if(hw
->autoneg_advertised
& ADVERTISE_10_FULL
) {
1616 DEBUGOUT("Advertise 10mb Full duplex\n");
1617 mii_autoneg_adv_reg
|= NWAY_AR_10T_FD_CAPS
;
1620 /* Do we want to advertise 100 Mb Half Duplex? */
1621 if(hw
->autoneg_advertised
& ADVERTISE_100_HALF
) {
1622 DEBUGOUT("Advertise 100mb Half duplex\n");
1623 mii_autoneg_adv_reg
|= NWAY_AR_100TX_HD_CAPS
;
1626 /* Do we want to advertise 100 Mb Full Duplex? */
1627 if(hw
->autoneg_advertised
& ADVERTISE_100_FULL
) {
1628 DEBUGOUT("Advertise 100mb Full duplex\n");
1629 mii_autoneg_adv_reg
|= NWAY_AR_100TX_FD_CAPS
;
1632 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1633 if(hw
->autoneg_advertised
& ADVERTISE_1000_HALF
) {
1634 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1637 /* Do we want to advertise 1000 Mb Full Duplex? */
1638 if(hw
->autoneg_advertised
& ADVERTISE_1000_FULL
) {
1639 DEBUGOUT("Advertise 1000mb Full duplex\n");
1640 mii_1000t_ctrl_reg
|= CR_1000T_FD_CAPS
;
1643 /* Check for a software override of the flow control settings, and
1644 * setup the PHY advertisement registers accordingly. If
1645 * auto-negotiation is enabled, then software will have to set the
1646 * "PAUSE" bits to the correct value in the Auto-Negotiation
1647 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1649 * The possible values of the "fc" parameter are:
1650 * 0: Flow control is completely disabled
1651 * 1: Rx flow control is enabled (we can receive pause frames
1652 * but not send pause frames).
1653 * 2: Tx flow control is enabled (we can send pause frames
1654 * but we do not support receiving pause frames).
1655 * 3: Both Rx and TX flow control (symmetric) are enabled.
1656 * other: No software override. The flow control configuration
1657 * in the EEPROM is used.
1660 case e1000_fc_none
: /* 0 */
1661 /* Flow control (RX & TX) is completely disabled by a
1662 * software over-ride.
1664 mii_autoneg_adv_reg
&= ~(NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1666 case e1000_fc_rx_pause
: /* 1 */
1667 /* RX Flow control is enabled, and TX Flow control is
1668 * disabled, by a software over-ride.
1670 /* Since there really isn't a way to advertise that we are
1671 * capable of RX Pause ONLY, we will advertise that we
1672 * support both symmetric and asymmetric RX PAUSE. Later
1673 * (in e1000_config_fc_after_link_up) we will disable the
1674 *hw's ability to send PAUSE frames.
1676 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1678 case e1000_fc_tx_pause
: /* 2 */
1679 /* TX Flow control is enabled, and RX Flow control is
1680 * disabled, by a software over-ride.
1682 mii_autoneg_adv_reg
|= NWAY_AR_ASM_DIR
;
1683 mii_autoneg_adv_reg
&= ~NWAY_AR_PAUSE
;
1685 case e1000_fc_full
: /* 3 */
1686 /* Flow control (both RX and TX) is enabled by a software
1689 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1692 DEBUGOUT("Flow control param set incorrectly\n");
1693 return -E1000_ERR_CONFIG
;
1696 ret_val
= e1000_write_phy_reg(hw
, PHY_AUTONEG_ADV
, mii_autoneg_adv_reg
);
1700 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg
);
1702 ret_val
= e1000_write_phy_reg(hw
, PHY_1000T_CTRL
, mii_1000t_ctrl_reg
);
1706 return E1000_SUCCESS
;
1709 /******************************************************************************
1710 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1712 * hw - Struct containing variables accessed by shared code
1713 ******************************************************************************/
1715 e1000_phy_force_speed_duplex(struct e1000_hw
*hw
)
1719 uint16_t mii_ctrl_reg
;
1720 uint16_t mii_status_reg
;
1724 DEBUGFUNC("e1000_phy_force_speed_duplex");
1726 /* Turn off Flow control if we are forcing speed and duplex. */
1727 hw
->fc
= e1000_fc_none
;
1729 DEBUGOUT1("hw->fc = %d\n", hw
->fc
);
1731 /* Read the Device Control Register. */
1732 ctrl
= E1000_READ_REG(hw
, CTRL
);
1734 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1735 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1736 ctrl
&= ~(DEVICE_SPEED_MASK
);
1738 /* Clear the Auto Speed Detect Enable bit. */
1739 ctrl
&= ~E1000_CTRL_ASDE
;
1741 /* Read the MII Control Register. */
1742 ret_val
= e1000_read_phy_reg(hw
, PHY_CTRL
, &mii_ctrl_reg
);
1746 /* We need to disable autoneg in order to force link and duplex. */
1748 mii_ctrl_reg
&= ~MII_CR_AUTO_NEG_EN
;
1750 /* Are we forcing Full or Half Duplex? */
1751 if(hw
->forced_speed_duplex
== e1000_100_full
||
1752 hw
->forced_speed_duplex
== e1000_10_full
) {
1753 /* We want to force full duplex so we SET the full duplex bits in the
1754 * Device and MII Control Registers.
1756 ctrl
|= E1000_CTRL_FD
;
1757 mii_ctrl_reg
|= MII_CR_FULL_DUPLEX
;
1758 DEBUGOUT("Full Duplex\n");
1760 /* We want to force half duplex so we CLEAR the full duplex bits in
1761 * the Device and MII Control Registers.
1763 ctrl
&= ~E1000_CTRL_FD
;
1764 mii_ctrl_reg
&= ~MII_CR_FULL_DUPLEX
;
1765 DEBUGOUT("Half Duplex\n");
1768 /* Are we forcing 100Mbps??? */
1769 if(hw
->forced_speed_duplex
== e1000_100_full
||
1770 hw
->forced_speed_duplex
== e1000_100_half
) {
1771 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1772 ctrl
|= E1000_CTRL_SPD_100
;
1773 mii_ctrl_reg
|= MII_CR_SPEED_100
;
1774 mii_ctrl_reg
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_10
);
1775 DEBUGOUT("Forcing 100mb ");
1777 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1778 ctrl
&= ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
1779 mii_ctrl_reg
|= MII_CR_SPEED_10
;
1780 mii_ctrl_reg
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_100
);
1781 DEBUGOUT("Forcing 10mb ");
1784 e1000_config_collision_dist(hw
);
1786 /* Write the configured values back to the Device Control Reg. */
1787 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
1789 if (hw
->phy_type
== e1000_phy_m88
) {
1790 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1794 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1795 * forced whenever speed are duplex are forced.
1797 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
1798 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1802 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data
);
1804 /* Need to reset the PHY or these changes will be ignored */
1805 mii_ctrl_reg
|= MII_CR_RESET
;
1807 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1808 * forced whenever speed or duplex are forced.
1810 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, &phy_data
);
1814 phy_data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
1815 phy_data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1817 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CTRL
, phy_data
);
1822 /* Write back the modified PHY MII control register. */
1823 ret_val
= e1000_write_phy_reg(hw
, PHY_CTRL
, mii_ctrl_reg
);
1829 /* The wait_autoneg_complete flag may be a little misleading here.
1830 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1831 * But we do want to delay for a period while forcing only so we
1832 * don't generate false No Link messages. So we will wait here
1833 * only if the user has set wait_autoneg_complete to 1, which is
1836 if(hw
->wait_autoneg_complete
) {
1837 /* We will wait for autoneg to complete. */
1838 DEBUGOUT("Waiting for forced speed/duplex link.\n");
1841 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1842 for(i
= PHY_FORCE_TIME
; i
> 0; i
--) {
1843 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1846 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
1850 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
1854 if(mii_status_reg
& MII_SR_LINK_STATUS
) break;
1858 (hw
->phy_type
== e1000_phy_m88
)) {
1859 /* We didn't get link. Reset the DSP and wait again for link. */
1860 ret_val
= e1000_phy_reset_dsp(hw
);
1862 DEBUGOUT("Error Resetting PHY DSP\n");
1866 /* This loop will early-out if the link condition has been met. */
1867 for(i
= PHY_FORCE_TIME
; i
> 0; i
--) {
1868 if(mii_status_reg
& MII_SR_LINK_STATUS
) break;
1870 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1873 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
1877 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
1883 if (hw
->phy_type
== e1000_phy_m88
) {
1884 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1885 * Extended PHY Specific Control Register to 25MHz clock. This value
1886 * defaults back to a 2.5MHz clock when the PHY is reset.
1888 ret_val
= e1000_read_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
1892 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
1893 ret_val
= e1000_write_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
1897 /* In addition, because of the s/w reset above, we need to enable CRS on
1898 * TX. This must be set for both full and half duplex operation.
1900 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1904 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
1905 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1909 if((hw
->mac_type
== e1000_82544
|| hw
->mac_type
== e1000_82543
) &&
1911 (hw
->forced_speed_duplex
== e1000_10_full
||
1912 hw
->forced_speed_duplex
== e1000_10_half
)) {
1913 ret_val
= e1000_polarity_reversal_workaround(hw
);
1918 return E1000_SUCCESS
;
1921 /******************************************************************************
1922 * Sets the collision distance in the Transmit Control register
1924 * hw - Struct containing variables accessed by shared code
1926 * Link should have been established previously. Reads the speed and duplex
1927 * information from the Device Status register.
1928 ******************************************************************************/
1930 e1000_config_collision_dist(struct e1000_hw
*hw
)
1934 DEBUGFUNC("e1000_config_collision_dist");
1936 tctl
= E1000_READ_REG(hw
, TCTL
);
1938 tctl
&= ~E1000_TCTL_COLD
;
1939 tctl
|= E1000_COLLISION_DISTANCE
<< E1000_COLD_SHIFT
;
1941 E1000_WRITE_REG(hw
, TCTL
, tctl
);
1942 E1000_WRITE_FLUSH(hw
);
1945 /******************************************************************************
1946 * Sets MAC speed and duplex settings to reflect the those in the PHY
1948 * hw - Struct containing variables accessed by shared code
1949 * mii_reg - data to write to the MII control register
1951 * The contents of the PHY register containing the needed information need to
1953 ******************************************************************************/
1955 e1000_config_mac_to_phy(struct e1000_hw
*hw
)
1961 DEBUGFUNC("e1000_config_mac_to_phy");
1963 /* 82544 or newer MAC, Auto Speed Detection takes care of
1964 * MAC speed/duplex configuration.*/
1965 if (hw
->mac_type
>= e1000_82544
)
1966 return E1000_SUCCESS
;
1968 /* Read the Device Control Register and set the bits to Force Speed
1971 ctrl
= E1000_READ_REG(hw
, CTRL
);
1972 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1973 ctrl
&= ~(E1000_CTRL_SPD_SEL
| E1000_CTRL_ILOS
);
1975 /* Set up duplex in the Device Control and Transmit Control
1976 * registers depending on negotiated values.
1978 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
1982 if(phy_data
& M88E1000_PSSR_DPLX
)
1983 ctrl
|= E1000_CTRL_FD
;
1985 ctrl
&= ~E1000_CTRL_FD
;
1987 e1000_config_collision_dist(hw
);
1989 /* Set up speed in the Device Control register depending on
1990 * negotiated values.
1992 if((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
)
1993 ctrl
|= E1000_CTRL_SPD_1000
;
1994 else if((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_100MBS
)
1995 ctrl
|= E1000_CTRL_SPD_100
;
1997 /* Write the configured values back to the Device Control Reg. */
1998 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
1999 return E1000_SUCCESS
;
2002 /******************************************************************************
2003 * Forces the MAC's flow control settings.
2005 * hw - Struct containing variables accessed by shared code
2007 * Sets the TFCE and RFCE bits in the device control register to reflect
2008 * the adapter settings. TFCE and RFCE need to be explicitly set by
2009 * software when a Copper PHY is used because autonegotiation is managed
2010 * by the PHY rather than the MAC. Software must also configure these
2011 * bits when link is forced on a fiber connection.
2012 *****************************************************************************/
2014 e1000_force_mac_fc(struct e1000_hw
*hw
)
2018 DEBUGFUNC("e1000_force_mac_fc");
2020 /* Get the current configuration of the Device Control Register */
2021 ctrl
= E1000_READ_REG(hw
, CTRL
);
2023 /* Because we didn't get link via the internal auto-negotiation
2024 * mechanism (we either forced link or we got link via PHY
2025 * auto-neg), we have to manually enable/disable transmit an
2026 * receive flow control.
2028 * The "Case" statement below enables/disable flow control
2029 * according to the "hw->fc" parameter.
2031 * The possible values of the "fc" parameter are:
2032 * 0: Flow control is completely disabled
2033 * 1: Rx flow control is enabled (we can receive pause
2034 * frames but not send pause frames).
2035 * 2: Tx flow control is enabled (we can send pause frames
2036 * frames but we do not receive pause frames).
2037 * 3: Both Rx and TX flow control (symmetric) is enabled.
2038 * other: No other values should be possible at this point.
2043 ctrl
&= (~(E1000_CTRL_TFCE
| E1000_CTRL_RFCE
));
2045 case e1000_fc_rx_pause
:
2046 ctrl
&= (~E1000_CTRL_TFCE
);
2047 ctrl
|= E1000_CTRL_RFCE
;
2049 case e1000_fc_tx_pause
:
2050 ctrl
&= (~E1000_CTRL_RFCE
);
2051 ctrl
|= E1000_CTRL_TFCE
;
2054 ctrl
|= (E1000_CTRL_TFCE
| E1000_CTRL_RFCE
);
2057 DEBUGOUT("Flow control param set incorrectly\n");
2058 return -E1000_ERR_CONFIG
;
2061 /* Disable TX Flow Control for 82542 (rev 2.0) */
2062 if(hw
->mac_type
== e1000_82542_rev2_0
)
2063 ctrl
&= (~E1000_CTRL_TFCE
);
2065 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2066 return E1000_SUCCESS
;
2069 /******************************************************************************
2070 * Configures flow control settings after link is established
2072 * hw - Struct containing variables accessed by shared code
2074 * Should be called immediately after a valid link has been established.
2075 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2076 * and autonegotiation is enabled, the MAC flow control settings will be set
2077 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2078 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2079 *****************************************************************************/
2081 e1000_config_fc_after_link_up(struct e1000_hw
*hw
)
2084 uint16_t mii_status_reg
;
2085 uint16_t mii_nway_adv_reg
;
2086 uint16_t mii_nway_lp_ability_reg
;
2090 DEBUGFUNC("e1000_config_fc_after_link_up");
2092 /* Check for the case where we have fiber media and auto-neg failed
2093 * so we had to force link. In this case, we need to force the
2094 * configuration of the MAC to match the "fc" parameter.
2096 if(((hw
->media_type
== e1000_media_type_fiber
) && (hw
->autoneg_failed
)) ||
2097 ((hw
->media_type
== e1000_media_type_internal_serdes
) && (hw
->autoneg_failed
)) ||
2098 ((hw
->media_type
== e1000_media_type_copper
) && (!hw
->autoneg
))) {
2099 ret_val
= e1000_force_mac_fc(hw
);
2101 DEBUGOUT("Error forcing flow control settings\n");
2106 /* Check for the case where we have copper media and auto-neg is
2107 * enabled. In this case, we need to check and see if Auto-Neg
2108 * has completed, and if so, how the PHY and link partner has
2109 * flow control configured.
2111 if((hw
->media_type
== e1000_media_type_copper
) && hw
->autoneg
) {
2112 /* Read the MII Status Register and check to see if AutoNeg
2113 * has completed. We read this twice because this reg has
2114 * some "sticky" (latched) bits.
2116 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
2119 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
2123 if(mii_status_reg
& MII_SR_AUTONEG_COMPLETE
) {
2124 /* The AutoNeg process has completed, so we now need to
2125 * read both the Auto Negotiation Advertisement Register
2126 * (Address 4) and the Auto_Negotiation Base Page Ability
2127 * Register (Address 5) to determine how flow control was
2130 ret_val
= e1000_read_phy_reg(hw
, PHY_AUTONEG_ADV
,
2134 ret_val
= e1000_read_phy_reg(hw
, PHY_LP_ABILITY
,
2135 &mii_nway_lp_ability_reg
);
2139 /* Two bits in the Auto Negotiation Advertisement Register
2140 * (Address 4) and two bits in the Auto Negotiation Base
2141 * Page Ability Register (Address 5) determine flow control
2142 * for both the PHY and the link partner. The following
2143 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2144 * 1999, describes these PAUSE resolution bits and how flow
2145 * control is determined based upon these settings.
2146 * NOTE: DC = Don't Care
2148 * LOCAL DEVICE | LINK PARTNER
2149 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2150 *-------|---------|-------|---------|--------------------
2151 * 0 | 0 | DC | DC | e1000_fc_none
2152 * 0 | 1 | 0 | DC | e1000_fc_none
2153 * 0 | 1 | 1 | 0 | e1000_fc_none
2154 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2155 * 1 | 0 | 0 | DC | e1000_fc_none
2156 * 1 | DC | 1 | DC | e1000_fc_full
2157 * 1 | 1 | 0 | 0 | e1000_fc_none
2158 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2161 /* Are both PAUSE bits set to 1? If so, this implies
2162 * Symmetric Flow Control is enabled at both ends. The
2163 * ASM_DIR bits are irrelevant per the spec.
2165 * For Symmetric Flow Control:
2167 * LOCAL DEVICE | LINK PARTNER
2168 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2169 *-------|---------|-------|---------|--------------------
2170 * 1 | DC | 1 | DC | e1000_fc_full
2173 if((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
2174 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
)) {
2175 /* Now we need to check if the user selected RX ONLY
2176 * of pause frames. In this case, we had to advertise
2177 * FULL flow control because we could not advertise RX
2178 * ONLY. Hence, we must now check to see if we need to
2179 * turn OFF the TRANSMISSION of PAUSE frames.
2181 if(hw
->original_fc
== e1000_fc_full
) {
2182 hw
->fc
= e1000_fc_full
;
2183 DEBUGOUT("Flow Control = FULL.\r\n");
2185 hw
->fc
= e1000_fc_rx_pause
;
2186 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2189 /* For receiving PAUSE frames ONLY.
2191 * LOCAL DEVICE | LINK PARTNER
2192 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2193 *-------|---------|-------|---------|--------------------
2194 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2197 else if(!(mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
2198 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
2199 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
2200 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
2201 hw
->fc
= e1000_fc_tx_pause
;
2202 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
2204 /* For transmitting PAUSE frames ONLY.
2206 * LOCAL DEVICE | LINK PARTNER
2207 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2208 *-------|---------|-------|---------|--------------------
2209 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2212 else if((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
2213 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
2214 !(mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
2215 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
2216 hw
->fc
= e1000_fc_rx_pause
;
2217 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2219 /* Per the IEEE spec, at this point flow control should be
2220 * disabled. However, we want to consider that we could
2221 * be connected to a legacy switch that doesn't advertise
2222 * desired flow control, but can be forced on the link
2223 * partner. So if we advertised no flow control, that is
2224 * what we will resolve to. If we advertised some kind of
2225 * receive capability (Rx Pause Only or Full Flow Control)
2226 * and the link partner advertised none, we will configure
2227 * ourselves to enable Rx Flow Control only. We can do
2228 * this safely for two reasons: If the link partner really
2229 * didn't want flow control enabled, and we enable Rx, no
2230 * harm done since we won't be receiving any PAUSE frames
2231 * anyway. If the intent on the link partner was to have
2232 * flow control enabled, then by us enabling RX only, we
2233 * can at least receive pause frames and process them.
2234 * This is a good idea because in most cases, since we are
2235 * predominantly a server NIC, more times than not we will
2236 * be asked to delay transmission of packets than asking
2237 * our link partner to pause transmission of frames.
2239 else if((hw
->original_fc
== e1000_fc_none
||
2240 hw
->original_fc
== e1000_fc_tx_pause
) ||
2241 hw
->fc_strict_ieee
) {
2242 hw
->fc
= e1000_fc_none
;
2243 DEBUGOUT("Flow Control = NONE.\r\n");
2245 hw
->fc
= e1000_fc_rx_pause
;
2246 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2249 /* Now we need to do one last check... If we auto-
2250 * negotiated to HALF DUPLEX, flow control should not be
2251 * enabled per IEEE 802.3 spec.
2253 ret_val
= e1000_get_speed_and_duplex(hw
, &speed
, &duplex
);
2255 DEBUGOUT("Error getting link speed and duplex\n");
2259 if(duplex
== HALF_DUPLEX
)
2260 hw
->fc
= e1000_fc_none
;
2262 /* Now we call a subroutine to actually force the MAC
2263 * controller to use the correct flow control settings.
2265 ret_val
= e1000_force_mac_fc(hw
);
2267 DEBUGOUT("Error forcing flow control settings\n");
2271 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
2274 return E1000_SUCCESS
;
2277 /******************************************************************************
2278 * Checks to see if the link status of the hardware has changed.
2280 * hw - Struct containing variables accessed by shared code
2282 * Called by any function that needs to check the link status of the adapter.
2283 *****************************************************************************/
2285 e1000_check_for_link(struct e1000_hw
*hw
)
2292 uint32_t signal
= 0;
2296 DEBUGFUNC("e1000_check_for_link");
2298 ctrl
= E1000_READ_REG(hw
, CTRL
);
2299 status
= E1000_READ_REG(hw
, STATUS
);
2301 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2302 * set when the optics detect a signal. On older adapters, it will be
2303 * cleared when there is a signal. This applies to fiber media only.
2305 if((hw
->media_type
== e1000_media_type_fiber
) ||
2306 (hw
->media_type
== e1000_media_type_internal_serdes
)) {
2307 rxcw
= E1000_READ_REG(hw
, RXCW
);
2309 if(hw
->media_type
== e1000_media_type_fiber
) {
2310 signal
= (hw
->mac_type
> e1000_82544
) ? E1000_CTRL_SWDPIN1
: 0;
2311 if(status
& E1000_STATUS_LU
)
2312 hw
->get_link_status
= FALSE
;
2316 /* If we have a copper PHY then we only want to go out to the PHY
2317 * registers to see if Auto-Neg has completed and/or if our link
2318 * status has changed. The get_link_status flag will be set if we
2319 * receive a Link Status Change interrupt or we have Rx Sequence
2322 if((hw
->media_type
== e1000_media_type_copper
) && hw
->get_link_status
) {
2323 /* First we want to see if the MII Status Register reports
2324 * link. If so, then we want to get the current speed/duplex
2326 * Read the register twice since the link bit is sticky.
2328 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
2331 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
2335 if(phy_data
& MII_SR_LINK_STATUS
) {
2336 hw
->get_link_status
= FALSE
;
2337 /* Check if there was DownShift, must be checked immediately after
2339 e1000_check_downshift(hw
);
2341 /* If we are on 82544 or 82543 silicon and speed/duplex
2342 * are forced to 10H or 10F, then we will implement the polarity
2343 * reversal workaround. We disable interrupts first, and upon
2344 * returning, place the devices interrupt state to its previous
2345 * value except for the link status change interrupt which will
2346 * happen due to the execution of this workaround.
2349 if((hw
->mac_type
== e1000_82544
|| hw
->mac_type
== e1000_82543
) &&
2351 (hw
->forced_speed_duplex
== e1000_10_full
||
2352 hw
->forced_speed_duplex
== e1000_10_half
)) {
2353 E1000_WRITE_REG(hw
, IMC
, 0xffffffff);
2354 ret_val
= e1000_polarity_reversal_workaround(hw
);
2355 icr
= E1000_READ_REG(hw
, ICR
);
2356 E1000_WRITE_REG(hw
, ICS
, (icr
& ~E1000_ICS_LSC
));
2357 E1000_WRITE_REG(hw
, IMS
, IMS_ENABLE_MASK
);
2361 /* No link detected */
2362 e1000_config_dsp_after_link_change(hw
, FALSE
);
2366 /* If we are forcing speed/duplex, then we simply return since
2367 * we have already determined whether we have link or not.
2369 if(!hw
->autoneg
) return -E1000_ERR_CONFIG
;
2371 /* optimize the dsp settings for the igp phy */
2372 e1000_config_dsp_after_link_change(hw
, TRUE
);
2374 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2375 * have Si on board that is 82544 or newer, Auto
2376 * Speed Detection takes care of MAC speed/duplex
2377 * configuration. So we only need to configure Collision
2378 * Distance in the MAC. Otherwise, we need to force
2379 * speed/duplex on the MAC to the current PHY speed/duplex
2382 if(hw
->mac_type
>= e1000_82544
)
2383 e1000_config_collision_dist(hw
);
2385 ret_val
= e1000_config_mac_to_phy(hw
);
2387 DEBUGOUT("Error configuring MAC to PHY settings\n");
2392 /* Configure Flow Control now that Auto-Neg has completed. First, we
2393 * need to restore the desired flow control settings because we may
2394 * have had to re-autoneg with a different link partner.
2396 ret_val
= e1000_config_fc_after_link_up(hw
);
2398 DEBUGOUT("Error configuring flow control\n");
2402 /* At this point we know that we are on copper and we have
2403 * auto-negotiated link. These are conditions for checking the link
2404 * partner capability register. We use the link speed to determine if
2405 * TBI compatibility needs to be turned on or off. If the link is not
2406 * at gigabit speed, then TBI compatibility is not needed. If we are
2407 * at gigabit speed, we turn on TBI compatibility.
2409 if(hw
->tbi_compatibility_en
) {
2410 uint16_t speed
, duplex
;
2411 e1000_get_speed_and_duplex(hw
, &speed
, &duplex
);
2412 if(speed
!= SPEED_1000
) {
2413 /* If link speed is not set to gigabit speed, we do not need
2414 * to enable TBI compatibility.
2416 if(hw
->tbi_compatibility_on
) {
2417 /* If we previously were in the mode, turn it off. */
2418 rctl
= E1000_READ_REG(hw
, RCTL
);
2419 rctl
&= ~E1000_RCTL_SBP
;
2420 E1000_WRITE_REG(hw
, RCTL
, rctl
);
2421 hw
->tbi_compatibility_on
= FALSE
;
2424 /* If TBI compatibility is was previously off, turn it on. For
2425 * compatibility with a TBI link partner, we will store bad
2426 * packets. Some frames have an additional byte on the end and
2427 * will look like CRC errors to to the hardware.
2429 if(!hw
->tbi_compatibility_on
) {
2430 hw
->tbi_compatibility_on
= TRUE
;
2431 rctl
= E1000_READ_REG(hw
, RCTL
);
2432 rctl
|= E1000_RCTL_SBP
;
2433 E1000_WRITE_REG(hw
, RCTL
, rctl
);
2438 /* If we don't have link (auto-negotiation failed or link partner cannot
2439 * auto-negotiate), the cable is plugged in (we have signal), and our
2440 * link partner is not trying to auto-negotiate with us (we are receiving
2441 * idles or data), we need to force link up. We also need to give
2442 * auto-negotiation time to complete, in case the cable was just plugged
2443 * in. The autoneg_failed flag does this.
2445 else if((((hw
->media_type
== e1000_media_type_fiber
) &&
2446 ((ctrl
& E1000_CTRL_SWDPIN1
) == signal
)) ||
2447 (hw
->media_type
== e1000_media_type_internal_serdes
)) &&
2448 (!(status
& E1000_STATUS_LU
)) &&
2449 (!(rxcw
& E1000_RXCW_C
))) {
2450 if(hw
->autoneg_failed
== 0) {
2451 hw
->autoneg_failed
= 1;
2454 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2456 /* Disable auto-negotiation in the TXCW register */
2457 E1000_WRITE_REG(hw
, TXCW
, (hw
->txcw
& ~E1000_TXCW_ANE
));
2459 /* Force link-up and also force full-duplex. */
2460 ctrl
= E1000_READ_REG(hw
, CTRL
);
2461 ctrl
|= (E1000_CTRL_SLU
| E1000_CTRL_FD
);
2462 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2464 /* Configure Flow Control after forcing link up. */
2465 ret_val
= e1000_config_fc_after_link_up(hw
);
2467 DEBUGOUT("Error configuring flow control\n");
2471 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2472 * auto-negotiation in the TXCW register and disable forced link in the
2473 * Device Control register in an attempt to auto-negotiate with our link
2476 else if(((hw
->media_type
== e1000_media_type_fiber
) ||
2477 (hw
->media_type
== e1000_media_type_internal_serdes
)) &&
2478 (ctrl
& E1000_CTRL_SLU
) && (rxcw
& E1000_RXCW_C
)) {
2479 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2480 E1000_WRITE_REG(hw
, TXCW
, hw
->txcw
);
2481 E1000_WRITE_REG(hw
, CTRL
, (ctrl
& ~E1000_CTRL_SLU
));
2483 hw
->serdes_link_down
= FALSE
;
2485 /* If we force link for non-auto-negotiation switch, check link status
2486 * based on MAC synchronization for internal serdes media type.
2488 else if((hw
->media_type
== e1000_media_type_internal_serdes
) &&
2489 !(E1000_TXCW_ANE
& E1000_READ_REG(hw
, TXCW
))) {
2490 /* SYNCH bit and IV bit are sticky. */
2492 if(E1000_RXCW_SYNCH
& E1000_READ_REG(hw
, RXCW
)) {
2493 if(!(rxcw
& E1000_RXCW_IV
)) {
2494 hw
->serdes_link_down
= FALSE
;
2495 DEBUGOUT("SERDES: Link is up.\n");
2498 hw
->serdes_link_down
= TRUE
;
2499 DEBUGOUT("SERDES: Link is down.\n");
2502 if((hw
->media_type
== e1000_media_type_internal_serdes
) &&
2503 (E1000_TXCW_ANE
& E1000_READ_REG(hw
, TXCW
))) {
2504 hw
->serdes_link_down
= !(E1000_STATUS_LU
& E1000_READ_REG(hw
, STATUS
));
2506 return E1000_SUCCESS
;
2509 /******************************************************************************
2510 * Detects the current speed and duplex settings of the hardware.
2512 * hw - Struct containing variables accessed by shared code
2513 * speed - Speed of the connection
2514 * duplex - Duplex setting of the connection
2515 *****************************************************************************/
2517 e1000_get_speed_and_duplex(struct e1000_hw
*hw
,
2525 DEBUGFUNC("e1000_get_speed_and_duplex");
2527 if(hw
->mac_type
>= e1000_82543
) {
2528 status
= E1000_READ_REG(hw
, STATUS
);
2529 if(status
& E1000_STATUS_SPEED_1000
) {
2530 *speed
= SPEED_1000
;
2531 DEBUGOUT("1000 Mbs, ");
2532 } else if(status
& E1000_STATUS_SPEED_100
) {
2534 DEBUGOUT("100 Mbs, ");
2537 DEBUGOUT("10 Mbs, ");
2540 if(status
& E1000_STATUS_FD
) {
2541 *duplex
= FULL_DUPLEX
;
2542 DEBUGOUT("Full Duplex\r\n");
2544 *duplex
= HALF_DUPLEX
;
2545 DEBUGOUT(" Half Duplex\r\n");
2548 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2549 *speed
= SPEED_1000
;
2550 *duplex
= FULL_DUPLEX
;
2553 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2554 * if it is operating at half duplex. Here we set the duplex settings to
2555 * match the duplex in the link partner's capabilities.
2557 if(hw
->phy_type
== e1000_phy_igp
&& hw
->speed_downgraded
) {
2558 ret_val
= e1000_read_phy_reg(hw
, PHY_AUTONEG_EXP
, &phy_data
);
2562 if(!(phy_data
& NWAY_ER_LP_NWAY_CAPS
))
2563 *duplex
= HALF_DUPLEX
;
2565 ret_val
= e1000_read_phy_reg(hw
, PHY_LP_ABILITY
, &phy_data
);
2568 if((*speed
== SPEED_100
&& !(phy_data
& NWAY_LPAR_100TX_FD_CAPS
)) ||
2569 (*speed
== SPEED_10
&& !(phy_data
& NWAY_LPAR_10T_FD_CAPS
)))
2570 *duplex
= HALF_DUPLEX
;
2574 return E1000_SUCCESS
;
2577 /******************************************************************************
2578 * Blocks until autoneg completes or times out (~4.5 seconds)
2580 * hw - Struct containing variables accessed by shared code
2581 ******************************************************************************/
2583 e1000_wait_autoneg(struct e1000_hw
*hw
)
2589 DEBUGFUNC("e1000_wait_autoneg");
2590 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2592 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2593 for(i
= PHY_AUTO_NEG_TIME
; i
> 0; i
--) {
2594 /* Read the MII Status Register and wait for Auto-Neg
2595 * Complete bit to be set.
2597 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
2600 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
2603 if(phy_data
& MII_SR_AUTONEG_COMPLETE
) {
2604 return E1000_SUCCESS
;
2608 return E1000_SUCCESS
;
2611 /******************************************************************************
2612 * Raises the Management Data Clock
2614 * hw - Struct containing variables accessed by shared code
2615 * ctrl - Device control register's current value
2616 ******************************************************************************/
2618 e1000_raise_mdi_clk(struct e1000_hw
*hw
,
2621 /* Raise the clock input to the Management Data Clock (by setting the MDC
2622 * bit), and then delay 10 microseconds.
2624 E1000_WRITE_REG(hw
, CTRL
, (*ctrl
| E1000_CTRL_MDC
));
2625 E1000_WRITE_FLUSH(hw
);
2629 /******************************************************************************
2630 * Lowers the Management Data Clock
2632 * hw - Struct containing variables accessed by shared code
2633 * ctrl - Device control register's current value
2634 ******************************************************************************/
2636 e1000_lower_mdi_clk(struct e1000_hw
*hw
,
2639 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2640 * bit), and then delay 10 microseconds.
2642 E1000_WRITE_REG(hw
, CTRL
, (*ctrl
& ~E1000_CTRL_MDC
));
2643 E1000_WRITE_FLUSH(hw
);
2647 /******************************************************************************
2648 * Shifts data bits out to the PHY
2650 * hw - Struct containing variables accessed by shared code
2651 * data - Data to send out to the PHY
2652 * count - Number of bits to shift out
2654 * Bits are shifted out in MSB to LSB order.
2655 ******************************************************************************/
2657 e1000_shift_out_mdi_bits(struct e1000_hw
*hw
,
2664 /* We need to shift "count" number of bits out to the PHY. So, the value
2665 * in the "data" parameter will be shifted out to the PHY one bit at a
2666 * time. In order to do this, "data" must be broken down into bits.
2669 mask
<<= (count
- 1);
2671 ctrl
= E1000_READ_REG(hw
, CTRL
);
2673 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2674 ctrl
|= (E1000_CTRL_MDIO_DIR
| E1000_CTRL_MDC_DIR
);
2677 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2678 * then raising and lowering the Management Data Clock. A "0" is
2679 * shifted out to the PHY by setting the MDIO bit to "0" and then
2680 * raising and lowering the clock.
2682 if(data
& mask
) ctrl
|= E1000_CTRL_MDIO
;
2683 else ctrl
&= ~E1000_CTRL_MDIO
;
2685 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2686 E1000_WRITE_FLUSH(hw
);
2690 e1000_raise_mdi_clk(hw
, &ctrl
);
2691 e1000_lower_mdi_clk(hw
, &ctrl
);
2697 /******************************************************************************
2698 * Shifts data bits in from the PHY
2700 * hw - Struct containing variables accessed by shared code
2702 * Bits are shifted in in MSB to LSB order.
2703 ******************************************************************************/
2705 e1000_shift_in_mdi_bits(struct e1000_hw
*hw
)
2711 /* In order to read a register from the PHY, we need to shift in a total
2712 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2713 * to avoid contention on the MDIO pin when a read operation is performed.
2714 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2715 * by raising the input to the Management Data Clock (setting the MDC bit),
2716 * and then reading the value of the MDIO bit.
2718 ctrl
= E1000_READ_REG(hw
, CTRL
);
2720 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2721 ctrl
&= ~E1000_CTRL_MDIO_DIR
;
2722 ctrl
&= ~E1000_CTRL_MDIO
;
2724 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2725 E1000_WRITE_FLUSH(hw
);
2727 /* Raise and Lower the clock before reading in the data. This accounts for
2728 * the turnaround bits. The first clock occurred when we clocked out the
2729 * last bit of the Register Address.
2731 e1000_raise_mdi_clk(hw
, &ctrl
);
2732 e1000_lower_mdi_clk(hw
, &ctrl
);
2734 for(data
= 0, i
= 0; i
< 16; i
++) {
2736 e1000_raise_mdi_clk(hw
, &ctrl
);
2737 ctrl
= E1000_READ_REG(hw
, CTRL
);
2738 /* Check to see if we shifted in a "1". */
2739 if(ctrl
& E1000_CTRL_MDIO
) data
|= 1;
2740 e1000_lower_mdi_clk(hw
, &ctrl
);
2743 e1000_raise_mdi_clk(hw
, &ctrl
);
2744 e1000_lower_mdi_clk(hw
, &ctrl
);
2749 /*****************************************************************************
2750 * Reads the value from a PHY register, if the value is on a specific non zero
2751 * page, sets the page first.
2752 * hw - Struct containing variables accessed by shared code
2753 * reg_addr - address of the PHY register to read
2754 ******************************************************************************/
2756 e1000_read_phy_reg(struct e1000_hw
*hw
,
2762 DEBUGFUNC("e1000_read_phy_reg");
2764 if((hw
->phy_type
== e1000_phy_igp
||
2765 hw
->phy_type
== e1000_phy_igp_2
) &&
2766 (reg_addr
> MAX_PHY_MULTI_PAGE_REG
)) {
2767 ret_val
= e1000_write_phy_reg_ex(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2768 (uint16_t)reg_addr
);
2774 ret_val
= e1000_read_phy_reg_ex(hw
, MAX_PHY_REG_ADDRESS
& reg_addr
,
2781 e1000_read_phy_reg_ex(struct e1000_hw
*hw
,
2787 const uint32_t phy_addr
= 1;
2789 DEBUGFUNC("e1000_read_phy_reg_ex");
2791 if(reg_addr
> MAX_PHY_REG_ADDRESS
) {
2792 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr
);
2793 return -E1000_ERR_PARAM
;
2796 if(hw
->mac_type
> e1000_82543
) {
2797 /* Set up Op-code, Phy Address, and register address in the MDI
2798 * Control register. The MAC will take care of interfacing with the
2799 * PHY to retrieve the desired data.
2801 mdic
= ((reg_addr
<< E1000_MDIC_REG_SHIFT
) |
2802 (phy_addr
<< E1000_MDIC_PHY_SHIFT
) |
2803 (E1000_MDIC_OP_READ
));
2805 E1000_WRITE_REG(hw
, MDIC
, mdic
);
2807 /* Poll the ready bit to see if the MDI read completed */
2808 for(i
= 0; i
< 64; i
++) {
2810 mdic
= E1000_READ_REG(hw
, MDIC
);
2811 if(mdic
& E1000_MDIC_READY
) break;
2813 if(!(mdic
& E1000_MDIC_READY
)) {
2814 DEBUGOUT("MDI Read did not complete\n");
2815 return -E1000_ERR_PHY
;
2817 if(mdic
& E1000_MDIC_ERROR
) {
2818 DEBUGOUT("MDI Error\n");
2819 return -E1000_ERR_PHY
;
2821 *phy_data
= (uint16_t) mdic
;
2823 /* We must first send a preamble through the MDIO pin to signal the
2824 * beginning of an MII instruction. This is done by sending 32
2825 * consecutive "1" bits.
2827 e1000_shift_out_mdi_bits(hw
, PHY_PREAMBLE
, PHY_PREAMBLE_SIZE
);
2829 /* Now combine the next few fields that are required for a read
2830 * operation. We use this method instead of calling the
2831 * e1000_shift_out_mdi_bits routine five different times. The format of
2832 * a MII read instruction consists of a shift out of 14 bits and is
2833 * defined as follows:
2834 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2835 * followed by a shift in of 18 bits. This first two bits shifted in
2836 * are TurnAround bits used to avoid contention on the MDIO pin when a
2837 * READ operation is performed. These two bits are thrown away
2838 * followed by a shift in of 16 bits which contains the desired data.
2840 mdic
= ((reg_addr
) | (phy_addr
<< 5) |
2841 (PHY_OP_READ
<< 10) | (PHY_SOF
<< 12));
2843 e1000_shift_out_mdi_bits(hw
, mdic
, 14);
2845 /* Now that we've shifted out the read command to the MII, we need to
2846 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2849 *phy_data
= e1000_shift_in_mdi_bits(hw
);
2851 return E1000_SUCCESS
;
2854 /******************************************************************************
2855 * Writes a value to a PHY register
2857 * hw - Struct containing variables accessed by shared code
2858 * reg_addr - address of the PHY register to write
2859 * data - data to write to the PHY
2860 ******************************************************************************/
2862 e1000_write_phy_reg(struct e1000_hw
*hw
,
2868 DEBUGFUNC("e1000_write_phy_reg");
2870 if((hw
->phy_type
== e1000_phy_igp
||
2871 hw
->phy_type
== e1000_phy_igp_2
) &&
2872 (reg_addr
> MAX_PHY_MULTI_PAGE_REG
)) {
2873 ret_val
= e1000_write_phy_reg_ex(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2874 (uint16_t)reg_addr
);
2880 ret_val
= e1000_write_phy_reg_ex(hw
, MAX_PHY_REG_ADDRESS
& reg_addr
,
2887 e1000_write_phy_reg_ex(struct e1000_hw
*hw
,
2893 const uint32_t phy_addr
= 1;
2895 DEBUGFUNC("e1000_write_phy_reg_ex");
2897 if(reg_addr
> MAX_PHY_REG_ADDRESS
) {
2898 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr
);
2899 return -E1000_ERR_PARAM
;
2902 if(hw
->mac_type
> e1000_82543
) {
2903 /* Set up Op-code, Phy Address, register address, and data intended
2904 * for the PHY register in the MDI Control register. The MAC will take
2905 * care of interfacing with the PHY to send the desired data.
2907 mdic
= (((uint32_t) phy_data
) |
2908 (reg_addr
<< E1000_MDIC_REG_SHIFT
) |
2909 (phy_addr
<< E1000_MDIC_PHY_SHIFT
) |
2910 (E1000_MDIC_OP_WRITE
));
2912 E1000_WRITE_REG(hw
, MDIC
, mdic
);
2914 /* Poll the ready bit to see if the MDI read completed */
2915 for(i
= 0; i
< 640; i
++) {
2917 mdic
= E1000_READ_REG(hw
, MDIC
);
2918 if(mdic
& E1000_MDIC_READY
) break;
2920 if(!(mdic
& E1000_MDIC_READY
)) {
2921 DEBUGOUT("MDI Write did not complete\n");
2922 return -E1000_ERR_PHY
;
2925 /* We'll need to use the SW defined pins to shift the write command
2926 * out to the PHY. We first send a preamble to the PHY to signal the
2927 * beginning of the MII instruction. This is done by sending 32
2928 * consecutive "1" bits.
2930 e1000_shift_out_mdi_bits(hw
, PHY_PREAMBLE
, PHY_PREAMBLE_SIZE
);
2932 /* Now combine the remaining required fields that will indicate a
2933 * write operation. We use this method instead of calling the
2934 * e1000_shift_out_mdi_bits routine for each field in the command. The
2935 * format of a MII write instruction is as follows:
2936 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2938 mdic
= ((PHY_TURNAROUND
) | (reg_addr
<< 2) | (phy_addr
<< 7) |
2939 (PHY_OP_WRITE
<< 12) | (PHY_SOF
<< 14));
2941 mdic
|= (uint32_t) phy_data
;
2943 e1000_shift_out_mdi_bits(hw
, mdic
, 32);
2946 return E1000_SUCCESS
;
2950 /******************************************************************************
2951 * Returns the PHY to the power-on reset state
2953 * hw - Struct containing variables accessed by shared code
2954 ******************************************************************************/
2956 e1000_phy_hw_reset(struct e1000_hw
*hw
)
2958 uint32_t ctrl
, ctrl_ext
;
2962 DEBUGFUNC("e1000_phy_hw_reset");
2964 /* In the case of the phy reset being blocked, it's not an error, we
2965 * simply return success without performing the reset. */
2966 ret_val
= e1000_check_phy_reset_block(hw
);
2968 return E1000_SUCCESS
;
2970 DEBUGOUT("Resetting Phy...\n");
2972 if(hw
->mac_type
> e1000_82543
) {
2973 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2974 * bit. Then, take it out of reset.
2975 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
2976 * and deassert. For e1000_82571 hardware and later, we instead delay
2977 * for 10ms after the deassertion.
2979 ctrl
= E1000_READ_REG(hw
, CTRL
);
2980 E1000_WRITE_REG(hw
, CTRL
, ctrl
| E1000_CTRL_PHY_RST
);
2981 E1000_WRITE_FLUSH(hw
);
2983 if (hw
->mac_type
< e1000_82571
)
2988 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
2989 E1000_WRITE_FLUSH(hw
);
2991 if (hw
->mac_type
>= e1000_82571
)
2994 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2995 * bit to put the PHY into reset. Then, take it out of reset.
2997 ctrl_ext
= E1000_READ_REG(hw
, CTRL_EXT
);
2998 ctrl_ext
|= E1000_CTRL_EXT_SDP4_DIR
;
2999 ctrl_ext
&= ~E1000_CTRL_EXT_SDP4_DATA
;
3000 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
3001 E1000_WRITE_FLUSH(hw
);
3003 ctrl_ext
|= E1000_CTRL_EXT_SDP4_DATA
;
3004 E1000_WRITE_REG(hw
, CTRL_EXT
, ctrl_ext
);
3005 E1000_WRITE_FLUSH(hw
);
3009 if((hw
->mac_type
== e1000_82541
) || (hw
->mac_type
== e1000_82547
)) {
3010 /* Configure activity LED after PHY reset */
3011 led_ctrl
= E1000_READ_REG(hw
, LEDCTL
);
3012 led_ctrl
&= IGP_ACTIVITY_LED_MASK
;
3013 led_ctrl
|= (IGP_ACTIVITY_LED_ENABLE
| IGP_LED3_MODE
);
3014 E1000_WRITE_REG(hw
, LEDCTL
, led_ctrl
);
3017 /* Wait for FW to finish PHY configuration. */
3018 ret_val
= e1000_get_phy_cfg_done(hw
);
3023 /******************************************************************************
3026 * hw - Struct containing variables accessed by shared code
3028 * Sets bit 15 of the MII Control regiser
3029 ******************************************************************************/
3031 e1000_phy_reset(struct e1000_hw
*hw
)
3036 DEBUGFUNC("e1000_phy_reset");
3038 /* In the case of the phy reset being blocked, it's not an error, we
3039 * simply return success without performing the reset. */
3040 ret_val
= e1000_check_phy_reset_block(hw
);
3042 return E1000_SUCCESS
;
3044 switch (hw
->mac_type
) {
3045 case e1000_82541_rev_2
:
3048 ret_val
= e1000_phy_hw_reset(hw
);
3053 ret_val
= e1000_read_phy_reg(hw
, PHY_CTRL
, &phy_data
);
3057 phy_data
|= MII_CR_RESET
;
3058 ret_val
= e1000_write_phy_reg(hw
, PHY_CTRL
, phy_data
);
3066 if(hw
->phy_type
== e1000_phy_igp
|| hw
->phy_type
== e1000_phy_igp_2
)
3067 e1000_phy_init_script(hw
);
3069 return E1000_SUCCESS
;
3072 /******************************************************************************
3073 * Probes the expected PHY address for known PHY IDs
3075 * hw - Struct containing variables accessed by shared code
3076 ******************************************************************************/
3078 e1000_detect_gig_phy(struct e1000_hw
*hw
)
3080 int32_t phy_init_status
, ret_val
;
3081 uint16_t phy_id_high
, phy_id_low
;
3082 boolean_t match
= FALSE
;
3084 DEBUGFUNC("e1000_detect_gig_phy");
3086 /* The 82571 firmware may still be configuring the PHY. In this
3087 * case, we cannot access the PHY until the configuration is done. So
3088 * we explicitly set the PHY values. */
3089 if(hw
->mac_type
== e1000_82571
||
3090 hw
->mac_type
== e1000_82572
) {
3091 hw
->phy_id
= IGP01E1000_I_PHY_ID
;
3092 hw
->phy_type
= e1000_phy_igp_2
;
3093 return E1000_SUCCESS
;
3096 /* Read the PHY ID Registers to identify which PHY is onboard. */
3097 ret_val
= e1000_read_phy_reg(hw
, PHY_ID1
, &phy_id_high
);
3101 hw
->phy_id
= (uint32_t) (phy_id_high
<< 16);
3103 ret_val
= e1000_read_phy_reg(hw
, PHY_ID2
, &phy_id_low
);
3107 hw
->phy_id
|= (uint32_t) (phy_id_low
& PHY_REVISION_MASK
);
3108 hw
->phy_revision
= (uint32_t) phy_id_low
& ~PHY_REVISION_MASK
;
3110 switch(hw
->mac_type
) {
3112 if(hw
->phy_id
== M88E1000_E_PHY_ID
) match
= TRUE
;
3115 if(hw
->phy_id
== M88E1000_I_PHY_ID
) match
= TRUE
;
3119 case e1000_82545_rev_3
:
3121 case e1000_82546_rev_3
:
3122 if(hw
->phy_id
== M88E1011_I_PHY_ID
) match
= TRUE
;
3125 case e1000_82541_rev_2
:
3127 case e1000_82547_rev_2
:
3128 if(hw
->phy_id
== IGP01E1000_I_PHY_ID
) match
= TRUE
;
3131 if(hw
->phy_id
== M88E1111_I_PHY_ID
) match
= TRUE
;
3134 DEBUGOUT1("Invalid MAC type %d\n", hw
->mac_type
);
3135 return -E1000_ERR_CONFIG
;
3137 phy_init_status
= e1000_set_phy_type(hw
);
3139 if ((match
) && (phy_init_status
== E1000_SUCCESS
)) {
3140 DEBUGOUT1("PHY ID 0x%X detected\n", hw
->phy_id
);
3141 return E1000_SUCCESS
;
3143 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw
->phy_id
);
3144 return -E1000_ERR_PHY
;
3147 /******************************************************************************
3148 * Resets the PHY's DSP
3150 * hw - Struct containing variables accessed by shared code
3151 ******************************************************************************/
3153 e1000_phy_reset_dsp(struct e1000_hw
*hw
)
3156 DEBUGFUNC("e1000_phy_reset_dsp");
3159 ret_val
= e1000_write_phy_reg(hw
, 29, 0x001d);
3161 ret_val
= e1000_write_phy_reg(hw
, 30, 0x00c1);
3163 ret_val
= e1000_write_phy_reg(hw
, 30, 0x0000);
3165 ret_val
= E1000_SUCCESS
;
3171 /******************************************************************************
3172 * Get PHY information from various PHY registers for igp PHY only.
3174 * hw - Struct containing variables accessed by shared code
3175 * phy_info - PHY information structure
3176 ******************************************************************************/
3178 e1000_phy_igp_get_info(struct e1000_hw
*hw
,
3179 struct e1000_phy_info
*phy_info
)
3182 uint16_t phy_data
, polarity
, min_length
, max_length
, average
;
3184 DEBUGFUNC("e1000_phy_igp_get_info");
3186 /* The downshift status is checked only once, after link is established,
3187 * and it stored in the hw->speed_downgraded parameter. */
3188 phy_info
->downshift
= (e1000_downshift
)hw
->speed_downgraded
;
3190 /* IGP01E1000 does not need to support it. */
3191 phy_info
->extended_10bt_distance
= e1000_10bt_ext_dist_enable_normal
;
3193 /* IGP01E1000 always correct polarity reversal */
3194 phy_info
->polarity_correction
= e1000_polarity_reversal_enabled
;
3196 /* Check polarity status */
3197 ret_val
= e1000_check_polarity(hw
, &polarity
);
3201 phy_info
->cable_polarity
= polarity
;
3203 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_STATUS
, &phy_data
);
3207 phy_info
->mdix_mode
= (phy_data
& IGP01E1000_PSSR_MDIX
) >>
3208 IGP01E1000_PSSR_MDIX_SHIFT
;
3210 if((phy_data
& IGP01E1000_PSSR_SPEED_MASK
) ==
3211 IGP01E1000_PSSR_SPEED_1000MBPS
) {
3212 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
3213 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_STATUS
, &phy_data
);
3217 phy_info
->local_rx
= (phy_data
& SR_1000T_LOCAL_RX_STATUS
) >>
3218 SR_1000T_LOCAL_RX_STATUS_SHIFT
;
3219 phy_info
->remote_rx
= (phy_data
& SR_1000T_REMOTE_RX_STATUS
) >>
3220 SR_1000T_REMOTE_RX_STATUS_SHIFT
;
3222 /* Get cable length */
3223 ret_val
= e1000_get_cable_length(hw
, &min_length
, &max_length
);
3227 /* Translate to old method */
3228 average
= (max_length
+ min_length
) / 2;
3230 if(average
<= e1000_igp_cable_length_50
)
3231 phy_info
->cable_length
= e1000_cable_length_50
;
3232 else if(average
<= e1000_igp_cable_length_80
)
3233 phy_info
->cable_length
= e1000_cable_length_50_80
;
3234 else if(average
<= e1000_igp_cable_length_110
)
3235 phy_info
->cable_length
= e1000_cable_length_80_110
;
3236 else if(average
<= e1000_igp_cable_length_140
)
3237 phy_info
->cable_length
= e1000_cable_length_110_140
;
3239 phy_info
->cable_length
= e1000_cable_length_140
;
3242 return E1000_SUCCESS
;
3245 /******************************************************************************
3246 * Get PHY information from various PHY registers fot m88 PHY only.
3248 * hw - Struct containing variables accessed by shared code
3249 * phy_info - PHY information structure
3250 ******************************************************************************/
3252 e1000_phy_m88_get_info(struct e1000_hw
*hw
,
3253 struct e1000_phy_info
*phy_info
)
3256 uint16_t phy_data
, polarity
;
3258 DEBUGFUNC("e1000_phy_m88_get_info");
3260 /* The downshift status is checked only once, after link is established,
3261 * and it stored in the hw->speed_downgraded parameter. */
3262 phy_info
->downshift
= (e1000_downshift
)hw
->speed_downgraded
;
3264 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
3268 phy_info
->extended_10bt_distance
=
3269 (phy_data
& M88E1000_PSCR_10BT_EXT_DIST_ENABLE
) >>
3270 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT
;
3271 phy_info
->polarity_correction
=
3272 (phy_data
& M88E1000_PSCR_POLARITY_REVERSAL
) >>
3273 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT
;
3275 /* Check polarity status */
3276 ret_val
= e1000_check_polarity(hw
, &polarity
);
3279 phy_info
->cable_polarity
= polarity
;
3281 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
3285 phy_info
->mdix_mode
= (phy_data
& M88E1000_PSSR_MDIX
) >>
3286 M88E1000_PSSR_MDIX_SHIFT
;
3288 if ((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
) {
3289 /* Cable Length Estimation and Local/Remote Receiver Information
3290 * are only valid at 1000 Mbps.
3292 phy_info
->cable_length
= ((phy_data
& M88E1000_PSSR_CABLE_LENGTH
) >>
3293 M88E1000_PSSR_CABLE_LENGTH_SHIFT
);
3295 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_STATUS
, &phy_data
);
3299 phy_info
->local_rx
= (phy_data
& SR_1000T_LOCAL_RX_STATUS
) >>
3300 SR_1000T_LOCAL_RX_STATUS_SHIFT
;
3302 phy_info
->remote_rx
= (phy_data
& SR_1000T_REMOTE_RX_STATUS
) >>
3303 SR_1000T_REMOTE_RX_STATUS_SHIFT
;
3306 return E1000_SUCCESS
;
3309 /******************************************************************************
3310 * Get PHY information from various PHY registers
3312 * hw - Struct containing variables accessed by shared code
3313 * phy_info - PHY information structure
3314 ******************************************************************************/
3316 e1000_phy_get_info(struct e1000_hw
*hw
,
3317 struct e1000_phy_info
*phy_info
)
3322 DEBUGFUNC("e1000_phy_get_info");
3324 phy_info
->cable_length
= e1000_cable_length_undefined
;
3325 phy_info
->extended_10bt_distance
= e1000_10bt_ext_dist_enable_undefined
;
3326 phy_info
->cable_polarity
= e1000_rev_polarity_undefined
;
3327 phy_info
->downshift
= e1000_downshift_undefined
;
3328 phy_info
->polarity_correction
= e1000_polarity_reversal_undefined
;
3329 phy_info
->mdix_mode
= e1000_auto_x_mode_undefined
;
3330 phy_info
->local_rx
= e1000_1000t_rx_status_undefined
;
3331 phy_info
->remote_rx
= e1000_1000t_rx_status_undefined
;
3333 if(hw
->media_type
!= e1000_media_type_copper
) {
3334 DEBUGOUT("PHY info is only valid for copper media\n");
3335 return -E1000_ERR_CONFIG
;
3338 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
3342 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &phy_data
);
3346 if((phy_data
& MII_SR_LINK_STATUS
) != MII_SR_LINK_STATUS
) {
3347 DEBUGOUT("PHY info is only valid if link is up\n");
3348 return -E1000_ERR_CONFIG
;
3351 if(hw
->phy_type
== e1000_phy_igp
||
3352 hw
->phy_type
== e1000_phy_igp_2
)
3353 return e1000_phy_igp_get_info(hw
, phy_info
);
3355 return e1000_phy_m88_get_info(hw
, phy_info
);
3359 e1000_validate_mdi_setting(struct e1000_hw
*hw
)
3361 DEBUGFUNC("e1000_validate_mdi_settings");
3363 if(!hw
->autoneg
&& (hw
->mdix
== 0 || hw
->mdix
== 3)) {
3364 DEBUGOUT("Invalid MDI setting detected\n");
3366 return -E1000_ERR_CONFIG
;
3368 return E1000_SUCCESS
;
3372 /******************************************************************************
3373 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3376 * hw - Struct containing variables accessed by shared code
3377 *****************************************************************************/
3379 e1000_init_eeprom_params(struct e1000_hw
*hw
)
3381 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3382 uint32_t eecd
= E1000_READ_REG(hw
, EECD
);
3383 int32_t ret_val
= E1000_SUCCESS
;
3384 uint16_t eeprom_size
;
3386 DEBUGFUNC("e1000_init_eeprom_params");
3388 switch (hw
->mac_type
) {
3389 case e1000_82542_rev2_0
:
3390 case e1000_82542_rev2_1
:
3393 eeprom
->type
= e1000_eeprom_microwire
;
3394 eeprom
->word_size
= 64;
3395 eeprom
->opcode_bits
= 3;
3396 eeprom
->address_bits
= 6;
3397 eeprom
->delay_usec
= 50;
3398 eeprom
->use_eerd
= FALSE
;
3399 eeprom
->use_eewr
= FALSE
;
3403 case e1000_82545_rev_3
:
3405 case e1000_82546_rev_3
:
3406 eeprom
->type
= e1000_eeprom_microwire
;
3407 eeprom
->opcode_bits
= 3;
3408 eeprom
->delay_usec
= 50;
3409 if(eecd
& E1000_EECD_SIZE
) {
3410 eeprom
->word_size
= 256;
3411 eeprom
->address_bits
= 8;
3413 eeprom
->word_size
= 64;
3414 eeprom
->address_bits
= 6;
3416 eeprom
->use_eerd
= FALSE
;
3417 eeprom
->use_eewr
= FALSE
;
3420 case e1000_82541_rev_2
:
3422 case e1000_82547_rev_2
:
3423 if (eecd
& E1000_EECD_TYPE
) {
3424 eeprom
->type
= e1000_eeprom_spi
;
3425 eeprom
->opcode_bits
= 8;
3426 eeprom
->delay_usec
= 1;
3427 if (eecd
& E1000_EECD_ADDR_BITS
) {
3428 eeprom
->page_size
= 32;
3429 eeprom
->address_bits
= 16;
3431 eeprom
->page_size
= 8;
3432 eeprom
->address_bits
= 8;
3435 eeprom
->type
= e1000_eeprom_microwire
;
3436 eeprom
->opcode_bits
= 3;
3437 eeprom
->delay_usec
= 50;
3438 if (eecd
& E1000_EECD_ADDR_BITS
) {
3439 eeprom
->word_size
= 256;
3440 eeprom
->address_bits
= 8;
3442 eeprom
->word_size
= 64;
3443 eeprom
->address_bits
= 6;
3446 eeprom
->use_eerd
= FALSE
;
3447 eeprom
->use_eewr
= FALSE
;
3451 eeprom
->type
= e1000_eeprom_spi
;
3452 eeprom
->opcode_bits
= 8;
3453 eeprom
->delay_usec
= 1;
3454 if (eecd
& E1000_EECD_ADDR_BITS
) {
3455 eeprom
->page_size
= 32;
3456 eeprom
->address_bits
= 16;
3458 eeprom
->page_size
= 8;
3459 eeprom
->address_bits
= 8;
3461 eeprom
->use_eerd
= FALSE
;
3462 eeprom
->use_eewr
= FALSE
;
3465 eeprom
->type
= e1000_eeprom_spi
;
3466 eeprom
->opcode_bits
= 8;
3467 eeprom
->delay_usec
= 1;
3468 if (eecd
& E1000_EECD_ADDR_BITS
) {
3469 eeprom
->page_size
= 32;
3470 eeprom
->address_bits
= 16;
3472 eeprom
->page_size
= 8;
3473 eeprom
->address_bits
= 8;
3475 eeprom
->use_eerd
= TRUE
;
3476 eeprom
->use_eewr
= TRUE
;
3477 if(e1000_is_onboard_nvm_eeprom(hw
) == FALSE
) {
3478 eeprom
->type
= e1000_eeprom_flash
;
3479 eeprom
->word_size
= 2048;
3481 /* Ensure that the Autonomous FLASH update bit is cleared due to
3482 * Flash update issue on parts which use a FLASH for NVM. */
3483 eecd
&= ~E1000_EECD_AUPDEN
;
3484 E1000_WRITE_REG(hw
, EECD
, eecd
);
3491 if (eeprom
->type
== e1000_eeprom_spi
) {
3492 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
3493 * 32KB (incremented by powers of 2).
3495 if(hw
->mac_type
<= e1000_82547_rev_2
) {
3496 /* Set to default value for initial eeprom read. */
3497 eeprom
->word_size
= 64;
3498 ret_val
= e1000_read_eeprom(hw
, EEPROM_CFG
, 1, &eeprom_size
);
3501 eeprom_size
= (eeprom_size
& EEPROM_SIZE_MASK
) >> EEPROM_SIZE_SHIFT
;
3502 /* 256B eeprom size was not supported in earlier hardware, so we
3503 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
3504 * is never the result used in the shifting logic below. */
3508 eeprom_size
= (uint16_t)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
3509 E1000_EECD_SIZE_EX_SHIFT
);
3512 eeprom
->word_size
= 1 << (eeprom_size
+ EEPROM_WORD_SIZE_SHIFT
);
3517 /******************************************************************************
3518 * Raises the EEPROM's clock input.
3520 * hw - Struct containing variables accessed by shared code
3521 * eecd - EECD's current value
3522 *****************************************************************************/
3524 e1000_raise_ee_clk(struct e1000_hw
*hw
,
3527 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3528 * wait <delay> microseconds.
3530 *eecd
= *eecd
| E1000_EECD_SK
;
3531 E1000_WRITE_REG(hw
, EECD
, *eecd
);
3532 E1000_WRITE_FLUSH(hw
);
3533 udelay(hw
->eeprom
.delay_usec
);
3536 /******************************************************************************
3537 * Lowers the EEPROM's clock input.
3539 * hw - Struct containing variables accessed by shared code
3540 * eecd - EECD's current value
3541 *****************************************************************************/
3543 e1000_lower_ee_clk(struct e1000_hw
*hw
,
3546 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3547 * wait 50 microseconds.
3549 *eecd
= *eecd
& ~E1000_EECD_SK
;
3550 E1000_WRITE_REG(hw
, EECD
, *eecd
);
3551 E1000_WRITE_FLUSH(hw
);
3552 udelay(hw
->eeprom
.delay_usec
);
3555 /******************************************************************************
3556 * Shift data bits out to the EEPROM.
3558 * hw - Struct containing variables accessed by shared code
3559 * data - data to send to the EEPROM
3560 * count - number of bits to shift out
3561 *****************************************************************************/
3563 e1000_shift_out_ee_bits(struct e1000_hw
*hw
,
3567 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3571 /* We need to shift "count" bits out to the EEPROM. So, value in the
3572 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3573 * In order to do this, "data" must be broken down into bits.
3575 mask
= 0x01 << (count
- 1);
3576 eecd
= E1000_READ_REG(hw
, EECD
);
3577 if (eeprom
->type
== e1000_eeprom_microwire
) {
3578 eecd
&= ~E1000_EECD_DO
;
3579 } else if (eeprom
->type
== e1000_eeprom_spi
) {
3580 eecd
|= E1000_EECD_DO
;
3583 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3584 * and then raising and then lowering the clock (the SK bit controls
3585 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3586 * by setting "DI" to "0" and then raising and then lowering the clock.
3588 eecd
&= ~E1000_EECD_DI
;
3591 eecd
|= E1000_EECD_DI
;
3593 E1000_WRITE_REG(hw
, EECD
, eecd
);
3594 E1000_WRITE_FLUSH(hw
);
3596 udelay(eeprom
->delay_usec
);
3598 e1000_raise_ee_clk(hw
, &eecd
);
3599 e1000_lower_ee_clk(hw
, &eecd
);
3605 /* We leave the "DI" bit set to "0" when we leave this routine. */
3606 eecd
&= ~E1000_EECD_DI
;
3607 E1000_WRITE_REG(hw
, EECD
, eecd
);
3610 /******************************************************************************
3611 * Shift data bits in from the EEPROM
3613 * hw - Struct containing variables accessed by shared code
3614 *****************************************************************************/
3616 e1000_shift_in_ee_bits(struct e1000_hw
*hw
,
3623 /* In order to read a register from the EEPROM, we need to shift 'count'
3624 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3625 * input to the EEPROM (setting the SK bit), and then reading the value of
3626 * the "DO" bit. During this "shifting in" process the "DI" bit should
3630 eecd
= E1000_READ_REG(hw
, EECD
);
3632 eecd
&= ~(E1000_EECD_DO
| E1000_EECD_DI
);
3635 for(i
= 0; i
< count
; i
++) {
3637 e1000_raise_ee_clk(hw
, &eecd
);
3639 eecd
= E1000_READ_REG(hw
, EECD
);
3641 eecd
&= ~(E1000_EECD_DI
);
3642 if(eecd
& E1000_EECD_DO
)
3645 e1000_lower_ee_clk(hw
, &eecd
);
3651 /******************************************************************************
3652 * Prepares EEPROM for access
3654 * hw - Struct containing variables accessed by shared code
3656 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3657 * function should be called before issuing a command to the EEPROM.
3658 *****************************************************************************/
3660 e1000_acquire_eeprom(struct e1000_hw
*hw
)
3662 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3665 DEBUGFUNC("e1000_acquire_eeprom");
3667 if(e1000_get_hw_eeprom_semaphore(hw
))
3668 return -E1000_ERR_EEPROM
;
3670 eecd
= E1000_READ_REG(hw
, EECD
);
3672 if (hw
->mac_type
!= e1000_82573
) {
3673 /* Request EEPROM Access */
3674 if(hw
->mac_type
> e1000_82544
) {
3675 eecd
|= E1000_EECD_REQ
;
3676 E1000_WRITE_REG(hw
, EECD
, eecd
);
3677 eecd
= E1000_READ_REG(hw
, EECD
);
3678 while((!(eecd
& E1000_EECD_GNT
)) &&
3679 (i
< E1000_EEPROM_GRANT_ATTEMPTS
)) {
3682 eecd
= E1000_READ_REG(hw
, EECD
);
3684 if(!(eecd
& E1000_EECD_GNT
)) {
3685 eecd
&= ~E1000_EECD_REQ
;
3686 E1000_WRITE_REG(hw
, EECD
, eecd
);
3687 DEBUGOUT("Could not acquire EEPROM grant\n");
3688 e1000_put_hw_eeprom_semaphore(hw
);
3689 return -E1000_ERR_EEPROM
;
3694 /* Setup EEPROM for Read/Write */
3696 if (eeprom
->type
== e1000_eeprom_microwire
) {
3697 /* Clear SK and DI */
3698 eecd
&= ~(E1000_EECD_DI
| E1000_EECD_SK
);
3699 E1000_WRITE_REG(hw
, EECD
, eecd
);
3702 eecd
|= E1000_EECD_CS
;
3703 E1000_WRITE_REG(hw
, EECD
, eecd
);
3704 } else if (eeprom
->type
== e1000_eeprom_spi
) {
3705 /* Clear SK and CS */
3706 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_SK
);
3707 E1000_WRITE_REG(hw
, EECD
, eecd
);
3711 return E1000_SUCCESS
;
3714 /******************************************************************************
3715 * Returns EEPROM to a "standby" state
3717 * hw - Struct containing variables accessed by shared code
3718 *****************************************************************************/
3720 e1000_standby_eeprom(struct e1000_hw
*hw
)
3722 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3725 eecd
= E1000_READ_REG(hw
, EECD
);
3727 if(eeprom
->type
== e1000_eeprom_microwire
) {
3728 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_SK
);
3729 E1000_WRITE_REG(hw
, EECD
, eecd
);
3730 E1000_WRITE_FLUSH(hw
);
3731 udelay(eeprom
->delay_usec
);
3734 eecd
|= E1000_EECD_SK
;
3735 E1000_WRITE_REG(hw
, EECD
, eecd
);
3736 E1000_WRITE_FLUSH(hw
);
3737 udelay(eeprom
->delay_usec
);
3740 eecd
|= E1000_EECD_CS
;
3741 E1000_WRITE_REG(hw
, EECD
, eecd
);
3742 E1000_WRITE_FLUSH(hw
);
3743 udelay(eeprom
->delay_usec
);
3746 eecd
&= ~E1000_EECD_SK
;
3747 E1000_WRITE_REG(hw
, EECD
, eecd
);
3748 E1000_WRITE_FLUSH(hw
);
3749 udelay(eeprom
->delay_usec
);
3750 } else if(eeprom
->type
== e1000_eeprom_spi
) {
3751 /* Toggle CS to flush commands */
3752 eecd
|= E1000_EECD_CS
;
3753 E1000_WRITE_REG(hw
, EECD
, eecd
);
3754 E1000_WRITE_FLUSH(hw
);
3755 udelay(eeprom
->delay_usec
);
3756 eecd
&= ~E1000_EECD_CS
;
3757 E1000_WRITE_REG(hw
, EECD
, eecd
);
3758 E1000_WRITE_FLUSH(hw
);
3759 udelay(eeprom
->delay_usec
);
3763 /******************************************************************************
3764 * Terminates a command by inverting the EEPROM's chip select pin
3766 * hw - Struct containing variables accessed by shared code
3767 *****************************************************************************/
3769 e1000_release_eeprom(struct e1000_hw
*hw
)
3773 DEBUGFUNC("e1000_release_eeprom");
3775 eecd
= E1000_READ_REG(hw
, EECD
);
3777 if (hw
->eeprom
.type
== e1000_eeprom_spi
) {
3778 eecd
|= E1000_EECD_CS
; /* Pull CS high */
3779 eecd
&= ~E1000_EECD_SK
; /* Lower SCK */
3781 E1000_WRITE_REG(hw
, EECD
, eecd
);
3783 udelay(hw
->eeprom
.delay_usec
);
3784 } else if(hw
->eeprom
.type
== e1000_eeprom_microwire
) {
3785 /* cleanup eeprom */
3787 /* CS on Microwire is active-high */
3788 eecd
&= ~(E1000_EECD_CS
| E1000_EECD_DI
);
3790 E1000_WRITE_REG(hw
, EECD
, eecd
);
3792 /* Rising edge of clock */
3793 eecd
|= E1000_EECD_SK
;
3794 E1000_WRITE_REG(hw
, EECD
, eecd
);
3795 E1000_WRITE_FLUSH(hw
);
3796 udelay(hw
->eeprom
.delay_usec
);
3798 /* Falling edge of clock */
3799 eecd
&= ~E1000_EECD_SK
;
3800 E1000_WRITE_REG(hw
, EECD
, eecd
);
3801 E1000_WRITE_FLUSH(hw
);
3802 udelay(hw
->eeprom
.delay_usec
);
3805 /* Stop requesting EEPROM access */
3806 if(hw
->mac_type
> e1000_82544
) {
3807 eecd
&= ~E1000_EECD_REQ
;
3808 E1000_WRITE_REG(hw
, EECD
, eecd
);
3811 e1000_put_hw_eeprom_semaphore(hw
);
3814 /******************************************************************************
3815 * Reads a 16 bit word from the EEPROM.
3817 * hw - Struct containing variables accessed by shared code
3818 *****************************************************************************/
3820 e1000_spi_eeprom_ready(struct e1000_hw
*hw
)
3822 uint16_t retry_count
= 0;
3823 uint8_t spi_stat_reg
;
3825 DEBUGFUNC("e1000_spi_eeprom_ready");
3827 /* Read "Status Register" repeatedly until the LSB is cleared. The
3828 * EEPROM will signal that the command has been completed by clearing
3829 * bit 0 of the internal status register. If it's not cleared within
3830 * 5 milliseconds, then error out.
3834 e1000_shift_out_ee_bits(hw
, EEPROM_RDSR_OPCODE_SPI
,
3835 hw
->eeprom
.opcode_bits
);
3836 spi_stat_reg
= (uint8_t)e1000_shift_in_ee_bits(hw
, 8);
3837 if (!(spi_stat_reg
& EEPROM_STATUS_RDY_SPI
))
3843 e1000_standby_eeprom(hw
);
3844 } while(retry_count
< EEPROM_MAX_RETRY_SPI
);
3846 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3847 * only 0-5mSec on 5V devices)
3849 if(retry_count
>= EEPROM_MAX_RETRY_SPI
) {
3850 DEBUGOUT("SPI EEPROM Status error\n");
3851 return -E1000_ERR_EEPROM
;
3854 return E1000_SUCCESS
;
3857 /******************************************************************************
3858 * Reads a 16 bit word from the EEPROM.
3860 * hw - Struct containing variables accessed by shared code
3861 * offset - offset of word in the EEPROM to read
3862 * data - word read from the EEPROM
3863 * words - number of words to read
3864 *****************************************************************************/
3866 e1000_read_eeprom(struct e1000_hw
*hw
,
3871 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
3875 DEBUGFUNC("e1000_read_eeprom");
3877 /* A check for invalid values: offset too large, too many words, and not
3880 if((offset
>= eeprom
->word_size
) || (words
> eeprom
->word_size
- offset
) ||
3882 DEBUGOUT("\"words\" parameter out of bounds\n");
3883 return -E1000_ERR_EEPROM
;
3886 /* FLASH reads without acquiring the semaphore are safe in 82573-based
3889 if ((e1000_is_onboard_nvm_eeprom(hw
) == TRUE
) ||
3890 (hw
->mac_type
!= e1000_82573
)) {
3891 /* Prepare the EEPROM for reading */
3892 if(e1000_acquire_eeprom(hw
) != E1000_SUCCESS
)
3893 return -E1000_ERR_EEPROM
;
3896 if(eeprom
->use_eerd
== TRUE
) {
3897 ret_val
= e1000_read_eeprom_eerd(hw
, offset
, words
, data
);
3898 if ((e1000_is_onboard_nvm_eeprom(hw
) == TRUE
) ||
3899 (hw
->mac_type
!= e1000_82573
))
3900 e1000_release_eeprom(hw
);
3904 if(eeprom
->type
== e1000_eeprom_spi
) {
3906 uint8_t read_opcode
= EEPROM_READ_OPCODE_SPI
;
3908 if(e1000_spi_eeprom_ready(hw
)) {
3909 e1000_release_eeprom(hw
);
3910 return -E1000_ERR_EEPROM
;
3913 e1000_standby_eeprom(hw
);
3915 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3916 if((eeprom
->address_bits
== 8) && (offset
>= 128))
3917 read_opcode
|= EEPROM_A8_OPCODE_SPI
;
3919 /* Send the READ command (opcode + addr) */
3920 e1000_shift_out_ee_bits(hw
, read_opcode
, eeprom
->opcode_bits
);
3921 e1000_shift_out_ee_bits(hw
, (uint16_t)(offset
*2), eeprom
->address_bits
);
3923 /* Read the data. The address of the eeprom internally increments with
3924 * each byte (spi) being read, saving on the overhead of eeprom setup
3925 * and tear-down. The address counter will roll over if reading beyond
3926 * the size of the eeprom, thus allowing the entire memory to be read
3927 * starting from any offset. */
3928 for (i
= 0; i
< words
; i
++) {
3929 word_in
= e1000_shift_in_ee_bits(hw
, 16);
3930 data
[i
] = (word_in
>> 8) | (word_in
<< 8);
3932 } else if(eeprom
->type
== e1000_eeprom_microwire
) {
3933 for (i
= 0; i
< words
; i
++) {
3934 /* Send the READ command (opcode + addr) */
3935 e1000_shift_out_ee_bits(hw
, EEPROM_READ_OPCODE_MICROWIRE
,
3936 eeprom
->opcode_bits
);
3937 e1000_shift_out_ee_bits(hw
, (uint16_t)(offset
+ i
),
3938 eeprom
->address_bits
);
3940 /* Read the data. For microwire, each word requires the overhead
3941 * of eeprom setup and tear-down. */
3942 data
[i
] = e1000_shift_in_ee_bits(hw
, 16);
3943 e1000_standby_eeprom(hw
);
3947 /* End this read operation */
3948 e1000_release_eeprom(hw
);
3950 return E1000_SUCCESS
;
3953 /******************************************************************************
3954 * Reads a 16 bit word from the EEPROM using the EERD register.
3956 * hw - Struct containing variables accessed by shared code
3957 * offset - offset of word in the EEPROM to read
3958 * data - word read from the EEPROM
3959 * words - number of words to read
3960 *****************************************************************************/
3962 e1000_read_eeprom_eerd(struct e1000_hw
*hw
,
3967 uint32_t i
, eerd
= 0;
3970 for (i
= 0; i
< words
; i
++) {
3971 eerd
= ((offset
+i
) << E1000_EEPROM_RW_ADDR_SHIFT
) +
3972 E1000_EEPROM_RW_REG_START
;
3974 E1000_WRITE_REG(hw
, EERD
, eerd
);
3975 error
= e1000_poll_eerd_eewr_done(hw
, E1000_EEPROM_POLL_READ
);
3980 data
[i
] = (E1000_READ_REG(hw
, EERD
) >> E1000_EEPROM_RW_REG_DATA
);
3987 /******************************************************************************
3988 * Writes a 16 bit word from the EEPROM using the EEWR register.
3990 * hw - Struct containing variables accessed by shared code
3991 * offset - offset of word in the EEPROM to read
3992 * data - word read from the EEPROM
3993 * words - number of words to read
3994 *****************************************************************************/
3996 e1000_write_eeprom_eewr(struct e1000_hw
*hw
,
4001 uint32_t register_value
= 0;
4005 for (i
= 0; i
< words
; i
++) {
4006 register_value
= (data
[i
] << E1000_EEPROM_RW_REG_DATA
) |
4007 ((offset
+i
) << E1000_EEPROM_RW_ADDR_SHIFT
) |
4008 E1000_EEPROM_RW_REG_START
;
4010 error
= e1000_poll_eerd_eewr_done(hw
, E1000_EEPROM_POLL_WRITE
);
4015 E1000_WRITE_REG(hw
, EEWR
, register_value
);
4017 error
= e1000_poll_eerd_eewr_done(hw
, E1000_EEPROM_POLL_WRITE
);
4027 /******************************************************************************
4028 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
4030 * hw - Struct containing variables accessed by shared code
4031 *****************************************************************************/
4033 e1000_poll_eerd_eewr_done(struct e1000_hw
*hw
, int eerd
)
4035 uint32_t attempts
= 100000;
4036 uint32_t i
, reg
= 0;
4037 int32_t done
= E1000_ERR_EEPROM
;
4039 for(i
= 0; i
< attempts
; i
++) {
4040 if(eerd
== E1000_EEPROM_POLL_READ
)
4041 reg
= E1000_READ_REG(hw
, EERD
);
4043 reg
= E1000_READ_REG(hw
, EEWR
);
4045 if(reg
& E1000_EEPROM_RW_REG_DONE
) {
4046 done
= E1000_SUCCESS
;
4055 /***************************************************************************
4056 * Description: Determines if the onboard NVM is FLASH or EEPROM.
4058 * hw - Struct containing variables accessed by shared code
4059 ****************************************************************************/
4061 e1000_is_onboard_nvm_eeprom(struct e1000_hw
*hw
)
4065 if(hw
->mac_type
== e1000_82573
) {
4066 eecd
= E1000_READ_REG(hw
, EECD
);
4068 /* Isolate bits 15 & 16 */
4069 eecd
= ((eecd
>> 15) & 0x03);
4071 /* If both bits are set, device is Flash type */
4079 /******************************************************************************
4080 * Verifies that the EEPROM has a valid checksum
4082 * hw - Struct containing variables accessed by shared code
4084 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
4085 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
4087 *****************************************************************************/
4089 e1000_validate_eeprom_checksum(struct e1000_hw
*hw
)
4091 uint16_t checksum
= 0;
4092 uint16_t i
, eeprom_data
;
4094 DEBUGFUNC("e1000_validate_eeprom_checksum");
4096 if ((hw
->mac_type
== e1000_82573
) &&
4097 (e1000_is_onboard_nvm_eeprom(hw
) == FALSE
)) {
4098 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
4099 * 10h-12h. Checksum may need to be fixed. */
4100 e1000_read_eeprom(hw
, 0x10, 1, &eeprom_data
);
4101 if ((eeprom_data
& 0x10) == 0) {
4102 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
4103 * has already been fixed. If the checksum is still wrong and this
4104 * bit is a 1, we need to return bad checksum. Otherwise, we need
4105 * to set this bit to a 1 and update the checksum. */
4106 e1000_read_eeprom(hw
, 0x23, 1, &eeprom_data
);
4107 if ((eeprom_data
& 0x8000) == 0) {
4108 eeprom_data
|= 0x8000;
4109 e1000_write_eeprom(hw
, 0x23, 1, &eeprom_data
);
4110 e1000_update_eeprom_checksum(hw
);
4115 for(i
= 0; i
< (EEPROM_CHECKSUM_REG
+ 1); i
++) {
4116 if(e1000_read_eeprom(hw
, i
, 1, &eeprom_data
) < 0) {
4117 DEBUGOUT("EEPROM Read Error\n");
4118 return -E1000_ERR_EEPROM
;
4120 checksum
+= eeprom_data
;
4123 if(checksum
== (uint16_t) EEPROM_SUM
)
4124 return E1000_SUCCESS
;
4126 DEBUGOUT("EEPROM Checksum Invalid\n");
4127 return -E1000_ERR_EEPROM
;
4131 /******************************************************************************
4132 * Calculates the EEPROM checksum and writes it to the EEPROM
4134 * hw - Struct containing variables accessed by shared code
4136 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
4137 * Writes the difference to word offset 63 of the EEPROM.
4138 *****************************************************************************/
4140 e1000_update_eeprom_checksum(struct e1000_hw
*hw
)
4142 uint16_t checksum
= 0;
4143 uint16_t i
, eeprom_data
;
4145 DEBUGFUNC("e1000_update_eeprom_checksum");
4147 for(i
= 0; i
< EEPROM_CHECKSUM_REG
; i
++) {
4148 if(e1000_read_eeprom(hw
, i
, 1, &eeprom_data
) < 0) {
4149 DEBUGOUT("EEPROM Read Error\n");
4150 return -E1000_ERR_EEPROM
;
4152 checksum
+= eeprom_data
;
4154 checksum
= (uint16_t) EEPROM_SUM
- checksum
;
4155 if(e1000_write_eeprom(hw
, EEPROM_CHECKSUM_REG
, 1, &checksum
) < 0) {
4156 DEBUGOUT("EEPROM Write Error\n");
4157 return -E1000_ERR_EEPROM
;
4158 } else if (hw
->eeprom
.type
== e1000_eeprom_flash
) {
4159 e1000_commit_shadow_ram(hw
);
4161 return E1000_SUCCESS
;
4164 /******************************************************************************
4165 * Parent function for writing words to the different EEPROM types.
4167 * hw - Struct containing variables accessed by shared code
4168 * offset - offset within the EEPROM to be written to
4169 * words - number of words to write
4170 * data - 16 bit word to be written to the EEPROM
4172 * If e1000_update_eeprom_checksum is not called after this function, the
4173 * EEPROM will most likely contain an invalid checksum.
4174 *****************************************************************************/
4176 e1000_write_eeprom(struct e1000_hw
*hw
,
4181 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
4184 DEBUGFUNC("e1000_write_eeprom");
4186 /* A check for invalid values: offset too large, too many words, and not
4189 if((offset
>= eeprom
->word_size
) || (words
> eeprom
->word_size
- offset
) ||
4191 DEBUGOUT("\"words\" parameter out of bounds\n");
4192 return -E1000_ERR_EEPROM
;
4195 /* 82573 writes only through eewr */
4196 if(eeprom
->use_eewr
== TRUE
)
4197 return e1000_write_eeprom_eewr(hw
, offset
, words
, data
);
4199 /* Prepare the EEPROM for writing */
4200 if (e1000_acquire_eeprom(hw
) != E1000_SUCCESS
)
4201 return -E1000_ERR_EEPROM
;
4203 if(eeprom
->type
== e1000_eeprom_microwire
) {
4204 status
= e1000_write_eeprom_microwire(hw
, offset
, words
, data
);
4206 status
= e1000_write_eeprom_spi(hw
, offset
, words
, data
);
4210 /* Done with writing */
4211 e1000_release_eeprom(hw
);
4216 /******************************************************************************
4217 * Writes a 16 bit word to a given offset in an SPI EEPROM.
4219 * hw - Struct containing variables accessed by shared code
4220 * offset - offset within the EEPROM to be written to
4221 * words - number of words to write
4222 * data - pointer to array of 8 bit words to be written to the EEPROM
4224 *****************************************************************************/
4226 e1000_write_eeprom_spi(struct e1000_hw
*hw
,
4231 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
4234 DEBUGFUNC("e1000_write_eeprom_spi");
4236 while (widx
< words
) {
4237 uint8_t write_opcode
= EEPROM_WRITE_OPCODE_SPI
;
4239 if(e1000_spi_eeprom_ready(hw
)) return -E1000_ERR_EEPROM
;
4241 e1000_standby_eeprom(hw
);
4243 /* Send the WRITE ENABLE command (8 bit opcode ) */
4244 e1000_shift_out_ee_bits(hw
, EEPROM_WREN_OPCODE_SPI
,
4245 eeprom
->opcode_bits
);
4247 e1000_standby_eeprom(hw
);
4249 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4250 if((eeprom
->address_bits
== 8) && (offset
>= 128))
4251 write_opcode
|= EEPROM_A8_OPCODE_SPI
;
4253 /* Send the Write command (8-bit opcode + addr) */
4254 e1000_shift_out_ee_bits(hw
, write_opcode
, eeprom
->opcode_bits
);
4256 e1000_shift_out_ee_bits(hw
, (uint16_t)((offset
+ widx
)*2),
4257 eeprom
->address_bits
);
4261 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
4262 while (widx
< words
) {
4263 uint16_t word_out
= data
[widx
];
4264 word_out
= (word_out
>> 8) | (word_out
<< 8);
4265 e1000_shift_out_ee_bits(hw
, word_out
, 16);
4268 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
4269 * operation, while the smaller eeproms are capable of an 8-byte
4270 * PAGE WRITE operation. Break the inner loop to pass new address
4272 if((((offset
+ widx
)*2) % eeprom
->page_size
) == 0) {
4273 e1000_standby_eeprom(hw
);
4279 return E1000_SUCCESS
;
4282 /******************************************************************************
4283 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
4285 * hw - Struct containing variables accessed by shared code
4286 * offset - offset within the EEPROM to be written to
4287 * words - number of words to write
4288 * data - pointer to array of 16 bit words to be written to the EEPROM
4290 *****************************************************************************/
4292 e1000_write_eeprom_microwire(struct e1000_hw
*hw
,
4297 struct e1000_eeprom_info
*eeprom
= &hw
->eeprom
;
4299 uint16_t words_written
= 0;
4302 DEBUGFUNC("e1000_write_eeprom_microwire");
4304 /* Send the write enable command to the EEPROM (3-bit opcode plus
4305 * 6/8-bit dummy address beginning with 11). It's less work to include
4306 * the 11 of the dummy address as part of the opcode than it is to shift
4307 * it over the correct number of bits for the address. This puts the
4308 * EEPROM into write/erase mode.
4310 e1000_shift_out_ee_bits(hw
, EEPROM_EWEN_OPCODE_MICROWIRE
,
4311 (uint16_t)(eeprom
->opcode_bits
+ 2));
4313 e1000_shift_out_ee_bits(hw
, 0, (uint16_t)(eeprom
->address_bits
- 2));
4315 /* Prepare the EEPROM */
4316 e1000_standby_eeprom(hw
);
4318 while (words_written
< words
) {
4319 /* Send the Write command (3-bit opcode + addr) */
4320 e1000_shift_out_ee_bits(hw
, EEPROM_WRITE_OPCODE_MICROWIRE
,
4321 eeprom
->opcode_bits
);
4323 e1000_shift_out_ee_bits(hw
, (uint16_t)(offset
+ words_written
),
4324 eeprom
->address_bits
);
4327 e1000_shift_out_ee_bits(hw
, data
[words_written
], 16);
4329 /* Toggle the CS line. This in effect tells the EEPROM to execute
4330 * the previous command.
4332 e1000_standby_eeprom(hw
);
4334 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
4335 * signal that the command has been completed by raising the DO signal.
4336 * If DO does not go high in 10 milliseconds, then error out.
4338 for(i
= 0; i
< 200; i
++) {
4339 eecd
= E1000_READ_REG(hw
, EECD
);
4340 if(eecd
& E1000_EECD_DO
) break;
4344 DEBUGOUT("EEPROM Write did not complete\n");
4345 return -E1000_ERR_EEPROM
;
4348 /* Recover from write */
4349 e1000_standby_eeprom(hw
);
4354 /* Send the write disable command to the EEPROM (3-bit opcode plus
4355 * 6/8-bit dummy address beginning with 10). It's less work to include
4356 * the 10 of the dummy address as part of the opcode than it is to shift
4357 * it over the correct number of bits for the address. This takes the
4358 * EEPROM out of write/erase mode.
4360 e1000_shift_out_ee_bits(hw
, EEPROM_EWDS_OPCODE_MICROWIRE
,
4361 (uint16_t)(eeprom
->opcode_bits
+ 2));
4363 e1000_shift_out_ee_bits(hw
, 0, (uint16_t)(eeprom
->address_bits
- 2));
4365 return E1000_SUCCESS
;
4368 /******************************************************************************
4369 * Flushes the cached eeprom to NVM. This is done by saving the modified values
4370 * in the eeprom cache and the non modified values in the currently active bank
4373 * hw - Struct containing variables accessed by shared code
4374 * offset - offset of word in the EEPROM to read
4375 * data - word read from the EEPROM
4376 * words - number of words to read
4377 *****************************************************************************/
4379 e1000_commit_shadow_ram(struct e1000_hw
*hw
)
4381 uint32_t attempts
= 100000;
4385 int32_t error
= E1000_SUCCESS
;
4387 /* The flop register will be used to determine if flash type is STM */
4388 flop
= E1000_READ_REG(hw
, FLOP
);
4390 if (hw
->mac_type
== e1000_82573
) {
4391 for (i
=0; i
< attempts
; i
++) {
4392 eecd
= E1000_READ_REG(hw
, EECD
);
4393 if ((eecd
& E1000_EECD_FLUPD
) == 0) {
4399 if (i
== attempts
) {
4400 return -E1000_ERR_EEPROM
;
4403 /* If STM opcode located in bits 15:8 of flop, reset firmware */
4404 if ((flop
& 0xFF00) == E1000_STM_OPCODE
) {
4405 E1000_WRITE_REG(hw
, HICR
, E1000_HICR_FW_RESET
);
4408 /* Perform the flash update */
4409 E1000_WRITE_REG(hw
, EECD
, eecd
| E1000_EECD_FLUPD
);
4411 for (i
=0; i
< attempts
; i
++) {
4412 eecd
= E1000_READ_REG(hw
, EECD
);
4413 if ((eecd
& E1000_EECD_FLUPD
) == 0) {
4419 if (i
== attempts
) {
4420 return -E1000_ERR_EEPROM
;
4427 /******************************************************************************
4428 * Reads the adapter's part number from the EEPROM
4430 * hw - Struct containing variables accessed by shared code
4431 * part_num - Adapter's part number
4432 *****************************************************************************/
4434 e1000_read_part_num(struct e1000_hw
*hw
,
4437 uint16_t offset
= EEPROM_PBA_BYTE_1
;
4438 uint16_t eeprom_data
;
4440 DEBUGFUNC("e1000_read_part_num");
4442 /* Get word 0 from EEPROM */
4443 if(e1000_read_eeprom(hw
, offset
, 1, &eeprom_data
) < 0) {
4444 DEBUGOUT("EEPROM Read Error\n");
4445 return -E1000_ERR_EEPROM
;
4447 /* Save word 0 in upper half of part_num */
4448 *part_num
= (uint32_t) (eeprom_data
<< 16);
4450 /* Get word 1 from EEPROM */
4451 if(e1000_read_eeprom(hw
, ++offset
, 1, &eeprom_data
) < 0) {
4452 DEBUGOUT("EEPROM Read Error\n");
4453 return -E1000_ERR_EEPROM
;
4455 /* Save word 1 in lower half of part_num */
4456 *part_num
|= eeprom_data
;
4458 return E1000_SUCCESS
;
4461 /******************************************************************************
4462 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
4463 * second function of dual function devices
4465 * hw - Struct containing variables accessed by shared code
4466 *****************************************************************************/
4468 e1000_read_mac_addr(struct e1000_hw
* hw
)
4471 uint16_t eeprom_data
, i
;
4473 DEBUGFUNC("e1000_read_mac_addr");
4475 for(i
= 0; i
< NODE_ADDRESS_SIZE
; i
+= 2) {
4477 if(e1000_read_eeprom(hw
, offset
, 1, &eeprom_data
) < 0) {
4478 DEBUGOUT("EEPROM Read Error\n");
4479 return -E1000_ERR_EEPROM
;
4481 hw
->perm_mac_addr
[i
] = (uint8_t) (eeprom_data
& 0x00FF);
4482 hw
->perm_mac_addr
[i
+1] = (uint8_t) (eeprom_data
>> 8);
4484 switch (hw
->mac_type
) {
4488 case e1000_82546_rev_3
:
4490 if(E1000_READ_REG(hw
, STATUS
) & E1000_STATUS_FUNC_1
)
4491 hw
->perm_mac_addr
[5] ^= 0x01;
4495 for(i
= 0; i
< NODE_ADDRESS_SIZE
; i
++)
4496 hw
->mac_addr
[i
] = hw
->perm_mac_addr
[i
];
4497 return E1000_SUCCESS
;
4500 /******************************************************************************
4501 * Initializes receive address filters.
4503 * hw - Struct containing variables accessed by shared code
4505 * Places the MAC address in receive address register 0 and clears the rest
4506 * of the receive addresss registers. Clears the multicast table. Assumes
4507 * the receiver is in reset when the routine is called.
4508 *****************************************************************************/
4510 e1000_init_rx_addrs(struct e1000_hw
*hw
)
4515 DEBUGFUNC("e1000_init_rx_addrs");
4517 /* Setup the receive address. */
4518 DEBUGOUT("Programming MAC Address into RAR[0]\n");
4520 e1000_rar_set(hw
, hw
->mac_addr
, 0);
4522 rar_num
= E1000_RAR_ENTRIES
;
4524 /* Reserve a spot for the Locally Administered Address to work around
4525 * an 82571 issue in which a reset on one port will reload the MAC on
4526 * the other port. */
4527 if ((hw
->mac_type
== e1000_82571
) && (hw
->laa_is_present
== TRUE
))
4529 /* Zero out the other 15 receive addresses. */
4530 DEBUGOUT("Clearing RAR[1-15]\n");
4531 for(i
= 1; i
< rar_num
; i
++) {
4532 E1000_WRITE_REG_ARRAY(hw
, RA
, (i
<< 1), 0);
4533 E1000_WRITE_REG_ARRAY(hw
, RA
, ((i
<< 1) + 1), 0);
4538 /******************************************************************************
4539 * Updates the MAC's list of multicast addresses.
4541 * hw - Struct containing variables accessed by shared code
4542 * mc_addr_list - the list of new multicast addresses
4543 * mc_addr_count - number of addresses
4544 * pad - number of bytes between addresses in the list
4545 * rar_used_count - offset where to start adding mc addresses into the RAR's
4547 * The given list replaces any existing list. Clears the last 15 receive
4548 * address registers and the multicast table. Uses receive address registers
4549 * for the first 15 multicast addresses, and hashes the rest into the
4551 *****************************************************************************/
4553 e1000_mc_addr_list_update(struct e1000_hw
*hw
,
4554 uint8_t *mc_addr_list
,
4555 uint32_t mc_addr_count
,
4557 uint32_t rar_used_count
)
4559 uint32_t hash_value
;
4561 uint32_t num_rar_entry
;
4562 uint32_t num_mta_entry
;
4564 DEBUGFUNC("e1000_mc_addr_list_update");
4566 /* Set the new number of MC addresses that we are being requested to use. */
4567 hw
->num_mc_addrs
= mc_addr_count
;
4569 /* Clear RAR[1-15] */
4570 DEBUGOUT(" Clearing RAR[1-15]\n");
4571 num_rar_entry
= E1000_RAR_ENTRIES
;
4572 /* Reserve a spot for the Locally Administered Address to work around
4573 * an 82571 issue in which a reset on one port will reload the MAC on
4574 * the other port. */
4575 if ((hw
->mac_type
== e1000_82571
) && (hw
->laa_is_present
== TRUE
))
4578 for(i
= rar_used_count
; i
< num_rar_entry
; i
++) {
4579 E1000_WRITE_REG_ARRAY(hw
, RA
, (i
<< 1), 0);
4580 E1000_WRITE_REG_ARRAY(hw
, RA
, ((i
<< 1) + 1), 0);
4584 DEBUGOUT(" Clearing MTA\n");
4585 num_mta_entry
= E1000_NUM_MTA_REGISTERS
;
4586 for(i
= 0; i
< num_mta_entry
; i
++) {
4587 E1000_WRITE_REG_ARRAY(hw
, MTA
, i
, 0);
4590 /* Add the new addresses */
4591 for(i
= 0; i
< mc_addr_count
; i
++) {
4592 DEBUGOUT(" Adding the multicast addresses:\n");
4593 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i
,
4594 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
)],
4595 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 1],
4596 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 2],
4597 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 3],
4598 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 4],
4599 mc_addr_list
[i
* (ETH_LENGTH_OF_ADDRESS
+ pad
) + 5]);
4601 hash_value
= e1000_hash_mc_addr(hw
,
4603 (i
* (ETH_LENGTH_OF_ADDRESS
+ pad
)));
4605 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value
);
4607 /* Place this multicast address in the RAR if there is room, *
4608 * else put it in the MTA
4610 if (rar_used_count
< num_rar_entry
) {
4612 mc_addr_list
+ (i
* (ETH_LENGTH_OF_ADDRESS
+ pad
)),
4616 e1000_mta_set(hw
, hash_value
);
4619 DEBUGOUT("MC Update Complete\n");
4623 /******************************************************************************
4624 * Hashes an address to determine its location in the multicast table
4626 * hw - Struct containing variables accessed by shared code
4627 * mc_addr - the multicast address to hash
4628 *****************************************************************************/
4630 e1000_hash_mc_addr(struct e1000_hw
*hw
,
4633 uint32_t hash_value
= 0;
4635 /* The portion of the address that is used for the hash table is
4636 * determined by the mc_filter_type setting.
4638 switch (hw
->mc_filter_type
) {
4639 /* [0] [1] [2] [3] [4] [5]
4644 /* [47:36] i.e. 0x563 for above example address */
4645 hash_value
= ((mc_addr
[4] >> 4) | (((uint16_t) mc_addr
[5]) << 4));
4648 /* [46:35] i.e. 0xAC6 for above example address */
4649 hash_value
= ((mc_addr
[4] >> 3) | (((uint16_t) mc_addr
[5]) << 5));
4652 /* [45:34] i.e. 0x5D8 for above example address */
4653 hash_value
= ((mc_addr
[4] >> 2) | (((uint16_t) mc_addr
[5]) << 6));
4656 /* [43:32] i.e. 0x634 for above example address */
4657 hash_value
= ((mc_addr
[4]) | (((uint16_t) mc_addr
[5]) << 8));
4661 hash_value
&= 0xFFF;
4666 /******************************************************************************
4667 * Sets the bit in the multicast table corresponding to the hash value.
4669 * hw - Struct containing variables accessed by shared code
4670 * hash_value - Multicast address hash value
4671 *****************************************************************************/
4673 e1000_mta_set(struct e1000_hw
*hw
,
4674 uint32_t hash_value
)
4676 uint32_t hash_bit
, hash_reg
;
4680 /* The MTA is a register array of 128 32-bit registers.
4681 * It is treated like an array of 4096 bits. We want to set
4682 * bit BitArray[hash_value]. So we figure out what register
4683 * the bit is in, read it, OR in the new bit, then write
4684 * back the new value. The register is determined by the
4685 * upper 7 bits of the hash value and the bit within that
4686 * register are determined by the lower 5 bits of the value.
4688 hash_reg
= (hash_value
>> 5) & 0x7F;
4689 hash_bit
= hash_value
& 0x1F;
4691 mta
= E1000_READ_REG_ARRAY(hw
, MTA
, hash_reg
);
4693 mta
|= (1 << hash_bit
);
4695 /* If we are on an 82544 and we are trying to write an odd offset
4696 * in the MTA, save off the previous entry before writing and
4697 * restore the old value after writing.
4699 if((hw
->mac_type
== e1000_82544
) && ((hash_reg
& 0x1) == 1)) {
4700 temp
= E1000_READ_REG_ARRAY(hw
, MTA
, (hash_reg
- 1));
4701 E1000_WRITE_REG_ARRAY(hw
, MTA
, hash_reg
, mta
);
4702 E1000_WRITE_REG_ARRAY(hw
, MTA
, (hash_reg
- 1), temp
);
4704 E1000_WRITE_REG_ARRAY(hw
, MTA
, hash_reg
, mta
);
4708 /******************************************************************************
4709 * Puts an ethernet address into a receive address register.
4711 * hw - Struct containing variables accessed by shared code
4712 * addr - Address to put into receive address register
4713 * index - Receive address register to write
4714 *****************************************************************************/
4716 e1000_rar_set(struct e1000_hw
*hw
,
4720 uint32_t rar_low
, rar_high
;
4722 /* HW expects these in little endian so we reverse the byte order
4723 * from network order (big endian) to little endian
4725 rar_low
= ((uint32_t) addr
[0] |
4726 ((uint32_t) addr
[1] << 8) |
4727 ((uint32_t) addr
[2] << 16) | ((uint32_t) addr
[3] << 24));
4729 rar_high
= ((uint32_t) addr
[4] | ((uint32_t) addr
[5] << 8) | E1000_RAH_AV
);
4731 E1000_WRITE_REG_ARRAY(hw
, RA
, (index
<< 1), rar_low
);
4732 E1000_WRITE_REG_ARRAY(hw
, RA
, ((index
<< 1) + 1), rar_high
);
4735 /******************************************************************************
4736 * Writes a value to the specified offset in the VLAN filter table.
4738 * hw - Struct containing variables accessed by shared code
4739 * offset - Offset in VLAN filer table to write
4740 * value - Value to write into VLAN filter table
4741 *****************************************************************************/
4743 e1000_write_vfta(struct e1000_hw
*hw
,
4749 if((hw
->mac_type
== e1000_82544
) && ((offset
& 0x1) == 1)) {
4750 temp
= E1000_READ_REG_ARRAY(hw
, VFTA
, (offset
- 1));
4751 E1000_WRITE_REG_ARRAY(hw
, VFTA
, offset
, value
);
4752 E1000_WRITE_REG_ARRAY(hw
, VFTA
, (offset
- 1), temp
);
4754 E1000_WRITE_REG_ARRAY(hw
, VFTA
, offset
, value
);
4758 /******************************************************************************
4759 * Clears the VLAN filer table
4761 * hw - Struct containing variables accessed by shared code
4762 *****************************************************************************/
4764 e1000_clear_vfta(struct e1000_hw
*hw
)
4767 uint32_t vfta_value
= 0;
4768 uint32_t vfta_offset
= 0;
4769 uint32_t vfta_bit_in_reg
= 0;
4771 if (hw
->mac_type
== e1000_82573
) {
4772 if (hw
->mng_cookie
.vlan_id
!= 0) {
4773 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
4774 * ID. The following operations determine which 32b entry
4775 * (i.e. offset) into the array we want to set the VLAN ID
4776 * (i.e. bit) of the manageability unit. */
4777 vfta_offset
= (hw
->mng_cookie
.vlan_id
>>
4778 E1000_VFTA_ENTRY_SHIFT
) &
4779 E1000_VFTA_ENTRY_MASK
;
4780 vfta_bit_in_reg
= 1 << (hw
->mng_cookie
.vlan_id
&
4781 E1000_VFTA_ENTRY_BIT_SHIFT_MASK
);
4784 for (offset
= 0; offset
< E1000_VLAN_FILTER_TBL_SIZE
; offset
++) {
4785 /* If the offset we want to clear is the same offset of the
4786 * manageability VLAN ID, then clear all bits except that of the
4787 * manageability unit */
4788 vfta_value
= (offset
== vfta_offset
) ? vfta_bit_in_reg
: 0;
4789 E1000_WRITE_REG_ARRAY(hw
, VFTA
, offset
, vfta_value
);
4794 e1000_id_led_init(struct e1000_hw
* hw
)
4797 const uint32_t ledctl_mask
= 0x000000FF;
4798 const uint32_t ledctl_on
= E1000_LEDCTL_MODE_LED_ON
;
4799 const uint32_t ledctl_off
= E1000_LEDCTL_MODE_LED_OFF
;
4800 uint16_t eeprom_data
, i
, temp
;
4801 const uint16_t led_mask
= 0x0F;
4803 DEBUGFUNC("e1000_id_led_init");
4805 if(hw
->mac_type
< e1000_82540
) {
4807 return E1000_SUCCESS
;
4810 ledctl
= E1000_READ_REG(hw
, LEDCTL
);
4811 hw
->ledctl_default
= ledctl
;
4812 hw
->ledctl_mode1
= hw
->ledctl_default
;
4813 hw
->ledctl_mode2
= hw
->ledctl_default
;
4815 if(e1000_read_eeprom(hw
, EEPROM_ID_LED_SETTINGS
, 1, &eeprom_data
) < 0) {
4816 DEBUGOUT("EEPROM Read Error\n");
4817 return -E1000_ERR_EEPROM
;
4819 if((eeprom_data
== ID_LED_RESERVED_0000
) ||
4820 (eeprom_data
== ID_LED_RESERVED_FFFF
)) eeprom_data
= ID_LED_DEFAULT
;
4821 for(i
= 0; i
< 4; i
++) {
4822 temp
= (eeprom_data
>> (i
<< 2)) & led_mask
;
4824 case ID_LED_ON1_DEF2
:
4825 case ID_LED_ON1_ON2
:
4826 case ID_LED_ON1_OFF2
:
4827 hw
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
4828 hw
->ledctl_mode1
|= ledctl_on
<< (i
<< 3);
4830 case ID_LED_OFF1_DEF2
:
4831 case ID_LED_OFF1_ON2
:
4832 case ID_LED_OFF1_OFF2
:
4833 hw
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
4834 hw
->ledctl_mode1
|= ledctl_off
<< (i
<< 3);
4841 case ID_LED_DEF1_ON2
:
4842 case ID_LED_ON1_ON2
:
4843 case ID_LED_OFF1_ON2
:
4844 hw
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
4845 hw
->ledctl_mode2
|= ledctl_on
<< (i
<< 3);
4847 case ID_LED_DEF1_OFF2
:
4848 case ID_LED_ON1_OFF2
:
4849 case ID_LED_OFF1_OFF2
:
4850 hw
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
4851 hw
->ledctl_mode2
|= ledctl_off
<< (i
<< 3);
4858 return E1000_SUCCESS
;
4861 /******************************************************************************
4862 * Prepares SW controlable LED for use and saves the current state of the LED.
4864 * hw - Struct containing variables accessed by shared code
4865 *****************************************************************************/
4867 e1000_setup_led(struct e1000_hw
*hw
)
4870 int32_t ret_val
= E1000_SUCCESS
;
4872 DEBUGFUNC("e1000_setup_led");
4874 switch(hw
->mac_type
) {
4875 case e1000_82542_rev2_0
:
4876 case e1000_82542_rev2_1
:
4879 /* No setup necessary */
4883 case e1000_82541_rev_2
:
4884 case e1000_82547_rev_2
:
4885 /* Turn off PHY Smart Power Down (if enabled) */
4886 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_GMII_FIFO
,
4887 &hw
->phy_spd_default
);
4890 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_GMII_FIFO
,
4891 (uint16_t)(hw
->phy_spd_default
&
4892 ~IGP01E1000_GMII_SPD
));
4897 if(hw
->media_type
== e1000_media_type_fiber
) {
4898 ledctl
= E1000_READ_REG(hw
, LEDCTL
);
4899 /* Save current LEDCTL settings */
4900 hw
->ledctl_default
= ledctl
;
4902 ledctl
&= ~(E1000_LEDCTL_LED0_IVRT
|
4903 E1000_LEDCTL_LED0_BLINK
|
4904 E1000_LEDCTL_LED0_MODE_MASK
);
4905 ledctl
|= (E1000_LEDCTL_MODE_LED_OFF
<<
4906 E1000_LEDCTL_LED0_MODE_SHIFT
);
4907 E1000_WRITE_REG(hw
, LEDCTL
, ledctl
);
4908 } else if(hw
->media_type
== e1000_media_type_copper
)
4909 E1000_WRITE_REG(hw
, LEDCTL
, hw
->ledctl_mode1
);
4913 return E1000_SUCCESS
;
4916 /******************************************************************************
4917 * Restores the saved state of the SW controlable LED.
4919 * hw - Struct containing variables accessed by shared code
4920 *****************************************************************************/
4922 e1000_cleanup_led(struct e1000_hw
*hw
)
4924 int32_t ret_val
= E1000_SUCCESS
;
4926 DEBUGFUNC("e1000_cleanup_led");
4928 switch(hw
->mac_type
) {
4929 case e1000_82542_rev2_0
:
4930 case e1000_82542_rev2_1
:
4933 /* No cleanup necessary */
4937 case e1000_82541_rev_2
:
4938 case e1000_82547_rev_2
:
4939 /* Turn on PHY Smart Power Down (if previously enabled) */
4940 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_GMII_FIFO
,
4941 hw
->phy_spd_default
);
4946 /* Restore LEDCTL settings */
4947 E1000_WRITE_REG(hw
, LEDCTL
, hw
->ledctl_default
);
4951 return E1000_SUCCESS
;
4954 /******************************************************************************
4955 * Turns on the software controllable LED
4957 * hw - Struct containing variables accessed by shared code
4958 *****************************************************************************/
4960 e1000_led_on(struct e1000_hw
*hw
)
4962 uint32_t ctrl
= E1000_READ_REG(hw
, CTRL
);
4964 DEBUGFUNC("e1000_led_on");
4966 switch(hw
->mac_type
) {
4967 case e1000_82542_rev2_0
:
4968 case e1000_82542_rev2_1
:
4970 /* Set SW Defineable Pin 0 to turn on the LED */
4971 ctrl
|= E1000_CTRL_SWDPIN0
;
4972 ctrl
|= E1000_CTRL_SWDPIO0
;
4975 if(hw
->media_type
== e1000_media_type_fiber
) {
4976 /* Set SW Defineable Pin 0 to turn on the LED */
4977 ctrl
|= E1000_CTRL_SWDPIN0
;
4978 ctrl
|= E1000_CTRL_SWDPIO0
;
4980 /* Clear SW Defineable Pin 0 to turn on the LED */
4981 ctrl
&= ~E1000_CTRL_SWDPIN0
;
4982 ctrl
|= E1000_CTRL_SWDPIO0
;
4986 if(hw
->media_type
== e1000_media_type_fiber
) {
4987 /* Clear SW Defineable Pin 0 to turn on the LED */
4988 ctrl
&= ~E1000_CTRL_SWDPIN0
;
4989 ctrl
|= E1000_CTRL_SWDPIO0
;
4990 } else if(hw
->media_type
== e1000_media_type_copper
) {
4991 E1000_WRITE_REG(hw
, LEDCTL
, hw
->ledctl_mode2
);
4992 return E1000_SUCCESS
;
4997 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
4999 return E1000_SUCCESS
;
5002 /******************************************************************************
5003 * Turns off the software controllable LED
5005 * hw - Struct containing variables accessed by shared code
5006 *****************************************************************************/
5008 e1000_led_off(struct e1000_hw
*hw
)
5010 uint32_t ctrl
= E1000_READ_REG(hw
, CTRL
);
5012 DEBUGFUNC("e1000_led_off");
5014 switch(hw
->mac_type
) {
5015 case e1000_82542_rev2_0
:
5016 case e1000_82542_rev2_1
:
5018 /* Clear SW Defineable Pin 0 to turn off the LED */
5019 ctrl
&= ~E1000_CTRL_SWDPIN0
;
5020 ctrl
|= E1000_CTRL_SWDPIO0
;
5023 if(hw
->media_type
== e1000_media_type_fiber
) {
5024 /* Clear SW Defineable Pin 0 to turn off the LED */
5025 ctrl
&= ~E1000_CTRL_SWDPIN0
;
5026 ctrl
|= E1000_CTRL_SWDPIO0
;
5028 /* Set SW Defineable Pin 0 to turn off the LED */
5029 ctrl
|= E1000_CTRL_SWDPIN0
;
5030 ctrl
|= E1000_CTRL_SWDPIO0
;
5034 if(hw
->media_type
== e1000_media_type_fiber
) {
5035 /* Set SW Defineable Pin 0 to turn off the LED */
5036 ctrl
|= E1000_CTRL_SWDPIN0
;
5037 ctrl
|= E1000_CTRL_SWDPIO0
;
5038 } else if(hw
->media_type
== e1000_media_type_copper
) {
5039 E1000_WRITE_REG(hw
, LEDCTL
, hw
->ledctl_mode1
);
5040 return E1000_SUCCESS
;
5045 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
5047 return E1000_SUCCESS
;
5050 /******************************************************************************
5051 * Clears all hardware statistics counters.
5053 * hw - Struct containing variables accessed by shared code
5054 *****************************************************************************/
5056 e1000_clear_hw_cntrs(struct e1000_hw
*hw
)
5058 volatile uint32_t temp
;
5060 temp
= E1000_READ_REG(hw
, CRCERRS
);
5061 temp
= E1000_READ_REG(hw
, SYMERRS
);
5062 temp
= E1000_READ_REG(hw
, MPC
);
5063 temp
= E1000_READ_REG(hw
, SCC
);
5064 temp
= E1000_READ_REG(hw
, ECOL
);
5065 temp
= E1000_READ_REG(hw
, MCC
);
5066 temp
= E1000_READ_REG(hw
, LATECOL
);
5067 temp
= E1000_READ_REG(hw
, COLC
);
5068 temp
= E1000_READ_REG(hw
, DC
);
5069 temp
= E1000_READ_REG(hw
, SEC
);
5070 temp
= E1000_READ_REG(hw
, RLEC
);
5071 temp
= E1000_READ_REG(hw
, XONRXC
);
5072 temp
= E1000_READ_REG(hw
, XONTXC
);
5073 temp
= E1000_READ_REG(hw
, XOFFRXC
);
5074 temp
= E1000_READ_REG(hw
, XOFFTXC
);
5075 temp
= E1000_READ_REG(hw
, FCRUC
);
5076 temp
= E1000_READ_REG(hw
, PRC64
);
5077 temp
= E1000_READ_REG(hw
, PRC127
);
5078 temp
= E1000_READ_REG(hw
, PRC255
);
5079 temp
= E1000_READ_REG(hw
, PRC511
);
5080 temp
= E1000_READ_REG(hw
, PRC1023
);
5081 temp
= E1000_READ_REG(hw
, PRC1522
);
5082 temp
= E1000_READ_REG(hw
, GPRC
);
5083 temp
= E1000_READ_REG(hw
, BPRC
);
5084 temp
= E1000_READ_REG(hw
, MPRC
);
5085 temp
= E1000_READ_REG(hw
, GPTC
);
5086 temp
= E1000_READ_REG(hw
, GORCL
);
5087 temp
= E1000_READ_REG(hw
, GORCH
);
5088 temp
= E1000_READ_REG(hw
, GOTCL
);
5089 temp
= E1000_READ_REG(hw
, GOTCH
);
5090 temp
= E1000_READ_REG(hw
, RNBC
);
5091 temp
= E1000_READ_REG(hw
, RUC
);
5092 temp
= E1000_READ_REG(hw
, RFC
);
5093 temp
= E1000_READ_REG(hw
, ROC
);
5094 temp
= E1000_READ_REG(hw
, RJC
);
5095 temp
= E1000_READ_REG(hw
, TORL
);
5096 temp
= E1000_READ_REG(hw
, TORH
);
5097 temp
= E1000_READ_REG(hw
, TOTL
);
5098 temp
= E1000_READ_REG(hw
, TOTH
);
5099 temp
= E1000_READ_REG(hw
, TPR
);
5100 temp
= E1000_READ_REG(hw
, TPT
);
5101 temp
= E1000_READ_REG(hw
, PTC64
);
5102 temp
= E1000_READ_REG(hw
, PTC127
);
5103 temp
= E1000_READ_REG(hw
, PTC255
);
5104 temp
= E1000_READ_REG(hw
, PTC511
);
5105 temp
= E1000_READ_REG(hw
, PTC1023
);
5106 temp
= E1000_READ_REG(hw
, PTC1522
);
5107 temp
= E1000_READ_REG(hw
, MPTC
);
5108 temp
= E1000_READ_REG(hw
, BPTC
);
5110 if(hw
->mac_type
< e1000_82543
) return;
5112 temp
= E1000_READ_REG(hw
, ALGNERRC
);
5113 temp
= E1000_READ_REG(hw
, RXERRC
);
5114 temp
= E1000_READ_REG(hw
, TNCRS
);
5115 temp
= E1000_READ_REG(hw
, CEXTERR
);
5116 temp
= E1000_READ_REG(hw
, TSCTC
);
5117 temp
= E1000_READ_REG(hw
, TSCTFC
);
5119 if(hw
->mac_type
<= e1000_82544
) return;
5121 temp
= E1000_READ_REG(hw
, MGTPRC
);
5122 temp
= E1000_READ_REG(hw
, MGTPDC
);
5123 temp
= E1000_READ_REG(hw
, MGTPTC
);
5125 if(hw
->mac_type
<= e1000_82547_rev_2
) return;
5127 temp
= E1000_READ_REG(hw
, IAC
);
5128 temp
= E1000_READ_REG(hw
, ICRXOC
);
5129 temp
= E1000_READ_REG(hw
, ICRXPTC
);
5130 temp
= E1000_READ_REG(hw
, ICRXATC
);
5131 temp
= E1000_READ_REG(hw
, ICTXPTC
);
5132 temp
= E1000_READ_REG(hw
, ICTXATC
);
5133 temp
= E1000_READ_REG(hw
, ICTXQEC
);
5134 temp
= E1000_READ_REG(hw
, ICTXQMTC
);
5135 temp
= E1000_READ_REG(hw
, ICRXDMTC
);
5138 /******************************************************************************
5139 * Resets Adaptive IFS to its default state.
5141 * hw - Struct containing variables accessed by shared code
5143 * Call this after e1000_init_hw. You may override the IFS defaults by setting
5144 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
5145 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
5146 * before calling this function.
5147 *****************************************************************************/
5149 e1000_reset_adaptive(struct e1000_hw
*hw
)
5151 DEBUGFUNC("e1000_reset_adaptive");
5153 if(hw
->adaptive_ifs
) {
5154 if(!hw
->ifs_params_forced
) {
5155 hw
->current_ifs_val
= 0;
5156 hw
->ifs_min_val
= IFS_MIN
;
5157 hw
->ifs_max_val
= IFS_MAX
;
5158 hw
->ifs_step_size
= IFS_STEP
;
5159 hw
->ifs_ratio
= IFS_RATIO
;
5161 hw
->in_ifs_mode
= FALSE
;
5162 E1000_WRITE_REG(hw
, AIT
, 0);
5164 DEBUGOUT("Not in Adaptive IFS mode!\n");
5168 /******************************************************************************
5169 * Called during the callback/watchdog routine to update IFS value based on
5170 * the ratio of transmits to collisions.
5172 * hw - Struct containing variables accessed by shared code
5173 * tx_packets - Number of transmits since last callback
5174 * total_collisions - Number of collisions since last callback
5175 *****************************************************************************/
5177 e1000_update_adaptive(struct e1000_hw
*hw
)
5179 DEBUGFUNC("e1000_update_adaptive");
5181 if(hw
->adaptive_ifs
) {
5182 if((hw
->collision_delta
* hw
->ifs_ratio
) > hw
->tx_packet_delta
) {
5183 if(hw
->tx_packet_delta
> MIN_NUM_XMITS
) {
5184 hw
->in_ifs_mode
= TRUE
;
5185 if(hw
->current_ifs_val
< hw
->ifs_max_val
) {
5186 if(hw
->current_ifs_val
== 0)
5187 hw
->current_ifs_val
= hw
->ifs_min_val
;
5189 hw
->current_ifs_val
+= hw
->ifs_step_size
;
5190 E1000_WRITE_REG(hw
, AIT
, hw
->current_ifs_val
);
5194 if(hw
->in_ifs_mode
&& (hw
->tx_packet_delta
<= MIN_NUM_XMITS
)) {
5195 hw
->current_ifs_val
= 0;
5196 hw
->in_ifs_mode
= FALSE
;
5197 E1000_WRITE_REG(hw
, AIT
, 0);
5201 DEBUGOUT("Not in Adaptive IFS mode!\n");
5205 /******************************************************************************
5206 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
5208 * hw - Struct containing variables accessed by shared code
5209 * frame_len - The length of the frame in question
5210 * mac_addr - The Ethernet destination address of the frame in question
5211 *****************************************************************************/
5213 e1000_tbi_adjust_stats(struct e1000_hw
*hw
,
5214 struct e1000_hw_stats
*stats
,
5220 /* First adjust the frame length. */
5222 /* We need to adjust the statistics counters, since the hardware
5223 * counters overcount this packet as a CRC error and undercount
5224 * the packet as a good packet
5226 /* This packet should not be counted as a CRC error. */
5228 /* This packet does count as a Good Packet Received. */
5231 /* Adjust the Good Octets received counters */
5232 carry_bit
= 0x80000000 & stats
->gorcl
;
5233 stats
->gorcl
+= frame_len
;
5234 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
5235 * Received Count) was one before the addition,
5236 * AND it is zero after, then we lost the carry out,
5237 * need to add one to Gorch (Good Octets Received Count High).
5238 * This could be simplified if all environments supported
5241 if(carry_bit
&& ((stats
->gorcl
& 0x80000000) == 0))
5243 /* Is this a broadcast or multicast? Check broadcast first,
5244 * since the test for a multicast frame will test positive on
5245 * a broadcast frame.
5247 if((mac_addr
[0] == (uint8_t) 0xff) && (mac_addr
[1] == (uint8_t) 0xff))
5248 /* Broadcast packet */
5250 else if(*mac_addr
& 0x01)
5251 /* Multicast packet */
5254 if(frame_len
== hw
->max_frame_size
) {
5255 /* In this case, the hardware has overcounted the number of
5262 /* Adjust the bin counters when the extra byte put the frame in the
5263 * wrong bin. Remember that the frame_len was adjusted above.
5265 if(frame_len
== 64) {
5268 } else if(frame_len
== 127) {
5271 } else if(frame_len
== 255) {
5274 } else if(frame_len
== 511) {
5277 } else if(frame_len
== 1023) {
5280 } else if(frame_len
== 1522) {
5285 /******************************************************************************
5286 * Gets the current PCI bus type, speed, and width of the hardware
5288 * hw - Struct containing variables accessed by shared code
5289 *****************************************************************************/
5291 e1000_get_bus_info(struct e1000_hw
*hw
)
5295 switch (hw
->mac_type
) {
5296 case e1000_82542_rev2_0
:
5297 case e1000_82542_rev2_1
:
5298 hw
->bus_type
= e1000_bus_type_unknown
;
5299 hw
->bus_speed
= e1000_bus_speed_unknown
;
5300 hw
->bus_width
= e1000_bus_width_unknown
;
5304 hw
->bus_type
= e1000_bus_type_pci_express
;
5305 hw
->bus_speed
= e1000_bus_speed_2500
;
5306 hw
->bus_width
= e1000_bus_width_pciex_1
;
5309 hw
->bus_type
= e1000_bus_type_pci_express
;
5310 hw
->bus_speed
= e1000_bus_speed_2500
;
5311 hw
->bus_width
= e1000_bus_width_pciex_4
;
5314 status
= E1000_READ_REG(hw
, STATUS
);
5315 hw
->bus_type
= (status
& E1000_STATUS_PCIX_MODE
) ?
5316 e1000_bus_type_pcix
: e1000_bus_type_pci
;
5318 if(hw
->device_id
== E1000_DEV_ID_82546EB_QUAD_COPPER
) {
5319 hw
->bus_speed
= (hw
->bus_type
== e1000_bus_type_pci
) ?
5320 e1000_bus_speed_66
: e1000_bus_speed_120
;
5321 } else if(hw
->bus_type
== e1000_bus_type_pci
) {
5322 hw
->bus_speed
= (status
& E1000_STATUS_PCI66
) ?
5323 e1000_bus_speed_66
: e1000_bus_speed_33
;
5325 switch (status
& E1000_STATUS_PCIX_SPEED
) {
5326 case E1000_STATUS_PCIX_SPEED_66
:
5327 hw
->bus_speed
= e1000_bus_speed_66
;
5329 case E1000_STATUS_PCIX_SPEED_100
:
5330 hw
->bus_speed
= e1000_bus_speed_100
;
5332 case E1000_STATUS_PCIX_SPEED_133
:
5333 hw
->bus_speed
= e1000_bus_speed_133
;
5336 hw
->bus_speed
= e1000_bus_speed_reserved
;
5340 hw
->bus_width
= (status
& E1000_STATUS_BUS64
) ?
5341 e1000_bus_width_64
: e1000_bus_width_32
;
5347 /******************************************************************************
5348 * Reads a value from one of the devices registers using port I/O (as opposed
5349 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5351 * hw - Struct containing variables accessed by shared code
5352 * offset - offset to read from
5353 *****************************************************************************/
5355 e1000_read_reg_io(struct e1000_hw
*hw
,
5358 unsigned long io_addr
= hw
->io_base
;
5359 unsigned long io_data
= hw
->io_base
+ 4;
5361 e1000_io_write(hw
, io_addr
, offset
);
5362 return e1000_io_read(hw
, io_data
);
5366 /******************************************************************************
5367 * Writes a value to one of the devices registers using port I/O (as opposed to
5368 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5370 * hw - Struct containing variables accessed by shared code
5371 * offset - offset to write to
5372 * value - value to write
5373 *****************************************************************************/
5375 e1000_write_reg_io(struct e1000_hw
*hw
,
5379 unsigned long io_addr
= hw
->io_base
;
5380 unsigned long io_data
= hw
->io_base
+ 4;
5382 e1000_io_write(hw
, io_addr
, offset
);
5383 e1000_io_write(hw
, io_data
, value
);
5387 /******************************************************************************
5388 * Estimates the cable length.
5390 * hw - Struct containing variables accessed by shared code
5391 * min_length - The estimated minimum length
5392 * max_length - The estimated maximum length
5394 * returns: - E1000_ERR_XXX
5397 * This function always returns a ranged length (minimum & maximum).
5398 * So for M88 phy's, this function interprets the one value returned from the
5399 * register to the minimum and maximum range.
5400 * For IGP phy's, the function calculates the range by the AGC registers.
5401 *****************************************************************************/
5403 e1000_get_cable_length(struct e1000_hw
*hw
,
5404 uint16_t *min_length
,
5405 uint16_t *max_length
)
5408 uint16_t agc_value
= 0;
5409 uint16_t cur_agc
, min_agc
= IGP01E1000_AGC_LENGTH_TABLE_SIZE
;
5410 uint16_t max_agc
= 0;
5411 uint16_t i
, phy_data
;
5412 uint16_t cable_length
;
5414 DEBUGFUNC("e1000_get_cable_length");
5416 *min_length
= *max_length
= 0;
5418 /* Use old method for Phy older than IGP */
5419 if(hw
->phy_type
== e1000_phy_m88
) {
5421 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
,
5425 cable_length
= (phy_data
& M88E1000_PSSR_CABLE_LENGTH
) >>
5426 M88E1000_PSSR_CABLE_LENGTH_SHIFT
;
5428 /* Convert the enum value to ranged values */
5429 switch (cable_length
) {
5430 case e1000_cable_length_50
:
5432 *max_length
= e1000_igp_cable_length_50
;
5434 case e1000_cable_length_50_80
:
5435 *min_length
= e1000_igp_cable_length_50
;
5436 *max_length
= e1000_igp_cable_length_80
;
5438 case e1000_cable_length_80_110
:
5439 *min_length
= e1000_igp_cable_length_80
;
5440 *max_length
= e1000_igp_cable_length_110
;
5442 case e1000_cable_length_110_140
:
5443 *min_length
= e1000_igp_cable_length_110
;
5444 *max_length
= e1000_igp_cable_length_140
;
5446 case e1000_cable_length_140
:
5447 *min_length
= e1000_igp_cable_length_140
;
5448 *max_length
= e1000_igp_cable_length_170
;
5451 return -E1000_ERR_PHY
;
5454 } else if(hw
->phy_type
== e1000_phy_igp
) { /* For IGP PHY */
5455 uint16_t agc_reg_array
[IGP01E1000_PHY_CHANNEL_NUM
] =
5456 {IGP01E1000_PHY_AGC_A
,
5457 IGP01E1000_PHY_AGC_B
,
5458 IGP01E1000_PHY_AGC_C
,
5459 IGP01E1000_PHY_AGC_D
};
5460 /* Read the AGC registers for all channels */
5461 for(i
= 0; i
< IGP01E1000_PHY_CHANNEL_NUM
; i
++) {
5463 ret_val
= e1000_read_phy_reg(hw
, agc_reg_array
[i
], &phy_data
);
5467 cur_agc
= phy_data
>> IGP01E1000_AGC_LENGTH_SHIFT
;
5469 /* Array bound check. */
5470 if((cur_agc
>= IGP01E1000_AGC_LENGTH_TABLE_SIZE
- 1) ||
5472 return -E1000_ERR_PHY
;
5474 agc_value
+= cur_agc
;
5476 /* Update minimal AGC value. */
5477 if(min_agc
> cur_agc
)
5481 /* Remove the minimal AGC result for length < 50m */
5482 if(agc_value
< IGP01E1000_PHY_CHANNEL_NUM
* e1000_igp_cable_length_50
) {
5483 agc_value
-= min_agc
;
5485 /* Get the average length of the remaining 3 channels */
5486 agc_value
/= (IGP01E1000_PHY_CHANNEL_NUM
- 1);
5488 /* Get the average length of all the 4 channels. */
5489 agc_value
/= IGP01E1000_PHY_CHANNEL_NUM
;
5492 /* Set the range of the calculated length. */
5493 *min_length
= ((e1000_igp_cable_length_table
[agc_value
] -
5494 IGP01E1000_AGC_RANGE
) > 0) ?
5495 (e1000_igp_cable_length_table
[agc_value
] -
5496 IGP01E1000_AGC_RANGE
) : 0;
5497 *max_length
= e1000_igp_cable_length_table
[agc_value
] +
5498 IGP01E1000_AGC_RANGE
;
5499 } else if (hw
->phy_type
== e1000_phy_igp_2
) {
5500 uint16_t agc_reg_array
[IGP02E1000_PHY_CHANNEL_NUM
] =
5501 {IGP02E1000_PHY_AGC_A
,
5502 IGP02E1000_PHY_AGC_B
,
5503 IGP02E1000_PHY_AGC_C
,
5504 IGP02E1000_PHY_AGC_D
};
5505 /* Read the AGC registers for all channels */
5506 for (i
= 0; i
< IGP02E1000_PHY_CHANNEL_NUM
; i
++) {
5507 ret_val
= e1000_read_phy_reg(hw
, agc_reg_array
[i
], &phy_data
);
5511 /* Getting bits 15:9, which represent the combination of course and
5512 * fine gain values. The result is a number that can be put into
5513 * the lookup table to obtain the approximate cable length. */
5514 cur_agc
= (phy_data
>> IGP02E1000_AGC_LENGTH_SHIFT
) &
5515 IGP02E1000_AGC_LENGTH_MASK
;
5517 /* Remove min & max AGC values from calculation. */
5518 if (e1000_igp_2_cable_length_table
[min_agc
] > e1000_igp_2_cable_length_table
[cur_agc
])
5520 if (e1000_igp_2_cable_length_table
[max_agc
] < e1000_igp_2_cable_length_table
[cur_agc
])
5523 agc_value
+= e1000_igp_2_cable_length_table
[cur_agc
];
5526 agc_value
-= (e1000_igp_2_cable_length_table
[min_agc
] + e1000_igp_2_cable_length_table
[max_agc
]);
5527 agc_value
/= (IGP02E1000_PHY_CHANNEL_NUM
- 2);
5529 /* Calculate cable length with the error range of +/- 10 meters. */
5530 *min_length
= ((agc_value
- IGP02E1000_AGC_RANGE
) > 0) ?
5531 (agc_value
- IGP02E1000_AGC_RANGE
) : 0;
5532 *max_length
= agc_value
+ IGP02E1000_AGC_RANGE
;
5535 return E1000_SUCCESS
;
5538 /******************************************************************************
5539 * Check the cable polarity
5541 * hw - Struct containing variables accessed by shared code
5542 * polarity - output parameter : 0 - Polarity is not reversed
5543 * 1 - Polarity is reversed.
5545 * returns: - E1000_ERR_XXX
5548 * For phy's older then IGP, this function simply reads the polarity bit in the
5549 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
5550 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
5551 * return 0. If the link speed is 1000 Mbps the polarity status is in the
5552 * IGP01E1000_PHY_PCS_INIT_REG.
5553 *****************************************************************************/
5555 e1000_check_polarity(struct e1000_hw
*hw
,
5561 DEBUGFUNC("e1000_check_polarity");
5563 if(hw
->phy_type
== e1000_phy_m88
) {
5564 /* return the Polarity bit in the Status register. */
5565 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
,
5569 *polarity
= (phy_data
& M88E1000_PSSR_REV_POLARITY
) >>
5570 M88E1000_PSSR_REV_POLARITY_SHIFT
;
5571 } else if(hw
->phy_type
== e1000_phy_igp
||
5572 hw
->phy_type
== e1000_phy_igp_2
) {
5573 /* Read the Status register to check the speed */
5574 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_STATUS
,
5579 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
5580 * find the polarity status */
5581 if((phy_data
& IGP01E1000_PSSR_SPEED_MASK
) ==
5582 IGP01E1000_PSSR_SPEED_1000MBPS
) {
5584 /* Read the GIG initialization PCS register (0x00B4) */
5585 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PCS_INIT_REG
,
5590 /* Check the polarity bits */
5591 *polarity
= (phy_data
& IGP01E1000_PHY_POLARITY_MASK
) ? 1 : 0;
5593 /* For 10 Mbps, read the polarity bit in the status register. (for
5594 * 100 Mbps this bit is always 0) */
5595 *polarity
= phy_data
& IGP01E1000_PSSR_POLARITY_REVERSED
;
5598 return E1000_SUCCESS
;
5601 /******************************************************************************
5602 * Check if Downshift occured
5604 * hw - Struct containing variables accessed by shared code
5605 * downshift - output parameter : 0 - No Downshift ocured.
5606 * 1 - Downshift ocured.
5608 * returns: - E1000_ERR_XXX
5611 * For phy's older then IGP, this function reads the Downshift bit in the Phy
5612 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
5613 * Link Health register. In IGP this bit is latched high, so the driver must
5614 * read it immediately after link is established.
5615 *****************************************************************************/
5617 e1000_check_downshift(struct e1000_hw
*hw
)
5622 DEBUGFUNC("e1000_check_downshift");
5624 if(hw
->phy_type
== e1000_phy_igp
||
5625 hw
->phy_type
== e1000_phy_igp_2
) {
5626 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_LINK_HEALTH
,
5631 hw
->speed_downgraded
= (phy_data
& IGP01E1000_PLHR_SS_DOWNGRADE
) ? 1 : 0;
5632 } else if(hw
->phy_type
== e1000_phy_m88
) {
5633 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_SPEC_STATUS
,
5638 hw
->speed_downgraded
= (phy_data
& M88E1000_PSSR_DOWNSHIFT
) >>
5639 M88E1000_PSSR_DOWNSHIFT_SHIFT
;
5642 return E1000_SUCCESS
;
5645 /*****************************************************************************
5647 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
5648 * gigabit link is achieved to improve link quality.
5650 * hw: Struct containing variables accessed by shared code
5652 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5653 * E1000_SUCCESS at any other case.
5655 ****************************************************************************/
5658 e1000_config_dsp_after_link_change(struct e1000_hw
*hw
,
5662 uint16_t phy_data
, phy_saved_data
, speed
, duplex
, i
;
5663 uint16_t dsp_reg_array
[IGP01E1000_PHY_CHANNEL_NUM
] =
5664 {IGP01E1000_PHY_AGC_PARAM_A
,
5665 IGP01E1000_PHY_AGC_PARAM_B
,
5666 IGP01E1000_PHY_AGC_PARAM_C
,
5667 IGP01E1000_PHY_AGC_PARAM_D
};
5668 uint16_t min_length
, max_length
;
5670 DEBUGFUNC("e1000_config_dsp_after_link_change");
5672 if(hw
->phy_type
!= e1000_phy_igp
)
5673 return E1000_SUCCESS
;
5676 ret_val
= e1000_get_speed_and_duplex(hw
, &speed
, &duplex
);
5678 DEBUGOUT("Error getting link speed and duplex\n");
5682 if(speed
== SPEED_1000
) {
5684 e1000_get_cable_length(hw
, &min_length
, &max_length
);
5686 if((hw
->dsp_config_state
== e1000_dsp_config_enabled
) &&
5687 min_length
>= e1000_igp_cable_length_50
) {
5689 for(i
= 0; i
< IGP01E1000_PHY_CHANNEL_NUM
; i
++) {
5690 ret_val
= e1000_read_phy_reg(hw
, dsp_reg_array
[i
],
5695 phy_data
&= ~IGP01E1000_PHY_EDAC_MU_INDEX
;
5697 ret_val
= e1000_write_phy_reg(hw
, dsp_reg_array
[i
],
5702 hw
->dsp_config_state
= e1000_dsp_config_activated
;
5705 if((hw
->ffe_config_state
== e1000_ffe_config_enabled
) &&
5706 (min_length
< e1000_igp_cable_length_50
)) {
5708 uint16_t ffe_idle_err_timeout
= FFE_IDLE_ERR_COUNT_TIMEOUT_20
;
5709 uint32_t idle_errs
= 0;
5711 /* clear previous idle error counts */
5712 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_STATUS
,
5717 for(i
= 0; i
< ffe_idle_err_timeout
; i
++) {
5719 ret_val
= e1000_read_phy_reg(hw
, PHY_1000T_STATUS
,
5724 idle_errs
+= (phy_data
& SR_1000T_IDLE_ERROR_CNT
);
5725 if(idle_errs
> SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT
) {
5726 hw
->ffe_config_state
= e1000_ffe_config_active
;
5728 ret_val
= e1000_write_phy_reg(hw
,
5729 IGP01E1000_PHY_DSP_FFE
,
5730 IGP01E1000_PHY_DSP_FFE_CM_CP
);
5737 ffe_idle_err_timeout
= FFE_IDLE_ERR_COUNT_TIMEOUT_100
;
5742 if(hw
->dsp_config_state
== e1000_dsp_config_activated
) {
5743 /* Save off the current value of register 0x2F5B to be restored at
5744 * the end of the routines. */
5745 ret_val
= e1000_read_phy_reg(hw
, 0x2F5B, &phy_saved_data
);
5750 /* Disable the PHY transmitter */
5751 ret_val
= e1000_write_phy_reg(hw
, 0x2F5B, 0x0003);
5758 ret_val
= e1000_write_phy_reg(hw
, 0x0000,
5759 IGP01E1000_IEEE_FORCE_GIGA
);
5762 for(i
= 0; i
< IGP01E1000_PHY_CHANNEL_NUM
; i
++) {
5763 ret_val
= e1000_read_phy_reg(hw
, dsp_reg_array
[i
], &phy_data
);
5767 phy_data
&= ~IGP01E1000_PHY_EDAC_MU_INDEX
;
5768 phy_data
|= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS
;
5770 ret_val
= e1000_write_phy_reg(hw
,dsp_reg_array
[i
], phy_data
);
5775 ret_val
= e1000_write_phy_reg(hw
, 0x0000,
5776 IGP01E1000_IEEE_RESTART_AUTONEG
);
5782 /* Now enable the transmitter */
5783 ret_val
= e1000_write_phy_reg(hw
, 0x2F5B, phy_saved_data
);
5788 hw
->dsp_config_state
= e1000_dsp_config_enabled
;
5791 if(hw
->ffe_config_state
== e1000_ffe_config_active
) {
5792 /* Save off the current value of register 0x2F5B to be restored at
5793 * the end of the routines. */
5794 ret_val
= e1000_read_phy_reg(hw
, 0x2F5B, &phy_saved_data
);
5799 /* Disable the PHY transmitter */
5800 ret_val
= e1000_write_phy_reg(hw
, 0x2F5B, 0x0003);
5807 ret_val
= e1000_write_phy_reg(hw
, 0x0000,
5808 IGP01E1000_IEEE_FORCE_GIGA
);
5811 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_DSP_FFE
,
5812 IGP01E1000_PHY_DSP_FFE_DEFAULT
);
5816 ret_val
= e1000_write_phy_reg(hw
, 0x0000,
5817 IGP01E1000_IEEE_RESTART_AUTONEG
);
5823 /* Now enable the transmitter */
5824 ret_val
= e1000_write_phy_reg(hw
, 0x2F5B, phy_saved_data
);
5829 hw
->ffe_config_state
= e1000_ffe_config_enabled
;
5832 return E1000_SUCCESS
;
5835 /*****************************************************************************
5836 * Set PHY to class A mode
5837 * Assumes the following operations will follow to enable the new class mode.
5838 * 1. Do a PHY soft reset
5839 * 2. Restart auto-negotiation or force link.
5841 * hw - Struct containing variables accessed by shared code
5842 ****************************************************************************/
5844 e1000_set_phy_mode(struct e1000_hw
*hw
)
5847 uint16_t eeprom_data
;
5849 DEBUGFUNC("e1000_set_phy_mode");
5851 if((hw
->mac_type
== e1000_82545_rev_3
) &&
5852 (hw
->media_type
== e1000_media_type_copper
)) {
5853 ret_val
= e1000_read_eeprom(hw
, EEPROM_PHY_CLASS_WORD
, 1, &eeprom_data
);
5858 if((eeprom_data
!= EEPROM_RESERVED_WORD
) &&
5859 (eeprom_data
& EEPROM_PHY_CLASS_A
)) {
5860 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x000B);
5863 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0x8104);
5867 hw
->phy_reset_disable
= FALSE
;
5871 return E1000_SUCCESS
;
5874 /*****************************************************************************
5876 * This function sets the lplu state according to the active flag. When
5877 * activating lplu this function also disables smart speed and vise versa.
5878 * lplu will not be activated unless the device autonegotiation advertisment
5879 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5880 * hw: Struct containing variables accessed by shared code
5881 * active - true to enable lplu false to disable lplu.
5883 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5884 * E1000_SUCCESS at any other case.
5886 ****************************************************************************/
5889 e1000_set_d3_lplu_state(struct e1000_hw
*hw
,
5894 DEBUGFUNC("e1000_set_d3_lplu_state");
5896 if(hw
->phy_type
!= e1000_phy_igp
&& hw
->phy_type
!= e1000_phy_igp_2
)
5897 return E1000_SUCCESS
;
5899 /* During driver activity LPLU should not be used or it will attain link
5900 * from the lowest speeds starting from 10Mbps. The capability is used for
5901 * Dx transitions and states */
5902 if(hw
->mac_type
== e1000_82541_rev_2
|| hw
->mac_type
== e1000_82547_rev_2
) {
5903 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_GMII_FIFO
, &phy_data
);
5907 ret_val
= e1000_read_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &phy_data
);
5913 if(hw
->mac_type
== e1000_82541_rev_2
||
5914 hw
->mac_type
== e1000_82547_rev_2
) {
5915 phy_data
&= ~IGP01E1000_GMII_FLEX_SPD
;
5916 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_GMII_FIFO
, phy_data
);
5920 phy_data
&= ~IGP02E1000_PM_D3_LPLU
;
5921 ret_val
= e1000_write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
5927 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5928 * Dx states where the power conservation is most important. During
5929 * driver activity we should enable SmartSpeed, so performance is
5931 if (hw
->smart_speed
== e1000_smart_speed_on
) {
5932 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5937 phy_data
|= IGP01E1000_PSCFR_SMART_SPEED
;
5938 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5942 } else if (hw
->smart_speed
== e1000_smart_speed_off
) {
5943 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5948 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
5949 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
5955 } else if((hw
->autoneg_advertised
== AUTONEG_ADVERTISE_SPEED_DEFAULT
) ||
5956 (hw
->autoneg_advertised
== AUTONEG_ADVERTISE_10_ALL
) ||
5957 (hw
->autoneg_advertised
== AUTONEG_ADVERTISE_10_100_ALL
)) {
5959 if(hw
->mac_type
== e1000_82541_rev_2
||
5960 hw
->mac_type
== e1000_82547_rev_2
) {
5961 phy_data
|= IGP01E1000_GMII_FLEX_SPD
;
5962 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_GMII_FIFO
, phy_data
);
5966 phy_data
|= IGP02E1000_PM_D3_LPLU
;
5967 ret_val
= e1000_write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
5973 /* When LPLU is enabled we should disable SmartSpeed */
5974 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, &phy_data
);
5978 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
5979 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, phy_data
);
5984 return E1000_SUCCESS
;
5987 /*****************************************************************************
5989 * This function sets the lplu d0 state according to the active flag. When
5990 * activating lplu this function also disables smart speed and vise versa.
5991 * lplu will not be activated unless the device autonegotiation advertisment
5992 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5993 * hw: Struct containing variables accessed by shared code
5994 * active - true to enable lplu false to disable lplu.
5996 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5997 * E1000_SUCCESS at any other case.
5999 ****************************************************************************/
6002 e1000_set_d0_lplu_state(struct e1000_hw
*hw
,
6007 DEBUGFUNC("e1000_set_d0_lplu_state");
6009 if(hw
->mac_type
<= e1000_82547_rev_2
)
6010 return E1000_SUCCESS
;
6012 ret_val
= e1000_read_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &phy_data
);
6017 phy_data
&= ~IGP02E1000_PM_D0_LPLU
;
6018 ret_val
= e1000_write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, phy_data
);
6022 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
6023 * Dx states where the power conservation is most important. During
6024 * driver activity we should enable SmartSpeed, so performance is
6026 if (hw
->smart_speed
== e1000_smart_speed_on
) {
6027 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
6032 phy_data
|= IGP01E1000_PSCFR_SMART_SPEED
;
6033 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
6037 } else if (hw
->smart_speed
== e1000_smart_speed_off
) {
6038 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
6043 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
6044 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
6053 phy_data
|= IGP02E1000_PM_D0_LPLU
;
6054 ret_val
= e1000_write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, phy_data
);
6058 /* When LPLU is enabled we should disable SmartSpeed */
6059 ret_val
= e1000_read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, &phy_data
);
6063 phy_data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
6064 ret_val
= e1000_write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
, phy_data
);
6069 return E1000_SUCCESS
;
6072 /******************************************************************************
6073 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
6075 * hw - Struct containing variables accessed by shared code
6076 *****************************************************************************/
6078 e1000_set_vco_speed(struct e1000_hw
*hw
)
6081 uint16_t default_page
= 0;
6084 DEBUGFUNC("e1000_set_vco_speed");
6086 switch(hw
->mac_type
) {
6087 case e1000_82545_rev_3
:
6088 case e1000_82546_rev_3
:
6091 return E1000_SUCCESS
;
6094 /* Set PHY register 30, page 5, bit 8 to 0 */
6096 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, &default_page
);
6100 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0005);
6104 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, &phy_data
);
6108 phy_data
&= ~M88E1000_PHY_VCO_REG_BIT8
;
6109 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, phy_data
);
6113 /* Set PHY register 30, page 4, bit 11 to 1 */
6115 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0004);
6119 ret_val
= e1000_read_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, &phy_data
);
6123 phy_data
|= M88E1000_PHY_VCO_REG_BIT11
;
6124 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, phy_data
);
6128 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, default_page
);
6132 return E1000_SUCCESS
;
6136 /*****************************************************************************
6137 * This function reads the cookie from ARC ram.
6139 * returns: - E1000_SUCCESS .
6140 ****************************************************************************/
6142 e1000_host_if_read_cookie(struct e1000_hw
* hw
, uint8_t *buffer
)
6145 uint32_t offset
= E1000_MNG_DHCP_COOKIE_OFFSET
;
6146 uint8_t length
= E1000_MNG_DHCP_COOKIE_LENGTH
;
6148 length
= (length
>> 2);
6149 offset
= (offset
>> 2);
6151 for (i
= 0; i
< length
; i
++) {
6152 *((uint32_t *) buffer
+ i
) =
6153 E1000_READ_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
+ i
);
6155 return E1000_SUCCESS
;
6159 /*****************************************************************************
6160 * This function checks whether the HOST IF is enabled for command operaton
6161 * and also checks whether the previous command is completed.
6162 * It busy waits in case of previous command is not completed.
6164 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
6166 * - E1000_SUCCESS for success.
6167 ****************************************************************************/
6169 e1000_mng_enable_host_if(struct e1000_hw
* hw
)
6174 /* Check that the host interface is enabled. */
6175 hicr
= E1000_READ_REG(hw
, HICR
);
6176 if ((hicr
& E1000_HICR_EN
) == 0) {
6177 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
6178 return -E1000_ERR_HOST_INTERFACE_COMMAND
;
6180 /* check the previous command is completed */
6181 for (i
= 0; i
< E1000_MNG_DHCP_COMMAND_TIMEOUT
; i
++) {
6182 hicr
= E1000_READ_REG(hw
, HICR
);
6183 if (!(hicr
& E1000_HICR_C
))
6188 if (i
== E1000_MNG_DHCP_COMMAND_TIMEOUT
) {
6189 DEBUGOUT("Previous command timeout failed .\n");
6190 return -E1000_ERR_HOST_INTERFACE_COMMAND
;
6192 return E1000_SUCCESS
;
6195 /*****************************************************************************
6196 * This function writes the buffer content at the offset given on the host if.
6197 * It also does alignment considerations to do the writes in most efficient way.
6198 * Also fills up the sum of the buffer in *buffer parameter.
6200 * returns - E1000_SUCCESS for success.
6201 ****************************************************************************/
6203 e1000_mng_host_if_write(struct e1000_hw
* hw
, uint8_t *buffer
,
6204 uint16_t length
, uint16_t offset
, uint8_t *sum
)
6207 uint8_t *bufptr
= buffer
;
6209 uint16_t remaining
, i
, j
, prev_bytes
;
6211 /* sum = only sum of the data and it is not checksum */
6213 if (length
== 0 || offset
+ length
> E1000_HI_MAX_MNG_DATA_LENGTH
) {
6214 return -E1000_ERR_PARAM
;
6217 tmp
= (uint8_t *)&data
;
6218 prev_bytes
= offset
& 0x3;
6223 data
= E1000_READ_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
);
6224 for (j
= prev_bytes
; j
< sizeof(uint32_t); j
++) {
6225 *(tmp
+ j
) = *bufptr
++;
6228 E1000_WRITE_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
, data
);
6229 length
-= j
- prev_bytes
;
6233 remaining
= length
& 0x3;
6234 length
-= remaining
;
6236 /* Calculate length in DWORDs */
6239 /* The device driver writes the relevant command block into the
6241 for (i
= 0; i
< length
; i
++) {
6242 for (j
= 0; j
< sizeof(uint32_t); j
++) {
6243 *(tmp
+ j
) = *bufptr
++;
6247 E1000_WRITE_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
+ i
, data
);
6250 for (j
= 0; j
< sizeof(uint32_t); j
++) {
6252 *(tmp
+ j
) = *bufptr
++;
6258 E1000_WRITE_REG_ARRAY_DWORD(hw
, HOST_IF
, offset
+ i
, data
);
6261 return E1000_SUCCESS
;
6265 /*****************************************************************************
6266 * This function writes the command header after does the checksum calculation.
6268 * returns - E1000_SUCCESS for success.
6269 ****************************************************************************/
6271 e1000_mng_write_cmd_header(struct e1000_hw
* hw
,
6272 struct e1000_host_mng_command_header
* hdr
)
6278 /* Write the whole command header structure which includes sum of
6281 uint16_t length
= sizeof(struct e1000_host_mng_command_header
);
6283 sum
= hdr
->checksum
;
6286 buffer
= (uint8_t *) hdr
;
6291 hdr
->checksum
= 0 - sum
;
6294 /* The device driver writes the relevant command block into the ram area. */
6295 for (i
= 0; i
< length
; i
++)
6296 E1000_WRITE_REG_ARRAY_DWORD(hw
, HOST_IF
, i
, *((uint32_t *) hdr
+ i
));
6298 return E1000_SUCCESS
;
6302 /*****************************************************************************
6303 * This function indicates to ARC that a new command is pending which completes
6304 * one write operation by the driver.
6306 * returns - E1000_SUCCESS for success.
6307 ****************************************************************************/
6309 e1000_mng_write_commit(
6310 struct e1000_hw
* hw
)
6314 hicr
= E1000_READ_REG(hw
, HICR
);
6315 /* Setting this bit tells the ARC that a new command is pending. */
6316 E1000_WRITE_REG(hw
, HICR
, hicr
| E1000_HICR_C
);
6318 return E1000_SUCCESS
;
6322 /*****************************************************************************
6323 * This function checks the mode of the firmware.
6325 * returns - TRUE when the mode is IAMT or FALSE.
6326 ****************************************************************************/
6328 e1000_check_mng_mode(
6329 struct e1000_hw
*hw
)
6333 fwsm
= E1000_READ_REG(hw
, FWSM
);
6335 if((fwsm
& E1000_FWSM_MODE_MASK
) ==
6336 (E1000_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
))
6343 /*****************************************************************************
6344 * This function writes the dhcp info .
6345 ****************************************************************************/
6347 e1000_mng_write_dhcp_info(struct e1000_hw
* hw
, uint8_t *buffer
,
6351 struct e1000_host_mng_command_header hdr
;
6353 hdr
.command_id
= E1000_MNG_DHCP_TX_PAYLOAD_CMD
;
6354 hdr
.command_length
= length
;
6359 ret_val
= e1000_mng_enable_host_if(hw
);
6360 if (ret_val
== E1000_SUCCESS
) {
6361 ret_val
= e1000_mng_host_if_write(hw
, buffer
, length
, sizeof(hdr
),
6363 if (ret_val
== E1000_SUCCESS
) {
6364 ret_val
= e1000_mng_write_cmd_header(hw
, &hdr
);
6365 if (ret_val
== E1000_SUCCESS
)
6366 ret_val
= e1000_mng_write_commit(hw
);
6373 /*****************************************************************************
6374 * This function calculates the checksum.
6376 * returns - checksum of buffer contents.
6377 ****************************************************************************/
6379 e1000_calculate_mng_checksum(char *buffer
, uint32_t length
)
6387 for (i
=0; i
< length
; i
++)
6390 return (uint8_t) (0 - sum
);
6393 /*****************************************************************************
6394 * This function checks whether tx pkt filtering needs to be enabled or not.
6396 * returns - TRUE for packet filtering or FALSE.
6397 ****************************************************************************/
6399 e1000_enable_tx_pkt_filtering(struct e1000_hw
*hw
)
6401 /* called in init as well as watchdog timer functions */
6403 int32_t ret_val
, checksum
;
6404 boolean_t tx_filter
= FALSE
;
6405 struct e1000_host_mng_dhcp_cookie
*hdr
= &(hw
->mng_cookie
);
6406 uint8_t *buffer
= (uint8_t *) &(hw
->mng_cookie
);
6408 if (e1000_check_mng_mode(hw
)) {
6409 ret_val
= e1000_mng_enable_host_if(hw
);
6410 if (ret_val
== E1000_SUCCESS
) {
6411 ret_val
= e1000_host_if_read_cookie(hw
, buffer
);
6412 if (ret_val
== E1000_SUCCESS
) {
6413 checksum
= hdr
->checksum
;
6415 if ((hdr
->signature
== E1000_IAMT_SIGNATURE
) &&
6416 checksum
== e1000_calculate_mng_checksum((char *)buffer
,
6417 E1000_MNG_DHCP_COOKIE_LENGTH
)) {
6419 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT
)
6428 hw
->tx_pkt_filtering
= tx_filter
;
6432 /******************************************************************************
6433 * Verifies the hardware needs to allow ARPs to be processed by the host
6435 * hw - Struct containing variables accessed by shared code
6437 * returns: - TRUE/FALSE
6439 *****************************************************************************/
6441 e1000_enable_mng_pass_thru(struct e1000_hw
*hw
)
6444 uint32_t fwsm
, factps
;
6446 if (hw
->asf_firmware_present
) {
6447 manc
= E1000_READ_REG(hw
, MANC
);
6449 if (!(manc
& E1000_MANC_RCV_TCO_EN
) ||
6450 !(manc
& E1000_MANC_EN_MAC_ADDR_FILTER
))
6452 if (e1000_arc_subsystem_valid(hw
) == TRUE
) {
6453 fwsm
= E1000_READ_REG(hw
, FWSM
);
6454 factps
= E1000_READ_REG(hw
, FACTPS
);
6456 if (((fwsm
& E1000_FWSM_MODE_MASK
) ==
6457 (e1000_mng_mode_pt
<< E1000_FWSM_MODE_SHIFT
)) &&
6458 (factps
& E1000_FACTPS_MNGCG
))
6461 if ((manc
& E1000_MANC_SMBUS_EN
) && !(manc
& E1000_MANC_ASF_EN
))
6468 e1000_polarity_reversal_workaround(struct e1000_hw
*hw
)
6471 uint16_t mii_status_reg
;
6474 /* Polarity reversal workaround for forced 10F/10H links. */
6476 /* Disable the transmitter on the PHY */
6478 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0019);
6481 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0xFFFF);
6485 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0000);
6489 /* This loop will early-out if the NO link condition has been met. */
6490 for(i
= PHY_FORCE_TIME
; i
> 0; i
--) {
6491 /* Read the MII Status Register and wait for Link Status bit
6495 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
6499 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
6503 if((mii_status_reg
& ~MII_SR_LINK_STATUS
) == 0) break;
6504 msec_delay_irq(100);
6507 /* Recommended delay time after link has been lost */
6508 msec_delay_irq(1000);
6510 /* Now we will re-enable th transmitter on the PHY */
6512 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0019);
6516 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0xFFF0);
6520 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0xFF00);
6524 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_GEN_CONTROL
, 0x0000);
6528 ret_val
= e1000_write_phy_reg(hw
, M88E1000_PHY_PAGE_SELECT
, 0x0000);
6532 /* This loop will early-out if the link condition has been met. */
6533 for(i
= PHY_FORCE_TIME
; i
> 0; i
--) {
6534 /* Read the MII Status Register and wait for Link Status bit
6538 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
6542 ret_val
= e1000_read_phy_reg(hw
, PHY_STATUS
, &mii_status_reg
);
6546 if(mii_status_reg
& MII_SR_LINK_STATUS
) break;
6547 msec_delay_irq(100);
6549 return E1000_SUCCESS
;
6552 /***************************************************************************
6554 * Disables PCI-Express master access.
6556 * hw: Struct containing variables accessed by shared code
6560 ***************************************************************************/
6562 e1000_set_pci_express_master_disable(struct e1000_hw
*hw
)
6566 DEBUGFUNC("e1000_set_pci_express_master_disable");
6568 if (hw
->bus_type
!= e1000_bus_type_pci_express
)
6571 ctrl
= E1000_READ_REG(hw
, CTRL
);
6572 ctrl
|= E1000_CTRL_GIO_MASTER_DISABLE
;
6573 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
6577 /***************************************************************************
6579 * Enables PCI-Express master access.
6581 * hw: Struct containing variables accessed by shared code
6585 ***************************************************************************/
6587 e1000_enable_pciex_master(struct e1000_hw
*hw
)
6591 DEBUGFUNC("e1000_enable_pciex_master");
6593 if (hw
->bus_type
!= e1000_bus_type_pci_express
)
6596 ctrl
= E1000_READ_REG(hw
, CTRL
);
6597 ctrl
&= ~E1000_CTRL_GIO_MASTER_DISABLE
;
6598 E1000_WRITE_REG(hw
, CTRL
, ctrl
);
6602 /*******************************************************************************
6604 * Disables PCI-Express master access and verifies there are no pending requests
6606 * hw: Struct containing variables accessed by shared code
6608 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
6609 * caused the master requests to be disabled.
6610 * E1000_SUCCESS master requests disabled.
6612 ******************************************************************************/
6614 e1000_disable_pciex_master(struct e1000_hw
*hw
)
6616 int32_t timeout
= MASTER_DISABLE_TIMEOUT
; /* 80ms */
6618 DEBUGFUNC("e1000_disable_pciex_master");
6620 if (hw
->bus_type
!= e1000_bus_type_pci_express
)
6621 return E1000_SUCCESS
;
6623 e1000_set_pci_express_master_disable(hw
);
6626 if(!(E1000_READ_REG(hw
, STATUS
) & E1000_STATUS_GIO_MASTER_ENABLE
))
6634 DEBUGOUT("Master requests are pending.\n");
6635 return -E1000_ERR_MASTER_REQUESTS_PENDING
;
6638 return E1000_SUCCESS
;
6641 /*******************************************************************************
6643 * Check for EEPROM Auto Read bit done.
6645 * hw: Struct containing variables accessed by shared code
6647 * returns: - E1000_ERR_RESET if fail to reset MAC
6648 * E1000_SUCCESS at any other case.
6650 ******************************************************************************/
6652 e1000_get_auto_rd_done(struct e1000_hw
*hw
)
6654 int32_t timeout
= AUTO_READ_DONE_TIMEOUT
;
6656 DEBUGFUNC("e1000_get_auto_rd_done");
6658 switch (hw
->mac_type
) {
6666 if (E1000_READ_REG(hw
, EECD
) & E1000_EECD_AUTO_RD
) break;
6672 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
6673 return -E1000_ERR_RESET
;
6678 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
6679 * Need to wait for PHY configuration completion before accessing NVM
6681 if (hw
->mac_type
== e1000_82573
)
6684 return E1000_SUCCESS
;
6687 /***************************************************************************
6688 * Checks if the PHY configuration is done
6690 * hw: Struct containing variables accessed by shared code
6692 * returns: - E1000_ERR_RESET if fail to reset MAC
6693 * E1000_SUCCESS at any other case.
6695 ***************************************************************************/
6697 e1000_get_phy_cfg_done(struct e1000_hw
*hw
)
6699 int32_t timeout
= PHY_CFG_TIMEOUT
;
6700 uint32_t cfg_mask
= E1000_EEPROM_CFG_DONE
;
6702 DEBUGFUNC("e1000_get_phy_cfg_done");
6704 switch (hw
->mac_type
) {
6711 if (E1000_READ_REG(hw
, EEMNGCTL
) & cfg_mask
)
6719 DEBUGOUT("MNG configuration cycle has not completed.\n");
6720 return -E1000_ERR_RESET
;
6725 return E1000_SUCCESS
;
6728 /***************************************************************************
6730 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
6731 * adapter or Eeprom access.
6733 * hw: Struct containing variables accessed by shared code
6735 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
6736 * E1000_SUCCESS at any other case.
6738 ***************************************************************************/
6740 e1000_get_hw_eeprom_semaphore(struct e1000_hw
*hw
)
6745 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
6747 if(!hw
->eeprom_semaphore_present
)
6748 return E1000_SUCCESS
;
6751 /* Get the FW semaphore. */
6752 timeout
= hw
->eeprom
.word_size
+ 1;
6754 swsm
= E1000_READ_REG(hw
, SWSM
);
6755 swsm
|= E1000_SWSM_SWESMBI
;
6756 E1000_WRITE_REG(hw
, SWSM
, swsm
);
6757 /* if we managed to set the bit we got the semaphore. */
6758 swsm
= E1000_READ_REG(hw
, SWSM
);
6759 if(swsm
& E1000_SWSM_SWESMBI
)
6767 /* Release semaphores */
6768 e1000_put_hw_eeprom_semaphore(hw
);
6769 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
6770 return -E1000_ERR_EEPROM
;
6773 return E1000_SUCCESS
;
6776 /***************************************************************************
6777 * This function clears HW semaphore bits.
6779 * hw: Struct containing variables accessed by shared code
6783 ***************************************************************************/
6785 e1000_put_hw_eeprom_semaphore(struct e1000_hw
*hw
)
6789 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
6791 if(!hw
->eeprom_semaphore_present
)
6794 swsm
= E1000_READ_REG(hw
, SWSM
);
6795 swsm
&= ~(E1000_SWSM_SWESMBI
);
6796 E1000_WRITE_REG(hw
, SWSM
, swsm
);
6799 /******************************************************************************
6800 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
6801 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
6802 * the caller to figure out how to deal with it.
6804 * hw - Struct containing variables accessed by shared code
6806 * returns: - E1000_BLK_PHY_RESET
6809 *****************************************************************************/
6811 e1000_check_phy_reset_block(struct e1000_hw
*hw
)
6814 if(hw
->mac_type
> e1000_82547_rev_2
)
6815 manc
= E1000_READ_REG(hw
, MANC
);
6816 return (manc
& E1000_MANC_BLK_PHY_RST_ON_IDE
) ?
6817 E1000_BLK_PHY_RESET
: E1000_SUCCESS
;
6821 e1000_arc_subsystem_valid(struct e1000_hw
*hw
)
6825 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
6826 * may not be provided a DMA clock when no manageability features are
6827 * enabled. We do not want to perform any reads/writes to these registers
6828 * if this is the case. We read FWSM to determine the manageability mode.
6830 switch (hw
->mac_type
) {
6834 fwsm
= E1000_READ_REG(hw
, FWSM
);
6835 if((fwsm
& E1000_FWSM_MODE_MASK
) != 0)