2 * arch/arch/mach-tegra/timer.c
4 * Copyright (C) 2010 Google, Inc.
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/init.h>
21 #include <linux/time.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/clockchips.h>
25 #include <linux/clocksource.h>
26 #include <linux/clk.h>
28 #include <linux/cnt32_to_63.h>
30 #include <asm/mach/time.h>
31 #include <asm/localtimer.h>
33 #include <mach/iomap.h>
34 #include <mach/irqs.h>
39 #define TIMERUS_CNTR_1US 0x10
40 #define TIMERUS_USEC_CFG 0x14
41 #define TIMERUS_CNTR_FREEZE 0x4c
43 #define TIMER1_BASE 0x0
44 #define TIMER2_BASE 0x8
45 #define TIMER3_BASE 0x50
46 #define TIMER4_BASE 0x58
53 static void __iomem
*timer_reg_base
= IO_ADDRESS(TEGRA_TMR1_BASE
);
55 #define timer_writel(value, reg) \
56 __raw_writel(value, (u32)timer_reg_base + (reg))
57 #define timer_readl(reg) \
58 __raw_readl((u32)timer_reg_base + (reg))
60 static int tegra_timer_set_next_event(unsigned long cycles
,
61 struct clock_event_device
*evt
)
65 reg
= 0x80000000 | ((cycles
> 1) ? (cycles
-1) : 0);
66 timer_writel(reg
, TIMER3_BASE
+ TIMER_PTV
);
71 static void tegra_timer_set_mode(enum clock_event_mode mode
,
72 struct clock_event_device
*evt
)
76 timer_writel(0, TIMER3_BASE
+ TIMER_PTV
);
79 case CLOCK_EVT_MODE_PERIODIC
:
80 reg
= 0xC0000000 | ((1000000/HZ
)-1);
81 timer_writel(reg
, TIMER3_BASE
+ TIMER_PTV
);
83 case CLOCK_EVT_MODE_ONESHOT
:
85 case CLOCK_EVT_MODE_UNUSED
:
86 case CLOCK_EVT_MODE_SHUTDOWN
:
87 case CLOCK_EVT_MODE_RESUME
:
92 static cycle_t
tegra_clocksource_read(struct clocksource
*cs
)
94 return cnt32_to_63(timer_readl(TIMERUS_CNTR_1US
));
97 static struct clock_event_device tegra_clockevent
= {
100 .features
= CLOCK_EVT_FEAT_ONESHOT
| CLOCK_EVT_FEAT_PERIODIC
,
101 .set_next_event
= tegra_timer_set_next_event
,
102 .set_mode
= tegra_timer_set_mode
,
105 static struct clocksource tegra_clocksource
= {
108 .read
= tegra_clocksource_read
,
109 .mask
= 0x7FFFFFFFFFFFFFFFULL
,
110 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
113 unsigned long long sched_clock(void)
115 return clocksource_cyc2ns(tegra_clocksource
.read(&tegra_clocksource
),
116 tegra_clocksource
.mult
, tegra_clocksource
.shift
);
119 static irqreturn_t
tegra_timer_interrupt(int irq
, void *dev_id
)
121 struct clock_event_device
*evt
= (struct clock_event_device
*)dev_id
;
122 timer_writel(1<<30, TIMER3_BASE
+ TIMER_PCR
);
123 evt
->event_handler(evt
);
127 static struct irqaction tegra_timer_irq
= {
129 .flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_TRIGGER_HIGH
,
130 .handler
= tegra_timer_interrupt
,
131 .dev_id
= &tegra_clockevent
,
135 static void __init
tegra_init_timer(void)
137 unsigned long rate
= clk_measure_input_freq();
140 #ifdef CONFIG_HAVE_ARM_TWD
141 twd_base
= IO_ADDRESS(TEGRA_ARM_PERIF_BASE
+ 0x600);
146 timer_writel(0x000b, TIMERUS_USEC_CFG
);
149 timer_writel(0x000c, TIMERUS_USEC_CFG
);
152 timer_writel(0x045f, TIMERUS_USEC_CFG
);
155 timer_writel(0x0019, TIMERUS_USEC_CFG
);
158 WARN(1, "Unknown clock rate");
161 if (clocksource_register_hz(&tegra_clocksource
, 1000000)) {
162 printk(KERN_ERR
"Failed to register clocksource\n");
166 ret
= setup_irq(tegra_timer_irq
.irq
, &tegra_timer_irq
);
168 printk(KERN_ERR
"Failed to register timer IRQ: %d\n", ret
);
172 clockevents_calc_mult_shift(&tegra_clockevent
, 1000000, 5);
173 tegra_clockevent
.max_delta_ns
=
174 clockevent_delta2ns(0x1fffffff, &tegra_clockevent
);
175 tegra_clockevent
.min_delta_ns
=
176 clockevent_delta2ns(0x1, &tegra_clockevent
);
177 tegra_clockevent
.cpumask
= cpu_all_mask
;
178 tegra_clockevent
.irq
= tegra_timer_irq
.irq
;
179 clockevents_register_device(&tegra_clockevent
);
184 struct sys_timer tegra_timer
= {
185 .init
= tegra_init_timer
,