2 * arch/arm/mach-tegra/tegra2_clocks.c
4 * Copyright (C) 2010 Google, Inc.
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/list.h>
23 #include <linux/spinlock.h>
24 #include <linux/delay.h>
26 #include <linux/hrtimer.h>
28 #include <asm/clkdev.h>
30 #include <mach/iomap.h>
34 #include "tegra2_dvfs.h"
36 #define RST_DEVICES 0x004
37 #define RST_DEVICES_SET 0x300
38 #define RST_DEVICES_CLR 0x304
39 #define RST_DEVICES_NUM 3
41 #define CLK_OUT_ENB 0x010
42 #define CLK_OUT_ENB_SET 0x320
43 #define CLK_OUT_ENB_CLR 0x324
44 #define CLK_OUT_ENB_NUM 3
46 #define CLK_MASK_ARM 0x44
47 #define MISC_CLK_ENB 0x48
50 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
51 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
52 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
53 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
54 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
55 #define OSC_CTRL_MASK 0x3f2
57 #define OSC_FREQ_DET 0x58
58 #define OSC_FREQ_DET_TRIG (1<<31)
60 #define OSC_FREQ_DET_STATUS 0x5C
61 #define OSC_FREQ_DET_BUSY (1<<31)
62 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
64 #define PERIPH_CLK_SOURCE_I2S1 0x100
65 #define PERIPH_CLK_SOURCE_EMC 0x19c
66 #define PERIPH_CLK_SOURCE_OSC 0x1fc
67 #define PERIPH_CLK_SOURCE_NUM \
68 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
70 #define PERIPH_CLK_SOURCE_MASK (3<<30)
71 #define PERIPH_CLK_SOURCE_SHIFT 30
72 #define PERIPH_CLK_SOURCE_ENABLE (1<<28)
73 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
74 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
75 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
78 #define PLL_BASE_BYPASS (1<<31)
79 #define PLL_BASE_ENABLE (1<<30)
80 #define PLL_BASE_REF_ENABLE (1<<29)
81 #define PLL_BASE_OVERRIDE (1<<28)
82 #define PLL_BASE_LOCK (1<<27)
83 #define PLL_BASE_DIVP_MASK (0x7<<20)
84 #define PLL_BASE_DIVP_SHIFT 20
85 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
86 #define PLL_BASE_DIVN_SHIFT 8
87 #define PLL_BASE_DIVM_MASK (0x1F)
88 #define PLL_BASE_DIVM_SHIFT 0
90 #define PLL_OUT_RATIO_MASK (0xFF<<8)
91 #define PLL_OUT_RATIO_SHIFT 8
92 #define PLL_OUT_OVERRIDE (1<<2)
93 #define PLL_OUT_CLKEN (1<<1)
94 #define PLL_OUT_RESET_DISABLE (1<<0)
96 #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
97 #define PLL_MISC_LOCK_ENABLE(c) (((c)->flags & PLLU) ? (1<<22) : (1<<18))
99 #define PLL_MISC_DCCON_SHIFT 20
100 #define PLL_MISC_CPCON_SHIFT 8
101 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
102 #define PLL_MISC_LFCON_SHIFT 4
103 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
104 #define PLL_MISC_VCOCON_SHIFT 0
105 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
107 #define PLLU_BASE_POST_DIV (1<<20)
109 #define PLLD_MISC_CLKENABLE (1<<30)
110 #define PLLD_MISC_DIV_RST (1<<23)
111 #define PLLD_MISC_DCCON_SHIFT 12
113 #define PLLE_MISC_READY (1 << 15)
115 #define PERIPH_CLK_TO_ENB_REG(c) ((c->clk_num / 32) * 4)
116 #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->clk_num / 32) * 8)
117 #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->clk_num % 32))
119 #define SUPER_CLK_MUX 0x00
120 #define SUPER_STATE_SHIFT 28
121 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
122 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
123 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
124 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
125 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
126 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
127 #define SUPER_SOURCE_MASK 0xF
128 #define SUPER_FIQ_SOURCE_SHIFT 12
129 #define SUPER_IRQ_SOURCE_SHIFT 8
130 #define SUPER_RUN_SOURCE_SHIFT 4
131 #define SUPER_IDLE_SOURCE_SHIFT 0
133 #define SUPER_CLK_DIVIDER 0x04
135 #define BUS_CLK_DISABLE (1<<3)
136 #define BUS_CLK_DIV_MASK 0x3
138 static void __iomem
*reg_clk_base
= IO_ADDRESS(TEGRA_CLK_RESET_BASE
);
140 #define clk_writel(value, reg) \
141 __raw_writel(value, (u32)reg_clk_base + (reg))
142 #define clk_readl(reg) \
143 __raw_readl((u32)reg_clk_base + (reg))
145 unsigned long clk_measure_input_freq(void)
147 u32 clock_autodetect
;
148 clk_writel(OSC_FREQ_DET_TRIG
| 1, OSC_FREQ_DET
);
149 do {} while (clk_readl(OSC_FREQ_DET_STATUS
) & OSC_FREQ_DET_BUSY
);
150 clock_autodetect
= clk_readl(OSC_FREQ_DET_STATUS
);
151 if (clock_autodetect
>= 732 - 3 && clock_autodetect
<= 732 + 3) {
153 } else if (clock_autodetect
>= 794 - 3 && clock_autodetect
<= 794 + 3) {
155 } else if (clock_autodetect
>= 1172 - 3 && clock_autodetect
<= 1172 + 3) {
157 } else if (clock_autodetect
>= 1587 - 3 && clock_autodetect
<= 1587 + 3) {
160 pr_err("%s: Unexpected clock autodetect value %d", __func__
, clock_autodetect
);
166 static int clk_div71_get_divider(unsigned long parent_rate
, unsigned long rate
)
168 s64 divider_u71
= parent_rate
* 2;
169 divider_u71
+= rate
- 1;
170 do_div(divider_u71
, rate
);
172 if (divider_u71
- 2 < 0)
175 if (divider_u71
- 2 > 255)
178 return divider_u71
- 2;
181 static int clk_div16_get_divider(unsigned long parent_rate
, unsigned long rate
)
185 divider_u16
= parent_rate
;
186 divider_u16
+= rate
- 1;
187 do_div(divider_u16
, rate
);
189 if (divider_u16
- 1 < 0)
192 if (divider_u16
- 1 > 255)
195 return divider_u16
- 1;
198 /* clk_m functions */
199 static unsigned long tegra2_clk_m_autodetect_rate(struct clk
*c
)
201 u32 auto_clock_control
= clk_readl(OSC_CTRL
) & ~OSC_CTRL_OSC_FREQ_MASK
;
203 c
->rate
= clk_measure_input_freq();
206 auto_clock_control
|= OSC_CTRL_OSC_FREQ_12MHZ
;
209 auto_clock_control
|= OSC_CTRL_OSC_FREQ_13MHZ
;
212 auto_clock_control
|= OSC_CTRL_OSC_FREQ_19_2MHZ
;
215 auto_clock_control
|= OSC_CTRL_OSC_FREQ_26MHZ
;
218 pr_err("%s: Unexpected clock rate %ld", __func__
, c
->rate
);
221 clk_writel(auto_clock_control
, OSC_CTRL
);
225 static void tegra2_clk_m_init(struct clk
*c
)
227 pr_debug("%s on clock %s\n", __func__
, c
->name
);
228 tegra2_clk_m_autodetect_rate(c
);
231 static int tegra2_clk_m_enable(struct clk
*c
)
233 pr_debug("%s on clock %s\n", __func__
, c
->name
);
237 static void tegra2_clk_m_disable(struct clk
*c
)
239 pr_debug("%s on clock %s\n", __func__
, c
->name
);
243 static struct clk_ops tegra_clk_m_ops
= {
244 .init
= tegra2_clk_m_init
,
245 .enable
= tegra2_clk_m_enable
,
246 .disable
= tegra2_clk_m_disable
,
249 /* super clock functions */
250 /* "super clocks" on tegra have two-stage muxes and a clock skipping
251 * super divider. We will ignore the clock skipping divider, since we
252 * can't lower the voltage when using the clock skip, but we can if we
253 * lower the PLL frequency.
255 static void tegra2_super_clk_init(struct clk
*c
)
260 const struct clk_mux_sel
*sel
;
261 val
= clk_readl(c
->reg
+ SUPER_CLK_MUX
);
263 BUG_ON(((val
& SUPER_STATE_MASK
) != SUPER_STATE_RUN
) &&
264 ((val
& SUPER_STATE_MASK
) != SUPER_STATE_IDLE
));
265 shift
= ((val
& SUPER_STATE_MASK
) == SUPER_STATE_IDLE
) ?
266 SUPER_IDLE_SOURCE_SHIFT
: SUPER_RUN_SOURCE_SHIFT
;
267 source
= (val
>> shift
) & SUPER_SOURCE_MASK
;
268 for (sel
= c
->inputs
; sel
->input
!= NULL
; sel
++) {
269 if (sel
->value
== source
)
272 BUG_ON(sel
->input
== NULL
);
273 c
->parent
= sel
->input
;
276 static int tegra2_super_clk_enable(struct clk
*c
)
278 clk_writel(0, c
->reg
+ SUPER_CLK_DIVIDER
);
282 static void tegra2_super_clk_disable(struct clk
*c
)
284 pr_debug("%s on clock %s\n", __func__
, c
->name
);
286 /* oops - don't disable the CPU clock! */
290 static int tegra2_super_clk_set_parent(struct clk
*c
, struct clk
*p
)
293 const struct clk_mux_sel
*sel
;
296 val
= clk_readl(c
->reg
+ SUPER_CLK_MUX
);;
297 BUG_ON(((val
& SUPER_STATE_MASK
) != SUPER_STATE_RUN
) &&
298 ((val
& SUPER_STATE_MASK
) != SUPER_STATE_IDLE
));
299 shift
= ((val
& SUPER_STATE_MASK
) == SUPER_STATE_IDLE
) ?
300 SUPER_IDLE_SOURCE_SHIFT
: SUPER_RUN_SOURCE_SHIFT
;
301 for (sel
= c
->inputs
; sel
->input
!= NULL
; sel
++) {
302 if (sel
->input
== p
) {
303 val
&= ~(SUPER_SOURCE_MASK
<< shift
);
304 val
|= sel
->value
<< shift
;
307 clk_enable_locked(p
);
309 clk_writel(val
, c
->reg
);
311 if (c
->refcnt
&& c
->parent
)
312 clk_disable_locked(c
->parent
);
321 static struct clk_ops tegra_super_ops
= {
322 .init
= tegra2_super_clk_init
,
323 .enable
= tegra2_super_clk_enable
,
324 .disable
= tegra2_super_clk_disable
,
325 .set_parent
= tegra2_super_clk_set_parent
,
328 /* virtual cpu clock functions */
329 /* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
330 To change the frequency of these clocks, the parent pll may need to be
331 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
332 and then the clock moved back to the pll. To hide this sequence, a virtual
335 static void tegra2_cpu_clk_init(struct clk
*c
)
339 static int tegra2_cpu_clk_enable(struct clk
*c
)
344 static void tegra2_cpu_clk_disable(struct clk
*c
)
346 pr_debug("%s on clock %s\n", __func__
, c
->name
);
348 /* oops - don't disable the CPU clock! */
352 static int tegra2_cpu_clk_set_rate(struct clk
*c
, unsigned long rate
)
355 ret
= clk_set_parent_locked(c
->parent
, c
->backup
);
357 pr_err("Failed to switch cpu to clock %s\n", c
->backup
->name
);
361 ret
= clk_set_rate_locked(c
->main
, rate
);
363 pr_err("Failed to change cpu pll to %lu\n", rate
);
367 ret
= clk_set_parent_locked(c
->parent
, c
->main
);
369 pr_err("Failed to switch cpu to clock %s\n", c
->main
->name
);
376 static struct clk_ops tegra_cpu_ops
= {
377 .init
= tegra2_cpu_clk_init
,
378 .enable
= tegra2_cpu_clk_enable
,
379 .disable
= tegra2_cpu_clk_disable
,
380 .set_rate
= tegra2_cpu_clk_set_rate
,
383 /* bus clock functions */
384 static void tegra2_bus_clk_init(struct clk
*c
)
386 u32 val
= clk_readl(c
->reg
);
387 c
->state
= ((val
>> c
->reg_shift
) & BUS_CLK_DISABLE
) ? OFF
: ON
;
388 c
->div
= ((val
>> c
->reg_shift
) & BUS_CLK_DIV_MASK
) + 1;
392 static int tegra2_bus_clk_enable(struct clk
*c
)
394 u32 val
= clk_readl(c
->reg
);
395 val
&= ~(BUS_CLK_DISABLE
<< c
->reg_shift
);
396 clk_writel(val
, c
->reg
);
400 static void tegra2_bus_clk_disable(struct clk
*c
)
402 u32 val
= clk_readl(c
->reg
);
403 val
|= BUS_CLK_DISABLE
<< c
->reg_shift
;
404 clk_writel(val
, c
->reg
);
407 static int tegra2_bus_clk_set_rate(struct clk
*c
, unsigned long rate
)
409 u32 val
= clk_readl(c
->reg
);
410 unsigned long parent_rate
= c
->parent
->rate
;
412 for (i
= 1; i
<= 4; i
++) {
413 if (rate
== parent_rate
/ i
) {
414 val
&= ~(BUS_CLK_DIV_MASK
<< c
->reg_shift
);
415 val
|= (i
- 1) << c
->reg_shift
;
416 clk_writel(val
, c
->reg
);
425 static struct clk_ops tegra_bus_ops
= {
426 .init
= tegra2_bus_clk_init
,
427 .enable
= tegra2_bus_clk_enable
,
428 .disable
= tegra2_bus_clk_disable
,
429 .set_rate
= tegra2_bus_clk_set_rate
,
433 static int tegra2_pll_clk_wait_for_lock(struct clk
*c
)
437 before
= ktime_get();
439 while (!(clk_readl(c
->reg
+ PLL_BASE
) & PLL_BASE_LOCK
)) {
440 if (ktime_us_delta(ktime_get(), before
) > 5000) {
441 pr_err("Timed out waiting for lock bit on pll %s",
450 static void tegra2_pll_clk_init(struct clk
*c
)
452 u32 val
= clk_readl(c
->reg
+ PLL_BASE
);
454 c
->state
= (val
& PLL_BASE_ENABLE
) ? ON
: OFF
;
456 if (c
->flags
& PLL_FIXED
&& !(val
& PLL_BASE_OVERRIDE
)) {
457 pr_warning("Clock %s has unknown fixed frequency\n", c
->name
);
460 } else if (val
& PLL_BASE_BYPASS
) {
464 c
->mul
= (val
& PLL_BASE_DIVN_MASK
) >> PLL_BASE_DIVN_SHIFT
;
465 c
->div
= (val
& PLL_BASE_DIVM_MASK
) >> PLL_BASE_DIVM_SHIFT
;
467 c
->div
*= (val
& PLLU_BASE_POST_DIV
) ? 1 : 2;
469 c
->div
*= (val
& PLL_BASE_DIVP_MASK
) ? 2 : 1;
473 static int tegra2_pll_clk_enable(struct clk
*c
)
476 pr_debug("%s on clock %s\n", __func__
, c
->name
);
478 val
= clk_readl(c
->reg
+ PLL_BASE
);
479 val
&= ~PLL_BASE_BYPASS
;
480 val
|= PLL_BASE_ENABLE
;
481 clk_writel(val
, c
->reg
+ PLL_BASE
);
483 val
= clk_readl(c
->reg
+ PLL_MISC(c
));
484 val
|= PLL_MISC_LOCK_ENABLE(c
);
485 clk_writel(val
, c
->reg
+ PLL_MISC(c
));
487 tegra2_pll_clk_wait_for_lock(c
);
492 static void tegra2_pll_clk_disable(struct clk
*c
)
495 pr_debug("%s on clock %s\n", __func__
, c
->name
);
497 val
= clk_readl(c
->reg
);
498 val
&= ~(PLL_BASE_BYPASS
| PLL_BASE_ENABLE
);
499 clk_writel(val
, c
->reg
);
502 static int tegra2_pll_clk_set_rate(struct clk
*c
, unsigned long rate
)
505 unsigned long input_rate
;
506 const struct clk_pll_table
*sel
;
508 pr_debug("%s: %s %lu\n", __func__
, c
->name
, rate
);
509 BUG_ON(c
->refcnt
!= 0);
511 input_rate
= c
->parent
->rate
;
512 for (sel
= c
->pll_table
; sel
->input_rate
!= 0; sel
++) {
513 if (sel
->input_rate
== input_rate
&& sel
->output_rate
== rate
) {
515 c
->div
= sel
->m
* sel
->p
;
517 val
= clk_readl(c
->reg
+ PLL_BASE
);
518 if (c
->flags
& PLL_FIXED
)
519 val
|= PLL_BASE_OVERRIDE
;
520 val
&= ~(PLL_BASE_DIVP_MASK
| PLL_BASE_DIVN_MASK
|
522 val
|= (sel
->m
<< PLL_BASE_DIVM_SHIFT
) |
523 (sel
->n
<< PLL_BASE_DIVN_SHIFT
);
524 BUG_ON(sel
->p
< 1 || sel
->p
> 2);
525 if (c
->flags
& PLLU
) {
527 val
|= PLLU_BASE_POST_DIV
;
530 val
|= 1 << PLL_BASE_DIVP_SHIFT
;
532 clk_writel(val
, c
->reg
+ PLL_BASE
);
534 if (c
->flags
& PLL_HAS_CPCON
) {
535 val
= clk_readl(c
->reg
+ PLL_MISC(c
));
536 val
&= ~PLL_MISC_CPCON_MASK
;
537 val
|= sel
->cpcon
<< PLL_MISC_CPCON_SHIFT
;
538 clk_writel(val
, c
->reg
+ PLL_MISC(c
));
542 tegra2_pll_clk_enable(c
);
550 static struct clk_ops tegra_pll_ops
= {
551 .init
= tegra2_pll_clk_init
,
552 .enable
= tegra2_pll_clk_enable
,
553 .disable
= tegra2_pll_clk_disable
,
554 .set_rate
= tegra2_pll_clk_set_rate
,
557 static void tegra2_pllx_clk_init(struct clk
*c
)
559 tegra2_pll_clk_init(c
);
561 if (tegra_sku_id() == 7)
562 c
->max_rate
= 750000000;
565 static struct clk_ops tegra_pllx_ops
= {
566 .init
= tegra2_pllx_clk_init
,
567 .enable
= tegra2_pll_clk_enable
,
568 .disable
= tegra2_pll_clk_disable
,
569 .set_rate
= tegra2_pll_clk_set_rate
,
572 static int tegra2_plle_clk_enable(struct clk
*c
)
576 pr_debug("%s on clock %s\n", __func__
, c
->name
);
580 val
= clk_readl(c
->reg
+ PLL_BASE
);
581 if (!(val
& PLLE_MISC_READY
))
584 val
= clk_readl(c
->reg
+ PLL_BASE
);
585 val
|= PLL_BASE_ENABLE
| PLL_BASE_BYPASS
;
586 clk_writel(val
, c
->reg
+ PLL_BASE
);
591 static struct clk_ops tegra_plle_ops
= {
592 .init
= tegra2_pll_clk_init
,
593 .enable
= tegra2_plle_clk_enable
,
594 .set_rate
= tegra2_pll_clk_set_rate
,
597 /* Clock divider ops */
598 static void tegra2_pll_div_clk_init(struct clk
*c
)
600 u32 val
= clk_readl(c
->reg
);
602 val
>>= c
->reg_shift
;
603 c
->state
= (val
& PLL_OUT_CLKEN
) ? ON
: OFF
;
604 if (!(val
& PLL_OUT_RESET_DISABLE
))
607 if (c
->flags
& DIV_U71
) {
608 divu71
= (val
& PLL_OUT_RATIO_MASK
) >> PLL_OUT_RATIO_SHIFT
;
609 c
->div
= (divu71
+ 2);
611 } else if (c
->flags
& DIV_2
) {
620 static int tegra2_pll_div_clk_enable(struct clk
*c
)
625 pr_debug("%s: %s\n", __func__
, c
->name
);
626 if (c
->flags
& DIV_U71
) {
627 val
= clk_readl(c
->reg
);
628 new_val
= val
>> c
->reg_shift
;
631 new_val
|= PLL_OUT_CLKEN
| PLL_OUT_RESET_DISABLE
;
633 val
&= ~(0xFFFF << c
->reg_shift
);
634 val
|= new_val
<< c
->reg_shift
;
635 clk_writel(val
, c
->reg
);
637 } else if (c
->flags
& DIV_2
) {
638 BUG_ON(!(c
->flags
& PLLD
));
639 val
= clk_readl(c
->reg
);
640 val
&= ~PLLD_MISC_DIV_RST
;
641 clk_writel(val
, c
->reg
);
647 static void tegra2_pll_div_clk_disable(struct clk
*c
)
652 pr_debug("%s: %s\n", __func__
, c
->name
);
653 if (c
->flags
& DIV_U71
) {
654 val
= clk_readl(c
->reg
);
655 new_val
= val
>> c
->reg_shift
;
658 new_val
&= ~(PLL_OUT_CLKEN
| PLL_OUT_RESET_DISABLE
);
660 val
&= ~(0xFFFF << c
->reg_shift
);
661 val
|= new_val
<< c
->reg_shift
;
662 clk_writel(val
, c
->reg
);
663 } else if (c
->flags
& DIV_2
) {
664 BUG_ON(!(c
->flags
& PLLD
));
665 val
= clk_readl(c
->reg
);
666 val
|= PLLD_MISC_DIV_RST
;
667 clk_writel(val
, c
->reg
);
671 static int tegra2_pll_div_clk_set_rate(struct clk
*c
, unsigned long rate
)
676 pr_debug("%s: %s %lu\n", __func__
, c
->name
, rate
);
677 if (c
->flags
& DIV_U71
) {
678 divider_u71
= clk_div71_get_divider(c
->parent
->rate
, rate
);
679 if (divider_u71
>= 0) {
680 val
= clk_readl(c
->reg
);
681 new_val
= val
>> c
->reg_shift
;
683 if (c
->flags
& DIV_U71_FIXED
)
684 new_val
|= PLL_OUT_OVERRIDE
;
685 new_val
&= ~PLL_OUT_RATIO_MASK
;
686 new_val
|= divider_u71
<< PLL_OUT_RATIO_SHIFT
;
688 val
&= ~(0xFFFF << c
->reg_shift
);
689 val
|= new_val
<< c
->reg_shift
;
690 clk_writel(val
, c
->reg
);
691 c
->div
= divider_u71
+ 2;
695 } else if (c
->flags
& DIV_2
) {
696 if (c
->parent
->rate
== rate
* 2)
702 static long tegra2_pll_div_clk_round_rate(struct clk
*c
, unsigned long rate
)
705 pr_debug("%s: %s %lu\n", __func__
, c
->name
, rate
);
707 if (c
->flags
& DIV_U71
) {
708 divider
= clk_div71_get_divider(c
->parent
->rate
, rate
);
711 return c
->parent
->rate
* 2 / (divider
+ 2);
712 } else if (c
->flags
& DIV_2
) {
713 return c
->parent
->rate
/ 2;
718 static struct clk_ops tegra_pll_div_ops
= {
719 .init
= tegra2_pll_div_clk_init
,
720 .enable
= tegra2_pll_div_clk_enable
,
721 .disable
= tegra2_pll_div_clk_disable
,
722 .set_rate
= tegra2_pll_div_clk_set_rate
,
723 .round_rate
= tegra2_pll_div_clk_round_rate
,
728 static void tegra2_periph_clk_init(struct clk
*c
)
730 u32 val
= clk_readl(c
->reg
);
731 const struct clk_mux_sel
*mux
= 0;
732 const struct clk_mux_sel
*sel
;
733 if (c
->flags
& MUX
) {
734 for (sel
= c
->inputs
; sel
->input
!= NULL
; sel
++) {
735 if (val
>> PERIPH_CLK_SOURCE_SHIFT
== sel
->value
)
740 c
->parent
= mux
->input
;
742 c
->parent
= c
->inputs
[0].input
;
745 if (c
->flags
& DIV_U71
) {
746 u32 divu71
= val
& PERIPH_CLK_SOURCE_DIVU71_MASK
;
749 } else if (c
->flags
& DIV_U16
) {
750 u32 divu16
= val
& PERIPH_CLK_SOURCE_DIVU16_MASK
;
759 if (!(clk_readl(CLK_OUT_ENB
+ PERIPH_CLK_TO_ENB_REG(c
)) &
760 PERIPH_CLK_TO_ENB_BIT(c
)))
762 if (!(c
->flags
& PERIPH_NO_RESET
))
763 if (clk_readl(RST_DEVICES
+ PERIPH_CLK_TO_ENB_REG(c
)) &
764 PERIPH_CLK_TO_ENB_BIT(c
))
768 static int tegra2_periph_clk_enable(struct clk
*c
)
771 pr_debug("%s on clock %s\n", __func__
, c
->name
);
773 clk_writel(PERIPH_CLK_TO_ENB_BIT(c
),
774 CLK_OUT_ENB_SET
+ PERIPH_CLK_TO_ENB_SET_REG(c
));
775 if (!(c
->flags
& PERIPH_NO_RESET
) && !(c
->flags
& PERIPH_MANUAL_RESET
))
776 clk_writel(PERIPH_CLK_TO_ENB_BIT(c
),
777 RST_DEVICES_CLR
+ PERIPH_CLK_TO_ENB_SET_REG(c
));
778 if (c
->flags
& PERIPH_EMC_ENB
) {
779 /* The EMC peripheral clock has 2 extra enable bits */
780 /* FIXME: Do they need to be disabled? */
781 val
= clk_readl(c
->reg
);
783 clk_writel(val
, c
->reg
);
788 static void tegra2_periph_clk_disable(struct clk
*c
)
790 pr_debug("%s on clock %s\n", __func__
, c
->name
);
792 clk_writel(PERIPH_CLK_TO_ENB_BIT(c
),
793 CLK_OUT_ENB_CLR
+ PERIPH_CLK_TO_ENB_SET_REG(c
));
796 void tegra2_periph_reset_deassert(struct clk
*c
)
798 pr_debug("%s on clock %s\n", __func__
, c
->name
);
799 if (!(c
->flags
& PERIPH_NO_RESET
))
800 clk_writel(PERIPH_CLK_TO_ENB_BIT(c
),
801 RST_DEVICES_CLR
+ PERIPH_CLK_TO_ENB_SET_REG(c
));
804 void tegra2_periph_reset_assert(struct clk
*c
)
806 pr_debug("%s on clock %s\n", __func__
, c
->name
);
807 if (!(c
->flags
& PERIPH_NO_RESET
))
808 clk_writel(PERIPH_CLK_TO_ENB_BIT(c
),
809 RST_DEVICES_SET
+ PERIPH_CLK_TO_ENB_SET_REG(c
));
813 static int tegra2_periph_clk_set_parent(struct clk
*c
, struct clk
*p
)
816 const struct clk_mux_sel
*sel
;
817 pr_debug("%s: %s %s\n", __func__
, c
->name
, p
->name
);
818 for (sel
= c
->inputs
; sel
->input
!= NULL
; sel
++) {
819 if (sel
->input
== p
) {
820 val
= clk_readl(c
->reg
);
821 val
&= ~PERIPH_CLK_SOURCE_MASK
;
822 val
|= (sel
->value
) << PERIPH_CLK_SOURCE_SHIFT
;
825 clk_enable_locked(p
);
827 clk_writel(val
, c
->reg
);
829 if (c
->refcnt
&& c
->parent
)
830 clk_disable_locked(c
->parent
);
840 static int tegra2_periph_clk_set_rate(struct clk
*c
, unsigned long rate
)
844 pr_debug("%s: %lu\n", __func__
, rate
);
845 if (c
->flags
& DIV_U71
) {
846 divider
= clk_div71_get_divider(c
->parent
->rate
, rate
);
848 val
= clk_readl(c
->reg
);
849 val
&= ~PERIPH_CLK_SOURCE_DIVU71_MASK
;
851 clk_writel(val
, c
->reg
);
852 c
->div
= divider
+ 2;
856 } else if (c
->flags
& DIV_U16
) {
857 divider
= clk_div16_get_divider(c
->parent
->rate
, rate
);
859 val
= clk_readl(c
->reg
);
860 val
&= ~PERIPH_CLK_SOURCE_DIVU16_MASK
;
862 clk_writel(val
, c
->reg
);
863 c
->div
= divider
+ 1;
867 } else if (c
->parent
->rate
<= rate
) {
875 static long tegra2_periph_clk_round_rate(struct clk
*c
,
879 pr_debug("%s: %s %lu\n", __func__
, c
->name
, rate
);
881 if (c
->flags
& DIV_U71
) {
882 divider
= clk_div71_get_divider(c
->parent
->rate
, rate
);
886 return c
->parent
->rate
* 2 / (divider
+ 2);
887 } else if (c
->flags
& DIV_U16
) {
888 divider
= clk_div16_get_divider(c
->parent
->rate
, rate
);
891 return c
->parent
->rate
/ (divider
+ 1);
896 static struct clk_ops tegra_periph_clk_ops
= {
897 .init
= &tegra2_periph_clk_init
,
898 .enable
= &tegra2_periph_clk_enable
,
899 .disable
= &tegra2_periph_clk_disable
,
900 .set_parent
= &tegra2_periph_clk_set_parent
,
901 .set_rate
= &tegra2_periph_clk_set_rate
,
902 .round_rate
= &tegra2_periph_clk_round_rate
,
905 /* Clock doubler ops */
906 static void tegra2_clk_double_init(struct clk
*c
)
911 if (!(clk_readl(CLK_OUT_ENB
+ PERIPH_CLK_TO_ENB_REG(c
)) &
912 PERIPH_CLK_TO_ENB_BIT(c
)))
916 static int tegra2_clk_double_set_rate(struct clk
*c
, unsigned long rate
)
918 if (rate
!= 2 * c
->parent
->rate
)
925 static struct clk_ops tegra_clk_double_ops
= {
926 .init
= &tegra2_clk_double_init
,
927 .enable
= &tegra2_periph_clk_enable
,
928 .disable
= &tegra2_periph_clk_disable
,
929 .set_rate
= &tegra2_clk_double_set_rate
,
932 static void tegra2_audio_sync_clk_init(struct clk
*c
)
935 const struct clk_mux_sel
*sel
;
936 u32 val
= clk_readl(c
->reg
);
937 c
->state
= (val
& (1<<4)) ? OFF
: ON
;
939 for (sel
= c
->inputs
; sel
->input
!= NULL
; sel
++)
940 if (sel
->value
== source
)
942 BUG_ON(sel
->input
== NULL
);
943 c
->parent
= sel
->input
;
946 static int tegra2_audio_sync_clk_enable(struct clk
*c
)
948 clk_writel(0, c
->reg
);
952 static void tegra2_audio_sync_clk_disable(struct clk
*c
)
954 clk_writel(1, c
->reg
);
957 static int tegra2_audio_sync_clk_set_parent(struct clk
*c
, struct clk
*p
)
960 const struct clk_mux_sel
*sel
;
961 for (sel
= c
->inputs
; sel
->input
!= NULL
; sel
++) {
962 if (sel
->input
== p
) {
963 val
= clk_readl(c
->reg
);
968 clk_enable_locked(p
);
970 clk_writel(val
, c
->reg
);
972 if (c
->refcnt
&& c
->parent
)
973 clk_disable_locked(c
->parent
);
983 static int tegra2_audio_sync_clk_set_rate(struct clk
*c
, unsigned long rate
)
985 unsigned long parent_rate
;
987 pr_err("%s: clock has no parent\n", __func__
);
990 parent_rate
= c
->parent
->rate
;
991 if (rate
!= parent_rate
) {
992 pr_err("%s: %s/%ld differs from parent %s/%ld\n",
995 c
->parent
->name
, parent_rate
);
998 c
->rate
= parent_rate
;
1002 static struct clk_ops tegra_audio_sync_clk_ops
= {
1003 .init
= tegra2_audio_sync_clk_init
,
1004 .enable
= tegra2_audio_sync_clk_enable
,
1005 .disable
= tegra2_audio_sync_clk_disable
,
1006 .set_rate
= tegra2_audio_sync_clk_set_rate
,
1007 .set_parent
= tegra2_audio_sync_clk_set_parent
,
1010 /* Clock definitions */
1011 static struct clk tegra_clk_32k
= {
1018 static struct clk_pll_table tegra_pll_s_table
[] = {
1019 {32768, 12000000, 366, 1, 1, 0},
1020 {32768, 13000000, 397, 1, 1, 0},
1021 {32768, 19200000, 586, 1, 1, 0},
1022 {32768, 26000000, 793, 1, 1, 0},
1026 static struct clk tegra_pll_s
= {
1028 .flags
= PLL_ALT_MISC_REG
,
1029 .ops
= &tegra_pll_ops
,
1033 .parent
= &tegra_clk_32k
,
1034 .cf_min
= 0, /* FIXME */
1035 .cf_max
= 0, /* FIXME */
1036 .vco_min
= 12000000,
1037 .vco_max
= 26000000,
1038 .pll_table
= tegra_pll_s_table
,
1039 .max_rate
= 26000000,
1042 static struct clk_mux_sel tegra_clk_m_sel
[] = {
1043 { .input
= &tegra_clk_32k
, .value
= 0},
1044 { .input
= &tegra_pll_s
, .value
= 1},
1047 static struct clk tegra_clk_m
= {
1049 .flags
= ENABLE_ON_INIT
,
1050 .ops
= &tegra_clk_m_ops
,
1051 .inputs
= tegra_clk_m_sel
,
1053 .reg_mask
= (1<<28),
1055 .max_rate
= 26000000,
1058 static struct clk_pll_table tegra_pll_c_table
[] = {
1059 { 0, 0, 0, 0, 0, 0 },
1062 static struct clk tegra_pll_c
= {
1064 .flags
= PLL_HAS_CPCON
,
1065 .ops
= &tegra_pll_ops
,
1067 .input_min
= 2000000,
1068 .input_max
= 31000000,
1069 .parent
= &tegra_clk_m
,
1072 .vco_min
= 20000000,
1073 .vco_max
= 1400000000,
1074 .pll_table
= tegra_pll_c_table
,
1075 .max_rate
= 600000000,
1078 static struct clk tegra_pll_c_out1
= {
1079 .name
= "pll_c_out1",
1080 .ops
= &tegra_pll_div_ops
,
1082 .parent
= &tegra_pll_c
,
1085 .max_rate
= 600000000,
1088 static struct clk_pll_table tegra_pll_m_table
[] = {
1089 { 12000000, 666000000, 666, 12, 1, 8},
1090 { 13000000, 666000000, 666, 13, 1, 8},
1091 { 19200000, 666000000, 555, 16, 1, 8},
1092 { 26000000, 666000000, 666, 26, 1, 8},
1093 { 12000000, 600000000, 600, 12, 1, 8},
1094 { 13000000, 600000000, 600, 13, 1, 8},
1095 { 19200000, 600000000, 375, 12, 1, 6},
1096 { 26000000, 600000000, 600, 26, 1, 8},
1097 { 0, 0, 0, 0, 0, 0 },
1100 static struct clk tegra_pll_m
= {
1102 .flags
= PLL_HAS_CPCON
,
1103 .ops
= &tegra_pll_ops
,
1105 .input_min
= 2000000,
1106 .input_max
= 31000000,
1107 .parent
= &tegra_clk_m
,
1110 .vco_min
= 20000000,
1111 .vco_max
= 1200000000,
1112 .pll_table
= tegra_pll_m_table
,
1113 .max_rate
= 800000000,
1116 static struct clk tegra_pll_m_out1
= {
1117 .name
= "pll_m_out1",
1118 .ops
= &tegra_pll_div_ops
,
1120 .parent
= &tegra_pll_m
,
1123 .max_rate
= 600000000,
1126 static struct clk_pll_table tegra_pll_p_table
[] = {
1127 { 12000000, 216000000, 432, 12, 2, 8},
1128 { 13000000, 216000000, 432, 13, 2, 8},
1129 { 19200000, 216000000, 90, 4, 2, 1},
1130 { 26000000, 216000000, 432, 26, 2, 8},
1131 { 12000000, 432000000, 432, 12, 1, 8},
1132 { 13000000, 432000000, 432, 13, 1, 8},
1133 { 19200000, 432000000, 90, 4, 1, 1},
1134 { 26000000, 432000000, 432, 26, 1, 8},
1135 { 0, 0, 0, 0, 0, 0 },
1138 static struct clk tegra_pll_p
= {
1140 .flags
= ENABLE_ON_INIT
| PLL_FIXED
| PLL_HAS_CPCON
,
1141 .ops
= &tegra_pll_ops
,
1143 .input_min
= 2000000,
1144 .input_max
= 31000000,
1145 .parent
= &tegra_clk_m
,
1148 .vco_min
= 20000000,
1149 .vco_max
= 1400000000,
1150 .pll_table
= tegra_pll_p_table
,
1151 .max_rate
= 432000000,
1154 static struct clk tegra_pll_p_out1
= {
1155 .name
= "pll_p_out1",
1156 .ops
= &tegra_pll_div_ops
,
1157 .flags
= ENABLE_ON_INIT
| DIV_U71
| DIV_U71_FIXED
,
1158 .parent
= &tegra_pll_p
,
1161 .max_rate
= 432000000,
1164 static struct clk tegra_pll_p_out2
= {
1165 .name
= "pll_p_out2",
1166 .ops
= &tegra_pll_div_ops
,
1167 .flags
= ENABLE_ON_INIT
| DIV_U71
| DIV_U71_FIXED
,
1168 .parent
= &tegra_pll_p
,
1171 .max_rate
= 432000000,
1174 static struct clk tegra_pll_p_out3
= {
1175 .name
= "pll_p_out3",
1176 .ops
= &tegra_pll_div_ops
,
1177 .flags
= ENABLE_ON_INIT
| DIV_U71
| DIV_U71_FIXED
,
1178 .parent
= &tegra_pll_p
,
1181 .max_rate
= 432000000,
1184 static struct clk tegra_pll_p_out4
= {
1185 .name
= "pll_p_out4",
1186 .ops
= &tegra_pll_div_ops
,
1187 .flags
= ENABLE_ON_INIT
| DIV_U71
| DIV_U71_FIXED
,
1188 .parent
= &tegra_pll_p
,
1191 .max_rate
= 432000000,
1194 static struct clk_pll_table tegra_pll_a_table
[] = {
1195 { 28800000, 56448000, 49, 25, 1, 1},
1196 { 28800000, 73728000, 64, 25, 1, 1},
1197 { 28800000, 11289600, 49, 25, 1, 1},
1198 { 28800000, 12288000, 64, 25, 1, 1},
1199 { 28800000, 24000000, 5, 6, 1, 1},
1200 { 0, 0, 0, 0, 0, 0 },
1203 static struct clk tegra_pll_a
= {
1205 .flags
= PLL_HAS_CPCON
,
1206 .ops
= &tegra_pll_ops
,
1208 .input_min
= 2000000,
1209 .input_max
= 31000000,
1210 .parent
= &tegra_pll_p_out1
,
1213 .vco_min
= 20000000,
1214 .vco_max
= 1400000000,
1215 .pll_table
= tegra_pll_a_table
,
1216 .max_rate
= 56448000,
1219 static struct clk tegra_pll_a_out0
= {
1220 .name
= "pll_a_out0",
1221 .ops
= &tegra_pll_div_ops
,
1223 .parent
= &tegra_pll_a
,
1226 .max_rate
= 56448000,
1229 static struct clk_pll_table tegra_pll_d_table
[] = {
1230 { 12000000, 1000000000, 1000, 12, 1, 12},
1231 { 13000000, 1000000000, 1000, 13, 1, 12},
1232 { 19200000, 1000000000, 625, 12, 1, 8},
1233 { 26000000, 1000000000, 1000, 26, 1, 12},
1234 { 0, 0, 0, 0, 0, 0 },
1237 static struct clk tegra_pll_d
= {
1239 .flags
= PLL_HAS_CPCON
| PLLD
,
1240 .ops
= &tegra_pll_ops
,
1242 .input_min
= 2000000,
1243 .input_max
= 40000000,
1244 .parent
= &tegra_clk_m
,
1247 .vco_min
= 40000000,
1248 .vco_max
= 1000000000,
1249 .pll_table
= tegra_pll_d_table
,
1250 .max_rate
= 1000000000,
1253 static struct clk tegra_pll_d_out0
= {
1254 .name
= "pll_d_out0",
1255 .ops
= &tegra_pll_div_ops
,
1256 .flags
= DIV_2
| PLLD
,
1257 .parent
= &tegra_pll_d
,
1258 .max_rate
= 500000000,
1261 static struct clk_pll_table tegra_pll_u_table
[] = {
1262 { 12000000, 480000000, 960, 12, 2, 0},
1263 { 13000000, 480000000, 960, 13, 2, 0},
1264 { 19200000, 480000000, 200, 4, 2, 0},
1265 { 26000000, 480000000, 960, 26, 2, 0},
1266 { 0, 0, 0, 0, 0, 0 },
1269 static struct clk tegra_pll_u
= {
1272 .ops
= &tegra_pll_ops
,
1274 .input_min
= 2000000,
1275 .input_max
= 40000000,
1276 .parent
= &tegra_clk_m
,
1279 .vco_min
= 480000000,
1280 .vco_max
= 960000000,
1281 .pll_table
= tegra_pll_u_table
,
1282 .max_rate
= 480000000,
1285 static struct clk_pll_table tegra_pll_x_table
[] = {
1287 { 12000000, 1000000000, 1000, 12, 1, 12},
1288 { 13000000, 1000000000, 1000, 13, 1, 12},
1289 { 19200000, 1000000000, 625, 12, 1, 8},
1290 { 26000000, 1000000000, 1000, 26, 1, 12},
1293 { 12000000, 912000000, 912, 12, 1, 12},
1294 { 13000000, 912000000, 912, 13, 1, 12},
1295 { 19200000, 912000000, 760, 16, 1, 8},
1296 { 26000000, 912000000, 912, 26, 1, 12},
1299 { 12000000, 816000000, 816, 12, 1, 12},
1300 { 13000000, 816000000, 816, 13, 1, 12},
1301 { 19200000, 816000000, 680, 16, 1, 8},
1302 { 26000000, 816000000, 816, 26, 1, 12},
1305 { 12000000, 760000000, 760, 12, 1, 12},
1306 { 13000000, 760000000, 760, 13, 1, 12},
1307 { 19200000, 760000000, 950, 24, 1, 8},
1308 { 26000000, 760000000, 760, 26, 1, 12},
1311 { 12000000, 608000000, 760, 12, 1, 12},
1312 { 13000000, 608000000, 760, 13, 1, 12},
1313 { 19200000, 608000000, 380, 12, 1, 8},
1314 { 26000000, 608000000, 760, 26, 1, 12},
1317 { 12000000, 456000000, 456, 12, 1, 12},
1318 { 13000000, 456000000, 456, 13, 1, 12},
1319 { 19200000, 456000000, 380, 16, 1, 8},
1320 { 26000000, 456000000, 456, 26, 1, 12},
1323 { 12000000, 312000000, 312, 12, 1, 12},
1324 { 13000000, 312000000, 312, 13, 1, 12},
1325 { 19200000, 312000000, 260, 16, 1, 8},
1326 { 26000000, 312000000, 312, 26, 1, 12},
1328 { 0, 0, 0, 0, 0, 0 },
1331 static struct clk tegra_pll_x
= {
1333 .flags
= PLL_HAS_CPCON
| PLL_ALT_MISC_REG
,
1334 .ops
= &tegra_pllx_ops
,
1336 .input_min
= 2000000,
1337 .input_max
= 31000000,
1338 .parent
= &tegra_clk_m
,
1341 .vco_min
= 20000000,
1342 .vco_max
= 1200000000,
1343 .pll_table
= tegra_pll_x_table
,
1344 .max_rate
= 1000000000,
1347 static struct clk_pll_table tegra_pll_e_table
[] = {
1348 { 12000000, 100000000, 200, 24, 1, 0 },
1349 { 0, 0, 0, 0, 0, 0 },
1352 static struct clk tegra_pll_e
= {
1354 .flags
= PLL_ALT_MISC_REG
,
1355 .ops
= &tegra_plle_ops
,
1356 .input_min
= 12000000,
1357 .input_max
= 12000000,
1358 .max_rate
= 100000000,
1359 .parent
= &tegra_clk_m
,
1361 .pll_table
= tegra_pll_e_table
,
1364 static struct clk tegra_clk_d
= {
1366 .flags
= PERIPH_NO_RESET
,
1367 .ops
= &tegra_clk_double_ops
,
1371 .parent
= &tegra_clk_m
,
1372 .max_rate
= 52000000,
1375 /* initialized before peripheral clocks */
1376 static struct clk_mux_sel mux_audio_sync_clk
[8+1];
1377 static const struct audio_sources
{
1380 } mux_audio_sync_clk_sources
[] = {
1381 { .name
= "spdif_in", .value
= 0 },
1382 { .name
= "i2s1", .value
= 1 },
1383 { .name
= "i2s2", .value
= 2 },
1384 { .name
= "pll_a_out0", .value
= 4 },
1385 #if 0 /* FIXME: not implemented */
1386 { .name
= "ac97", .value
= 3 },
1387 { .name
= "ext_audio_clk2", .value
= 5 },
1388 { .name
= "ext_audio_clk1", .value
= 6 },
1389 { .name
= "ext_vimclk", .value
= 7 },
1394 static struct clk tegra_clk_audio
= {
1396 .inputs
= mux_audio_sync_clk
,
1398 .max_rate
= 24000000,
1399 .ops
= &tegra_audio_sync_clk_ops
1402 static struct clk tegra_clk_audio_2x
= {
1404 .flags
= PERIPH_NO_RESET
,
1405 .max_rate
= 48000000,
1406 .ops
= &tegra_clk_double_ops
,
1410 .parent
= &tegra_clk_audio
,
1413 struct clk_lookup tegra_audio_clk_lookups
[] = {
1414 { .con_id
= "audio", .clk
= &tegra_clk_audio
},
1415 { .con_id
= "audio_2x", .clk
= &tegra_clk_audio_2x
}
1418 /* This is called after peripheral clocks are initialized, as the
1419 * audio_sync clock depends on some of the peripheral clocks.
1422 static void init_audio_sync_clock_mux(void)
1425 struct clk_mux_sel
*sel
= mux_audio_sync_clk
;
1426 const struct audio_sources
*src
= mux_audio_sync_clk_sources
;
1427 struct clk_lookup
*lookup
;
1429 for (i
= 0; src
->name
; i
++, sel
++, src
++) {
1430 sel
->input
= tegra_get_clock_by_name(src
->name
);
1432 pr_err("%s: could not find clk %s\n", __func__
,
1434 sel
->value
= src
->value
;
1437 lookup
= tegra_audio_clk_lookups
;
1438 for (i
= 0; i
< ARRAY_SIZE(tegra_audio_clk_lookups
); i
++, lookup
++) {
1439 clk_init(lookup
->clk
);
1444 static struct clk_mux_sel mux_cclk
[] = {
1445 { .input
= &tegra_clk_m
, .value
= 0},
1446 { .input
= &tegra_pll_c
, .value
= 1},
1447 { .input
= &tegra_clk_32k
, .value
= 2},
1448 { .input
= &tegra_pll_m
, .value
= 3},
1449 { .input
= &tegra_pll_p
, .value
= 4},
1450 { .input
= &tegra_pll_p_out4
, .value
= 5},
1451 { .input
= &tegra_pll_p_out3
, .value
= 6},
1452 { .input
= &tegra_clk_d
, .value
= 7},
1453 { .input
= &tegra_pll_x
, .value
= 8},
1457 static struct clk_mux_sel mux_sclk
[] = {
1458 { .input
= &tegra_clk_m
, .value
= 0},
1459 { .input
= &tegra_pll_c_out1
, .value
= 1},
1460 { .input
= &tegra_pll_p_out4
, .value
= 2},
1461 { .input
= &tegra_pll_p_out3
, .value
= 3},
1462 { .input
= &tegra_pll_p_out2
, .value
= 4},
1463 { .input
= &tegra_clk_d
, .value
= 5},
1464 { .input
= &tegra_clk_32k
, .value
= 6},
1465 { .input
= &tegra_pll_m_out1
, .value
= 7},
1469 static struct clk tegra_clk_cclk
= {
1473 .ops
= &tegra_super_ops
,
1474 .max_rate
= 1000000000,
1477 static struct clk tegra_clk_sclk
= {
1481 .ops
= &tegra_super_ops
,
1482 .max_rate
= 600000000,
1485 static struct clk tegra_clk_virtual_cpu
= {
1487 .parent
= &tegra_clk_cclk
,
1488 .main
= &tegra_pll_x
,
1489 .backup
= &tegra_clk_m
,
1490 .ops
= &tegra_cpu_ops
,
1491 .max_rate
= 1000000000,
1492 .dvfs
= &tegra_dvfs_virtual_cpu_dvfs
,
1495 static struct clk tegra_clk_hclk
= {
1498 .parent
= &tegra_clk_sclk
,
1501 .ops
= &tegra_bus_ops
,
1502 .max_rate
= 240000000,
1505 static struct clk tegra_clk_pclk
= {
1508 .parent
= &tegra_clk_hclk
,
1511 .ops
= &tegra_bus_ops
,
1512 .max_rate
= 108000000,
1515 static struct clk_mux_sel mux_pllm_pllc_pllp_plla
[] = {
1516 { .input
= &tegra_pll_m
, .value
= 0},
1517 { .input
= &tegra_pll_c
, .value
= 1},
1518 { .input
= &tegra_pll_p
, .value
= 2},
1519 { .input
= &tegra_pll_a_out0
, .value
= 3},
1523 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm
[] = {
1524 { .input
= &tegra_pll_m
, .value
= 0},
1525 { .input
= &tegra_pll_c
, .value
= 1},
1526 { .input
= &tegra_pll_p
, .value
= 2},
1527 { .input
= &tegra_clk_m
, .value
= 3},
1531 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm
[] = {
1532 { .input
= &tegra_pll_p
, .value
= 0},
1533 { .input
= &tegra_pll_c
, .value
= 1},
1534 { .input
= &tegra_pll_m
, .value
= 2},
1535 { .input
= &tegra_clk_m
, .value
= 3},
1539 static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm
[] = {
1540 {.input
= &tegra_pll_a_out0
, .value
= 0},
1541 {.input
= &tegra_clk_audio_2x
, .value
= 1},
1542 {.input
= &tegra_pll_p
, .value
= 2},
1543 {.input
= &tegra_clk_m
, .value
= 3},
1547 static struct clk_mux_sel mux_pllp_plld_pllc_clkm
[] = {
1548 {.input
= &tegra_pll_p
, .value
= 0},
1549 {.input
= &tegra_pll_d_out0
, .value
= 1},
1550 {.input
= &tegra_pll_c
, .value
= 2},
1551 {.input
= &tegra_clk_m
, .value
= 3},
1555 static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32
[] = {
1556 {.input
= &tegra_pll_p
, .value
= 0},
1557 {.input
= &tegra_pll_c
, .value
= 1},
1558 {.input
= &tegra_clk_audio
, .value
= 2},
1559 {.input
= &tegra_clk_m
, .value
= 3},
1560 {.input
= &tegra_clk_32k
, .value
= 4},
1564 static struct clk_mux_sel mux_pllp_pllc_pllm
[] = {
1565 {.input
= &tegra_pll_p
, .value
= 0},
1566 {.input
= &tegra_pll_c
, .value
= 1},
1567 {.input
= &tegra_pll_m
, .value
= 2},
1571 static struct clk_mux_sel mux_clk_m
[] = {
1572 { .input
= &tegra_clk_m
, .value
= 0},
1576 static struct clk_mux_sel mux_pllp_out3
[] = {
1577 { .input
= &tegra_pll_p_out3
, .value
= 0},
1581 static struct clk_mux_sel mux_plld
[] = {
1582 { .input
= &tegra_pll_d
, .value
= 0},
1586 static struct clk_mux_sel mux_clk_32k
[] = {
1587 { .input
= &tegra_clk_32k
, .value
= 0},
1591 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
1598 .ops = &tegra_periph_clk_ops, \
1599 .clk_num = _clk_num, \
1601 .inputs = _inputs, \
1606 struct clk tegra_periph_clks
[] = {
1607 PERIPH_CLK("rtc", "rtc-tegra", NULL
, 4, 0, 32768, mux_clk_32k
, PERIPH_NO_RESET
),
1608 PERIPH_CLK("timer", "timer", NULL
, 5, 0, 26000000, mux_clk_m
, 0),
1609 PERIPH_CLK("i2s1", "i2s.0", NULL
, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm
, MUX
| DIV_U71
),
1610 PERIPH_CLK("i2s2", "i2s.1", NULL
, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm
, MUX
| DIV_U71
),
1611 /* FIXME: spdif has 2 clocks but 1 enable */
1612 PERIPH_CLK("spdif_out", "spdif_out", NULL
, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm
, MUX
| DIV_U71
),
1613 PERIPH_CLK("spdif_in", "spdif_in", NULL
, 10, 0x10c, 100000000, mux_pllp_pllc_pllm
, MUX
| DIV_U71
),
1614 PERIPH_CLK("pwm", "pwm", NULL
, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32
, MUX
| DIV_U71
),
1615 PERIPH_CLK("spi", "spi", NULL
, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
),
1616 PERIPH_CLK("xio", "xio", NULL
, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
),
1617 PERIPH_CLK("twc", "twc", NULL
, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
),
1618 PERIPH_CLK("sbc1", "spi_tegra.0", NULL
, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
),
1619 PERIPH_CLK("sbc2", "spi_tegra.1", NULL
, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
),
1620 PERIPH_CLK("sbc3", "spi_tegra.2", NULL
, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
),
1621 PERIPH_CLK("sbc4", "spi_tegra.3", NULL
, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
),
1622 PERIPH_CLK("ide", "ide", NULL
, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
), /* requires min voltage */
1623 PERIPH_CLK("ndflash", "tegra_nand", NULL
, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
), /* scales with voltage */
1624 /* FIXME: vfir shares an enable with uartb */
1625 PERIPH_CLK("vfir", "vfir", NULL
, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
),
1626 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL
, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
), /* scales with voltage */
1627 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL
, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
), /* scales with voltage */
1628 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL
, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
), /* scales with voltage */
1629 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL
, 15, 0x160, 52000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
), /* scales with voltage */
1630 PERIPH_CLK("vde", "vde", NULL
, 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
), /* scales with voltage and process_id */
1631 PERIPH_CLK("csite", "csite", NULL
, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
), /* max rate ??? */
1632 /* FIXME: what is la? */
1633 PERIPH_CLK("la", "la", NULL
, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
),
1634 PERIPH_CLK("owr", "tegra_w1", NULL
, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
),
1635 PERIPH_CLK("nor", "nor", NULL
, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
), /* requires min voltage */
1636 PERIPH_CLK("mipi", "mipi", NULL
, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U71
), /* scales with voltage */
1637 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL
, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U16
),
1638 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL
, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U16
),
1639 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL
, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U16
),
1640 PERIPH_CLK("dvc", "tegra-i2c.3", NULL
, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm
, MUX
| DIV_U16
),
1641 PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3
, 0),
1642 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3
, 0),
1643 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3
, 0),
1644 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3
, 0),
1645 PERIPH_CLK("uarta", "uart.0", NULL
, 6, 0x178, 216000000, mux_pllp_pllc_pllm_clkm
, MUX
),
1646 PERIPH_CLK("uartb", "uart.1", NULL
, 7, 0x17c, 216000000, mux_pllp_pllc_pllm_clkm
, MUX
),
1647 PERIPH_CLK("uartc", "uart.2", NULL
, 55, 0x1a0, 216000000, mux_pllp_pllc_pllm_clkm
, MUX
),
1648 PERIPH_CLK("uartd", "uart.3", NULL
, 65, 0x1c0, 216000000, mux_pllp_pllc_pllm_clkm
, MUX
),
1649 PERIPH_CLK("uarte", "uart.4", NULL
, 66, 0x1c4, 216000000, mux_pllp_pllc_pllm_clkm
, MUX
),
1650 PERIPH_CLK("3d", "3d", NULL
, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla
, MUX
| DIV_U71
| PERIPH_MANUAL_RESET
), /* scales with voltage and process_id */
1651 PERIPH_CLK("2d", "2d", NULL
, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla
, MUX
| DIV_U71
), /* scales with voltage and process_id */
1652 /* FIXME: vi and vi_sensor share an enable */
1653 PERIPH_CLK("vi", "vi", NULL
, 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla
, MUX
| DIV_U71
), /* scales with voltage and process_id */
1654 PERIPH_CLK("vi_sensor", "vi_sensor", NULL
, 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla
, MUX
| DIV_U71
| PERIPH_NO_RESET
), /* scales with voltage and process_id */
1655 PERIPH_CLK("epp", "epp", NULL
, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla
, MUX
| DIV_U71
), /* scales with voltage and process_id */
1656 PERIPH_CLK("mpe", "mpe", NULL
, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla
, MUX
| DIV_U71
), /* scales with voltage and process_id */
1657 PERIPH_CLK("host1x", "host1x", NULL
, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla
, MUX
| DIV_U71
), /* scales with voltage and process_id */
1658 /* FIXME: cve and tvo share an enable */
1659 PERIPH_CLK("cve", "cve", NULL
, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm
, MUX
| DIV_U71
), /* requires min voltage */
1660 PERIPH_CLK("tvo", "tvo", NULL
, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm
, MUX
| DIV_U71
), /* requires min voltage */
1661 PERIPH_CLK("hdmi", "hdmi", NULL
, 51, 0x18c, 148500000, mux_pllp_plld_pllc_clkm
, MUX
| DIV_U71
), /* requires min voltage */
1662 PERIPH_CLK("tvdac", "tvdac", NULL
, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm
, MUX
| DIV_U71
), /* requires min voltage */
1663 PERIPH_CLK("disp1", "tegrafb.0", NULL
, 27, 0x138, 190000000, mux_pllp_plld_pllc_clkm
, MUX
| DIV_U71
), /* scales with voltage and process_id */
1664 PERIPH_CLK("disp2", "tegrafb.1", NULL
, 26, 0x13c, 190000000, mux_pllp_plld_pllc_clkm
, MUX
| DIV_U71
), /* scales with voltage and process_id */
1665 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL
, 22, 0, 480000000, mux_clk_m
, 0), /* requires min voltage */
1666 PERIPH_CLK("usb2", "tegra-ehci.1", NULL
, 58, 0, 480000000, mux_clk_m
, 0), /* requires min voltage */
1667 PERIPH_CLK("usb3", "tegra-ehci.2", NULL
, 59, 0, 480000000, mux_clk_m
, 0), /* requires min voltage */
1668 PERIPH_CLK("emc", "emc", NULL
, 57, 0x19c, 800000000, mux_pllm_pllc_pllp_clkm
, MUX
| DIV_U71
| PERIPH_EMC_ENB
),
1669 PERIPH_CLK("dsi", "dsi", NULL
, 48, 0, 500000000, mux_plld
, 0), /* scales with voltage */
1670 PERIPH_CLK("csi", "csi", NULL
, 52, 0, 72000000, mux_pllp_out3
, 0),
1671 PERIPH_CLK("isp", "isp", NULL
, 23, 0, 150000000, mux_clk_m
, 0), /* same frequency as VI */
1672 PERIPH_CLK("csus", "csus", NULL
, 92, 0, 150000000, mux_clk_m
, PERIPH_NO_RESET
),
1673 PERIPH_CLK("pex", NULL
, "pex", 70, 0, 26000000, mux_clk_m
, PERIPH_MANUAL_RESET
),
1674 PERIPH_CLK("afi", NULL
, "afi", 72, 0, 26000000, mux_clk_m
, PERIPH_MANUAL_RESET
),
1675 PERIPH_CLK("pcie_xclk", NULL
, "pcie_xclk", 74, 0, 26000000, mux_clk_m
, PERIPH_MANUAL_RESET
),
1678 #define CLK_DUPLICATE(_name, _dev, _con) \
1687 /* Some clocks may be used by different drivers depending on the board
1688 * configuration. List those here to register them twice in the clock lookup
1689 * table under two names.
1691 struct clk_duplicate tegra_clk_duplicates
[] = {
1692 CLK_DUPLICATE("uarta", "tegra_uart.0", NULL
),
1693 CLK_DUPLICATE("uartb", "tegra_uart.1", NULL
),
1694 CLK_DUPLICATE("uartc", "tegra_uart.2", NULL
),
1695 CLK_DUPLICATE("uartd", "tegra_uart.3", NULL
),
1696 CLK_DUPLICATE("uarte", "tegra_uart.4", NULL
),
1697 CLK_DUPLICATE("host1x", "tegrafb.0", "host1x"),
1698 CLK_DUPLICATE("host1x", "tegrafb.1", "host1x"),
1699 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL
),
1702 #define CLK(dev, con, ck) \
1709 struct clk_lookup tegra_clk_lookups
[] = {
1710 /* external root sources */
1711 CLK(NULL
, "32k_clk", &tegra_clk_32k
),
1712 CLK(NULL
, "pll_s", &tegra_pll_s
),
1713 CLK(NULL
, "clk_m", &tegra_clk_m
),
1714 CLK(NULL
, "pll_m", &tegra_pll_m
),
1715 CLK(NULL
, "pll_m_out1", &tegra_pll_m_out1
),
1716 CLK(NULL
, "pll_c", &tegra_pll_c
),
1717 CLK(NULL
, "pll_c_out1", &tegra_pll_c_out1
),
1718 CLK(NULL
, "pll_p", &tegra_pll_p
),
1719 CLK(NULL
, "pll_p_out1", &tegra_pll_p_out1
),
1720 CLK(NULL
, "pll_p_out2", &tegra_pll_p_out2
),
1721 CLK(NULL
, "pll_p_out3", &tegra_pll_p_out3
),
1722 CLK(NULL
, "pll_p_out4", &tegra_pll_p_out4
),
1723 CLK(NULL
, "pll_a", &tegra_pll_a
),
1724 CLK(NULL
, "pll_a_out0", &tegra_pll_a_out0
),
1725 CLK(NULL
, "pll_d", &tegra_pll_d
),
1726 CLK(NULL
, "pll_d_out0", &tegra_pll_d_out0
),
1727 CLK(NULL
, "pll_u", &tegra_pll_u
),
1728 CLK(NULL
, "pll_x", &tegra_pll_x
),
1729 CLK(NULL
, "pll_e", &tegra_pll_e
),
1730 CLK(NULL
, "cclk", &tegra_clk_cclk
),
1731 CLK(NULL
, "sclk", &tegra_clk_sclk
),
1732 CLK(NULL
, "hclk", &tegra_clk_hclk
),
1733 CLK(NULL
, "pclk", &tegra_clk_pclk
),
1734 CLK(NULL
, "clk_d", &tegra_clk_d
),
1735 CLK(NULL
, "cpu", &tegra_clk_virtual_cpu
),
1738 void __init
tegra2_init_clocks(void)
1741 struct clk_lookup
*cl
;
1743 struct clk_duplicate
*cd
;
1745 for (i
= 0; i
< ARRAY_SIZE(tegra_clk_lookups
); i
++) {
1746 cl
= &tegra_clk_lookups
[i
];
1751 for (i
= 0; i
< ARRAY_SIZE(tegra_periph_clks
); i
++) {
1752 c
= &tegra_periph_clks
[i
];
1760 for (i
= 0; i
< ARRAY_SIZE(tegra_clk_duplicates
); i
++) {
1761 cd
= &tegra_clk_duplicates
[i
];
1762 c
= tegra_get_clock_by_name(cd
->name
);
1768 pr_err("%s: Unknown duplicate clock %s\n", __func__
,
1773 init_audio_sync_clock_mux();
1777 static u32 clk_rst_suspend
[RST_DEVICES_NUM
+ CLK_OUT_ENB_NUM
+
1778 PERIPH_CLK_SOURCE_NUM
+ 3];
1780 void tegra_clk_suspend(void)
1782 unsigned long off
, i
;
1783 u32
*ctx
= clk_rst_suspend
;
1785 *ctx
++ = clk_readl(OSC_CTRL
) & OSC_CTRL_MASK
;
1787 for (off
= PERIPH_CLK_SOURCE_I2S1
; off
<= PERIPH_CLK_SOURCE_OSC
;
1789 if (off
== PERIPH_CLK_SOURCE_EMC
)
1791 *ctx
++ = clk_readl(off
);
1795 for (i
= 0; i
< RST_DEVICES_NUM
; i
++, off
+= 4)
1796 *ctx
++ = clk_readl(off
);
1799 for (i
= 0; i
< CLK_OUT_ENB_NUM
; i
++, off
+= 4)
1800 *ctx
++ = clk_readl(off
);
1802 *ctx
++ = clk_readl(MISC_CLK_ENB
);
1803 *ctx
++ = clk_readl(CLK_MASK_ARM
);
1806 void tegra_clk_resume(void)
1808 unsigned long off
, i
;
1809 const u32
*ctx
= clk_rst_suspend
;
1812 val
= clk_readl(OSC_CTRL
) & ~OSC_CTRL_MASK
;
1814 clk_writel(val
, OSC_CTRL
);
1816 /* enable all clocks before configuring clock sources */
1817 clk_writel(0xbffffff9ul
, CLK_OUT_ENB
);
1818 clk_writel(0xfefffff7ul
, CLK_OUT_ENB
+ 4);
1819 clk_writel(0x77f01bfful
, CLK_OUT_ENB
+ 8);
1822 for (off
= PERIPH_CLK_SOURCE_I2S1
; off
<= PERIPH_CLK_SOURCE_OSC
;
1824 if (off
== PERIPH_CLK_SOURCE_EMC
)
1826 clk_writel(*ctx
++, off
);
1831 for (i
= 0; i
< RST_DEVICES_NUM
; i
++, off
+= 4)
1832 clk_writel(*ctx
++, off
);
1836 for (i
= 0; i
< CLK_OUT_ENB_NUM
; i
++, off
+= 4)
1837 clk_writel(*ctx
++, off
);
1840 clk_writel(*ctx
++, MISC_CLK_ENB
);
1841 clk_writel(*ctx
++, CLK_MASK_ARM
);