2 * OMAP Power Management debug routines
4 * Copyright (C) 2005 Texas Instruments, Inc.
5 * Copyright (C) 2006-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * Amit Kucheria <amit.kucheria@nokia.com>
12 * Igor Stoppa <igor.stoppa@nokia.com>
15 * Based on pm.c for omap2
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
22 #include <linux/kernel.h>
23 #include <linux/sched.h>
24 #include <linux/clk.h>
25 #include <linux/err.h>
27 #include <linux/module.h>
28 #include <linux/slab.h>
30 #include <plat/clock.h>
31 #include <plat/board.h>
32 #include <plat/powerdomain.h>
33 #include <plat/clockdomain.h>
34 #include <plat/dmtimer.h>
43 u32 wakeup_timer_seconds
;
44 u32 wakeup_timer_milliseconds
;
46 #define DUMP_PRM_MOD_REG(mod, reg) \
47 regs[reg_count].name = #mod "." #reg; \
48 regs[reg_count++].val = prm_read_mod_reg(mod, reg)
49 #define DUMP_CM_MOD_REG(mod, reg) \
50 regs[reg_count].name = #mod "." #reg; \
51 regs[reg_count++].val = cm_read_mod_reg(mod, reg)
52 #define DUMP_PRM_REG(reg) \
53 regs[reg_count].name = #reg; \
54 regs[reg_count++].val = __raw_readl(reg)
55 #define DUMP_CM_REG(reg) \
56 regs[reg_count].name = #reg; \
57 regs[reg_count++].val = __raw_readl(reg)
58 #define DUMP_INTC_REG(reg, off) \
59 regs[reg_count].name = #reg; \
60 regs[reg_count++].val = \
61 __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
63 void omap2_pm_dump(int mode
, int resume
, unsigned int us
)
70 const char *s1
= NULL
, *s2
= NULL
;
75 DUMP_PRM_MOD_REG(OCP_MOD
, OMAP2_PRM_IRQENABLE_MPU_OFFSET
);
76 DUMP_CM_MOD_REG(MPU_MOD
, OMAP2_CM_CLKSTCTRL
);
77 DUMP_PRM_MOD_REG(MPU_MOD
, OMAP2_PM_PWSTCTRL
);
78 DUMP_PRM_MOD_REG(MPU_MOD
, OMAP2_PM_PWSTST
);
79 DUMP_PRM_MOD_REG(MPU_MOD
, PM_WKDEP
);
83 DUMP_INTC_REG(INTC_MIR0
, 0x0084);
84 DUMP_INTC_REG(INTC_MIR1
, 0x00a4);
85 DUMP_INTC_REG(INTC_MIR2
, 0x00c4);
88 DUMP_CM_MOD_REG(CORE_MOD
, CM_FCLKEN1
);
89 if (cpu_is_omap24xx()) {
90 DUMP_CM_MOD_REG(CORE_MOD
, OMAP24XX_CM_FCLKEN2
);
91 DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD
,
92 OMAP2_PRCM_CLKEMUL_CTRL_OFFSET
);
93 DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD
,
94 OMAP2_PRCM_CLKSRC_CTRL_OFFSET
);
96 DUMP_CM_MOD_REG(WKUP_MOD
, CM_FCLKEN
);
97 DUMP_CM_MOD_REG(CORE_MOD
, CM_ICLKEN1
);
98 DUMP_CM_MOD_REG(CORE_MOD
, CM_ICLKEN2
);
99 DUMP_CM_MOD_REG(WKUP_MOD
, CM_ICLKEN
);
100 DUMP_CM_MOD_REG(PLL_MOD
, CM_CLKEN
);
101 DUMP_CM_MOD_REG(PLL_MOD
, CM_AUTOIDLE
);
102 DUMP_PRM_MOD_REG(CORE_MOD
, OMAP2_PM_PWSTST
);
106 if (cpu_is_omap24xx()) {
107 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD
, CM_FCLKEN
);
108 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD
, CM_ICLKEN
);
109 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD
, CM_IDLEST
);
110 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD
, CM_AUTOIDLE
);
111 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD
, CM_CLKSEL
);
112 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD
, OMAP2_CM_CLKSTCTRL
);
113 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD
, OMAP2_RM_RSTCTRL
);
114 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD
, OMAP2_RM_RSTST
);
115 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD
, OMAP2_PM_PWSTCTRL
);
116 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD
, OMAP2_PM_PWSTST
);
120 DUMP_PRM_MOD_REG(CORE_MOD
, PM_WKST1
);
121 if (cpu_is_omap24xx())
122 DUMP_PRM_MOD_REG(CORE_MOD
, OMAP24XX_PM_WKST2
);
123 DUMP_PRM_MOD_REG(WKUP_MOD
, PM_WKST
);
124 DUMP_PRM_MOD_REG(OCP_MOD
, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
);
126 DUMP_INTC_REG(INTC_PENDING_IRQ0
, 0x0098);
127 DUMP_INTC_REG(INTC_PENDING_IRQ1
, 0x00b8);
128 DUMP_INTC_REG(INTC_PENDING_IRQ2
, 0x00d8);
150 "--- Going to %s %s (next timer after %u ms)\n", s1
, s2
,
151 jiffies_to_msecs(get_next_timer_interrupt(jiffies
) -
154 printk(KERN_INFO
"--- Going to %s %s\n", s1
, s2
);
157 printk(KERN_INFO
"--- Woke up (slept for %u.%03u ms)\n",
158 us
/ 1000, us
% 1000);
160 for (i
= 0; i
< reg_count
; i
++)
161 printk(KERN_INFO
"%-20s: 0x%08x\n", regs
[i
].name
, regs
[i
].val
);
164 void omap2_pm_wakeup_on_timer(u32 seconds
, u32 milliseconds
)
166 u32 tick_rate
, cycles
;
168 if (!seconds
&& !milliseconds
)
171 tick_rate
= clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup
));
172 cycles
= tick_rate
* seconds
+ tick_rate
* milliseconds
/ 1000;
173 omap_dm_timer_stop(gptimer_wakeup
);
174 omap_dm_timer_set_load_start(gptimer_wakeup
, 0, 0xffffffff - cycles
);
176 pr_info("PM: Resume timer in %u.%03u secs"
177 " (%d ticks at %d ticks/sec.)\n",
178 seconds
, milliseconds
, cycles
, tick_rate
);
181 #ifdef CONFIG_DEBUG_FS
182 #include <linux/debugfs.h>
183 #include <linux/seq_file.h>
185 static void pm_dbg_regset_store(u32
*ptr
);
187 static struct dentry
*pm_dbg_dir
;
189 static int pm_dbg_init_done
;
191 static int __init
pm_dbg_init(void);
194 DEBUG_FILE_COUNTERS
= 0,
198 struct pm_module_def
{
199 char name
[8]; /* Name of the module */
200 short type
; /* CM or PRM */
201 unsigned short offset
;
202 int low
; /* First register address on this module */
203 int high
; /* Last register address on this module */
209 static const struct pm_module_def
*pm_dbg_reg_modules
;
210 static const struct pm_module_def omap3_pm_reg_modules
[] = {
211 { "IVA2", MOD_CM
, OMAP3430_IVA2_MOD
, 0, 0x4c },
212 { "OCP", MOD_CM
, OCP_MOD
, 0, 0x10 },
213 { "MPU", MOD_CM
, MPU_MOD
, 4, 0x4c },
214 { "CORE", MOD_CM
, CORE_MOD
, 0, 0x4c },
215 { "SGX", MOD_CM
, OMAP3430ES2_SGX_MOD
, 0, 0x4c },
216 { "WKUP", MOD_CM
, WKUP_MOD
, 0, 0x40 },
217 { "CCR", MOD_CM
, PLL_MOD
, 0, 0x70 },
218 { "DSS", MOD_CM
, OMAP3430_DSS_MOD
, 0, 0x4c },
219 { "CAM", MOD_CM
, OMAP3430_CAM_MOD
, 0, 0x4c },
220 { "PER", MOD_CM
, OMAP3430_PER_MOD
, 0, 0x4c },
221 { "EMU", MOD_CM
, OMAP3430_EMU_MOD
, 0x40, 0x54 },
222 { "NEON", MOD_CM
, OMAP3430_NEON_MOD
, 0x20, 0x48 },
223 { "USB", MOD_CM
, OMAP3430ES2_USBHOST_MOD
, 0, 0x4c },
225 { "IVA2", MOD_PRM
, OMAP3430_IVA2_MOD
, 0x50, 0xfc },
226 { "OCP", MOD_PRM
, OCP_MOD
, 4, 0x1c },
227 { "MPU", MOD_PRM
, MPU_MOD
, 0x58, 0xe8 },
228 { "CORE", MOD_PRM
, CORE_MOD
, 0x58, 0xf8 },
229 { "SGX", MOD_PRM
, OMAP3430ES2_SGX_MOD
, 0x58, 0xe8 },
230 { "WKUP", MOD_PRM
, WKUP_MOD
, 0xa0, 0xb0 },
231 { "CCR", MOD_PRM
, PLL_MOD
, 0x40, 0x70 },
232 { "DSS", MOD_PRM
, OMAP3430_DSS_MOD
, 0x58, 0xe8 },
233 { "CAM", MOD_PRM
, OMAP3430_CAM_MOD
, 0x58, 0xe8 },
234 { "PER", MOD_PRM
, OMAP3430_PER_MOD
, 0x58, 0xe8 },
235 { "EMU", MOD_PRM
, OMAP3430_EMU_MOD
, 0x58, 0xe4 },
236 { "GLBL", MOD_PRM
, OMAP3430_GR_MOD
, 0x20, 0xe4 },
237 { "NEON", MOD_PRM
, OMAP3430_NEON_MOD
, 0x58, 0xe8 },
238 { "USB", MOD_PRM
, OMAP3430ES2_USBHOST_MOD
, 0x58, 0xe8 },
242 #define PM_DBG_MAX_REG_SETS 4
244 static void *pm_dbg_reg_set
[PM_DBG_MAX_REG_SETS
];
246 static int pm_dbg_get_regset_size(void)
248 static int regset_size
;
250 if (regset_size
== 0) {
253 while (pm_dbg_reg_modules
[i
].name
[0] != 0) {
254 regset_size
+= pm_dbg_reg_modules
[i
].high
+
255 4 - pm_dbg_reg_modules
[i
].low
;
262 static int pm_dbg_show_regs(struct seq_file
*s
, void *unused
)
266 int reg_set
= (int)s
->private;
273 store
= kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL
);
275 pm_dbg_regset_store(ptr
);
277 ptr
= pm_dbg_reg_set
[reg_set
- 1];
282 while (pm_dbg_reg_modules
[i
].name
[0] != 0) {
285 if (pm_dbg_reg_modules
[i
].type
== MOD_CM
)
286 seq_printf(s
, "MOD: CM_%s (%08x)\n",
287 pm_dbg_reg_modules
[i
].name
,
288 (u32
)(OMAP3430_CM_BASE
+
289 pm_dbg_reg_modules
[i
].offset
));
291 seq_printf(s
, "MOD: PRM_%s (%08x)\n",
292 pm_dbg_reg_modules
[i
].name
,
293 (u32
)(OMAP3430_PRM_BASE
+
294 pm_dbg_reg_modules
[i
].offset
));
296 for (j
= pm_dbg_reg_modules
[i
].low
;
297 j
<= pm_dbg_reg_modules
[i
].high
; j
+= 4) {
305 seq_printf(s
, " %02x => %08lx", j
, val
);
320 static void pm_dbg_regset_store(u32
*ptr
)
327 while (pm_dbg_reg_modules
[i
].name
[0] != 0) {
328 for (j
= pm_dbg_reg_modules
[i
].low
;
329 j
<= pm_dbg_reg_modules
[i
].high
; j
+= 4) {
330 if (pm_dbg_reg_modules
[i
].type
== MOD_CM
)
331 val
= cm_read_mod_reg(
332 pm_dbg_reg_modules
[i
].offset
, j
);
334 val
= prm_read_mod_reg(
335 pm_dbg_reg_modules
[i
].offset
, j
);
342 int pm_dbg_regset_save(int reg_set
)
344 if (pm_dbg_reg_set
[reg_set
-1] == NULL
)
347 pm_dbg_regset_store(pm_dbg_reg_set
[reg_set
-1]);
352 static const char pwrdm_state_names
[][PWRDM_MAX_PWRSTS
] = {
359 void pm_dbg_update_time(struct powerdomain
*pwrdm
, int prev
)
363 if (!pm_dbg_init_done
)
366 /* Update timer for previous state */
369 pwrdm
->state_timer
[prev
] += t
- pwrdm
->timer
;
374 static int clkdm_dbg_show_counter(struct clockdomain
*clkdm
, void *user
)
376 struct seq_file
*s
= (struct seq_file
*)user
;
378 if (strcmp(clkdm
->name
, "emu_clkdm") == 0 ||
379 strcmp(clkdm
->name
, "wkup_clkdm") == 0 ||
380 strncmp(clkdm
->name
, "dpll", 4) == 0)
383 seq_printf(s
, "%s->%s (%d)", clkdm
->name
,
384 clkdm
->pwrdm
.ptr
->name
,
385 atomic_read(&clkdm
->usecount
));
391 static int pwrdm_dbg_show_counter(struct powerdomain
*pwrdm
, void *user
)
393 struct seq_file
*s
= (struct seq_file
*)user
;
396 if (strcmp(pwrdm
->name
, "emu_pwrdm") == 0 ||
397 strcmp(pwrdm
->name
, "wkup_pwrdm") == 0 ||
398 strncmp(pwrdm
->name
, "dpll", 4) == 0)
401 if (pwrdm
->state
!= pwrdm_read_pwrst(pwrdm
))
402 printk(KERN_ERR
"pwrdm state mismatch(%s) %d != %d\n",
403 pwrdm
->name
, pwrdm
->state
, pwrdm_read_pwrst(pwrdm
));
405 seq_printf(s
, "%s (%s)", pwrdm
->name
,
406 pwrdm_state_names
[pwrdm
->state
]);
407 for (i
= 0; i
< PWRDM_MAX_PWRSTS
; i
++)
408 seq_printf(s
, ",%s:%d", pwrdm_state_names
[i
],
409 pwrdm
->state_counter
[i
]);
411 seq_printf(s
, ",RET-LOGIC-OFF:%d", pwrdm
->ret_logic_off_counter
);
412 for (i
= 0; i
< pwrdm
->banks
; i
++)
413 seq_printf(s
, ",RET-MEMBANK%d-OFF:%d", i
+ 1,
414 pwrdm
->ret_mem_off_counter
[i
]);
421 static int pwrdm_dbg_show_timer(struct powerdomain
*pwrdm
, void *user
)
423 struct seq_file
*s
= (struct seq_file
*)user
;
426 if (strcmp(pwrdm
->name
, "emu_pwrdm") == 0 ||
427 strcmp(pwrdm
->name
, "wkup_pwrdm") == 0 ||
428 strncmp(pwrdm
->name
, "dpll", 4) == 0)
431 pwrdm_state_switch(pwrdm
);
433 seq_printf(s
, "%s (%s)", pwrdm
->name
,
434 pwrdm_state_names
[pwrdm
->state
]);
436 for (i
= 0; i
< 4; i
++)
437 seq_printf(s
, ",%s:%lld", pwrdm_state_names
[i
],
438 pwrdm
->state_timer
[i
]);
444 static int pm_dbg_show_counters(struct seq_file
*s
, void *unused
)
446 pwrdm_for_each(pwrdm_dbg_show_counter
, s
);
447 clkdm_for_each(clkdm_dbg_show_counter
, s
);
452 static int pm_dbg_show_timers(struct seq_file
*s
, void *unused
)
454 pwrdm_for_each(pwrdm_dbg_show_timer
, s
);
458 static int pm_dbg_open(struct inode
*inode
, struct file
*file
)
460 switch ((int)inode
->i_private
) {
461 case DEBUG_FILE_COUNTERS
:
462 return single_open(file
, pm_dbg_show_counters
,
464 case DEBUG_FILE_TIMERS
:
466 return single_open(file
, pm_dbg_show_timers
,
471 static int pm_dbg_reg_open(struct inode
*inode
, struct file
*file
)
473 return single_open(file
, pm_dbg_show_regs
, inode
->i_private
);
476 static const struct file_operations debug_fops
= {
480 .release
= single_release
,
483 static const struct file_operations debug_reg_fops
= {
484 .open
= pm_dbg_reg_open
,
487 .release
= single_release
,
490 int pm_dbg_regset_init(int reg_set
)
494 if (!pm_dbg_init_done
)
497 if (reg_set
< 1 || reg_set
> PM_DBG_MAX_REG_SETS
||
498 pm_dbg_reg_set
[reg_set
-1] != NULL
)
501 pm_dbg_reg_set
[reg_set
-1] =
502 kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL
);
504 if (pm_dbg_reg_set
[reg_set
-1] == NULL
)
507 if (pm_dbg_dir
!= NULL
) {
508 sprintf(name
, "%d", reg_set
);
510 (void) debugfs_create_file(name
, S_IRUGO
,
511 pm_dbg_dir
, (void *)reg_set
, &debug_reg_fops
);
517 static int pwrdm_suspend_get(void *data
, u64
*val
)
521 if (cpu_is_omap34xx())
522 ret
= omap3_pm_get_suspend_state((struct powerdomain
*)data
);
530 static int pwrdm_suspend_set(void *data
, u64 val
)
532 if (cpu_is_omap34xx())
533 return omap3_pm_set_suspend_state(
534 (struct powerdomain
*)data
, (int)val
);
538 DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops
, pwrdm_suspend_get
,
539 pwrdm_suspend_set
, "%llu\n");
541 static int __init
pwrdms_setup(struct powerdomain
*pwrdm
, void *dir
)
549 for (i
= 0; i
< 4; i
++)
550 pwrdm
->state_timer
[i
] = 0;
554 if (strncmp(pwrdm
->name
, "dpll", 4) == 0)
557 d
= debugfs_create_dir(pwrdm
->name
, (struct dentry
*)dir
);
559 (void) debugfs_create_file("suspend", S_IRUGO
|S_IWUSR
, d
,
560 (void *)pwrdm
, &pwrdm_suspend_fops
);
565 static int option_get(void *data
, u64
*val
)
574 static int option_set(void *data
, u64 val
)
578 if (option
== &wakeup_timer_milliseconds
&& val
>= 1000)
583 if (option
== &enable_off_mode
) {
584 if (cpu_is_omap34xx())
585 omap3_pm_off_mode_enable(val
);
591 DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops
, option_get
, option_set
, "%llu\n");
593 static int __init
pm_dbg_init(void)
599 if (pm_dbg_init_done
)
602 if (cpu_is_omap34xx())
603 pm_dbg_reg_modules
= omap3_pm_reg_modules
;
605 printk(KERN_ERR
"%s: only OMAP3 supported\n", __func__
);
609 d
= debugfs_create_dir("pm_debug", NULL
);
613 (void) debugfs_create_file("count", S_IRUGO
,
614 d
, (void *)DEBUG_FILE_COUNTERS
, &debug_fops
);
615 (void) debugfs_create_file("time", S_IRUGO
,
616 d
, (void *)DEBUG_FILE_TIMERS
, &debug_fops
);
618 pwrdm_for_each(pwrdms_setup
, (void *)d
);
620 pm_dbg_dir
= debugfs_create_dir("registers", d
);
621 if (IS_ERR(pm_dbg_dir
))
622 return PTR_ERR(pm_dbg_dir
);
624 (void) debugfs_create_file("current", S_IRUGO
,
625 pm_dbg_dir
, (void *)0, &debug_reg_fops
);
627 for (i
= 0; i
< PM_DBG_MAX_REG_SETS
; i
++)
628 if (pm_dbg_reg_set
[i
] != NULL
) {
629 sprintf(name
, "%d", i
+1);
630 (void) debugfs_create_file(name
, S_IRUGO
,
631 pm_dbg_dir
, (void *)(i
+1), &debug_reg_fops
);
635 (void) debugfs_create_file("enable_off_mode", S_IRUGO
| S_IWUGO
, d
,
636 &enable_off_mode
, &pm_dbg_option_fops
);
637 (void) debugfs_create_file("sleep_while_idle", S_IRUGO
| S_IWUGO
, d
,
638 &sleep_while_idle
, &pm_dbg_option_fops
);
639 (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO
| S_IWUGO
, d
,
640 &wakeup_timer_seconds
, &pm_dbg_option_fops
);
641 (void) debugfs_create_file("wakeup_timer_milliseconds",
642 S_IRUGO
| S_IWUGO
, d
, &wakeup_timer_milliseconds
,
643 &pm_dbg_option_fops
);
644 pm_dbg_init_done
= 1;
648 arch_initcall(pm_dbg_init
);