2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
23 #include <plat/omap_hwmod.h>
26 #include "omap_hwmod_common_data.h"
29 #include "prm-regbits-44xx.h"
31 /* Base offset for all OMAP4 interrupts external to MPUSS */
32 #define OMAP44XX_IRQ_GIC_START 32
34 /* Base offset for all OMAP4 dma requests */
35 #define OMAP44XX_DMA_REQ_START 1
37 /* Backward references (IPs with Bus Master capability) */
38 static struct omap_hwmod omap44xx_dmm_hwmod
;
39 static struct omap_hwmod omap44xx_emif_fw_hwmod
;
40 static struct omap_hwmod omap44xx_l3_instr_hwmod
;
41 static struct omap_hwmod omap44xx_l3_main_1_hwmod
;
42 static struct omap_hwmod omap44xx_l3_main_2_hwmod
;
43 static struct omap_hwmod omap44xx_l3_main_3_hwmod
;
44 static struct omap_hwmod omap44xx_l4_abe_hwmod
;
45 static struct omap_hwmod omap44xx_l4_cfg_hwmod
;
46 static struct omap_hwmod omap44xx_l4_per_hwmod
;
47 static struct omap_hwmod omap44xx_l4_wkup_hwmod
;
48 static struct omap_hwmod omap44xx_mpu_hwmod
;
49 static struct omap_hwmod omap44xx_mpu_private_hwmod
;
52 * Interconnects omap_hwmod structures
53 * hwmods that compose the global OMAP interconnect
60 static struct omap_hwmod_class omap44xx_dmm_hwmod_class
= {
64 /* dmm interface data */
65 /* l3_main_1 -> dmm */
66 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm
= {
67 .master
= &omap44xx_l3_main_1_hwmod
,
68 .slave
= &omap44xx_dmm_hwmod
,
70 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
74 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm
= {
75 .master
= &omap44xx_mpu_hwmod
,
76 .slave
= &omap44xx_dmm_hwmod
,
78 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
82 static struct omap_hwmod_ocp_if
*omap44xx_dmm_slaves
[] = {
83 &omap44xx_l3_main_1__dmm
,
87 static struct omap_hwmod_irq_info omap44xx_dmm_irqs
[] = {
88 { .irq
= 113 + OMAP44XX_IRQ_GIC_START
},
91 static struct omap_hwmod omap44xx_dmm_hwmod
= {
93 .class = &omap44xx_dmm_hwmod_class
,
94 .slaves
= omap44xx_dmm_slaves
,
95 .slaves_cnt
= ARRAY_SIZE(omap44xx_dmm_slaves
),
96 .mpu_irqs
= omap44xx_dmm_irqs
,
97 .mpu_irqs_cnt
= ARRAY_SIZE(omap44xx_dmm_irqs
),
98 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
103 * instance(s): emif_fw
105 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class
= {
109 /* emif_fw interface data */
111 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw
= {
112 .master
= &omap44xx_dmm_hwmod
,
113 .slave
= &omap44xx_emif_fw_hwmod
,
115 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
118 /* l4_cfg -> emif_fw */
119 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw
= {
120 .master
= &omap44xx_l4_cfg_hwmod
,
121 .slave
= &omap44xx_emif_fw_hwmod
,
123 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
126 /* emif_fw slave ports */
127 static struct omap_hwmod_ocp_if
*omap44xx_emif_fw_slaves
[] = {
128 &omap44xx_dmm__emif_fw
,
129 &omap44xx_l4_cfg__emif_fw
,
132 static struct omap_hwmod omap44xx_emif_fw_hwmod
= {
134 .class = &omap44xx_emif_fw_hwmod_class
,
135 .slaves
= omap44xx_emif_fw_slaves
,
136 .slaves_cnt
= ARRAY_SIZE(omap44xx_emif_fw_slaves
),
137 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
142 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
144 static struct omap_hwmod_class omap44xx_l3_hwmod_class
= {
148 /* l3_instr interface data */
149 /* l3_main_3 -> l3_instr */
150 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr
= {
151 .master
= &omap44xx_l3_main_3_hwmod
,
152 .slave
= &omap44xx_l3_instr_hwmod
,
154 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
157 /* l3_instr slave ports */
158 static struct omap_hwmod_ocp_if
*omap44xx_l3_instr_slaves
[] = {
159 &omap44xx_l3_main_3__l3_instr
,
162 static struct omap_hwmod omap44xx_l3_instr_hwmod
= {
164 .class = &omap44xx_l3_hwmod_class
,
165 .slaves
= omap44xx_l3_instr_slaves
,
166 .slaves_cnt
= ARRAY_SIZE(omap44xx_l3_instr_slaves
),
167 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
170 /* l3_main_2 -> l3_main_1 */
171 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1
= {
172 .master
= &omap44xx_l3_main_2_hwmod
,
173 .slave
= &omap44xx_l3_main_1_hwmod
,
175 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
178 /* l4_cfg -> l3_main_1 */
179 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1
= {
180 .master
= &omap44xx_l4_cfg_hwmod
,
181 .slave
= &omap44xx_l3_main_1_hwmod
,
183 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
186 /* mpu -> l3_main_1 */
187 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1
= {
188 .master
= &omap44xx_mpu_hwmod
,
189 .slave
= &omap44xx_l3_main_1_hwmod
,
191 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
194 /* l3_main_1 slave ports */
195 static struct omap_hwmod_ocp_if
*omap44xx_l3_main_1_slaves
[] = {
196 &omap44xx_l3_main_2__l3_main_1
,
197 &omap44xx_l4_cfg__l3_main_1
,
198 &omap44xx_mpu__l3_main_1
,
201 static struct omap_hwmod omap44xx_l3_main_1_hwmod
= {
203 .class = &omap44xx_l3_hwmod_class
,
204 .slaves
= omap44xx_l3_main_1_slaves
,
205 .slaves_cnt
= ARRAY_SIZE(omap44xx_l3_main_1_slaves
),
206 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
209 /* l3_main_2 interface data */
210 /* l3_main_1 -> l3_main_2 */
211 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2
= {
212 .master
= &omap44xx_l3_main_1_hwmod
,
213 .slave
= &omap44xx_l3_main_2_hwmod
,
215 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
218 /* l4_cfg -> l3_main_2 */
219 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2
= {
220 .master
= &omap44xx_l4_cfg_hwmod
,
221 .slave
= &omap44xx_l3_main_2_hwmod
,
223 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
226 /* l3_main_2 slave ports */
227 static struct omap_hwmod_ocp_if
*omap44xx_l3_main_2_slaves
[] = {
228 &omap44xx_l3_main_1__l3_main_2
,
229 &omap44xx_l4_cfg__l3_main_2
,
232 static struct omap_hwmod omap44xx_l3_main_2_hwmod
= {
234 .class = &omap44xx_l3_hwmod_class
,
235 .slaves
= omap44xx_l3_main_2_slaves
,
236 .slaves_cnt
= ARRAY_SIZE(omap44xx_l3_main_2_slaves
),
237 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
240 /* l3_main_3 interface data */
241 /* l3_main_1 -> l3_main_3 */
242 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3
= {
243 .master
= &omap44xx_l3_main_1_hwmod
,
244 .slave
= &omap44xx_l3_main_3_hwmod
,
246 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
249 /* l3_main_2 -> l3_main_3 */
250 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3
= {
251 .master
= &omap44xx_l3_main_2_hwmod
,
252 .slave
= &omap44xx_l3_main_3_hwmod
,
254 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
257 /* l4_cfg -> l3_main_3 */
258 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3
= {
259 .master
= &omap44xx_l4_cfg_hwmod
,
260 .slave
= &omap44xx_l3_main_3_hwmod
,
262 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
265 /* l3_main_3 slave ports */
266 static struct omap_hwmod_ocp_if
*omap44xx_l3_main_3_slaves
[] = {
267 &omap44xx_l3_main_1__l3_main_3
,
268 &omap44xx_l3_main_2__l3_main_3
,
269 &omap44xx_l4_cfg__l3_main_3
,
272 static struct omap_hwmod omap44xx_l3_main_3_hwmod
= {
274 .class = &omap44xx_l3_hwmod_class
,
275 .slaves
= omap44xx_l3_main_3_slaves
,
276 .slaves_cnt
= ARRAY_SIZE(omap44xx_l3_main_3_slaves
),
277 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
282 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
284 static struct omap_hwmod_class omap44xx_l4_hwmod_class
= {
288 /* l4_abe interface data */
289 /* l3_main_1 -> l4_abe */
290 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe
= {
291 .master
= &omap44xx_l3_main_1_hwmod
,
292 .slave
= &omap44xx_l4_abe_hwmod
,
294 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
298 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe
= {
299 .master
= &omap44xx_mpu_hwmod
,
300 .slave
= &omap44xx_l4_abe_hwmod
,
301 .clk
= "ocp_abe_iclk",
302 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
305 /* l4_abe slave ports */
306 static struct omap_hwmod_ocp_if
*omap44xx_l4_abe_slaves
[] = {
307 &omap44xx_l3_main_1__l4_abe
,
308 &omap44xx_mpu__l4_abe
,
311 static struct omap_hwmod omap44xx_l4_abe_hwmod
= {
313 .class = &omap44xx_l4_hwmod_class
,
314 .slaves
= omap44xx_l4_abe_slaves
,
315 .slaves_cnt
= ARRAY_SIZE(omap44xx_l4_abe_slaves
),
316 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
319 /* l4_cfg interface data */
320 /* l3_main_1 -> l4_cfg */
321 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg
= {
322 .master
= &omap44xx_l3_main_1_hwmod
,
323 .slave
= &omap44xx_l4_cfg_hwmod
,
325 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
328 /* l4_cfg slave ports */
329 static struct omap_hwmod_ocp_if
*omap44xx_l4_cfg_slaves
[] = {
330 &omap44xx_l3_main_1__l4_cfg
,
333 static struct omap_hwmod omap44xx_l4_cfg_hwmod
= {
335 .class = &omap44xx_l4_hwmod_class
,
336 .slaves
= omap44xx_l4_cfg_slaves
,
337 .slaves_cnt
= ARRAY_SIZE(omap44xx_l4_cfg_slaves
),
338 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
341 /* l4_per interface data */
342 /* l3_main_2 -> l4_per */
343 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per
= {
344 .master
= &omap44xx_l3_main_2_hwmod
,
345 .slave
= &omap44xx_l4_per_hwmod
,
347 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
350 /* l4_per slave ports */
351 static struct omap_hwmod_ocp_if
*omap44xx_l4_per_slaves
[] = {
352 &omap44xx_l3_main_2__l4_per
,
355 static struct omap_hwmod omap44xx_l4_per_hwmod
= {
357 .class = &omap44xx_l4_hwmod_class
,
358 .slaves
= omap44xx_l4_per_slaves
,
359 .slaves_cnt
= ARRAY_SIZE(omap44xx_l4_per_slaves
),
360 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
363 /* l4_wkup interface data */
364 /* l4_cfg -> l4_wkup */
365 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup
= {
366 .master
= &omap44xx_l4_cfg_hwmod
,
367 .slave
= &omap44xx_l4_wkup_hwmod
,
369 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
372 /* l4_wkup slave ports */
373 static struct omap_hwmod_ocp_if
*omap44xx_l4_wkup_slaves
[] = {
374 &omap44xx_l4_cfg__l4_wkup
,
377 static struct omap_hwmod omap44xx_l4_wkup_hwmod
= {
379 .class = &omap44xx_l4_hwmod_class
,
380 .slaves
= omap44xx_l4_wkup_slaves
,
381 .slaves_cnt
= ARRAY_SIZE(omap44xx_l4_wkup_slaves
),
382 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
387 * instance(s): mpu_private
389 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class
= {
393 /* mpu_private interface data */
394 /* mpu -> mpu_private */
395 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private
= {
396 .master
= &omap44xx_mpu_hwmod
,
397 .slave
= &omap44xx_mpu_private_hwmod
,
399 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
402 /* mpu_private slave ports */
403 static struct omap_hwmod_ocp_if
*omap44xx_mpu_private_slaves
[] = {
404 &omap44xx_mpu__mpu_private
,
407 static struct omap_hwmod omap44xx_mpu_private_hwmod
= {
408 .name
= "mpu_private",
409 .class = &omap44xx_mpu_bus_hwmod_class
,
410 .slaves
= omap44xx_mpu_private_slaves
,
411 .slaves_cnt
= ARRAY_SIZE(omap44xx_mpu_private_slaves
),
412 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
420 static struct omap_hwmod_class omap44xx_mpu_hwmod_class
= {
425 static struct omap_hwmod_irq_info omap44xx_mpu_irqs
[] = {
426 { .name
= "pl310", .irq
= 0 + OMAP44XX_IRQ_GIC_START
},
427 { .name
= "cti0", .irq
= 1 + OMAP44XX_IRQ_GIC_START
},
428 { .name
= "cti1", .irq
= 2 + OMAP44XX_IRQ_GIC_START
},
431 /* mpu master ports */
432 static struct omap_hwmod_ocp_if
*omap44xx_mpu_masters
[] = {
433 &omap44xx_mpu__l3_main_1
,
434 &omap44xx_mpu__l4_abe
,
438 static struct omap_hwmod omap44xx_mpu_hwmod
= {
440 .class = &omap44xx_mpu_hwmod_class
,
441 .flags
= (HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
),
442 .mpu_irqs
= omap44xx_mpu_irqs
,
443 .mpu_irqs_cnt
= ARRAY_SIZE(omap44xx_mpu_irqs
),
444 .main_clk
= "dpll_mpu_m2_ck",
447 .clkctrl_reg
= OMAP4430_CM_MPU_MPU_CLKCTRL
,
450 .masters
= omap44xx_mpu_masters
,
451 .masters_cnt
= ARRAY_SIZE(omap44xx_mpu_masters
),
452 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
457 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
461 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc
= {
465 .sysc_flags
= (SYSC_HAS_SIDLEMODE
| SYSC_HAS_EMUFREE
|
467 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
468 .sysc_fields
= &omap_hwmod_sysc_type1
,
473 * universal asynchronous receiver/transmitter (uart)
476 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc
= {
480 .sysc_flags
= (SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
481 SYSC_HAS_SOFTRESET
| SYSC_HAS_AUTOIDLE
),
482 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
483 .sysc_fields
= &omap_hwmod_sysc_type1
,
486 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class
= {
488 .sysc
= &omap44xx_wd_timer_sysc
,
492 static struct omap_hwmod omap44xx_wd_timer2_hwmod
;
493 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs
[] = {
494 { .irq
= 80 + OMAP44XX_IRQ_GIC_START
},
497 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs
[] = {
499 .pa_start
= 0x4a314000,
500 .pa_end
= 0x4a31407f,
501 .flags
= ADDR_TYPE_RT
505 static struct omap_hwmod_class omap44xx_uart_hwmod_class
= {
507 .sysc
= &omap44xx_uart_sysc
,
511 static struct omap_hwmod omap44xx_uart1_hwmod
;
512 static struct omap_hwmod_irq_info omap44xx_uart1_irqs
[] = {
513 { .irq
= 72 + OMAP44XX_IRQ_GIC_START
},
516 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs
[] = {
517 { .name
= "tx", .dma_req
= 48 + OMAP44XX_DMA_REQ_START
},
518 { .name
= "rx", .dma_req
= 49 + OMAP44XX_DMA_REQ_START
},
521 static struct omap_hwmod_addr_space omap44xx_uart1_addrs
[] = {
523 .pa_start
= 0x4806a000,
524 .pa_end
= 0x4806a0ff,
525 .flags
= ADDR_TYPE_RT
529 /* l4_per -> uart1 */
530 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1
= {
531 .master
= &omap44xx_l4_per_hwmod
,
532 .slave
= &omap44xx_uart1_hwmod
,
534 .addr
= omap44xx_uart1_addrs
,
535 .addr_cnt
= ARRAY_SIZE(omap44xx_uart1_addrs
),
536 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
539 /* uart1 slave ports */
540 static struct omap_hwmod_ocp_if
*omap44xx_uart1_slaves
[] = {
541 &omap44xx_l4_per__uart1
,
544 static struct omap_hwmod omap44xx_uart1_hwmod
= {
546 .class = &omap44xx_uart_hwmod_class
,
547 .mpu_irqs
= omap44xx_uart1_irqs
,
548 .mpu_irqs_cnt
= ARRAY_SIZE(omap44xx_uart1_irqs
),
549 .sdma_reqs
= omap44xx_uart1_sdma_reqs
,
550 .sdma_reqs_cnt
= ARRAY_SIZE(omap44xx_uart1_sdma_reqs
),
551 .main_clk
= "uart1_fck",
554 .clkctrl_reg
= OMAP4430_CM_L4PER_UART1_CLKCTRL
,
557 .slaves
= omap44xx_uart1_slaves
,
558 .slaves_cnt
= ARRAY_SIZE(omap44xx_uart1_slaves
),
559 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
563 static struct omap_hwmod omap44xx_uart2_hwmod
;
564 static struct omap_hwmod_irq_info omap44xx_uart2_irqs
[] = {
565 { .irq
= 73 + OMAP44XX_IRQ_GIC_START
},
568 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs
[] = {
569 { .name
= "tx", .dma_req
= 50 + OMAP44XX_DMA_REQ_START
},
570 { .name
= "rx", .dma_req
= 51 + OMAP44XX_DMA_REQ_START
},
573 static struct omap_hwmod_addr_space omap44xx_uart2_addrs
[] = {
575 .pa_start
= 0x4806c000,
576 .pa_end
= 0x4806c0ff,
577 .flags
= ADDR_TYPE_RT
581 /* l4_wkup -> wd_timer2 */
582 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2
= {
583 .master
= &omap44xx_l4_wkup_hwmod
,
584 .slave
= &omap44xx_wd_timer2_hwmod
,
585 .clk
= "l4_wkup_clk_mux_ck",
586 .addr
= omap44xx_wd_timer2_addrs
,
587 .addr_cnt
= ARRAY_SIZE(omap44xx_wd_timer2_addrs
),
588 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
591 /* wd_timer2 slave ports */
592 static struct omap_hwmod_ocp_if
*omap44xx_wd_timer2_slaves
[] = {
593 &omap44xx_l4_wkup__wd_timer2
,
596 static struct omap_hwmod omap44xx_wd_timer2_hwmod
= {
598 .class = &omap44xx_wd_timer_hwmod_class
,
599 .mpu_irqs
= omap44xx_wd_timer2_irqs
,
600 .mpu_irqs_cnt
= ARRAY_SIZE(omap44xx_wd_timer2_irqs
),
601 .main_clk
= "wd_timer2_fck",
604 .clkctrl_reg
= OMAP4430_CM_WKUP_WDT2_CLKCTRL
,
607 .slaves
= omap44xx_wd_timer2_slaves
,
608 .slaves_cnt
= ARRAY_SIZE(omap44xx_wd_timer2_slaves
),
609 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
613 static struct omap_hwmod omap44xx_wd_timer3_hwmod
;
614 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs
[] = {
615 { .irq
= 36 + OMAP44XX_IRQ_GIC_START
},
618 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs
[] = {
620 .pa_start
= 0x40130000,
621 .pa_end
= 0x4013007f,
622 .flags
= ADDR_TYPE_RT
626 /* l4_per -> uart2 */
627 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2
= {
628 .master
= &omap44xx_l4_per_hwmod
,
629 .slave
= &omap44xx_uart2_hwmod
,
631 .addr
= omap44xx_uart2_addrs
,
632 .addr_cnt
= ARRAY_SIZE(omap44xx_uart2_addrs
),
633 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
636 /* uart2 slave ports */
637 static struct omap_hwmod_ocp_if
*omap44xx_uart2_slaves
[] = {
638 &omap44xx_l4_per__uart2
,
641 static struct omap_hwmod omap44xx_uart2_hwmod
= {
643 .class = &omap44xx_uart_hwmod_class
,
644 .mpu_irqs
= omap44xx_uart2_irqs
,
645 .mpu_irqs_cnt
= ARRAY_SIZE(omap44xx_uart2_irqs
),
646 .sdma_reqs
= omap44xx_uart2_sdma_reqs
,
647 .sdma_reqs_cnt
= ARRAY_SIZE(omap44xx_uart2_sdma_reqs
),
648 .main_clk
= "uart2_fck",
651 .clkctrl_reg
= OMAP4430_CM_L4PER_UART2_CLKCTRL
,
654 .slaves
= omap44xx_uart2_slaves
,
655 .slaves_cnt
= ARRAY_SIZE(omap44xx_uart2_slaves
),
656 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
660 static struct omap_hwmod omap44xx_uart3_hwmod
;
661 static struct omap_hwmod_irq_info omap44xx_uart3_irqs
[] = {
662 { .irq
= 74 + OMAP44XX_IRQ_GIC_START
},
665 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs
[] = {
666 { .name
= "tx", .dma_req
= 52 + OMAP44XX_DMA_REQ_START
},
667 { .name
= "rx", .dma_req
= 53 + OMAP44XX_DMA_REQ_START
},
670 static struct omap_hwmod_addr_space omap44xx_uart3_addrs
[] = {
672 .pa_start
= 0x48020000,
673 .pa_end
= 0x480200ff,
674 .flags
= ADDR_TYPE_RT
678 /* l4_abe -> wd_timer3 */
679 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3
= {
680 .master
= &omap44xx_l4_abe_hwmod
,
681 .slave
= &omap44xx_wd_timer3_hwmod
,
682 .clk
= "ocp_abe_iclk",
683 .addr
= omap44xx_wd_timer3_addrs
,
684 .addr_cnt
= ARRAY_SIZE(omap44xx_wd_timer3_addrs
),
685 .user
= OCP_USER_MPU
,
688 /* l4_abe -> wd_timer3 (dma) */
689 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs
[] = {
691 .pa_start
= 0x49030000,
692 .pa_end
= 0x4903007f,
693 .flags
= ADDR_TYPE_RT
697 /* l4_per -> uart3 */
698 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3
= {
699 .master
= &omap44xx_l4_per_hwmod
,
700 .slave
= &omap44xx_uart3_hwmod
,
702 .addr
= omap44xx_uart3_addrs
,
703 .addr_cnt
= ARRAY_SIZE(omap44xx_uart3_addrs
),
704 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
707 /* uart3 slave ports */
708 static struct omap_hwmod_ocp_if
*omap44xx_uart3_slaves
[] = {
709 &omap44xx_l4_per__uart3
,
712 static struct omap_hwmod omap44xx_uart3_hwmod
= {
714 .class = &omap44xx_uart_hwmod_class
,
715 .flags
= (HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
),
716 .mpu_irqs
= omap44xx_uart3_irqs
,
717 .mpu_irqs_cnt
= ARRAY_SIZE(omap44xx_uart3_irqs
),
718 .sdma_reqs
= omap44xx_uart3_sdma_reqs
,
719 .sdma_reqs_cnt
= ARRAY_SIZE(omap44xx_uart3_sdma_reqs
),
720 .main_clk
= "uart3_fck",
723 .clkctrl_reg
= OMAP4430_CM_L4PER_UART3_CLKCTRL
,
726 .slaves
= omap44xx_uart3_slaves
,
727 .slaves_cnt
= ARRAY_SIZE(omap44xx_uart3_slaves
),
728 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
732 static struct omap_hwmod omap44xx_uart4_hwmod
;
733 static struct omap_hwmod_irq_info omap44xx_uart4_irqs
[] = {
734 { .irq
= 70 + OMAP44XX_IRQ_GIC_START
},
737 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs
[] = {
738 { .name
= "tx", .dma_req
= 54 + OMAP44XX_DMA_REQ_START
},
739 { .name
= "rx", .dma_req
= 55 + OMAP44XX_DMA_REQ_START
},
742 static struct omap_hwmod_addr_space omap44xx_uart4_addrs
[] = {
744 .pa_start
= 0x4806e000,
745 .pa_end
= 0x4806e0ff,
746 .flags
= ADDR_TYPE_RT
750 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma
= {
751 .master
= &omap44xx_l4_abe_hwmod
,
752 .slave
= &omap44xx_wd_timer3_hwmod
,
753 .clk
= "ocp_abe_iclk",
754 .addr
= omap44xx_wd_timer3_dma_addrs
,
755 .addr_cnt
= ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs
),
756 .user
= OCP_USER_SDMA
,
759 /* wd_timer3 slave ports */
760 static struct omap_hwmod_ocp_if
*omap44xx_wd_timer3_slaves
[] = {
761 &omap44xx_l4_abe__wd_timer3
,
762 &omap44xx_l4_abe__wd_timer3_dma
,
765 static struct omap_hwmod omap44xx_wd_timer3_hwmod
= {
767 .class = &omap44xx_wd_timer_hwmod_class
,
768 .mpu_irqs
= omap44xx_wd_timer3_irqs
,
769 .mpu_irqs_cnt
= ARRAY_SIZE(omap44xx_wd_timer3_irqs
),
770 .main_clk
= "wd_timer3_fck",
773 .clkctrl_reg
= OMAP4430_CM1_ABE_WDT3_CLKCTRL
,
776 .slaves
= omap44xx_wd_timer3_slaves
,
777 .slaves_cnt
= ARRAY_SIZE(omap44xx_wd_timer3_slaves
),
778 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
781 /* l4_per -> uart4 */
782 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4
= {
783 .master
= &omap44xx_l4_per_hwmod
,
784 .slave
= &omap44xx_uart4_hwmod
,
786 .addr
= omap44xx_uart4_addrs
,
787 .addr_cnt
= ARRAY_SIZE(omap44xx_uart4_addrs
),
788 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
791 /* uart4 slave ports */
792 static struct omap_hwmod_ocp_if
*omap44xx_uart4_slaves
[] = {
793 &omap44xx_l4_per__uart4
,
796 static struct omap_hwmod omap44xx_uart4_hwmod
= {
798 .class = &omap44xx_uart_hwmod_class
,
799 .mpu_irqs
= omap44xx_uart4_irqs
,
800 .mpu_irqs_cnt
= ARRAY_SIZE(omap44xx_uart4_irqs
),
801 .sdma_reqs
= omap44xx_uart4_sdma_reqs
,
802 .sdma_reqs_cnt
= ARRAY_SIZE(omap44xx_uart4_sdma_reqs
),
803 .main_clk
= "uart4_fck",
806 .clkctrl_reg
= OMAP4430_CM_L4PER_UART4_CLKCTRL
,
809 .slaves
= omap44xx_uart4_slaves
,
810 .slaves_cnt
= ARRAY_SIZE(omap44xx_uart4_slaves
),
811 .omap_chip
= OMAP_CHIP_INIT(CHIP_IS_OMAP4430
),
814 static __initdata
struct omap_hwmod
*omap44xx_hwmods
[] = {
818 &omap44xx_emif_fw_hwmod
,
820 &omap44xx_l3_instr_hwmod
,
821 &omap44xx_l3_main_1_hwmod
,
822 &omap44xx_l3_main_2_hwmod
,
823 &omap44xx_l3_main_3_hwmod
,
825 &omap44xx_l4_abe_hwmod
,
826 &omap44xx_l4_cfg_hwmod
,
827 &omap44xx_l4_per_hwmod
,
828 &omap44xx_l4_wkup_hwmod
,
830 &omap44xx_mpu_private_hwmod
,
835 &omap44xx_wd_timer2_hwmod
,
836 &omap44xx_wd_timer3_hwmod
,
839 &omap44xx_uart1_hwmod
,
840 &omap44xx_uart2_hwmod
,
841 &omap44xx_uart3_hwmod
,
842 &omap44xx_uart4_hwmod
,
846 int __init
omap44xx_hwmod_init(void)
848 return omap_hwmod_init(omap44xx_hwmods
);