2 * linux/arch/arm/mach-omap2/io.c
4 * OMAP2 I/O mapping code
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
24 #include <linux/clk.h>
25 #include <linux/omapfb.h>
29 #include <asm/mach/map.h>
31 #include <plat/sram.h>
32 #include <plat/sdrc.h>
33 #include <plat/gpmc.h>
34 #include <plat/serial.h>
36 #include "clock2xxx.h"
37 #include "clock3xxx.h"
38 #include "clock44xx.h"
41 #include <plat/omap-pm.h>
42 #include <plat/powerdomain.h>
43 #include "powerdomains.h"
45 #include <plat/clockdomain.h>
46 #include "clockdomains.h"
48 #include <plat/omap_hwmod.h>
51 * The machine specific code may provide the extra mapping besides the
52 * default mapping provided here.
55 #ifdef CONFIG_ARCH_OMAP2
56 static struct map_desc omap24xx_io_desc
[] __initdata
= {
58 .virtual = L3_24XX_VIRT
,
59 .pfn
= __phys_to_pfn(L3_24XX_PHYS
),
60 .length
= L3_24XX_SIZE
,
64 .virtual = L4_24XX_VIRT
,
65 .pfn
= __phys_to_pfn(L4_24XX_PHYS
),
66 .length
= L4_24XX_SIZE
,
71 #ifdef CONFIG_ARCH_OMAP2420
72 static struct map_desc omap242x_io_desc
[] __initdata
= {
74 .virtual = DSP_MEM_2420_VIRT
,
75 .pfn
= __phys_to_pfn(DSP_MEM_2420_PHYS
),
76 .length
= DSP_MEM_2420_SIZE
,
80 .virtual = DSP_IPI_2420_VIRT
,
81 .pfn
= __phys_to_pfn(DSP_IPI_2420_PHYS
),
82 .length
= DSP_IPI_2420_SIZE
,
86 .virtual = DSP_MMU_2420_VIRT
,
87 .pfn
= __phys_to_pfn(DSP_MMU_2420_PHYS
),
88 .length
= DSP_MMU_2420_SIZE
,
95 #ifdef CONFIG_ARCH_OMAP2430
96 static struct map_desc omap243x_io_desc
[] __initdata
= {
98 .virtual = L4_WK_243X_VIRT
,
99 .pfn
= __phys_to_pfn(L4_WK_243X_PHYS
),
100 .length
= L4_WK_243X_SIZE
,
104 .virtual = OMAP243X_GPMC_VIRT
,
105 .pfn
= __phys_to_pfn(OMAP243X_GPMC_PHYS
),
106 .length
= OMAP243X_GPMC_SIZE
,
110 .virtual = OMAP243X_SDRC_VIRT
,
111 .pfn
= __phys_to_pfn(OMAP243X_SDRC_PHYS
),
112 .length
= OMAP243X_SDRC_SIZE
,
116 .virtual = OMAP243X_SMS_VIRT
,
117 .pfn
= __phys_to_pfn(OMAP243X_SMS_PHYS
),
118 .length
= OMAP243X_SMS_SIZE
,
125 #ifdef CONFIG_ARCH_OMAP3
126 static struct map_desc omap34xx_io_desc
[] __initdata
= {
128 .virtual = L3_34XX_VIRT
,
129 .pfn
= __phys_to_pfn(L3_34XX_PHYS
),
130 .length
= L3_34XX_SIZE
,
134 .virtual = L4_34XX_VIRT
,
135 .pfn
= __phys_to_pfn(L4_34XX_PHYS
),
136 .length
= L4_34XX_SIZE
,
140 .virtual = OMAP34XX_GPMC_VIRT
,
141 .pfn
= __phys_to_pfn(OMAP34XX_GPMC_PHYS
),
142 .length
= OMAP34XX_GPMC_SIZE
,
146 .virtual = OMAP343X_SMS_VIRT
,
147 .pfn
= __phys_to_pfn(OMAP343X_SMS_PHYS
),
148 .length
= OMAP343X_SMS_SIZE
,
152 .virtual = OMAP343X_SDRC_VIRT
,
153 .pfn
= __phys_to_pfn(OMAP343X_SDRC_PHYS
),
154 .length
= OMAP343X_SDRC_SIZE
,
158 .virtual = L4_PER_34XX_VIRT
,
159 .pfn
= __phys_to_pfn(L4_PER_34XX_PHYS
),
160 .length
= L4_PER_34XX_SIZE
,
164 .virtual = L4_EMU_34XX_VIRT
,
165 .pfn
= __phys_to_pfn(L4_EMU_34XX_PHYS
),
166 .length
= L4_EMU_34XX_SIZE
,
169 #if defined(CONFIG_DEBUG_LL) && \
170 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
172 .virtual = ZOOM_UART_VIRT
,
173 .pfn
= __phys_to_pfn(ZOOM_UART_BASE
),
180 #ifdef CONFIG_ARCH_OMAP4
181 static struct map_desc omap44xx_io_desc
[] __initdata
= {
183 .virtual = L3_44XX_VIRT
,
184 .pfn
= __phys_to_pfn(L3_44XX_PHYS
),
185 .length
= L3_44XX_SIZE
,
189 .virtual = L4_44XX_VIRT
,
190 .pfn
= __phys_to_pfn(L4_44XX_PHYS
),
191 .length
= L4_44XX_SIZE
,
195 .virtual = OMAP44XX_GPMC_VIRT
,
196 .pfn
= __phys_to_pfn(OMAP44XX_GPMC_PHYS
),
197 .length
= OMAP44XX_GPMC_SIZE
,
201 .virtual = OMAP44XX_EMIF1_VIRT
,
202 .pfn
= __phys_to_pfn(OMAP44XX_EMIF1_PHYS
),
203 .length
= OMAP44XX_EMIF1_SIZE
,
207 .virtual = OMAP44XX_EMIF2_VIRT
,
208 .pfn
= __phys_to_pfn(OMAP44XX_EMIF2_PHYS
),
209 .length
= OMAP44XX_EMIF2_SIZE
,
213 .virtual = OMAP44XX_DMM_VIRT
,
214 .pfn
= __phys_to_pfn(OMAP44XX_DMM_PHYS
),
215 .length
= OMAP44XX_DMM_SIZE
,
219 .virtual = L4_PER_44XX_VIRT
,
220 .pfn
= __phys_to_pfn(L4_PER_44XX_PHYS
),
221 .length
= L4_PER_44XX_SIZE
,
225 .virtual = L4_EMU_44XX_VIRT
,
226 .pfn
= __phys_to_pfn(L4_EMU_44XX_PHYS
),
227 .length
= L4_EMU_44XX_SIZE
,
233 static void __init
_omap2_map_common_io(void)
235 /* Normally devicemaps_init() would flush caches and tlb after
236 * mdesc->map_io(), but we must also do it here because of the CPU
237 * revision check below.
239 local_flush_tlb_all();
242 omap2_check_revision();
246 #ifdef CONFIG_ARCH_OMAP2420
247 void __init
omap242x_map_common_io(void)
249 iotable_init(omap24xx_io_desc
, ARRAY_SIZE(omap24xx_io_desc
));
250 iotable_init(omap242x_io_desc
, ARRAY_SIZE(omap242x_io_desc
));
251 _omap2_map_common_io();
255 #ifdef CONFIG_ARCH_OMAP2430
256 void __init
omap243x_map_common_io(void)
258 iotable_init(omap24xx_io_desc
, ARRAY_SIZE(omap24xx_io_desc
));
259 iotable_init(omap243x_io_desc
, ARRAY_SIZE(omap243x_io_desc
));
260 _omap2_map_common_io();
264 #ifdef CONFIG_ARCH_OMAP3
265 void __init
omap34xx_map_common_io(void)
267 iotable_init(omap34xx_io_desc
, ARRAY_SIZE(omap34xx_io_desc
));
268 _omap2_map_common_io();
272 #ifdef CONFIG_ARCH_OMAP4
273 void __init
omap44xx_map_common_io(void)
275 iotable_init(omap44xx_io_desc
, ARRAY_SIZE(omap44xx_io_desc
));
276 _omap2_map_common_io();
281 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
283 * Sets the CORE DPLL3 M2 divider to the same value that it's at
284 * currently. This has the effect of setting the SDRC SDRAM AC timing
285 * registers to the values currently defined by the kernel. Currently
286 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
287 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
288 * or passes along the return value of clk_set_rate().
290 static int __init
_omap2_init_reprogram_sdrc(void)
292 struct clk
*dpll3_m2_ck
;
296 if (!cpu_is_omap34xx())
299 dpll3_m2_ck
= clk_get(NULL
, "dpll3_m2_ck");
300 if (IS_ERR(dpll3_m2_ck
))
303 rate
= clk_get_rate(dpll3_m2_ck
);
304 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate
);
305 v
= clk_set_rate(dpll3_m2_ck
, rate
);
307 pr_err("dpll3_m2_clk rate change failed: %d\n", v
);
309 clk_put(dpll3_m2_ck
);
314 void __init
omap2_init_common_hw(struct omap_sdrc_params
*sdrc_cs0
,
315 struct omap_sdrc_params
*sdrc_cs1
)
317 u8 skip_setup_idle
= 0;
319 pwrdm_init(powerdomains_omap
);
320 clkdm_init(clockdomains_omap
, clkdm_autodeps
);
321 if (cpu_is_omap242x())
322 omap2420_hwmod_init();
323 else if (cpu_is_omap243x())
324 omap2430_hwmod_init();
325 else if (cpu_is_omap34xx())
326 omap3xxx_hwmod_init();
327 else if (cpu_is_omap44xx())
328 omap44xx_hwmod_init();
330 /* The OPP tables have to be registered before a clk init */
331 omap_pm_if_early_init(mpu_opps
, dsp_opps
, l3_opps
);
333 if (cpu_is_omap2420())
335 else if (cpu_is_omap2430())
337 else if (cpu_is_omap34xx())
339 else if (cpu_is_omap44xx())
342 pr_err("Could not init clock framework - unknown CPU\n");
344 omap_serial_early_init();
346 #ifndef CONFIG_PM_RUNTIME
349 omap_hwmod_late_init(skip_setup_idle
);
350 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
351 omap2_sdrc_init(sdrc_cs0
, sdrc_cs1
);
352 _omap2_init_reprogram_sdrc();