arch/arm/mach-omap2/clock2430_data.c

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock2430_data.c
   3  *
   4  *  Copyright (C) 2005-2009 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2010 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/clk.h>
  18 #include <linux/list.h>
  19
  20 #include <plat/clkdev_omap.h>
  21
  22 #include "clock.h"
  23 #include "clock2xxx.h"
  24 #include "opp2xxx.h"
  25 #include "prm.h"
  26 #include "cm.h"
  27 #include "prm-regbits-24xx.h"
  28 #include "cm-regbits-24xx.h"
  29 #include "sdrc.h"
  30 #include "control.h"
  31
  32 #define OMAP_CM_REGADDR                 OMAP2430_CM_REGADDR
  33
  34 /*
  35  * 2430 clock tree.
  36  *
  37  * NOTE:In many cases here we are assigning a 'default' parent. In many
  38  *      cases the parent is selectable. The get/set parent calls will also
  39  *      switch sources.
  40  *
  41  *      Many some clocks say always_enabled, but they can be auto idled for
  42  *      power savings. They will always be available upon clock request.
  43  *
  44  *      Several sources are given initial rates which may be wrong, this will
  45  *      be fixed up in the init func.
  46  *
  47  *      Things are broadly separated below by clock domains. It is
  48  *      noteworthy that most periferals have dependencies on multiple clock
  49  *      domains. Many get their interface clocks from the L4 domain, but get
  50  *      functional clocks from fixed sources or other core domain derived
  51  *      clocks.
  52  */
  53
  54 /* Base external input clocks */
  55 static struct clk func_32k_ck = {
  56         .name           = "func_32k_ck",
  57         .ops            = &clkops_null,
  58         .rate           = 32000,
  59         .clkdm_name     = "wkup_clkdm",
  60 };
  61
  62 static struct clk secure_32k_ck = {
  63         .name           = "secure_32k_ck",
  64         .ops            = &clkops_null,
  65         .rate           = 32768,
  66         .clkdm_name     = "wkup_clkdm",
  67 };
  68
  69 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
  70 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
  71         .name           = "osc_ck",
  72         .ops            = &clkops_oscck,
  73         .clkdm_name     = "wkup_clkdm",
  74         .recalc         = &omap2_osc_clk_recalc,
  75 };
  76
  77 /* Without modem likely 12MHz, with modem likely 13MHz */
  78 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
  79         .name           = "sys_ck",             /* ~ ref_clk also */
  80         .ops            = &clkops_null,
  81         .parent         = &osc_ck,
  82         .clkdm_name     = "wkup_clkdm",
  83         .recalc         = &omap2xxx_sys_clk_recalc,
  84 };
  85
  86 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
  87         .name           = "alt_ck",
  88         .ops            = &clkops_null,
  89         .rate           = 54000000,
  90         .clkdm_name     = "wkup_clkdm",
  91 };
  92
  93 /* Optional external clock input for McBSP CLKS */
  94 static struct clk mcbsp_clks = {
  95         .name           = "mcbsp_clks",
  96         .ops            = &clkops_null,
  97 };
  98
  99 /*
 100  * Analog domain root source clocks
 101  */
 102
 103 /* dpll_ck, is broken out in to special cases through clksel */
 104 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 105  * deal with this
 106  */
 107
 108 static struct dpll_data dpll_dd = {
 109         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 110         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 111         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 112         .clk_bypass             = &sys_ck,
 113         .clk_ref                = &sys_ck,
 114         .control_reg            = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 115         .enable_mask            = OMAP24XX_EN_DPLL_MASK,
 116         .max_multiplier         = 1023,
 117         .min_divider            = 1,
 118         .max_divider            = 16,
 119         .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 120 };
 121
 122 /*
 123  * XXX Cannot add round_rate here yet, as this is still a composite clock,
 124  * not just a DPLL
 125  */
 126 static struct clk dpll_ck = {
 127         .name           = "dpll_ck",
 128         .ops            = &clkops_null,
 129         .parent         = &sys_ck,              /* Can be func_32k also */
 130         .dpll_data      = &dpll_dd,
 131         .clkdm_name     = "wkup_clkdm",
 132         .recalc         = &omap2_dpllcore_recalc,
 133         .set_rate       = &omap2_reprogram_dpllcore,
 134 };
 135
 136 static struct clk apll96_ck = {
 137         .name           = "apll96_ck",
 138         .ops            = &clkops_apll96,
 139         .parent         = &sys_ck,
 140         .rate           = 96000000,
 141         .flags          = ENABLE_ON_INIT,
 142         .clkdm_name     = "wkup_clkdm",
 143         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 144         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 145 };
 146
 147 static struct clk apll54_ck = {
 148         .name           = "apll54_ck",
 149         .ops            = &clkops_apll54,
 150         .parent         = &sys_ck,
 151         .rate           = 54000000,
 152         .flags          = ENABLE_ON_INIT,
 153         .clkdm_name     = "wkup_clkdm",
 154         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 155         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 156 };
 157
 158 /*
 159  * PRCM digital base sources
 160  */
 161
 162 /* func_54m_ck */
 163
 164 static const struct clksel_rate func_54m_apll54_rates[] = {
 165         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 166         { .div = 0 },
 167 };
 168
 169 static const struct clksel_rate func_54m_alt_rates[] = {
 170         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 171         { .div = 0 },
 172 };
 173
 174 static const struct clksel func_54m_clksel[] = {
 175         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 176         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 177         { .parent = NULL },
 178 };
 179
 180 static struct clk func_54m_ck = {
 181         .name           = "func_54m_ck",
 182         .ops            = &clkops_null,
 183         .parent         = &apll54_ck,   /* can also be alt_clk */
 184         .clkdm_name     = "wkup_clkdm",
 185         .init           = &omap2_init_clksel_parent,
 186         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 187         .clksel_mask    = OMAP24XX_54M_SOURCE_MASK,
 188         .clksel         = func_54m_clksel,
 189         .recalc         = &omap2_clksel_recalc,
 190 };
 191
 192 static struct clk core_ck = {
 193         .name           = "core_ck",
 194         .ops            = &clkops_null,
 195         .parent         = &dpll_ck,             /* can also be 32k */
 196         .clkdm_name     = "wkup_clkdm",
 197         .recalc         = &followparent_recalc,
 198 };
 199
 200 /* func_96m_ck */
 201 static const struct clksel_rate func_96m_apll96_rates[] = {
 202         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 203         { .div = 0 },
 204 };
 205
 206 static const struct clksel_rate func_96m_alt_rates[] = {
 207         { .div = 1, .val = 1, .flags = RATE_IN_243X },
 208         { .div = 0 },
 209 };
 210
 211 static const struct clksel func_96m_clksel[] = {
 212         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 213         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 214         { .parent = NULL }
 215 };
 216
 217 static struct clk func_96m_ck = {
 218         .name           = "func_96m_ck",
 219         .ops            = &clkops_null,
 220         .parent         = &apll96_ck,
 221         .clkdm_name     = "wkup_clkdm",
 222         .init           = &omap2_init_clksel_parent,
 223         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 224         .clksel_mask    = OMAP2430_96M_SOURCE_MASK,
 225         .clksel         = func_96m_clksel,
 226         .recalc         = &omap2_clksel_recalc,
 227 };
 228
 229 /* func_48m_ck */
 230
 231 static const struct clksel_rate func_48m_apll96_rates[] = {
 232         { .div = 2, .val = 0, .flags = RATE_IN_24XX },
 233         { .div = 0 },
 234 };
 235
 236 static const struct clksel_rate func_48m_alt_rates[] = {
 237         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 238         { .div = 0 },
 239 };
 240
 241 static const struct clksel func_48m_clksel[] = {
 242         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 243         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 244         { .parent = NULL }
 245 };
 246
 247 static struct clk func_48m_ck = {
 248         .name           = "func_48m_ck",
 249         .ops            = &clkops_null,
 250         .parent         = &apll96_ck,    /* 96M or Alt */
 251         .clkdm_name     = "wkup_clkdm",
 252         .init           = &omap2_init_clksel_parent,
 253         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 254         .clksel_mask    = OMAP24XX_48M_SOURCE_MASK,
 255         .clksel         = func_48m_clksel,
 256         .recalc         = &omap2_clksel_recalc,
 257         .round_rate     = &omap2_clksel_round_rate,
 258         .set_rate       = &omap2_clksel_set_rate
 259 };
 260
 261 static struct clk func_12m_ck = {
 262         .name           = "func_12m_ck",
 263         .ops            = &clkops_null,
 264         .parent         = &func_48m_ck,
 265         .fixed_div      = 4,
 266         .clkdm_name     = "wkup_clkdm",
 267         .recalc         = &omap_fixed_divisor_recalc,
 268 };
 269
 270 /* Secure timer, only available in secure mode */
 271 static struct clk wdt1_osc_ck = {
 272         .name           = "ck_wdt1_osc",
 273         .ops            = &clkops_null, /* RMK: missing? */
 274         .parent         = &osc_ck,
 275         .recalc         = &followparent_recalc,
 276 };
 277
 278 /*
 279  * The common_clkout* clksel_rate structs are common to
 280  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 281  * sys_clkout2_* are 2420-only, so the
 282  * clksel_rate flags fields are inaccurate for those clocks. This is
 283  * harmless since access to those clocks are gated by the struct clk
 284  * flags fields, which mark them as 2420-only.
 285  */
 286 static const struct clksel_rate common_clkout_src_core_rates[] = {
 287         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 288         { .div = 0 }
 289 };
 290
 291 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 292         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 293         { .div = 0 }
 294 };
 295
 296 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 297         { .div = 1, .val = 2, .flags = RATE_IN_24XX },
 298         { .div = 0 }
 299 };
 300
 301 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 302         { .div = 1, .val = 3, .flags = RATE_IN_24XX },
 303         { .div = 0 }
 304 };
 305
 306 static const struct clksel common_clkout_src_clksel[] = {
 307         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 308         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 309         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 310         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 311         { .parent = NULL }
 312 };
 313
 314 static struct clk sys_clkout_src = {
 315         .name           = "sys_clkout_src",
 316         .ops            = &clkops_omap2_dflt,
 317         .parent         = &func_54m_ck,
 318         .clkdm_name     = "wkup_clkdm",
 319         .enable_reg     = OMAP2430_PRCM_CLKOUT_CTRL,
 320         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 321         .init           = &omap2_init_clksel_parent,
 322         .clksel_reg     = OMAP2430_PRCM_CLKOUT_CTRL,
 323         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 324         .clksel         = common_clkout_src_clksel,
 325         .recalc         = &omap2_clksel_recalc,
 326         .round_rate     = &omap2_clksel_round_rate,
 327         .set_rate       = &omap2_clksel_set_rate
 328 };
 329
 330 static const struct clksel_rate common_clkout_rates[] = {
 331         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 332         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 333         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 334         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 335         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 336         { .div = 0 },
 337 };
 338
 339 static const struct clksel sys_clkout_clksel[] = {
 340         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 341         { .parent = NULL }
 342 };
 343
 344 static struct clk sys_clkout = {
 345         .name           = "sys_clkout",
 346         .ops            = &clkops_null,
 347         .parent         = &sys_clkout_src,
 348         .clkdm_name     = "wkup_clkdm",
 349         .clksel_reg     = OMAP2430_PRCM_CLKOUT_CTRL,
 350         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 351         .clksel         = sys_clkout_clksel,
 352         .recalc         = &omap2_clksel_recalc,
 353         .round_rate     = &omap2_clksel_round_rate,
 354         .set_rate       = &omap2_clksel_set_rate
 355 };
 356
 357 static struct clk emul_ck = {
 358         .name           = "emul_ck",
 359         .ops            = &clkops_omap2_dflt,
 360         .parent         = &func_54m_ck,
 361         .clkdm_name     = "wkup_clkdm",
 362         .enable_reg     = OMAP2430_PRCM_CLKEMUL_CTRL,
 363         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 364         .recalc         = &followparent_recalc,
 365
 366 };
 367
 368 /*
 369  * MPU clock domain
 370  *      Clocks:
 371  *              MPU_FCLK, MPU_ICLK
 372  *              INT_M_FCLK, INT_M_I_CLK
 373  *
 374  * - Individual clocks are hardware managed.
 375  * - Base divider comes from: CM_CLKSEL_MPU
 376  *
 377  */
 378 static const struct clksel_rate mpu_core_rates[] = {
 379         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 380         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 381         { .div = 0 },
 382 };
 383
 384 static const struct clksel mpu_clksel[] = {
 385         { .parent = &core_ck, .rates = mpu_core_rates },
 386         { .parent = NULL }
 387 };
 388
 389 static struct clk mpu_ck = {    /* Control cpu */
 390         .name           = "mpu_ck",
 391         .ops            = &clkops_null,
 392         .parent         = &core_ck,
 393         .clkdm_name     = "mpu_clkdm",
 394         .init           = &omap2_init_clksel_parent,
 395         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
 396         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
 397         .clksel         = mpu_clksel,
 398         .recalc         = &omap2_clksel_recalc,
 399 };
 400
 401 /*
 402  * DSP (2430-IVA2.1) clock domain
 403  * Clocks:
 404  *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
 405  *
 406  * Won't be too specific here. The core clock comes into this block
 407  * it is divided then tee'ed. One branch goes directly to xyz enable
 408  * controls. The other branch gets further divided by 2 then possibly
 409  * routed into a synchronizer and out of clocks abc.
 410  */
 411 static const struct clksel_rate dsp_fck_core_rates[] = {
 412         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 413         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 414         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 415         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 416         { .div = 0 },
 417 };
 418
 419 static const struct clksel dsp_fck_clksel[] = {
 420         { .parent = &core_ck, .rates = dsp_fck_core_rates },
 421         { .parent = NULL }
 422 };
 423
 424 static struct clk dsp_fck = {
 425         .name           = "dsp_fck",
 426         .ops            = &clkops_omap2_dflt_wait,
 427         .parent         = &core_ck,
 428         .clkdm_name     = "dsp_clkdm",
 429         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
 430         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 431         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 432         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
 433         .clksel         = dsp_fck_clksel,
 434         .recalc         = &omap2_clksel_recalc,
 435 };
 436
 437 /* DSP interface clock */
 438 static const struct clksel_rate dsp_irate_ick_rates[] = {
 439         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 440         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 441         { .div = 3, .val = 3, .flags = RATE_IN_243X },
 442         { .div = 0 },
 443 };
 444
 445 static const struct clksel dsp_irate_ick_clksel[] = {
 446         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
 447         { .parent = NULL }
 448 };
 449
 450 /* This clock does not exist as such in the TRM. */
 451 static struct clk dsp_irate_ick = {
 452         .name           = "dsp_irate_ick",
 453         .ops            = &clkops_null,
 454         .parent         = &dsp_fck,
 455         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 456         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
 457         .clksel         = dsp_irate_ick_clksel,
 458         .recalc         = &omap2_clksel_recalc,
 459 };
 460
 461 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
 462 static struct clk iva2_1_ick = {
 463         .name           = "iva2_1_ick",
 464         .ops            = &clkops_omap2_dflt_wait,
 465         .parent         = &dsp_irate_ick,
 466         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
 467         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 468 };
 469
 470 /*
 471  * L3 clock domain
 472  * L3 clocks are used for both interface and functional clocks to
 473  * multiple entities. Some of these clocks are completely managed
 474  * by hardware, and some others allow software control. Hardware
 475  * managed ones general are based on directly CLK_REQ signals and
 476  * various auto idle settings. The functional spec sets many of these
 477  * as 'tie-high' for their enables.
 478  *
 479  * I-CLOCKS:
 480  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
 481  *      CAM, HS-USB.
 482  * F-CLOCK
 483  *      SSI.
 484  *
 485  * GPMC memories and SDRC have timing and clock sensitive registers which
 486  * may very well need notification when the clock changes. Currently for low
 487  * operating points, these are taken care of in sleep.S.
 488  */
 489 static const struct clksel_rate core_l3_core_rates[] = {
 490         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 491         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 492         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
 493         { .div = 0 }
 494 };
 495
 496 static const struct clksel core_l3_clksel[] = {
 497         { .parent = &core_ck, .rates = core_l3_core_rates },
 498         { .parent = NULL }
 499 };
 500
 501 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
 502         .name           = "core_l3_ck",
 503         .ops            = &clkops_null,
 504         .parent         = &core_ck,
 505         .clkdm_name     = "core_l3_clkdm",
 506         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 507         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
 508         .clksel         = core_l3_clksel,
 509         .recalc         = &omap2_clksel_recalc,
 510 };
 511
 512 /* usb_l4_ick */
 513 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
 514         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 515         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 516         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 517         { .div = 0 }
 518 };
 519
 520 static const struct clksel usb_l4_ick_clksel[] = {
 521         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
 522         { .parent = NULL },
 523 };
 524
 525 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
 526 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
 527         .name           = "usb_l4_ick",
 528         .ops            = &clkops_omap2_dflt_wait,
 529         .parent         = &core_l3_ck,
 530         .clkdm_name     = "core_l4_clkdm",
 531         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 532         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
 533         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 534         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
 535         .clksel         = usb_l4_ick_clksel,
 536         .recalc         = &omap2_clksel_recalc,
 537 };
 538
 539 /*
 540  * L4 clock management domain
 541  *
 542  * This domain contains lots of interface clocks from the L4 interface, some
 543  * functional clocks.   Fixed APLL functional source clocks are managed in
 544  * this domain.
 545  */
 546 static const struct clksel_rate l4_core_l3_rates[] = {
 547         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 548         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 549         { .div = 0 }
 550 };
 551
 552 static const struct clksel l4_clksel[] = {
 553         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
 554         { .parent = NULL }
 555 };
 556
 557 static struct clk l4_ck = {             /* used both as an ick and fck */
 558         .name           = "l4_ck",
 559         .ops            = &clkops_null,
 560         .parent         = &core_l3_ck,
 561         .clkdm_name     = "core_l4_clkdm",
 562         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 563         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
 564         .clksel         = l4_clksel,
 565         .recalc         = &omap2_clksel_recalc,
 566 };
 567
 568 /*
 569  * SSI is in L3 management domain, its direct parent is core not l3,
 570  * many core power domain entities are grouped into the L3 clock
 571  * domain.
 572  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
 573  *
 574  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
 575  */
 576 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
 577         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 578         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 579         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 580         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 581         { .div = 5, .val = 5, .flags = RATE_IN_243X },
 582         { .div = 0 }
 583 };
 584
 585 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
 586         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
 587         { .parent = NULL }
 588 };
 589
 590 static struct clk ssi_ssr_sst_fck = {
 591         .name           = "ssi_fck",
 592         .ops            = &clkops_omap2_dflt_wait,
 593         .parent         = &core_ck,
 594         .clkdm_name     = "core_l3_clkdm",
 595         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 596         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
 597         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 598         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
 599         .clksel         = ssi_ssr_sst_fck_clksel,
 600         .recalc         = &omap2_clksel_recalc,
 601 };
 602
 603 /*
 604  * Presumably this is the same as SSI_ICLK.
 605  * TRM contradicts itself on what clockdomain SSI_ICLK is in
 606  */
 607 static struct clk ssi_l4_ick = {
 608         .name           = "ssi_l4_ick",
 609         .ops            = &clkops_omap2_dflt_wait,
 610         .parent         = &l4_ck,
 611         .clkdm_name     = "core_l4_clkdm",
 612         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 613         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
 614         .recalc         = &followparent_recalc,
 615 };
 616
 617
 618 /*
 619  * GFX clock domain
 620  *      Clocks:
 621  * GFX_FCLK, GFX_ICLK
 622  * GFX_CG1(2d), GFX_CG2(3d)
 623  *
 624  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
 625  * The 2d and 3d clocks run at a hardware determined
 626  * divided value of fclk.
 627  *
 628  */
 629
 630 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
 631 static const struct clksel gfx_fck_clksel[] = {
 632         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
 633         { .parent = NULL },
 634 };
 635
 636 static struct clk gfx_3d_fck = {
 637         .name           = "gfx_3d_fck",
 638         .ops            = &clkops_omap2_dflt_wait,
 639         .parent         = &core_l3_ck,
 640         .clkdm_name     = "gfx_clkdm",
 641         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 642         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
 643         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
 644         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
 645         .clksel         = gfx_fck_clksel,
 646         .recalc         = &omap2_clksel_recalc,
 647         .round_rate     = &omap2_clksel_round_rate,
 648         .set_rate       = &omap2_clksel_set_rate
 649 };
 650
 651 static struct clk gfx_2d_fck = {
 652         .name           = "gfx_2d_fck",
 653         .ops            = &clkops_omap2_dflt_wait,
 654         .parent         = &core_l3_ck,
 655         .clkdm_name     = "gfx_clkdm",
 656         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 657         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
 658         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
 659         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
 660         .clksel         = gfx_fck_clksel,
 661         .recalc         = &omap2_clksel_recalc,
 662 };
 663
 664 static struct clk gfx_ick = {
 665         .name           = "gfx_ick",            /* From l3 */
 666         .ops            = &clkops_omap2_dflt_wait,
 667         .parent         = &core_l3_ck,
 668         .clkdm_name     = "gfx_clkdm",
 669         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
 670         .enable_bit     = OMAP_EN_GFX_SHIFT,
 671         .recalc         = &followparent_recalc,
 672 };
 673
 674 /*
 675  * Modem clock domain (2430)
 676  *      CLOCKS:
 677  *              MDM_OSC_CLK
 678  *              MDM_ICLK
 679  * These clocks are usable in chassis mode only.
 680  */
 681 static const struct clksel_rate mdm_ick_core_rates[] = {
 682         { .div = 1, .val = 1, .flags = RATE_IN_243X },
 683         { .div = 4, .val = 4, .flags = RATE_IN_243X },
 684         { .div = 6, .val = 6, .flags = RATE_IN_243X },
 685         { .div = 9, .val = 9, .flags = RATE_IN_243X },
 686         { .div = 0 }
 687 };
 688
 689 static const struct clksel mdm_ick_clksel[] = {
 690         { .parent = &core_ck, .rates = mdm_ick_core_rates },
 691         { .parent = NULL }
 692 };
 693
 694 static struct clk mdm_ick = {           /* used both as a ick and fck */
 695         .name           = "mdm_ick",
 696         .ops            = &clkops_omap2_dflt_wait,
 697         .parent         = &core_ck,
 698         .clkdm_name     = "mdm_clkdm",
 699         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
 700         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
 701         .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
 702         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
 703         .clksel         = mdm_ick_clksel,
 704         .recalc         = &omap2_clksel_recalc,
 705 };
 706
 707 static struct clk mdm_osc_ck = {
 708         .name           = "mdm_osc_ck",
 709         .ops            = &clkops_omap2_dflt_wait,
 710         .parent         = &osc_ck,
 711         .clkdm_name     = "mdm_clkdm",
 712         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
 713         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
 714         .recalc         = &followparent_recalc,
 715 };
 716
 717 /*
 718  * DSS clock domain
 719  * CLOCKs:
 720  * DSS_L4_ICLK, DSS_L3_ICLK,
 721  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
 722  *
 723  * DSS is both initiator and target.
 724  */
 725 /* XXX Add RATE_NOT_VALIDATED */
 726
 727 static const struct clksel_rate dss1_fck_sys_rates[] = {
 728         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 729         { .div = 0 }
 730 };
 731
 732 static const struct clksel_rate dss1_fck_core_rates[] = {
 733         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 734         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 735         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 736         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 737         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
 738         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
 739         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
 740         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
 741         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
 742         { .div = 16, .val = 16, .flags = RATE_IN_24XX },
 743         { .div = 0 }
 744 };
 745
 746 static const struct clksel dss1_fck_clksel[] = {
 747         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
 748         { .parent = &core_ck, .rates = dss1_fck_core_rates },
 749         { .parent = NULL },
 750 };
 751
 752 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
 753         .name           = "dss_ick",
 754         .ops            = &clkops_omap2_dflt,
 755         .parent         = &l4_ck,       /* really both l3 and l4 */
 756         .clkdm_name     = "dss_clkdm",
 757         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 758         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
 759         .recalc         = &followparent_recalc,
 760 };
 761
 762 static struct clk dss1_fck = {
 763         .name           = "dss1_fck",
 764         .ops            = &clkops_omap2_dflt,
 765         .parent         = &core_ck,             /* Core or sys */
 766         .clkdm_name     = "dss_clkdm",
 767         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 768         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
 769         .init           = &omap2_init_clksel_parent,
 770         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 771         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
 772         .clksel         = dss1_fck_clksel,
 773         .recalc         = &omap2_clksel_recalc,
 774 };
 775
 776 static const struct clksel_rate dss2_fck_sys_rates[] = {
 777         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 778         { .div = 0 }
 779 };
 780
 781 static const struct clksel_rate dss2_fck_48m_rates[] = {
 782         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 783         { .div = 0 }
 784 };
 785
 786 static const struct clksel dss2_fck_clksel[] = {
 787         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
 788         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
 789         { .parent = NULL }
 790 };
 791
 792 static struct clk dss2_fck = {          /* Alt clk used in power management */
 793         .name           = "dss2_fck",
 794         .ops            = &clkops_omap2_dflt,
 795         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
 796         .clkdm_name     = "dss_clkdm",
 797         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 798         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
 799         .init           = &omap2_init_clksel_parent,
 800         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 801         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
 802         .clksel         = dss2_fck_clksel,
 803         .recalc         = &followparent_recalc,
 804 };
 805
 806 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
 807         .name           = "dss_54m_fck",        /* 54m tv clk */
 808         .ops            = &clkops_omap2_dflt_wait,
 809         .parent         = &func_54m_ck,
 810         .clkdm_name     = "dss_clkdm",
 811         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 812         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
 813         .recalc         = &followparent_recalc,
 814 };
 815
 816 /*
 817  * CORE power domain ICLK & FCLK defines.
 818  * Many of the these can have more than one possible parent. Entries
 819  * here will likely have an L4 interface parent, and may have multiple
 820  * functional clock parents.
 821  */
 822 static const struct clksel_rate gpt_alt_rates[] = {
 823         { .div = 1, .val = 2, .flags = RATE_IN_24XX },
 824         { .div = 0 }
 825 };
 826
 827 static const struct clksel omap24xx_gpt_clksel[] = {
 828         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
 829         { .parent = &sys_ck,      .rates = gpt_sys_rates },
 830         { .parent = &alt_ck,      .rates = gpt_alt_rates },
 831         { .parent = NULL },
 832 };
 833
 834 static struct clk gpt1_ick = {
 835         .name           = "gpt1_ick",
 836         .ops            = &clkops_omap2_dflt_wait,
 837         .parent         = &l4_ck,
 838         .clkdm_name     = "core_l4_clkdm",
 839         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 840         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
 841         .recalc         = &followparent_recalc,
 842 };
 843
 844 static struct clk gpt1_fck = {
 845         .name           = "gpt1_fck",
 846         .ops            = &clkops_omap2_dflt_wait,
 847         .parent         = &func_32k_ck,
 848         .clkdm_name     = "core_l4_clkdm",
 849         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 850         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
 851         .init           = &omap2_init_clksel_parent,
 852         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
 853         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
 854         .clksel         = omap24xx_gpt_clksel,
 855         .recalc         = &omap2_clksel_recalc,
 856         .round_rate     = &omap2_clksel_round_rate,
 857         .set_rate       = &omap2_clksel_set_rate
 858 };
 859
 860 static struct clk gpt2_ick = {
 861         .name           = "gpt2_ick",
 862         .ops            = &clkops_omap2_dflt_wait,
 863         .parent         = &l4_ck,
 864         .clkdm_name     = "core_l4_clkdm",
 865         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 866         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
 867         .recalc         = &followparent_recalc,
 868 };
 869
 870 static struct clk gpt2_fck = {
 871         .name           = "gpt2_fck",
 872         .ops            = &clkops_omap2_dflt_wait,
 873         .parent         = &func_32k_ck,
 874         .clkdm_name     = "core_l4_clkdm",
 875         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 876         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
 877         .init           = &omap2_init_clksel_parent,
 878         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 879         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
 880         .clksel         = omap24xx_gpt_clksel,
 881         .recalc         = &omap2_clksel_recalc,
 882 };
 883
 884 static struct clk gpt3_ick = {
 885         .name           = "gpt3_ick",
 886         .ops            = &clkops_omap2_dflt_wait,
 887         .parent         = &l4_ck,
 888         .clkdm_name     = "core_l4_clkdm",
 889         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 890         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
 891         .recalc         = &followparent_recalc,
 892 };
 893
 894 static struct clk gpt3_fck = {
 895         .name           = "gpt3_fck",
 896         .ops            = &clkops_omap2_dflt_wait,
 897         .parent         = &func_32k_ck,
 898         .clkdm_name     = "core_l4_clkdm",
 899         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 900         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
 901         .init           = &omap2_init_clksel_parent,
 902         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 903         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
 904         .clksel         = omap24xx_gpt_clksel,
 905         .recalc         = &omap2_clksel_recalc,
 906 };
 907
 908 static struct clk gpt4_ick = {
 909         .name           = "gpt4_ick",
 910         .ops            = &clkops_omap2_dflt_wait,
 911         .parent         = &l4_ck,
 912         .clkdm_name     = "core_l4_clkdm",
 913         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 914         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
 915         .recalc         = &followparent_recalc,
 916 };
 917
 918 static struct clk gpt4_fck = {
 919         .name           = "gpt4_fck",
 920         .ops            = &clkops_omap2_dflt_wait,
 921         .parent         = &func_32k_ck,
 922         .clkdm_name     = "core_l4_clkdm",
 923         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 924         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
 925         .init           = &omap2_init_clksel_parent,
 926         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 927         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
 928         .clksel         = omap24xx_gpt_clksel,
 929         .recalc         = &omap2_clksel_recalc,
 930 };
 931
 932 static struct clk gpt5_ick = {
 933         .name           = "gpt5_ick",
 934         .ops            = &clkops_omap2_dflt_wait,
 935         .parent         = &l4_ck,
 936         .clkdm_name     = "core_l4_clkdm",
 937         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 938         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
 939         .recalc         = &followparent_recalc,
 940 };
 941
 942 static struct clk gpt5_fck = {
 943         .name           = "gpt5_fck",
 944         .ops            = &clkops_omap2_dflt_wait,
 945         .parent         = &func_32k_ck,
 946         .clkdm_name     = "core_l4_clkdm",
 947         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 948         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
 949         .init           = &omap2_init_clksel_parent,
 950         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 951         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
 952         .clksel         = omap24xx_gpt_clksel,
 953         .recalc         = &omap2_clksel_recalc,
 954 };
 955
 956 static struct clk gpt6_ick = {
 957         .name           = "gpt6_ick",
 958         .ops            = &clkops_omap2_dflt_wait,
 959         .parent         = &l4_ck,
 960         .clkdm_name     = "core_l4_clkdm",
 961         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 962         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
 963         .recalc         = &followparent_recalc,
 964 };
 965
 966 static struct clk gpt6_fck = {
 967         .name           = "gpt6_fck",
 968         .ops            = &clkops_omap2_dflt_wait,
 969         .parent         = &func_32k_ck,
 970         .clkdm_name     = "core_l4_clkdm",
 971         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 972         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
 973         .init           = &omap2_init_clksel_parent,
 974         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 975         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
 976         .clksel         = omap24xx_gpt_clksel,
 977         .recalc         = &omap2_clksel_recalc,
 978 };
 979
 980 static struct clk gpt7_ick = {
 981         .name           = "gpt7_ick",
 982         .ops            = &clkops_omap2_dflt_wait,
 983         .parent         = &l4_ck,
 984         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 985         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
 986         .recalc         = &followparent_recalc,
 987 };
 988
 989 static struct clk gpt7_fck = {
 990         .name           = "gpt7_fck",
 991         .ops            = &clkops_omap2_dflt_wait,
 992         .parent         = &func_32k_ck,
 993         .clkdm_name     = "core_l4_clkdm",
 994         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 995         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
 996         .init           = &omap2_init_clksel_parent,
 997         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 998         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
 999         .clksel         = omap24xx_gpt_clksel,
1000         .recalc         = &omap2_clksel_recalc,
1001 };
1002
1003 static struct clk gpt8_ick = {
1004         .name           = "gpt8_ick",
1005         .ops            = &clkops_omap2_dflt_wait,
1006         .parent         = &l4_ck,
1007         .clkdm_name     = "core_l4_clkdm",
1008         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1009         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1010         .recalc         = &followparent_recalc,
1011 };
1012
1013 static struct clk gpt8_fck = {
1014         .name           = "gpt8_fck",
1015         .ops            = &clkops_omap2_dflt_wait,
1016         .parent         = &func_32k_ck,
1017         .clkdm_name     = "core_l4_clkdm",
1018         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1019         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1020         .init           = &omap2_init_clksel_parent,
1021         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1022         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1023         .clksel         = omap24xx_gpt_clksel,
1024         .recalc         = &omap2_clksel_recalc,
1025 };
1026
1027 static struct clk gpt9_ick = {
1028         .name           = "gpt9_ick",
1029         .ops            = &clkops_omap2_dflt_wait,
1030         .parent         = &l4_ck,
1031         .clkdm_name     = "core_l4_clkdm",
1032         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1033         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1034         .recalc         = &followparent_recalc,
1035 };
1036
1037 static struct clk gpt9_fck = {
1038         .name           = "gpt9_fck",
1039         .ops            = &clkops_omap2_dflt_wait,
1040         .parent         = &func_32k_ck,
1041         .clkdm_name     = "core_l4_clkdm",
1042         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1043         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1044         .init           = &omap2_init_clksel_parent,
1045         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1046         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1047         .clksel         = omap24xx_gpt_clksel,
1048         .recalc         = &omap2_clksel_recalc,
1049 };
1050
1051 static struct clk gpt10_ick = {
1052         .name           = "gpt10_ick",
1053         .ops            = &clkops_omap2_dflt_wait,
1054         .parent         = &l4_ck,
1055         .clkdm_name     = "core_l4_clkdm",
1056         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1057         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1058         .recalc         = &followparent_recalc,
1059 };
1060
1061 static struct clk gpt10_fck = {
1062         .name           = "gpt10_fck",
1063         .ops            = &clkops_omap2_dflt_wait,
1064         .parent         = &func_32k_ck,
1065         .clkdm_name     = "core_l4_clkdm",
1066         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1067         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1068         .init           = &omap2_init_clksel_parent,
1069         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1070         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1071         .clksel         = omap24xx_gpt_clksel,
1072         .recalc         = &omap2_clksel_recalc,
1073 };
1074
1075 static struct clk gpt11_ick = {
1076         .name           = "gpt11_ick",
1077         .ops            = &clkops_omap2_dflt_wait,
1078         .parent         = &l4_ck,
1079         .clkdm_name     = "core_l4_clkdm",
1080         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1081         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1082         .recalc         = &followparent_recalc,
1083 };
1084
1085 static struct clk gpt11_fck = {
1086         .name           = "gpt11_fck",
1087         .ops            = &clkops_omap2_dflt_wait,
1088         .parent         = &func_32k_ck,
1089         .clkdm_name     = "core_l4_clkdm",
1090         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1091         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1092         .init           = &omap2_init_clksel_parent,
1093         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1094         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1095         .clksel         = omap24xx_gpt_clksel,
1096         .recalc         = &omap2_clksel_recalc,
1097 };
1098
1099 static struct clk gpt12_ick = {
1100         .name           = "gpt12_ick",
1101         .ops            = &clkops_omap2_dflt_wait,
1102         .parent         = &l4_ck,
1103         .clkdm_name     = "core_l4_clkdm",
1104         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1105         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1106         .recalc         = &followparent_recalc,
1107 };
1108
1109 static struct clk gpt12_fck = {
1110         .name           = "gpt12_fck",
1111         .ops            = &clkops_omap2_dflt_wait,
1112         .parent         = &secure_32k_ck,
1113         .clkdm_name     = "core_l4_clkdm",
1114         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1115         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1116         .init           = &omap2_init_clksel_parent,
1117         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1118         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1119         .clksel         = omap24xx_gpt_clksel,
1120         .recalc         = &omap2_clksel_recalc,
1121 };
1122
1123 static struct clk mcbsp1_ick = {
1124         .name           = "mcbsp1_ick",
1125         .ops            = &clkops_omap2_dflt_wait,
1126         .parent         = &l4_ck,
1127         .clkdm_name     = "core_l4_clkdm",
1128         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1129         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1130         .recalc         = &followparent_recalc,
1131 };
1132
1133 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1134         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1135         { .div = 0 }
1136 };
1137
1138 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1139         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1140         { .div = 0 }
1141 };
1142
1143 static const struct clksel mcbsp_fck_clksel[] = {
1144         { .parent = &func_96m_ck,  .rates = common_mcbsp_96m_rates },
1145         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1146         { .parent = NULL }
1147 };
1148
1149 static struct clk mcbsp1_fck = {
1150         .name           = "mcbsp1_fck",
1151         .ops            = &clkops_omap2_dflt_wait,
1152         .parent         = &func_96m_ck,
1153         .init           = &omap2_init_clksel_parent,
1154         .clkdm_name     = "core_l4_clkdm",
1155         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1156         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1157         .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1158         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1159         .clksel         = mcbsp_fck_clksel,
1160         .recalc         = &omap2_clksel_recalc,
1161 };
1162
1163 static struct clk mcbsp2_ick = {
1164         .name           = "mcbsp2_ick",
1165         .ops            = &clkops_omap2_dflt_wait,
1166         .parent         = &l4_ck,
1167         .clkdm_name     = "core_l4_clkdm",
1168         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1169         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1170         .recalc         = &followparent_recalc,
1171 };
1172
1173 static struct clk mcbsp2_fck = {
1174         .name           = "mcbsp2_fck",
1175         .ops            = &clkops_omap2_dflt_wait,
1176         .parent         = &func_96m_ck,
1177         .init           = &omap2_init_clksel_parent,
1178         .clkdm_name     = "core_l4_clkdm",
1179         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1180         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1181         .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1182         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
1183         .clksel         = mcbsp_fck_clksel,
1184         .recalc         = &omap2_clksel_recalc,
1185 };
1186
1187 static struct clk mcbsp3_ick = {
1188         .name           = "mcbsp3_ick",
1189         .ops            = &clkops_omap2_dflt_wait,
1190         .parent         = &l4_ck,
1191         .clkdm_name     = "core_l4_clkdm",
1192         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1193         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1194         .recalc         = &followparent_recalc,
1195 };
1196
1197 static struct clk mcbsp3_fck = {
1198         .name           = "mcbsp3_fck",
1199         .ops            = &clkops_omap2_dflt_wait,
1200         .parent         = &func_96m_ck,
1201         .init           = &omap2_init_clksel_parent,
1202         .clkdm_name     = "core_l4_clkdm",
1203         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1204         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1205         .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1206         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
1207         .clksel         = mcbsp_fck_clksel,
1208         .recalc         = &omap2_clksel_recalc,
1209 };
1210
1211 static struct clk mcbsp4_ick = {
1212         .name           = "mcbsp4_ick",
1213         .ops            = &clkops_omap2_dflt_wait,
1214         .parent         = &l4_ck,
1215         .clkdm_name     = "core_l4_clkdm",
1216         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1217         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1218         .recalc         = &followparent_recalc,
1219 };
1220
1221 static struct clk mcbsp4_fck = {
1222         .name           = "mcbsp4_fck",
1223         .ops            = &clkops_omap2_dflt_wait,
1224         .parent         = &func_96m_ck,
1225         .init           = &omap2_init_clksel_parent,
1226         .clkdm_name     = "core_l4_clkdm",
1227         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1228         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1229         .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1230         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
1231         .clksel         = mcbsp_fck_clksel,
1232         .recalc         = &omap2_clksel_recalc,
1233 };
1234
1235 static struct clk mcbsp5_ick = {
1236         .name           = "mcbsp5_ick",
1237         .ops            = &clkops_omap2_dflt_wait,
1238         .parent         = &l4_ck,
1239         .clkdm_name     = "core_l4_clkdm",
1240         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1241         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1242         .recalc         = &followparent_recalc,
1243 };
1244
1245 static struct clk mcbsp5_fck = {
1246         .name           = "mcbsp5_fck",
1247         .ops            = &clkops_omap2_dflt_wait,
1248         .parent         = &func_96m_ck,
1249         .init           = &omap2_init_clksel_parent,
1250         .clkdm_name     = "core_l4_clkdm",
1251         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1252         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1253         .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1254         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1255         .clksel         = mcbsp_fck_clksel,
1256         .recalc         = &omap2_clksel_recalc,
1257 };
1258
1259 static struct clk mcspi1_ick = {
1260         .name           = "mcspi1_ick",
1261         .ops            = &clkops_omap2_dflt_wait,
1262         .parent         = &l4_ck,
1263         .clkdm_name     = "core_l4_clkdm",
1264         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1265         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1266         .recalc         = &followparent_recalc,
1267 };
1268
1269 static struct clk mcspi1_fck = {
1270         .name           = "mcspi1_fck",
1271         .ops            = &clkops_omap2_dflt_wait,
1272         .parent         = &func_48m_ck,
1273         .clkdm_name     = "core_l4_clkdm",
1274         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1275         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1276         .recalc         = &followparent_recalc,
1277 };
1278
1279 static struct clk mcspi2_ick = {
1280         .name           = "mcspi2_ick",
1281         .ops            = &clkops_omap2_dflt_wait,
1282         .parent         = &l4_ck,
1283         .clkdm_name     = "core_l4_clkdm",
1284         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1285         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1286         .recalc         = &followparent_recalc,
1287 };
1288
1289 static struct clk mcspi2_fck = {
1290         .name           = "mcspi2_fck",
1291         .ops            = &clkops_omap2_dflt_wait,
1292         .parent         = &func_48m_ck,
1293         .clkdm_name     = "core_l4_clkdm",
1294         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1295         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1296         .recalc         = &followparent_recalc,
1297 };
1298
1299 static struct clk mcspi3_ick = {
1300         .name           = "mcspi3_ick",
1301         .ops            = &clkops_omap2_dflt_wait,
1302         .parent         = &l4_ck,
1303         .clkdm_name     = "core_l4_clkdm",
1304         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1305         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1306         .recalc         = &followparent_recalc,
1307 };
1308
1309 static struct clk mcspi3_fck = {
1310         .name           = "mcspi3_fck",
1311         .ops            = &clkops_omap2_dflt_wait,
1312         .parent         = &func_48m_ck,
1313         .clkdm_name     = "core_l4_clkdm",
1314         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1315         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1316         .recalc         = &followparent_recalc,
1317 };
1318
1319 static struct clk uart1_ick = {
1320         .name           = "uart1_ick",
1321         .ops            = &clkops_omap2_dflt_wait,
1322         .parent         = &l4_ck,
1323         .clkdm_name     = "core_l4_clkdm",
1324         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1325         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1326         .recalc         = &followparent_recalc,
1327 };
1328
1329 static struct clk uart1_fck = {
1330         .name           = "uart1_fck",
1331         .ops            = &clkops_omap2_dflt_wait,
1332         .parent         = &func_48m_ck,
1333         .clkdm_name     = "core_l4_clkdm",
1334         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1335         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1336         .recalc         = &followparent_recalc,
1337 };
1338
1339 static struct clk uart2_ick = {
1340         .name           = "uart2_ick",
1341         .ops            = &clkops_omap2_dflt_wait,
1342         .parent         = &l4_ck,
1343         .clkdm_name     = "core_l4_clkdm",
1344         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1345         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1346         .recalc         = &followparent_recalc,
1347 };
1348
1349 static struct clk uart2_fck = {
1350         .name           = "uart2_fck",
1351         .ops            = &clkops_omap2_dflt_wait,
1352         .parent         = &func_48m_ck,
1353         .clkdm_name     = "core_l4_clkdm",
1354         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1355         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1356         .recalc         = &followparent_recalc,
1357 };
1358
1359 static struct clk uart3_ick = {
1360         .name           = "uart3_ick",
1361         .ops            = &clkops_omap2_dflt_wait,
1362         .parent         = &l4_ck,
1363         .clkdm_name     = "core_l4_clkdm",
1364         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1365         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1366         .recalc         = &followparent_recalc,
1367 };
1368
1369 static struct clk uart3_fck = {
1370         .name           = "uart3_fck",
1371         .ops            = &clkops_omap2_dflt_wait,
1372         .parent         = &func_48m_ck,
1373         .clkdm_name     = "core_l4_clkdm",
1374         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1375         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1376         .recalc         = &followparent_recalc,
1377 };
1378
1379 static struct clk gpios_ick = {
1380         .name           = "gpios_ick",
1381         .ops            = &clkops_omap2_dflt_wait,
1382         .parent         = &l4_ck,
1383         .clkdm_name     = "core_l4_clkdm",
1384         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1385         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1386         .recalc         = &followparent_recalc,
1387 };
1388
1389 static struct clk gpios_fck = {
1390         .name           = "gpios_fck",
1391         .ops            = &clkops_omap2_dflt_wait,
1392         .parent         = &func_32k_ck,
1393         .clkdm_name     = "wkup_clkdm",
1394         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1395         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1396         .recalc         = &followparent_recalc,
1397 };
1398
1399 static struct clk mpu_wdt_ick = {
1400         .name           = "mpu_wdt_ick",
1401         .ops            = &clkops_omap2_dflt_wait,
1402         .parent         = &l4_ck,
1403         .clkdm_name     = "core_l4_clkdm",
1404         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1405         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1406         .recalc         = &followparent_recalc,
1407 };
1408
1409 static struct clk mpu_wdt_fck = {
1410         .name           = "mpu_wdt_fck",
1411         .ops            = &clkops_omap2_dflt_wait,
1412         .parent         = &func_32k_ck,
1413         .clkdm_name     = "wkup_clkdm",
1414         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1415         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1416         .recalc         = &followparent_recalc,
1417 };
1418
1419 static struct clk sync_32k_ick = {
1420         .name           = "sync_32k_ick",
1421         .ops            = &clkops_omap2_dflt_wait,
1422         .parent         = &l4_ck,
1423         .flags          = ENABLE_ON_INIT,
1424         .clkdm_name     = "core_l4_clkdm",
1425         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1426         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
1427         .recalc         = &followparent_recalc,
1428 };
1429
1430 static struct clk wdt1_ick = {
1431         .name           = "wdt1_ick",
1432         .ops            = &clkops_omap2_dflt_wait,
1433         .parent         = &l4_ck,
1434         .clkdm_name     = "core_l4_clkdm",
1435         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1436         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
1437         .recalc         = &followparent_recalc,
1438 };
1439
1440 static struct clk omapctrl_ick = {
1441         .name           = "omapctrl_ick",
1442         .ops            = &clkops_omap2_dflt_wait,
1443         .parent         = &l4_ck,
1444         .flags          = ENABLE_ON_INIT,
1445         .clkdm_name     = "core_l4_clkdm",
1446         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1447         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
1448         .recalc         = &followparent_recalc,
1449 };
1450
1451 static struct clk icr_ick = {
1452         .name           = "icr_ick",
1453         .ops            = &clkops_omap2_dflt_wait,
1454         .parent         = &l4_ck,
1455         .clkdm_name     = "core_l4_clkdm",
1456         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1457         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
1458         .recalc         = &followparent_recalc,
1459 };
1460
1461 static struct clk cam_ick = {
1462         .name           = "cam_ick",
1463         .ops            = &clkops_omap2_dflt,
1464         .parent         = &l4_ck,
1465         .clkdm_name     = "core_l4_clkdm",
1466         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1467         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
1468         .recalc         = &followparent_recalc,
1469 };
1470
1471 /*
1472  * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
1473  * split into two separate clocks, since the parent clocks are different
1474  * and the clockdomains are also different.
1475  */
1476 static struct clk cam_fck = {
1477         .name           = "cam_fck",
1478         .ops            = &clkops_omap2_dflt,
1479         .parent         = &func_96m_ck,
1480         .clkdm_name     = "core_l3_clkdm",
1481         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1482         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
1483         .recalc         = &followparent_recalc,
1484 };
1485
1486 static struct clk mailboxes_ick = {
1487         .name           = "mailboxes_ick",
1488         .ops            = &clkops_omap2_dflt_wait,
1489         .parent         = &l4_ck,
1490         .clkdm_name     = "core_l4_clkdm",
1491         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1492         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
1493         .recalc         = &followparent_recalc,
1494 };
1495
1496 static struct clk wdt4_ick = {
1497         .name           = "wdt4_ick",
1498         .ops            = &clkops_omap2_dflt_wait,
1499         .parent         = &l4_ck,
1500         .clkdm_name     = "core_l4_clkdm",
1501         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1502         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
1503         .recalc         = &followparent_recalc,
1504 };
1505
1506 static struct clk wdt4_fck = {
1507         .name           = "wdt4_fck",
1508         .ops            = &clkops_omap2_dflt_wait,
1509         .parent         = &func_32k_ck,
1510         .clkdm_name     = "core_l4_clkdm",
1511         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1512         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
1513         .recalc         = &followparent_recalc,
1514 };
1515
1516 static struct clk mspro_ick = {
1517         .name           = "mspro_ick",
1518         .ops            = &clkops_omap2_dflt_wait,
1519         .parent         = &l4_ck,
1520         .clkdm_name     = "core_l4_clkdm",
1521         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1522         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
1523         .recalc         = &followparent_recalc,
1524 };
1525
1526 static struct clk mspro_fck = {
1527         .name           = "mspro_fck",
1528         .ops            = &clkops_omap2_dflt_wait,
1529         .parent         = &func_96m_ck,
1530         .clkdm_name     = "core_l4_clkdm",
1531         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1532         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
1533         .recalc         = &followparent_recalc,
1534 };
1535
1536 static struct clk fac_ick = {
1537         .name           = "fac_ick",
1538         .ops            = &clkops_omap2_dflt_wait,
1539         .parent         = &l4_ck,
1540         .clkdm_name     = "core_l4_clkdm",
1541         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1542         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
1543         .recalc         = &followparent_recalc,
1544 };
1545
1546 static struct clk fac_fck = {
1547         .name           = "fac_fck",
1548         .ops            = &clkops_omap2_dflt_wait,
1549         .parent         = &func_12m_ck,
1550         .clkdm_name     = "core_l4_clkdm",
1551         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1552         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
1553         .recalc         = &followparent_recalc,
1554 };
1555
1556 static struct clk hdq_ick = {
1557         .name           = "hdq_ick",
1558         .ops            = &clkops_omap2_dflt_wait,
1559         .parent         = &l4_ck,
1560         .clkdm_name     = "core_l4_clkdm",
1561         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1562         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
1563         .recalc         = &followparent_recalc,
1564 };
1565
1566 static struct clk hdq_fck = {
1567         .name           = "hdq_fck",
1568         .ops            = &clkops_omap2_dflt_wait,
1569         .parent         = &func_12m_ck,
1570         .clkdm_name     = "core_l4_clkdm",
1571         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1572         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
1573         .recalc         = &followparent_recalc,
1574 };
1575
1576 /*
1577  * XXX This is marked as a 2420-only define, but it claims to be present
1578  * on 2430 also.  Double-check.
1579  */
1580 static struct clk i2c2_ick = {
1581         .name           = "i2c2_ick",
1582         .ops            = &clkops_omap2_dflt_wait,
1583         .parent         = &l4_ck,
1584         .clkdm_name     = "core_l4_clkdm",
1585         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1586         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
1587         .recalc         = &followparent_recalc,
1588 };
1589
1590 static struct clk i2chs2_fck = {
1591         .name           = "i2chs2_fck",
1592         .ops            = &clkops_omap2430_i2chs_wait,
1593         .parent         = &func_96m_ck,
1594         .clkdm_name     = "core_l4_clkdm",
1595         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1596         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
1597         .recalc         = &followparent_recalc,
1598 };
1599
1600 /*
1601  * XXX This is marked as a 2420-only define, but it claims to be present
1602  * on 2430 also.  Double-check.
1603  */
1604 static struct clk i2c1_ick = {
1605         .name           = "i2c1_ick",
1606         .ops            = &clkops_omap2_dflt_wait,
1607         .parent         = &l4_ck,
1608         .clkdm_name     = "core_l4_clkdm",
1609         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1610         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
1611         .recalc         = &followparent_recalc,
1612 };
1613
1614 static struct clk i2chs1_fck = {
1615         .name           = "i2chs1_fck",
1616         .ops            = &clkops_omap2430_i2chs_wait,
1617         .parent         = &func_96m_ck,
1618         .clkdm_name     = "core_l4_clkdm",
1619         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1620         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
1621         .recalc         = &followparent_recalc,
1622 };
1623
1624 static struct clk gpmc_fck = {
1625         .name           = "gpmc_fck",
1626         .ops            = &clkops_null, /* RMK: missing? */
1627         .parent         = &core_l3_ck,
1628         .flags          = ENABLE_ON_INIT,
1629         .clkdm_name     = "core_l3_clkdm",
1630         .recalc         = &followparent_recalc,
1631 };
1632
1633 static struct clk sdma_fck = {
1634         .name           = "sdma_fck",
1635         .ops            = &clkops_null, /* RMK: missing? */
1636         .parent         = &core_l3_ck,
1637         .clkdm_name     = "core_l3_clkdm",
1638         .recalc         = &followparent_recalc,
1639 };
1640
1641 static struct clk sdma_ick = {
1642         .name           = "sdma_ick",
1643         .ops            = &clkops_null, /* RMK: missing? */
1644         .parent         = &l4_ck,
1645         .clkdm_name     = "core_l3_clkdm",
1646         .recalc         = &followparent_recalc,
1647 };
1648
1649 static struct clk sdrc_ick = {
1650         .name           = "sdrc_ick",
1651         .ops            = &clkops_omap2_dflt_wait,
1652         .parent         = &l4_ck,
1653         .flags          = ENABLE_ON_INIT,
1654         .clkdm_name     = "core_l4_clkdm",
1655         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1656         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
1657         .recalc         = &followparent_recalc,
1658 };
1659
1660 static struct clk des_ick = {
1661         .name           = "des_ick",
1662         .ops            = &clkops_omap2_dflt_wait,
1663         .parent         = &l4_ck,
1664         .clkdm_name     = "core_l4_clkdm",
1665         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1666         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
1667         .recalc         = &followparent_recalc,
1668 };
1669
1670 static struct clk sha_ick = {
1671         .name           = "sha_ick",
1672         .ops            = &clkops_omap2_dflt_wait,
1673         .parent         = &l4_ck,
1674         .clkdm_name     = "core_l4_clkdm",
1675         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1676         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
1677         .recalc         = &followparent_recalc,
1678 };
1679
1680 static struct clk rng_ick = {
1681         .name           = "rng_ick",
1682         .ops            = &clkops_omap2_dflt_wait,
1683         .parent         = &l4_ck,
1684         .clkdm_name     = "core_l4_clkdm",
1685         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1686         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
1687         .recalc         = &followparent_recalc,
1688 };
1689
1690 static struct clk aes_ick = {
1691         .name           = "aes_ick",
1692         .ops            = &clkops_omap2_dflt_wait,
1693         .parent         = &l4_ck,
1694         .clkdm_name     = "core_l4_clkdm",
1695         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1696         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
1697         .recalc         = &followparent_recalc,
1698 };
1699
1700 static struct clk pka_ick = {
1701         .name           = "pka_ick",
1702         .ops            = &clkops_omap2_dflt_wait,
1703         .parent         = &l4_ck,
1704         .clkdm_name     = "core_l4_clkdm",
1705         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1706         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
1707         .recalc         = &followparent_recalc,
1708 };
1709
1710 static struct clk usb_fck = {
1711         .name           = "usb_fck",
1712         .ops            = &clkops_omap2_dflt_wait,
1713         .parent         = &func_48m_ck,
1714         .clkdm_name     = "core_l3_clkdm",
1715         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1716         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1717         .recalc         = &followparent_recalc,
1718 };
1719
1720 static struct clk usbhs_ick = {
1721         .name           = "usbhs_ick",
1722         .ops            = &clkops_omap2_dflt_wait,
1723         .parent         = &core_l3_ck,
1724         .clkdm_name     = "core_l3_clkdm",
1725         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1726         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
1727         .recalc         = &followparent_recalc,
1728 };
1729
1730 static struct clk mmchs1_ick = {
1731         .name           = "mmchs1_ick",
1732         .ops            = &clkops_omap2_dflt_wait,
1733         .parent         = &l4_ck,
1734         .clkdm_name     = "core_l4_clkdm",
1735         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1736         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
1737         .recalc         = &followparent_recalc,
1738 };
1739
1740 static struct clk mmchs1_fck = {
1741         .name           = "mmchs1_fck",
1742         .ops            = &clkops_omap2_dflt_wait,
1743         .parent         = &func_96m_ck,
1744         .clkdm_name     = "core_l3_clkdm",
1745         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1746         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
1747         .recalc         = &followparent_recalc,
1748 };
1749
1750 static struct clk mmchs2_ick = {
1751         .name           = "mmchs2_ick",
1752         .ops            = &clkops_omap2_dflt_wait,
1753         .parent         = &l4_ck,
1754         .clkdm_name     = "core_l4_clkdm",
1755         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1756         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
1757         .recalc         = &followparent_recalc,
1758 };
1759
1760 static struct clk mmchs2_fck = {
1761         .name           = "mmchs2_fck",
1762         .ops            = &clkops_omap2_dflt_wait,
1763         .parent         = &func_96m_ck,
1764         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1765         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
1766         .recalc         = &followparent_recalc,
1767 };
1768
1769 static struct clk gpio5_ick = {
1770         .name           = "gpio5_ick",
1771         .ops            = &clkops_omap2_dflt_wait,
1772         .parent         = &l4_ck,
1773         .clkdm_name     = "core_l4_clkdm",
1774         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1775         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
1776         .recalc         = &followparent_recalc,
1777 };
1778
1779 static struct clk gpio5_fck = {
1780         .name           = "gpio5_fck",
1781         .ops            = &clkops_omap2_dflt_wait,
1782         .parent         = &func_32k_ck,
1783         .clkdm_name     = "core_l4_clkdm",
1784         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1785         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
1786         .recalc         = &followparent_recalc,
1787 };
1788
1789 static struct clk mdm_intc_ick = {
1790         .name           = "mdm_intc_ick",
1791         .ops            = &clkops_omap2_dflt_wait,
1792         .parent         = &l4_ck,
1793         .clkdm_name     = "core_l4_clkdm",
1794         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1795         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
1796         .recalc         = &followparent_recalc,
1797 };
1798
1799 static struct clk mmchsdb1_fck = {
1800         .name           = "mmchsdb1_fck",
1801         .ops            = &clkops_omap2_dflt_wait,
1802         .parent         = &func_32k_ck,
1803         .clkdm_name     = "core_l4_clkdm",
1804         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1805         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
1806         .recalc         = &followparent_recalc,
1807 };
1808
1809 static struct clk mmchsdb2_fck = {
1810         .name           = "mmchsdb2_fck",
1811         .ops            = &clkops_omap2_dflt_wait,
1812         .parent         = &func_32k_ck,
1813         .clkdm_name     = "core_l4_clkdm",
1814         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1815         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
1816         .recalc         = &followparent_recalc,
1817 };
1818
1819 /*
1820  * This clock is a composite clock which does entire set changes then
1821  * forces a rebalance. It keys on the MPU speed, but it really could
1822  * be any key speed part of a set in the rate table.
1823  *
1824  * to really change a set, you need memory table sets which get changed
1825  * in sram, pre-notifiers & post notifiers, changing the top set, without
1826  * having low level display recalc's won't work... this is why dpm notifiers
1827  * work, isr's off, walk a list of clocks already _off_ and not messing with
1828  * the bus.
1829  *
1830  * This clock should have no parent. It embodies the entire upper level
1831  * active set. A parent will mess up some of the init also.
1832  */
1833 static struct clk virt_prcm_set = {
1834         .name           = "virt_prcm_set",
1835         .ops            = &clkops_null,
1836         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
1837         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
1838         .set_rate       = &omap2_select_table_rate,
1839         .round_rate     = &omap2_round_to_table_rate,
1840 };
1841
1842
1843 /*
1844  * clkdev integration
1845  */
1846
1847 static struct omap_clk omap2430_clks[] = {
1848         /* external root sources */
1849         CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_243X),
1850         CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_243X),
1851         CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X),
1852         CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X),
1853         CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X),
1854         CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_243X),
1855         CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_243X),
1856         CLK("omap-mcbsp.3",     "pad_fck",      &mcbsp_clks,    CK_243X),
1857         CLK("omap-mcbsp.4",     "pad_fck",      &mcbsp_clks,    CK_243X),
1858         CLK("omap-mcbsp.5",     "pad_fck",      &mcbsp_clks,    CK_243X),
1859         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_243X),
1860         /* internal analog sources */
1861         CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X),
1862         CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_243X),
1863         CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_243X),
1864         /* internal prcm root sources */
1865         CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X),
1866         CLK(NULL,       "core_ck",      &core_ck,       CK_243X),
1867         CLK("omap-mcbsp.1",     "prcm_fck",     &func_96m_ck,   CK_243X),
1868         CLK("omap-mcbsp.2",     "prcm_fck",     &func_96m_ck,   CK_243X),
1869         CLK("omap-mcbsp.3",     "prcm_fck",     &func_96m_ck,   CK_243X),
1870         CLK("omap-mcbsp.4",     "prcm_fck",     &func_96m_ck,   CK_243X),
1871         CLK("omap-mcbsp.5",     "prcm_fck",     &func_96m_ck,   CK_243X),
1872         CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X),
1873         CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X),
1874         CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X),
1875         CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_243X),
1876         CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_243X),
1877         CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_243X),
1878         CLK(NULL,       "emul_ck",      &emul_ck,       CK_243X),
1879         /* mpu domain clocks */
1880         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_243X),
1881         /* dsp domain clocks */
1882         CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_243X),
1883         CLK(NULL,       "dsp_irate_ick", &dsp_irate_ick, CK_243X),
1884         CLK(NULL,       "iva2_1_ick",   &iva2_1_ick,    CK_243X),
1885         /* GFX domain clocks */
1886         CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_243X),
1887         CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_243X),
1888         CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_243X),
1889         /* Modem domain clocks */
1890         CLK(NULL,       "mdm_ick",      &mdm_ick,       CK_243X),
1891         CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
1892         /* DSS domain clocks */
1893         CLK("omapdss",  "ick",          &dss_ick,       CK_243X),
1894         CLK("omapdss",  "dss1_fck",     &dss1_fck,      CK_243X),
1895         CLK("omapdss",  "dss2_fck",     &dss2_fck,      CK_243X),
1896         CLK("omapdss",  "tv_fck",       &dss_54m_fck,   CK_243X),
1897         /* L3 domain clocks */
1898         CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X),
1899         CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X),
1900         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_243X),
1901         /* L4 domain clocks */
1902         CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X),
1903         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X),
1904         /* virtual meta-group clock */
1905         CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X),
1906         /* general l4 interface ck, multi-parent functional clk */
1907         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_243X),
1908         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_243X),
1909         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_243X),
1910         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_243X),
1911         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_243X),
1912         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_243X),
1913         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_243X),
1914         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_243X),
1915         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_243X),
1916         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_243X),
1917         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_243X),
1918         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_243X),
1919         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_243X),
1920         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_243X),
1921         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_243X),
1922         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_243X),
1923         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_243X),
1924         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_243X),
1925         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_243X),
1926         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_243X),
1927         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_243X),
1928         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_243X),
1929         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X),
1930         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X),
1931         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X),
1932         CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_243X),
1933         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X),
1934         CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_243X),
1935         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
1936         CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_243X),
1937         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
1938         CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_243X),
1939         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
1940         CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_243X),
1941         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X),
1942         CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_243X),
1943         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X),
1944         CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_243X),
1945         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
1946         CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_243X),
1947         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X),
1948         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X),
1949         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_243X),
1950         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_243X),
1951         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_243X),
1952         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_243X),
1953         CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X),
1954         CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X),
1955         CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X),
1956         CLK("omap_wdt", "fck",          &mpu_wdt_fck,   CK_243X),
1957         CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X),
1958         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X),
1959         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X),
1960         CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
1961         CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X),
1962         CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X),
1963         CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X),
1964         CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X),
1965         CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X),
1966         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_243X),
1967         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_243X),
1968         CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X),
1969         CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X),
1970         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X),
1971         CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X),
1972         CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_243X),
1973         CLK("i2c_omap.1", "fck",        &i2chs1_fck,    CK_243X),
1974         CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_243X),
1975         CLK("i2c_omap.2", "fck",        &i2chs2_fck,    CK_243X),
1976         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X),
1977         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X),
1978         CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X),
1979         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_243X),
1980         CLK(NULL,       "des_ick",      &des_ick,       CK_243X),
1981         CLK("omap-sham",        "ick",  &sha_ick,       CK_243X),
1982         CLK("omap_rng", "ick",          &rng_ick,       CK_243X),
1983         CLK("omap-aes", "ick",  &aes_ick,       CK_243X),
1984         CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X),
1985         CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X),
1986         CLK("musb_hdrc",        "ick",  &usbhs_ick,     CK_243X),
1987         CLK("mmci-omap-hs.0", "ick",    &mmchs1_ick,    CK_243X),
1988         CLK("mmci-omap-hs.0", "fck",    &mmchs1_fck,    CK_243X),
1989         CLK("mmci-omap-hs.1", "ick",    &mmchs2_ick,    CK_243X),
1990         CLK("mmci-omap-hs.1", "fck",    &mmchs2_fck,    CK_243X),
1991         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
1992         CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
1993         CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
1994         CLK("mmci-omap-hs.0", "mmchsdb_fck",    &mmchsdb1_fck,  CK_243X),
1995         CLK("mmci-omap-hs.1", "mmchsdb_fck",    &mmchsdb2_fck,  CK_243X),
1996 };
1997
1998 /*
1999  * init code
2000  */
2001
2002 int __init omap2430_clk_init(void)
2003 {
2004         const struct prcm_config *prcm;
2005         struct omap_clk *c;
2006         u32 clkrate;
2007
2008         prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
2009         cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
2010         cpu_mask = RATE_IN_243X;
2011         rate_table = omap2430_rate_table;
2012
2013         clk_init(&omap2_clk_functions);
2014
2015         for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
2016              c++)
2017                 clk_preinit(c->lk.clk);
2018
2019         osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
2020         propagate_rate(&osc_ck);
2021         sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
2022         propagate_rate(&sys_ck);
2023
2024         for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
2025              c++) {
2026                 clkdev_add(&c->lk);
2027                 clk_register(c->lk.clk);
2028                 omap2_init_clk_clkdm(c->lk.clk);
2029         }
2030
2031         /* Check the MPU rate set by bootloader */
2032         clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
2033         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
2034                 if (!(prcm->flags & cpu_mask))
2035                         continue;
2036                 if (prcm->xtal_speed != sys_ck.rate)
2037                         continue;
2038                 if (prcm->dpll_speed <= clkrate)
2039                         break;
2040         }
2041         curr_prcm_set = prcm;
2042
2043         recalculate_root_clocks();
2044
2045         pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
2046                 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
2047                 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
2048
2049         /*
2050          * Only enable those clocks we will need, let the drivers
2051          * enable other clocks as necessary
2052          */
2053         clk_enable_init_clocks();
2054
2055         /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
2056         vclk = clk_get(NULL, "virt_prcm_set");
2057         sclk = clk_get(NULL, "sys_ck");
2058         dclk = clk_get(NULL, "dpll_ck");
2059
2060         return 0;
2061 }
2062