2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/usb.h>
24 #include <linux/pci.h>
25 #include <linux/slab.h>
26 #include <linux/dmapool.h>
31 * Allocates a generic ring segment from the ring pool, sets the dma address,
32 * initializes the segment to zero, and sets the private next pointer to NULL.
35 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
37 static struct xhci_segment
*xhci_segment_alloc(struct xhci_hcd
*xhci
, gfp_t flags
)
39 struct xhci_segment
*seg
;
42 seg
= kzalloc(sizeof *seg
, flags
);
45 xhci_dbg(xhci
, "Allocating priv segment structure at %p\n", seg
);
47 seg
->trbs
= dma_pool_alloc(xhci
->segment_pool
, flags
, &dma
);
52 xhci_dbg(xhci
, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n",
53 seg
->trbs
, (unsigned long long)dma
);
55 memset(seg
->trbs
, 0, SEGMENT_SIZE
);
62 static void xhci_segment_free(struct xhci_hcd
*xhci
, struct xhci_segment
*seg
)
67 xhci_dbg(xhci
, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n",
68 seg
->trbs
, (unsigned long long)seg
->dma
);
69 dma_pool_free(xhci
->segment_pool
, seg
->trbs
, seg
->dma
);
72 xhci_dbg(xhci
, "Freeing priv segment structure at %p\n", seg
);
77 * Make the prev segment point to the next segment.
79 * Change the last TRB in the prev segment to be a Link TRB which points to the
80 * DMA address of the next segment. The caller needs to set any Link TRB
81 * related flags, such as End TRB, Toggle Cycle, and no snoop.
83 static void xhci_link_segments(struct xhci_hcd
*xhci
, struct xhci_segment
*prev
,
84 struct xhci_segment
*next
, bool link_trbs
)
92 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.
93 segment_ptr
= cpu_to_le64(next
->dma
);
95 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
96 val
= le32_to_cpu(prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
);
97 val
&= ~TRB_TYPE_BITMASK
;
98 val
|= TRB_TYPE(TRB_LINK
);
99 /* Always set the chain bit with 0.95 hardware */
100 if (xhci_link_trb_quirk(xhci
))
102 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
= cpu_to_le32(val
);
104 xhci_dbg(xhci
, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
105 (unsigned long long)prev
->dma
,
106 (unsigned long long)next
->dma
);
109 /* XXX: Do we need the hcd structure in all these functions? */
110 void xhci_ring_free(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
112 struct xhci_segment
*seg
;
113 struct xhci_segment
*first_seg
;
115 if (!ring
|| !ring
->first_seg
)
117 first_seg
= ring
->first_seg
;
118 seg
= first_seg
->next
;
119 xhci_dbg(xhci
, "Freeing ring at %p\n", ring
);
120 while (seg
!= first_seg
) {
121 struct xhci_segment
*next
= seg
->next
;
122 xhci_segment_free(xhci
, seg
);
125 xhci_segment_free(xhci
, first_seg
);
126 ring
->first_seg
= NULL
;
130 static void xhci_initialize_ring_info(struct xhci_ring
*ring
)
132 /* The ring is empty, so the enqueue pointer == dequeue pointer */
133 ring
->enqueue
= ring
->first_seg
->trbs
;
134 ring
->enq_seg
= ring
->first_seg
;
135 ring
->dequeue
= ring
->enqueue
;
136 ring
->deq_seg
= ring
->first_seg
;
137 /* The ring is initialized to 0. The producer must write 1 to the cycle
138 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
139 * compare CCS to the cycle bit to check ownership, so CCS = 1.
141 ring
->cycle_state
= 1;
142 /* Not necessary for new rings, but needed for re-initialized rings */
143 ring
->enq_updates
= 0;
144 ring
->deq_updates
= 0;
148 * Create a new ring with zero or more segments.
150 * Link each segment together into a ring.
151 * Set the end flag and the cycle toggle bit on the last segment.
152 * See section 4.9.1 and figures 15 and 16.
154 static struct xhci_ring
*xhci_ring_alloc(struct xhci_hcd
*xhci
,
155 unsigned int num_segs
, bool link_trbs
, gfp_t flags
)
157 struct xhci_ring
*ring
;
158 struct xhci_segment
*prev
;
160 ring
= kzalloc(sizeof *(ring
), flags
);
161 xhci_dbg(xhci
, "Allocating ring at %p\n", ring
);
165 INIT_LIST_HEAD(&ring
->td_list
);
169 ring
->first_seg
= xhci_segment_alloc(xhci
, flags
);
170 if (!ring
->first_seg
)
174 prev
= ring
->first_seg
;
175 while (num_segs
> 0) {
176 struct xhci_segment
*next
;
178 next
= xhci_segment_alloc(xhci
, flags
);
181 xhci_link_segments(xhci
, prev
, next
, link_trbs
);
186 xhci_link_segments(xhci
, prev
, ring
->first_seg
, link_trbs
);
189 /* See section 4.9.2.1 and 6.4.4.1 */
190 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.
191 control
|= cpu_to_le32(LINK_TOGGLE
);
192 xhci_dbg(xhci
, "Wrote link toggle flag to"
193 " segment %p (virtual), 0x%llx (DMA)\n",
194 prev
, (unsigned long long)prev
->dma
);
196 xhci_initialize_ring_info(ring
);
200 xhci_ring_free(xhci
, ring
);
204 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd
*xhci
,
205 struct xhci_virt_device
*virt_dev
,
206 unsigned int ep_index
)
210 rings_cached
= virt_dev
->num_rings_cached
;
211 if (rings_cached
< XHCI_MAX_RINGS_CACHED
) {
212 virt_dev
->num_rings_cached
++;
213 rings_cached
= virt_dev
->num_rings_cached
;
214 virt_dev
->ring_cache
[rings_cached
] =
215 virt_dev
->eps
[ep_index
].ring
;
216 xhci_dbg(xhci
, "Cached old ring, "
217 "%d ring%s cached\n",
219 (rings_cached
> 1) ? "s" : "");
221 xhci_ring_free(xhci
, virt_dev
->eps
[ep_index
].ring
);
222 xhci_dbg(xhci
, "Ring cache full (%d rings), "
224 virt_dev
->num_rings_cached
);
226 virt_dev
->eps
[ep_index
].ring
= NULL
;
229 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
230 * pointers to the beginning of the ring.
232 static void xhci_reinit_cached_ring(struct xhci_hcd
*xhci
,
233 struct xhci_ring
*ring
)
235 struct xhci_segment
*seg
= ring
->first_seg
;
238 sizeof(union xhci_trb
)*TRBS_PER_SEGMENT
);
239 /* All endpoint rings have link TRBs */
240 xhci_link_segments(xhci
, seg
, seg
->next
, 1);
242 } while (seg
!= ring
->first_seg
);
243 xhci_initialize_ring_info(ring
);
244 /* td list should be empty since all URBs have been cancelled,
245 * but just in case...
247 INIT_LIST_HEAD(&ring
->td_list
);
250 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
252 static struct xhci_container_ctx
*xhci_alloc_container_ctx(struct xhci_hcd
*xhci
,
253 int type
, gfp_t flags
)
255 struct xhci_container_ctx
*ctx
= kzalloc(sizeof(*ctx
), flags
);
259 BUG_ON((type
!= XHCI_CTX_TYPE_DEVICE
) && (type
!= XHCI_CTX_TYPE_INPUT
));
261 ctx
->size
= HCC_64BYTE_CONTEXT(xhci
->hcc_params
) ? 2048 : 1024;
262 if (type
== XHCI_CTX_TYPE_INPUT
)
263 ctx
->size
+= CTX_SIZE(xhci
->hcc_params
);
265 ctx
->bytes
= dma_pool_alloc(xhci
->device_pool
, flags
, &ctx
->dma
);
266 memset(ctx
->bytes
, 0, ctx
->size
);
270 static void xhci_free_container_ctx(struct xhci_hcd
*xhci
,
271 struct xhci_container_ctx
*ctx
)
275 dma_pool_free(xhci
->device_pool
, ctx
->bytes
, ctx
->dma
);
279 struct xhci_input_control_ctx
*xhci_get_input_control_ctx(struct xhci_hcd
*xhci
,
280 struct xhci_container_ctx
*ctx
)
282 BUG_ON(ctx
->type
!= XHCI_CTX_TYPE_INPUT
);
283 return (struct xhci_input_control_ctx
*)ctx
->bytes
;
286 struct xhci_slot_ctx
*xhci_get_slot_ctx(struct xhci_hcd
*xhci
,
287 struct xhci_container_ctx
*ctx
)
289 if (ctx
->type
== XHCI_CTX_TYPE_DEVICE
)
290 return (struct xhci_slot_ctx
*)ctx
->bytes
;
292 return (struct xhci_slot_ctx
*)
293 (ctx
->bytes
+ CTX_SIZE(xhci
->hcc_params
));
296 struct xhci_ep_ctx
*xhci_get_ep_ctx(struct xhci_hcd
*xhci
,
297 struct xhci_container_ctx
*ctx
,
298 unsigned int ep_index
)
300 /* increment ep index by offset of start of ep ctx array */
302 if (ctx
->type
== XHCI_CTX_TYPE_INPUT
)
305 return (struct xhci_ep_ctx
*)
306 (ctx
->bytes
+ (ep_index
* CTX_SIZE(xhci
->hcc_params
)));
310 /***************** Streams structures manipulation *************************/
312 static void xhci_free_stream_ctx(struct xhci_hcd
*xhci
,
313 unsigned int num_stream_ctxs
,
314 struct xhci_stream_ctx
*stream_ctx
, dma_addr_t dma
)
316 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
318 if (num_stream_ctxs
> MEDIUM_STREAM_ARRAY_SIZE
)
319 pci_free_consistent(pdev
,
320 sizeof(struct xhci_stream_ctx
)*num_stream_ctxs
,
322 else if (num_stream_ctxs
<= SMALL_STREAM_ARRAY_SIZE
)
323 return dma_pool_free(xhci
->small_streams_pool
,
326 return dma_pool_free(xhci
->medium_streams_pool
,
331 * The stream context array for each endpoint with bulk streams enabled can
332 * vary in size, based on:
333 * - how many streams the endpoint supports,
334 * - the maximum primary stream array size the host controller supports,
335 * - and how many streams the device driver asks for.
337 * The stream context array must be a power of 2, and can be as small as
338 * 64 bytes or as large as 1MB.
340 static struct xhci_stream_ctx
*xhci_alloc_stream_ctx(struct xhci_hcd
*xhci
,
341 unsigned int num_stream_ctxs
, dma_addr_t
*dma
,
344 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
346 if (num_stream_ctxs
> MEDIUM_STREAM_ARRAY_SIZE
)
347 return pci_alloc_consistent(pdev
,
348 sizeof(struct xhci_stream_ctx
)*num_stream_ctxs
,
350 else if (num_stream_ctxs
<= SMALL_STREAM_ARRAY_SIZE
)
351 return dma_pool_alloc(xhci
->small_streams_pool
,
354 return dma_pool_alloc(xhci
->medium_streams_pool
,
358 struct xhci_ring
*xhci_dma_to_transfer_ring(
359 struct xhci_virt_ep
*ep
,
362 if (ep
->ep_state
& EP_HAS_STREAMS
)
363 return radix_tree_lookup(&ep
->stream_info
->trb_address_map
,
364 address
>> SEGMENT_SHIFT
);
368 /* Only use this when you know stream_info is valid */
369 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
370 static struct xhci_ring
*dma_to_stream_ring(
371 struct xhci_stream_info
*stream_info
,
374 return radix_tree_lookup(&stream_info
->trb_address_map
,
375 address
>> SEGMENT_SHIFT
);
377 #endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */
379 struct xhci_ring
*xhci_stream_id_to_ring(
380 struct xhci_virt_device
*dev
,
381 unsigned int ep_index
,
382 unsigned int stream_id
)
384 struct xhci_virt_ep
*ep
= &dev
->eps
[ep_index
];
388 if (!ep
->stream_info
)
391 if (stream_id
> ep
->stream_info
->num_streams
)
393 return ep
->stream_info
->stream_rings
[stream_id
];
396 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
397 static int xhci_test_radix_tree(struct xhci_hcd
*xhci
,
398 unsigned int num_streams
,
399 struct xhci_stream_info
*stream_info
)
402 struct xhci_ring
*cur_ring
;
405 for (cur_stream
= 1; cur_stream
< num_streams
; cur_stream
++) {
406 struct xhci_ring
*mapped_ring
;
407 int trb_size
= sizeof(union xhci_trb
);
409 cur_ring
= stream_info
->stream_rings
[cur_stream
];
410 for (addr
= cur_ring
->first_seg
->dma
;
411 addr
< cur_ring
->first_seg
->dma
+ SEGMENT_SIZE
;
413 mapped_ring
= dma_to_stream_ring(stream_info
, addr
);
414 if (cur_ring
!= mapped_ring
) {
415 xhci_warn(xhci
, "WARN: DMA address 0x%08llx "
416 "didn't map to stream ID %u; "
417 "mapped to ring %p\n",
418 (unsigned long long) addr
,
424 /* One TRB after the end of the ring segment shouldn't return a
425 * pointer to the current ring (although it may be a part of a
428 mapped_ring
= dma_to_stream_ring(stream_info
, addr
);
429 if (mapped_ring
!= cur_ring
) {
430 /* One TRB before should also fail */
431 addr
= cur_ring
->first_seg
->dma
- trb_size
;
432 mapped_ring
= dma_to_stream_ring(stream_info
, addr
);
434 if (mapped_ring
== cur_ring
) {
435 xhci_warn(xhci
, "WARN: Bad DMA address 0x%08llx "
436 "mapped to valid stream ID %u; "
437 "mapped ring = %p\n",
438 (unsigned long long) addr
,
446 #endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */
449 * Change an endpoint's internal structure so it supports stream IDs. The
450 * number of requested streams includes stream 0, which cannot be used by device
453 * The number of stream contexts in the stream context array may be bigger than
454 * the number of streams the driver wants to use. This is because the number of
455 * stream context array entries must be a power of two.
457 * We need a radix tree for mapping physical addresses of TRBs to which stream
458 * ID they belong to. We need to do this because the host controller won't tell
459 * us which stream ring the TRB came from. We could store the stream ID in an
460 * event data TRB, but that doesn't help us for the cancellation case, since the
461 * endpoint may stop before it reaches that event data TRB.
463 * The radix tree maps the upper portion of the TRB DMA address to a ring
464 * segment that has the same upper portion of DMA addresses. For example, say I
465 * have segments of size 1KB, that are always 64-byte aligned. A segment may
466 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
467 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to
468 * pass the radix tree a key to get the right stream ID:
470 * 0x10c90fff >> 10 = 0x43243
471 * 0x10c912c0 >> 10 = 0x43244
472 * 0x10c91400 >> 10 = 0x43245
474 * Obviously, only those TRBs with DMA addresses that are within the segment
475 * will make the radix tree return the stream ID for that ring.
477 * Caveats for the radix tree:
479 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
480 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
481 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
482 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
483 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
484 * extended systems (where the DMA address can be bigger than 32-bits),
485 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
487 struct xhci_stream_info
*xhci_alloc_stream_info(struct xhci_hcd
*xhci
,
488 unsigned int num_stream_ctxs
,
489 unsigned int num_streams
, gfp_t mem_flags
)
491 struct xhci_stream_info
*stream_info
;
493 struct xhci_ring
*cur_ring
;
498 xhci_dbg(xhci
, "Allocating %u streams and %u "
499 "stream context array entries.\n",
500 num_streams
, num_stream_ctxs
);
501 if (xhci
->cmd_ring_reserved_trbs
== MAX_RSVD_CMD_TRBS
) {
502 xhci_dbg(xhci
, "Command ring has no reserved TRBs available\n");
505 xhci
->cmd_ring_reserved_trbs
++;
507 stream_info
= kzalloc(sizeof(struct xhci_stream_info
), mem_flags
);
511 stream_info
->num_streams
= num_streams
;
512 stream_info
->num_stream_ctxs
= num_stream_ctxs
;
514 /* Initialize the array of virtual pointers to stream rings. */
515 stream_info
->stream_rings
= kzalloc(
516 sizeof(struct xhci_ring
*)*num_streams
,
518 if (!stream_info
->stream_rings
)
521 /* Initialize the array of DMA addresses for stream rings for the HW. */
522 stream_info
->stream_ctx_array
= xhci_alloc_stream_ctx(xhci
,
523 num_stream_ctxs
, &stream_info
->ctx_array_dma
,
525 if (!stream_info
->stream_ctx_array
)
527 memset(stream_info
->stream_ctx_array
, 0,
528 sizeof(struct xhci_stream_ctx
)*num_stream_ctxs
);
530 /* Allocate everything needed to free the stream rings later */
531 stream_info
->free_streams_command
=
532 xhci_alloc_command(xhci
, true, true, mem_flags
);
533 if (!stream_info
->free_streams_command
)
536 INIT_RADIX_TREE(&stream_info
->trb_address_map
, GFP_ATOMIC
);
538 /* Allocate rings for all the streams that the driver will use,
539 * and add their segment DMA addresses to the radix tree.
540 * Stream 0 is reserved.
542 for (cur_stream
= 1; cur_stream
< num_streams
; cur_stream
++) {
543 stream_info
->stream_rings
[cur_stream
] =
544 xhci_ring_alloc(xhci
, 1, true, mem_flags
);
545 cur_ring
= stream_info
->stream_rings
[cur_stream
];
548 cur_ring
->stream_id
= cur_stream
;
549 /* Set deq ptr, cycle bit, and stream context type */
550 addr
= cur_ring
->first_seg
->dma
|
551 SCT_FOR_CTX(SCT_PRI_TR
) |
552 cur_ring
->cycle_state
;
553 stream_info
->stream_ctx_array
[cur_stream
].
554 stream_ring
= cpu_to_le64(addr
);
555 xhci_dbg(xhci
, "Setting stream %d ring ptr to 0x%08llx\n",
556 cur_stream
, (unsigned long long) addr
);
558 key
= (unsigned long)
559 (cur_ring
->first_seg
->dma
>> SEGMENT_SHIFT
);
560 ret
= radix_tree_insert(&stream_info
->trb_address_map
,
563 xhci_ring_free(xhci
, cur_ring
);
564 stream_info
->stream_rings
[cur_stream
] = NULL
;
568 /* Leave the other unused stream ring pointers in the stream context
569 * array initialized to zero. This will cause the xHC to give us an
570 * error if the device asks for a stream ID we don't have setup (if it
571 * was any other way, the host controller would assume the ring is
572 * "empty" and wait forever for data to be queued to that stream ID).
575 /* Do a little test on the radix tree to make sure it returns the
578 if (xhci_test_radix_tree(xhci
, num_streams
, stream_info
))
585 for (cur_stream
= 1; cur_stream
< num_streams
; cur_stream
++) {
586 cur_ring
= stream_info
->stream_rings
[cur_stream
];
588 addr
= cur_ring
->first_seg
->dma
;
589 radix_tree_delete(&stream_info
->trb_address_map
,
590 addr
>> SEGMENT_SHIFT
);
591 xhci_ring_free(xhci
, cur_ring
);
592 stream_info
->stream_rings
[cur_stream
] = NULL
;
595 xhci_free_command(xhci
, stream_info
->free_streams_command
);
597 kfree(stream_info
->stream_rings
);
601 xhci
->cmd_ring_reserved_trbs
--;
605 * Sets the MaxPStreams field and the Linear Stream Array field.
606 * Sets the dequeue pointer to the stream context array.
608 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd
*xhci
,
609 struct xhci_ep_ctx
*ep_ctx
,
610 struct xhci_stream_info
*stream_info
)
612 u32 max_primary_streams
;
613 /* MaxPStreams is the number of stream context array entries, not the
614 * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
615 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
617 max_primary_streams
= fls(stream_info
->num_stream_ctxs
) - 2;
618 xhci_dbg(xhci
, "Setting number of stream ctx array entries to %u\n",
619 1 << (max_primary_streams
+ 1));
620 ep_ctx
->ep_info
&= cpu_to_le32(~EP_MAXPSTREAMS_MASK
);
621 ep_ctx
->ep_info
|= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams
)
623 ep_ctx
->deq
= cpu_to_le64(stream_info
->ctx_array_dma
);
627 * Sets the MaxPStreams field and the Linear Stream Array field to 0.
628 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
629 * not at the beginning of the ring).
631 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd
*xhci
,
632 struct xhci_ep_ctx
*ep_ctx
,
633 struct xhci_virt_ep
*ep
)
636 ep_ctx
->ep_info
&= cpu_to_le32(~(EP_MAXPSTREAMS_MASK
| EP_HAS_LSA
));
637 addr
= xhci_trb_virt_to_dma(ep
->ring
->deq_seg
, ep
->ring
->dequeue
);
638 ep_ctx
->deq
= cpu_to_le64(addr
| ep
->ring
->cycle_state
);
641 /* Frees all stream contexts associated with the endpoint,
643 * Caller should fix the endpoint context streams fields.
645 void xhci_free_stream_info(struct xhci_hcd
*xhci
,
646 struct xhci_stream_info
*stream_info
)
649 struct xhci_ring
*cur_ring
;
655 for (cur_stream
= 1; cur_stream
< stream_info
->num_streams
;
657 cur_ring
= stream_info
->stream_rings
[cur_stream
];
659 addr
= cur_ring
->first_seg
->dma
;
660 radix_tree_delete(&stream_info
->trb_address_map
,
661 addr
>> SEGMENT_SHIFT
);
662 xhci_ring_free(xhci
, cur_ring
);
663 stream_info
->stream_rings
[cur_stream
] = NULL
;
666 xhci_free_command(xhci
, stream_info
->free_streams_command
);
667 xhci
->cmd_ring_reserved_trbs
--;
668 if (stream_info
->stream_ctx_array
)
669 xhci_free_stream_ctx(xhci
,
670 stream_info
->num_stream_ctxs
,
671 stream_info
->stream_ctx_array
,
672 stream_info
->ctx_array_dma
);
675 kfree(stream_info
->stream_rings
);
680 /***************** Device context manipulation *************************/
682 static void xhci_init_endpoint_timer(struct xhci_hcd
*xhci
,
683 struct xhci_virt_ep
*ep
)
685 init_timer(&ep
->stop_cmd_timer
);
686 ep
->stop_cmd_timer
.data
= (unsigned long) ep
;
687 ep
->stop_cmd_timer
.function
= xhci_stop_endpoint_command_watchdog
;
691 /* All the xhci_tds in the ring's TD list should be freed at this point */
692 void xhci_free_virt_device(struct xhci_hcd
*xhci
, int slot_id
)
694 struct xhci_virt_device
*dev
;
697 /* Slot ID 0 is reserved */
698 if (slot_id
== 0 || !xhci
->devs
[slot_id
])
701 dev
= xhci
->devs
[slot_id
];
702 xhci
->dcbaa
->dev_context_ptrs
[slot_id
] = 0;
706 for (i
= 0; i
< 31; ++i
) {
707 if (dev
->eps
[i
].ring
)
708 xhci_ring_free(xhci
, dev
->eps
[i
].ring
);
709 if (dev
->eps
[i
].stream_info
)
710 xhci_free_stream_info(xhci
,
711 dev
->eps
[i
].stream_info
);
714 if (dev
->ring_cache
) {
715 for (i
= 0; i
< dev
->num_rings_cached
; i
++)
716 xhci_ring_free(xhci
, dev
->ring_cache
[i
]);
717 kfree(dev
->ring_cache
);
721 xhci_free_container_ctx(xhci
, dev
->in_ctx
);
723 xhci_free_container_ctx(xhci
, dev
->out_ctx
);
725 kfree(xhci
->devs
[slot_id
]);
726 xhci
->devs
[slot_id
] = NULL
;
729 int xhci_alloc_virt_device(struct xhci_hcd
*xhci
, int slot_id
,
730 struct usb_device
*udev
, gfp_t flags
)
732 struct xhci_virt_device
*dev
;
735 /* Slot ID 0 is reserved */
736 if (slot_id
== 0 || xhci
->devs
[slot_id
]) {
737 xhci_warn(xhci
, "Bad Slot ID %d\n", slot_id
);
741 xhci
->devs
[slot_id
] = kzalloc(sizeof(*xhci
->devs
[slot_id
]), flags
);
742 if (!xhci
->devs
[slot_id
])
744 dev
= xhci
->devs
[slot_id
];
746 /* Allocate the (output) device context that will be used in the HC. */
747 dev
->out_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_DEVICE
, flags
);
751 xhci_dbg(xhci
, "Slot %d output ctx = 0x%llx (dma)\n", slot_id
,
752 (unsigned long long)dev
->out_ctx
->dma
);
754 /* Allocate the (input) device context for address device command */
755 dev
->in_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_INPUT
, flags
);
759 xhci_dbg(xhci
, "Slot %d input ctx = 0x%llx (dma)\n", slot_id
,
760 (unsigned long long)dev
->in_ctx
->dma
);
762 /* Initialize the cancellation list and watchdog timers for each ep */
763 for (i
= 0; i
< 31; i
++) {
764 xhci_init_endpoint_timer(xhci
, &dev
->eps
[i
]);
765 INIT_LIST_HEAD(&dev
->eps
[i
].cancelled_td_list
);
768 /* Allocate endpoint 0 ring */
769 dev
->eps
[0].ring
= xhci_ring_alloc(xhci
, 1, true, flags
);
770 if (!dev
->eps
[0].ring
)
773 /* Allocate pointers to the ring cache */
774 dev
->ring_cache
= kzalloc(
775 sizeof(struct xhci_ring
*)*XHCI_MAX_RINGS_CACHED
,
777 if (!dev
->ring_cache
)
779 dev
->num_rings_cached
= 0;
781 init_completion(&dev
->cmd_completion
);
782 INIT_LIST_HEAD(&dev
->cmd_list
);
785 /* Point to output device context in dcbaa. */
786 xhci
->dcbaa
->dev_context_ptrs
[slot_id
] = cpu_to_le64(dev
->out_ctx
->dma
);
787 xhci_dbg(xhci
, "Set slot id %d dcbaa entry %p to 0x%llx\n",
789 &xhci
->dcbaa
->dev_context_ptrs
[slot_id
],
790 (unsigned long long) le64_to_cpu(xhci
->dcbaa
->dev_context_ptrs
[slot_id
]));
794 xhci_free_virt_device(xhci
, slot_id
);
798 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd
*xhci
,
799 struct usb_device
*udev
)
801 struct xhci_virt_device
*virt_dev
;
802 struct xhci_ep_ctx
*ep0_ctx
;
803 struct xhci_ring
*ep_ring
;
805 virt_dev
= xhci
->devs
[udev
->slot_id
];
806 ep0_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, 0);
807 ep_ring
= virt_dev
->eps
[0].ring
;
809 * FIXME we don't keep track of the dequeue pointer very well after a
810 * Set TR dequeue pointer, so we're setting the dequeue pointer of the
811 * host to our enqueue pointer. This should only be called after a
812 * configured device has reset, so all control transfers should have
813 * been completed or cancelled before the reset.
815 ep0_ctx
->deq
= cpu_to_le64(xhci_trb_virt_to_dma(ep_ring
->enq_seg
,
817 | ep_ring
->cycle_state
);
821 * The xHCI roothub may have ports of differing speeds in any order in the port
822 * status registers. xhci->port_array provides an array of the port speed for
823 * each offset into the port status registers.
825 * The xHCI hardware wants to know the roothub port number that the USB device
826 * is attached to (or the roothub port its ancestor hub is attached to). All we
827 * know is the index of that port under either the USB 2.0 or the USB 3.0
828 * roothub, but that doesn't give us the real index into the HW port status
829 * registers. Scan through the xHCI roothub port array, looking for the Nth
830 * entry of the correct port speed. Return the port number of that entry.
832 static u32
xhci_find_real_port_number(struct xhci_hcd
*xhci
,
833 struct usb_device
*udev
)
835 struct usb_device
*top_dev
;
836 unsigned int num_similar_speed_ports
;
837 unsigned int faked_port_num
;
840 for (top_dev
= udev
; top_dev
->parent
&& top_dev
->parent
->parent
;
841 top_dev
= top_dev
->parent
)
842 /* Found device below root hub */;
843 faked_port_num
= top_dev
->portnum
;
844 for (i
= 0, num_similar_speed_ports
= 0;
845 i
< HCS_MAX_PORTS(xhci
->hcs_params1
); i
++) {
846 u8 port_speed
= xhci
->port_array
[i
];
849 * Skip ports that don't have known speeds, or have duplicate
850 * Extended Capabilities port speed entries.
852 if (port_speed
== 0 || port_speed
== DUPLICATE_ENTRY
)
856 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
857 * 1.1 ports are under the USB 2.0 hub. If the port speed
858 * matches the device speed, it's a similar speed port.
860 if ((port_speed
== 0x03) == (udev
->speed
== USB_SPEED_SUPER
))
861 num_similar_speed_ports
++;
862 if (num_similar_speed_ports
== faked_port_num
)
863 /* Roothub ports are numbered from 1 to N */
869 /* Setup an xHCI virtual device for a Set Address command */
870 int xhci_setup_addressable_virt_dev(struct xhci_hcd
*xhci
, struct usb_device
*udev
)
872 struct xhci_virt_device
*dev
;
873 struct xhci_ep_ctx
*ep0_ctx
;
874 struct xhci_slot_ctx
*slot_ctx
;
875 struct xhci_input_control_ctx
*ctrl_ctx
;
877 struct usb_device
*top_dev
;
879 dev
= xhci
->devs
[udev
->slot_id
];
880 /* Slot ID 0 is reserved */
881 if (udev
->slot_id
== 0 || !dev
) {
882 xhci_warn(xhci
, "Slot ID %d is not assigned to this device\n",
886 ep0_ctx
= xhci_get_ep_ctx(xhci
, dev
->in_ctx
, 0);
887 ctrl_ctx
= xhci_get_input_control_ctx(xhci
, dev
->in_ctx
);
888 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->in_ctx
);
890 /* 2) New slot context and endpoint 0 context are valid*/
891 ctrl_ctx
->add_flags
= cpu_to_le32(SLOT_FLAG
| EP0_FLAG
);
893 /* 3) Only the control endpoint is valid - one endpoint context */
894 slot_ctx
->dev_info
|= cpu_to_le32(LAST_CTX(1) | (u32
) udev
->route
);
895 switch (udev
->speed
) {
896 case USB_SPEED_SUPER
:
897 slot_ctx
->dev_info
|= cpu_to_le32((u32
) SLOT_SPEED_SS
);
900 slot_ctx
->dev_info
|= cpu_to_le32((u32
) SLOT_SPEED_HS
);
903 slot_ctx
->dev_info
|= cpu_to_le32((u32
) SLOT_SPEED_FS
);
906 slot_ctx
->dev_info
|= cpu_to_le32((u32
) SLOT_SPEED_LS
);
908 case USB_SPEED_WIRELESS
:
909 xhci_dbg(xhci
, "FIXME xHCI doesn't support wireless speeds\n");
913 /* Speed was set earlier, this shouldn't happen. */
916 /* Find the root hub port this device is under */
917 port_num
= xhci_find_real_port_number(xhci
, udev
);
920 slot_ctx
->dev_info2
|= cpu_to_le32((u32
) ROOT_HUB_PORT(port_num
));
921 /* Set the port number in the virtual_device to the faked port number */
922 for (top_dev
= udev
; top_dev
->parent
&& top_dev
->parent
->parent
;
923 top_dev
= top_dev
->parent
)
924 /* Found device below root hub */;
925 dev
->port
= top_dev
->portnum
;
926 xhci_dbg(xhci
, "Set root hub portnum to %d\n", port_num
);
927 xhci_dbg(xhci
, "Set fake root hub portnum to %d\n", dev
->port
);
929 /* Is this a LS/FS device under an external HS hub? */
930 if (udev
->tt
&& udev
->tt
->hub
->parent
) {
931 slot_ctx
->tt_info
= cpu_to_le32(udev
->tt
->hub
->slot_id
|
932 (udev
->ttport
<< 8));
934 slot_ctx
->dev_info
|= cpu_to_le32(DEV_MTT
);
936 xhci_dbg(xhci
, "udev->tt = %p\n", udev
->tt
);
937 xhci_dbg(xhci
, "udev->ttport = 0x%x\n", udev
->ttport
);
939 /* Step 4 - ring already allocated */
941 ep0_ctx
->ep_info2
= cpu_to_le32(EP_TYPE(CTRL_EP
));
943 * XXX: Not sure about wireless USB devices.
945 switch (udev
->speed
) {
946 case USB_SPEED_SUPER
:
947 ep0_ctx
->ep_info2
|= cpu_to_le32(MAX_PACKET(512));
950 /* USB core guesses at a 64-byte max packet first for FS devices */
952 ep0_ctx
->ep_info2
|= cpu_to_le32(MAX_PACKET(64));
955 ep0_ctx
->ep_info2
|= cpu_to_le32(MAX_PACKET(8));
957 case USB_SPEED_WIRELESS
:
958 xhci_dbg(xhci
, "FIXME xHCI doesn't support wireless speeds\n");
965 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
966 ep0_ctx
->ep_info2
|= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
968 ep0_ctx
->deq
= cpu_to_le64(dev
->eps
[0].ring
->first_seg
->dma
|
969 dev
->eps
[0].ring
->cycle_state
);
971 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
977 * Convert interval expressed as 2^(bInterval - 1) == interval into
978 * straight exponent value 2^n == interval.
981 static unsigned int xhci_parse_exponent_interval(struct usb_device
*udev
,
982 struct usb_host_endpoint
*ep
)
984 unsigned int interval
;
986 interval
= clamp_val(ep
->desc
.bInterval
, 1, 16) - 1;
987 if (interval
!= ep
->desc
.bInterval
- 1)
989 "ep %#x - rounding interval to %d microframes\n",
990 ep
->desc
.bEndpointAddress
,
997 * Convert bInterval expressed in frames (in 1-255 range) to exponent of
998 * microframes, rounded down to nearest power of 2.
1000 static unsigned int xhci_parse_frame_interval(struct usb_device
*udev
,
1001 struct usb_host_endpoint
*ep
)
1003 unsigned int interval
;
1005 interval
= fls(8 * ep
->desc
.bInterval
) - 1;
1006 interval
= clamp_val(interval
, 3, 10);
1007 if ((1 << interval
) != 8 * ep
->desc
.bInterval
)
1008 dev_warn(&udev
->dev
,
1009 "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1010 ep
->desc
.bEndpointAddress
,
1012 8 * ep
->desc
.bInterval
);
1017 /* Return the polling or NAK interval.
1019 * The polling interval is expressed in "microframes". If xHCI's Interval field
1020 * is set to N, it will service the endpoint every 2^(Interval)*125us.
1022 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1025 static unsigned int xhci_get_endpoint_interval(struct usb_device
*udev
,
1026 struct usb_host_endpoint
*ep
)
1028 unsigned int interval
= 0;
1030 switch (udev
->speed
) {
1031 case USB_SPEED_HIGH
:
1033 if (usb_endpoint_xfer_control(&ep
->desc
) ||
1034 usb_endpoint_xfer_bulk(&ep
->desc
)) {
1035 interval
= ep
->desc
.bInterval
;
1038 /* Fall through - SS and HS isoc/int have same decoding */
1040 case USB_SPEED_SUPER
:
1041 if (usb_endpoint_xfer_int(&ep
->desc
) ||
1042 usb_endpoint_xfer_isoc(&ep
->desc
)) {
1043 interval
= xhci_parse_exponent_interval(udev
, ep
);
1047 case USB_SPEED_FULL
:
1048 if (usb_endpoint_xfer_isoc(&ep
->desc
)) {
1049 interval
= xhci_parse_exponent_interval(udev
, ep
);
1053 * Fall through for interrupt endpoint interval decoding
1054 * since it uses the same rules as low speed interrupt
1059 if (usb_endpoint_xfer_int(&ep
->desc
) ||
1060 usb_endpoint_xfer_isoc(&ep
->desc
)) {
1062 interval
= xhci_parse_frame_interval(udev
, ep
);
1069 return EP_INTERVAL(interval
);
1072 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1073 * High speed endpoint descriptors can define "the number of additional
1074 * transaction opportunities per microframe", but that goes in the Max Burst
1075 * endpoint context field.
1077 static u32
xhci_get_endpoint_mult(struct usb_device
*udev
,
1078 struct usb_host_endpoint
*ep
)
1080 if (udev
->speed
!= USB_SPEED_SUPER
||
1081 !usb_endpoint_xfer_isoc(&ep
->desc
))
1083 return ep
->ss_ep_comp
.bmAttributes
;
1086 static u32
xhci_get_endpoint_type(struct usb_device
*udev
,
1087 struct usb_host_endpoint
*ep
)
1092 in
= usb_endpoint_dir_in(&ep
->desc
);
1093 if (usb_endpoint_xfer_control(&ep
->desc
)) {
1094 type
= EP_TYPE(CTRL_EP
);
1095 } else if (usb_endpoint_xfer_bulk(&ep
->desc
)) {
1097 type
= EP_TYPE(BULK_IN_EP
);
1099 type
= EP_TYPE(BULK_OUT_EP
);
1100 } else if (usb_endpoint_xfer_isoc(&ep
->desc
)) {
1102 type
= EP_TYPE(ISOC_IN_EP
);
1104 type
= EP_TYPE(ISOC_OUT_EP
);
1105 } else if (usb_endpoint_xfer_int(&ep
->desc
)) {
1107 type
= EP_TYPE(INT_IN_EP
);
1109 type
= EP_TYPE(INT_OUT_EP
);
1116 /* Return the maximum endpoint service interval time (ESIT) payload.
1117 * Basically, this is the maxpacket size, multiplied by the burst size
1120 static u32
xhci_get_max_esit_payload(struct xhci_hcd
*xhci
,
1121 struct usb_device
*udev
,
1122 struct usb_host_endpoint
*ep
)
1127 /* Only applies for interrupt or isochronous endpoints */
1128 if (usb_endpoint_xfer_control(&ep
->desc
) ||
1129 usb_endpoint_xfer_bulk(&ep
->desc
))
1132 if (udev
->speed
== USB_SPEED_SUPER
)
1133 return le16_to_cpu(ep
->ss_ep_comp
.wBytesPerInterval
);
1135 max_packet
= GET_MAX_PACKET(le16_to_cpu(ep
->desc
.wMaxPacketSize
));
1136 max_burst
= (le16_to_cpu(ep
->desc
.wMaxPacketSize
) & 0x1800) >> 11;
1137 /* A 0 in max burst means 1 transfer per ESIT */
1138 return max_packet
* (max_burst
+ 1);
1141 /* Set up an endpoint with one ring segment. Do not allocate stream rings.
1142 * Drivers will have to call usb_alloc_streams() to do that.
1144 int xhci_endpoint_init(struct xhci_hcd
*xhci
,
1145 struct xhci_virt_device
*virt_dev
,
1146 struct usb_device
*udev
,
1147 struct usb_host_endpoint
*ep
,
1150 unsigned int ep_index
;
1151 struct xhci_ep_ctx
*ep_ctx
;
1152 struct xhci_ring
*ep_ring
;
1153 unsigned int max_packet
;
1154 unsigned int max_burst
;
1155 u32 max_esit_payload
;
1157 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1158 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
1160 /* Set up the endpoint ring */
1162 * Isochronous endpoint ring needs bigger size because one isoc URB
1163 * carries multiple packets and it will insert multiple tds to the
1165 * This should be replaced with dynamic ring resizing in the future.
1167 if (usb_endpoint_xfer_isoc(&ep
->desc
))
1168 virt_dev
->eps
[ep_index
].new_ring
=
1169 xhci_ring_alloc(xhci
, 8, true, mem_flags
);
1171 virt_dev
->eps
[ep_index
].new_ring
=
1172 xhci_ring_alloc(xhci
, 1, true, mem_flags
);
1173 if (!virt_dev
->eps
[ep_index
].new_ring
) {
1174 /* Attempt to use the ring cache */
1175 if (virt_dev
->num_rings_cached
== 0)
1177 virt_dev
->eps
[ep_index
].new_ring
=
1178 virt_dev
->ring_cache
[virt_dev
->num_rings_cached
];
1179 virt_dev
->ring_cache
[virt_dev
->num_rings_cached
] = NULL
;
1180 virt_dev
->num_rings_cached
--;
1181 xhci_reinit_cached_ring(xhci
, virt_dev
->eps
[ep_index
].new_ring
);
1183 virt_dev
->eps
[ep_index
].skip
= false;
1184 ep_ring
= virt_dev
->eps
[ep_index
].new_ring
;
1185 ep_ctx
->deq
= cpu_to_le64(ep_ring
->first_seg
->dma
| ep_ring
->cycle_state
);
1187 ep_ctx
->ep_info
= cpu_to_le32(xhci_get_endpoint_interval(udev
, ep
)
1188 | EP_MULT(xhci_get_endpoint_mult(udev
, ep
)));
1190 /* FIXME dig Mult and streams info out of ep companion desc */
1192 /* Allow 3 retries for everything but isoc;
1193 * CErr shall be set to 0 for Isoch endpoints.
1195 if (!usb_endpoint_xfer_isoc(&ep
->desc
))
1196 ep_ctx
->ep_info2
= cpu_to_le32(ERROR_COUNT(3));
1198 ep_ctx
->ep_info2
= cpu_to_le32(ERROR_COUNT(0));
1200 ep_ctx
->ep_info2
|= cpu_to_le32(xhci_get_endpoint_type(udev
, ep
));
1202 /* Set the max packet size and max burst */
1203 switch (udev
->speed
) {
1204 case USB_SPEED_SUPER
:
1205 max_packet
= le16_to_cpu(ep
->desc
.wMaxPacketSize
);
1206 ep_ctx
->ep_info2
|= cpu_to_le32(MAX_PACKET(max_packet
));
1207 /* dig out max burst from ep companion desc */
1208 max_packet
= ep
->ss_ep_comp
.bMaxBurst
;
1210 xhci_warn(xhci
, "WARN no SS endpoint bMaxBurst\n");
1211 ep_ctx
->ep_info2
|= cpu_to_le32(MAX_BURST(max_packet
));
1213 case USB_SPEED_HIGH
:
1214 /* bits 11:12 specify the number of additional transaction
1215 * opportunities per microframe (USB 2.0, section 9.6.6)
1217 if (usb_endpoint_xfer_isoc(&ep
->desc
) ||
1218 usb_endpoint_xfer_int(&ep
->desc
)) {
1219 max_burst
= (le16_to_cpu(ep
->desc
.wMaxPacketSize
)
1221 ep_ctx
->ep_info2
|= cpu_to_le32(MAX_BURST(max_burst
));
1224 case USB_SPEED_FULL
:
1226 max_packet
= GET_MAX_PACKET(le16_to_cpu(ep
->desc
.wMaxPacketSize
));
1227 ep_ctx
->ep_info2
|= cpu_to_le32(MAX_PACKET(max_packet
));
1232 max_esit_payload
= xhci_get_max_esit_payload(xhci
, udev
, ep
);
1233 ep_ctx
->tx_info
= cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload
));
1236 * XXX no idea how to calculate the average TRB buffer length for bulk
1237 * endpoints, as the driver gives us no clue how big each scatter gather
1238 * list entry (or buffer) is going to be.
1240 * For isochronous and interrupt endpoints, we set it to the max
1241 * available, until we have new API in the USB core to allow drivers to
1242 * declare how much bandwidth they actually need.
1244 * Normally, it would be calculated by taking the total of the buffer
1245 * lengths in the TD and then dividing by the number of TRBs in a TD,
1246 * including link TRBs, No-op TRBs, and Event data TRBs. Since we don't
1247 * use Event Data TRBs, and we don't chain in a link TRB on short
1248 * transfers, we're basically dividing by 1.
1250 * xHCI 1.0 specification indicates that the Average TRB Length should
1251 * be set to 8 for control endpoints.
1253 if (usb_endpoint_xfer_control(&ep
->desc
) && xhci
->hci_version
== 0x100)
1254 ep_ctx
->tx_info
|= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
1257 cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload
));
1259 /* FIXME Debug endpoint context */
1263 void xhci_endpoint_zero(struct xhci_hcd
*xhci
,
1264 struct xhci_virt_device
*virt_dev
,
1265 struct usb_host_endpoint
*ep
)
1267 unsigned int ep_index
;
1268 struct xhci_ep_ctx
*ep_ctx
;
1270 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1271 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
1273 ep_ctx
->ep_info
= 0;
1274 ep_ctx
->ep_info2
= 0;
1276 ep_ctx
->tx_info
= 0;
1277 /* Don't free the endpoint ring until the set interface or configuration
1282 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1283 * Useful when you want to change one particular aspect of the endpoint and then
1284 * issue a configure endpoint command.
1286 void xhci_endpoint_copy(struct xhci_hcd
*xhci
,
1287 struct xhci_container_ctx
*in_ctx
,
1288 struct xhci_container_ctx
*out_ctx
,
1289 unsigned int ep_index
)
1291 struct xhci_ep_ctx
*out_ep_ctx
;
1292 struct xhci_ep_ctx
*in_ep_ctx
;
1294 out_ep_ctx
= xhci_get_ep_ctx(xhci
, out_ctx
, ep_index
);
1295 in_ep_ctx
= xhci_get_ep_ctx(xhci
, in_ctx
, ep_index
);
1297 in_ep_ctx
->ep_info
= out_ep_ctx
->ep_info
;
1298 in_ep_ctx
->ep_info2
= out_ep_ctx
->ep_info2
;
1299 in_ep_ctx
->deq
= out_ep_ctx
->deq
;
1300 in_ep_ctx
->tx_info
= out_ep_ctx
->tx_info
;
1303 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1304 * Useful when you want to change one particular aspect of the endpoint and then
1305 * issue a configure endpoint command. Only the context entries field matters,
1306 * but we'll copy the whole thing anyway.
1308 void xhci_slot_copy(struct xhci_hcd
*xhci
,
1309 struct xhci_container_ctx
*in_ctx
,
1310 struct xhci_container_ctx
*out_ctx
)
1312 struct xhci_slot_ctx
*in_slot_ctx
;
1313 struct xhci_slot_ctx
*out_slot_ctx
;
1315 in_slot_ctx
= xhci_get_slot_ctx(xhci
, in_ctx
);
1316 out_slot_ctx
= xhci_get_slot_ctx(xhci
, out_ctx
);
1318 in_slot_ctx
->dev_info
= out_slot_ctx
->dev_info
;
1319 in_slot_ctx
->dev_info2
= out_slot_ctx
->dev_info2
;
1320 in_slot_ctx
->tt_info
= out_slot_ctx
->tt_info
;
1321 in_slot_ctx
->dev_state
= out_slot_ctx
->dev_state
;
1324 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1325 static int scratchpad_alloc(struct xhci_hcd
*xhci
, gfp_t flags
)
1328 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
1329 int num_sp
= HCS_MAX_SCRATCHPAD(xhci
->hcs_params2
);
1331 xhci_dbg(xhci
, "Allocating %d scratchpad buffers\n", num_sp
);
1336 xhci
->scratchpad
= kzalloc(sizeof(*xhci
->scratchpad
), flags
);
1337 if (!xhci
->scratchpad
)
1340 xhci
->scratchpad
->sp_array
=
1341 pci_alloc_consistent(to_pci_dev(dev
),
1342 num_sp
* sizeof(u64
),
1343 &xhci
->scratchpad
->sp_dma
);
1344 if (!xhci
->scratchpad
->sp_array
)
1347 xhci
->scratchpad
->sp_buffers
= kzalloc(sizeof(void *) * num_sp
, flags
);
1348 if (!xhci
->scratchpad
->sp_buffers
)
1351 xhci
->scratchpad
->sp_dma_buffers
=
1352 kzalloc(sizeof(dma_addr_t
) * num_sp
, flags
);
1354 if (!xhci
->scratchpad
->sp_dma_buffers
)
1357 xhci
->dcbaa
->dev_context_ptrs
[0] = cpu_to_le64(xhci
->scratchpad
->sp_dma
);
1358 for (i
= 0; i
< num_sp
; i
++) {
1360 void *buf
= pci_alloc_consistent(to_pci_dev(dev
),
1361 xhci
->page_size
, &dma
);
1365 xhci
->scratchpad
->sp_array
[i
] = dma
;
1366 xhci
->scratchpad
->sp_buffers
[i
] = buf
;
1367 xhci
->scratchpad
->sp_dma_buffers
[i
] = dma
;
1373 for (i
= i
- 1; i
>= 0; i
--) {
1374 pci_free_consistent(to_pci_dev(dev
), xhci
->page_size
,
1375 xhci
->scratchpad
->sp_buffers
[i
],
1376 xhci
->scratchpad
->sp_dma_buffers
[i
]);
1378 kfree(xhci
->scratchpad
->sp_dma_buffers
);
1381 kfree(xhci
->scratchpad
->sp_buffers
);
1384 pci_free_consistent(to_pci_dev(dev
), num_sp
* sizeof(u64
),
1385 xhci
->scratchpad
->sp_array
,
1386 xhci
->scratchpad
->sp_dma
);
1389 kfree(xhci
->scratchpad
);
1390 xhci
->scratchpad
= NULL
;
1396 static void scratchpad_free(struct xhci_hcd
*xhci
)
1400 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
1402 if (!xhci
->scratchpad
)
1405 num_sp
= HCS_MAX_SCRATCHPAD(xhci
->hcs_params2
);
1407 for (i
= 0; i
< num_sp
; i
++) {
1408 pci_free_consistent(pdev
, xhci
->page_size
,
1409 xhci
->scratchpad
->sp_buffers
[i
],
1410 xhci
->scratchpad
->sp_dma_buffers
[i
]);
1412 kfree(xhci
->scratchpad
->sp_dma_buffers
);
1413 kfree(xhci
->scratchpad
->sp_buffers
);
1414 pci_free_consistent(pdev
, num_sp
* sizeof(u64
),
1415 xhci
->scratchpad
->sp_array
,
1416 xhci
->scratchpad
->sp_dma
);
1417 kfree(xhci
->scratchpad
);
1418 xhci
->scratchpad
= NULL
;
1421 struct xhci_command
*xhci_alloc_command(struct xhci_hcd
*xhci
,
1422 bool allocate_in_ctx
, bool allocate_completion
,
1425 struct xhci_command
*command
;
1427 command
= kzalloc(sizeof(*command
), mem_flags
);
1431 if (allocate_in_ctx
) {
1433 xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_INPUT
,
1435 if (!command
->in_ctx
) {
1441 if (allocate_completion
) {
1442 command
->completion
=
1443 kzalloc(sizeof(struct completion
), mem_flags
);
1444 if (!command
->completion
) {
1445 xhci_free_container_ctx(xhci
, command
->in_ctx
);
1449 init_completion(command
->completion
);
1452 command
->status
= 0;
1453 INIT_LIST_HEAD(&command
->cmd_list
);
1457 void xhci_urb_free_priv(struct xhci_hcd
*xhci
, struct urb_priv
*urb_priv
)
1464 last
= urb_priv
->length
- 1;
1467 for (i
= 0; i
<= last
; i
++)
1468 kfree(urb_priv
->td
[i
]);
1473 void xhci_free_command(struct xhci_hcd
*xhci
,
1474 struct xhci_command
*command
)
1476 xhci_free_container_ctx(xhci
,
1478 kfree(command
->completion
);
1482 void xhci_mem_cleanup(struct xhci_hcd
*xhci
)
1484 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
1488 /* Free the Event Ring Segment Table and the actual Event Ring */
1490 xhci_writel(xhci
, 0, &xhci
->ir_set
->erst_size
);
1491 xhci_write_64(xhci
, 0, &xhci
->ir_set
->erst_base
);
1492 xhci_write_64(xhci
, 0, &xhci
->ir_set
->erst_dequeue
);
1494 size
= sizeof(struct xhci_erst_entry
)*(xhci
->erst
.num_entries
);
1495 if (xhci
->erst
.entries
)
1496 pci_free_consistent(pdev
, size
,
1497 xhci
->erst
.entries
, xhci
->erst
.erst_dma_addr
);
1498 xhci
->erst
.entries
= NULL
;
1499 xhci_dbg(xhci
, "Freed ERST\n");
1500 if (xhci
->event_ring
)
1501 xhci_ring_free(xhci
, xhci
->event_ring
);
1502 xhci
->event_ring
= NULL
;
1503 xhci_dbg(xhci
, "Freed event ring\n");
1505 xhci_write_64(xhci
, 0, &xhci
->op_regs
->cmd_ring
);
1507 xhci_ring_free(xhci
, xhci
->cmd_ring
);
1508 xhci
->cmd_ring
= NULL
;
1509 xhci_dbg(xhci
, "Freed command ring\n");
1511 for (i
= 1; i
< MAX_HC_SLOTS
; ++i
)
1512 xhci_free_virt_device(xhci
, i
);
1514 if (xhci
->segment_pool
)
1515 dma_pool_destroy(xhci
->segment_pool
);
1516 xhci
->segment_pool
= NULL
;
1517 xhci_dbg(xhci
, "Freed segment pool\n");
1519 if (xhci
->device_pool
)
1520 dma_pool_destroy(xhci
->device_pool
);
1521 xhci
->device_pool
= NULL
;
1522 xhci_dbg(xhci
, "Freed device context pool\n");
1524 if (xhci
->small_streams_pool
)
1525 dma_pool_destroy(xhci
->small_streams_pool
);
1526 xhci
->small_streams_pool
= NULL
;
1527 xhci_dbg(xhci
, "Freed small stream array pool\n");
1529 if (xhci
->medium_streams_pool
)
1530 dma_pool_destroy(xhci
->medium_streams_pool
);
1531 xhci
->medium_streams_pool
= NULL
;
1532 xhci_dbg(xhci
, "Freed medium stream array pool\n");
1534 xhci_write_64(xhci
, 0, &xhci
->op_regs
->dcbaa_ptr
);
1536 pci_free_consistent(pdev
, sizeof(*xhci
->dcbaa
),
1537 xhci
->dcbaa
, xhci
->dcbaa
->dma
);
1540 scratchpad_free(xhci
);
1542 xhci
->num_usb2_ports
= 0;
1543 xhci
->num_usb3_ports
= 0;
1544 kfree(xhci
->usb2_ports
);
1545 kfree(xhci
->usb3_ports
);
1546 kfree(xhci
->port_array
);
1548 xhci
->page_size
= 0;
1549 xhci
->page_shift
= 0;
1550 xhci
->bus_state
[0].bus_suspended
= 0;
1551 xhci
->bus_state
[1].bus_suspended
= 0;
1554 static int xhci_test_trb_in_td(struct xhci_hcd
*xhci
,
1555 struct xhci_segment
*input_seg
,
1556 union xhci_trb
*start_trb
,
1557 union xhci_trb
*end_trb
,
1558 dma_addr_t input_dma
,
1559 struct xhci_segment
*result_seg
,
1560 char *test_name
, int test_number
)
1562 unsigned long long start_dma
;
1563 unsigned long long end_dma
;
1564 struct xhci_segment
*seg
;
1566 start_dma
= xhci_trb_virt_to_dma(input_seg
, start_trb
);
1567 end_dma
= xhci_trb_virt_to_dma(input_seg
, end_trb
);
1569 seg
= trb_in_td(input_seg
, start_trb
, end_trb
, input_dma
);
1570 if (seg
!= result_seg
) {
1571 xhci_warn(xhci
, "WARN: %s TRB math test %d failed!\n",
1572 test_name
, test_number
);
1573 xhci_warn(xhci
, "Tested TRB math w/ seg %p and "
1574 "input DMA 0x%llx\n",
1576 (unsigned long long) input_dma
);
1577 xhci_warn(xhci
, "starting TRB %p (0x%llx DMA), "
1578 "ending TRB %p (0x%llx DMA)\n",
1579 start_trb
, start_dma
,
1581 xhci_warn(xhci
, "Expected seg %p, got seg %p\n",
1588 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1589 static int xhci_check_trb_in_td_math(struct xhci_hcd
*xhci
, gfp_t mem_flags
)
1592 dma_addr_t input_dma
;
1593 struct xhci_segment
*result_seg
;
1594 } simple_test_vector
[] = {
1595 /* A zeroed DMA field should fail */
1597 /* One TRB before the ring start should fail */
1598 { xhci
->event_ring
->first_seg
->dma
- 16, NULL
},
1599 /* One byte before the ring start should fail */
1600 { xhci
->event_ring
->first_seg
->dma
- 1, NULL
},
1601 /* Starting TRB should succeed */
1602 { xhci
->event_ring
->first_seg
->dma
, xhci
->event_ring
->first_seg
},
1603 /* Ending TRB should succeed */
1604 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 1)*16,
1605 xhci
->event_ring
->first_seg
},
1606 /* One byte after the ring end should fail */
1607 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 1)*16 + 1, NULL
},
1608 /* One TRB after the ring end should fail */
1609 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
)*16, NULL
},
1610 /* An address of all ones should fail */
1611 { (dma_addr_t
) (~0), NULL
},
1614 struct xhci_segment
*input_seg
;
1615 union xhci_trb
*start_trb
;
1616 union xhci_trb
*end_trb
;
1617 dma_addr_t input_dma
;
1618 struct xhci_segment
*result_seg
;
1619 } complex_test_vector
[] = {
1620 /* Test feeding a valid DMA address from a different ring */
1621 { .input_seg
= xhci
->event_ring
->first_seg
,
1622 .start_trb
= xhci
->event_ring
->first_seg
->trbs
,
1623 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1624 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1627 /* Test feeding a valid end TRB from a different ring */
1628 { .input_seg
= xhci
->event_ring
->first_seg
,
1629 .start_trb
= xhci
->event_ring
->first_seg
->trbs
,
1630 .end_trb
= &xhci
->cmd_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1631 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1634 /* Test feeding a valid start and end TRB from a different ring */
1635 { .input_seg
= xhci
->event_ring
->first_seg
,
1636 .start_trb
= xhci
->cmd_ring
->first_seg
->trbs
,
1637 .end_trb
= &xhci
->cmd_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1638 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1641 /* TRB in this ring, but after this TD */
1642 { .input_seg
= xhci
->event_ring
->first_seg
,
1643 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[0],
1644 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[3],
1645 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 4*16,
1648 /* TRB in this ring, but before this TD */
1649 { .input_seg
= xhci
->event_ring
->first_seg
,
1650 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[3],
1651 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[6],
1652 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 2*16,
1655 /* TRB in this ring, but after this wrapped TD */
1656 { .input_seg
= xhci
->event_ring
->first_seg
,
1657 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
1658 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
1659 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 2*16,
1662 /* TRB in this ring, but before this wrapped TD */
1663 { .input_seg
= xhci
->event_ring
->first_seg
,
1664 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
1665 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
1666 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 4)*16,
1669 /* TRB not in this ring, and we have a wrapped TD */
1670 { .input_seg
= xhci
->event_ring
->first_seg
,
1671 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
1672 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
1673 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
+ 2*16,
1678 unsigned int num_tests
;
1681 num_tests
= ARRAY_SIZE(simple_test_vector
);
1682 for (i
= 0; i
< num_tests
; i
++) {
1683 ret
= xhci_test_trb_in_td(xhci
,
1684 xhci
->event_ring
->first_seg
,
1685 xhci
->event_ring
->first_seg
->trbs
,
1686 &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1687 simple_test_vector
[i
].input_dma
,
1688 simple_test_vector
[i
].result_seg
,
1694 num_tests
= ARRAY_SIZE(complex_test_vector
);
1695 for (i
= 0; i
< num_tests
; i
++) {
1696 ret
= xhci_test_trb_in_td(xhci
,
1697 complex_test_vector
[i
].input_seg
,
1698 complex_test_vector
[i
].start_trb
,
1699 complex_test_vector
[i
].end_trb
,
1700 complex_test_vector
[i
].input_dma
,
1701 complex_test_vector
[i
].result_seg
,
1706 xhci_dbg(xhci
, "TRB math tests passed.\n");
1710 static void xhci_set_hc_event_deq(struct xhci_hcd
*xhci
)
1715 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
1716 xhci
->event_ring
->dequeue
);
1717 if (deq
== 0 && !in_interrupt())
1718 xhci_warn(xhci
, "WARN something wrong with SW event ring "
1720 /* Update HC event ring dequeue pointer */
1721 temp
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
1722 temp
&= ERST_PTR_MASK
;
1723 /* Don't clear the EHB bit (which is RW1C) because
1724 * there might be more events to service.
1727 xhci_dbg(xhci
, "// Write event ring dequeue pointer, "
1728 "preserving EHB bit\n");
1729 xhci_write_64(xhci
, ((u64
) deq
& (u64
) ~ERST_PTR_MASK
) | temp
,
1730 &xhci
->ir_set
->erst_dequeue
);
1733 static void xhci_add_in_port(struct xhci_hcd
*xhci
, unsigned int num_ports
,
1734 __le32 __iomem
*addr
, u8 major_revision
)
1736 u32 temp
, port_offset
, port_count
;
1739 if (major_revision
> 0x03) {
1740 xhci_warn(xhci
, "Ignoring unknown port speed, "
1741 "Ext Cap %p, revision = 0x%x\n",
1742 addr
, major_revision
);
1743 /* Ignoring port protocol we can't understand. FIXME */
1747 /* Port offset and count in the third dword, see section 7.2 */
1748 temp
= xhci_readl(xhci
, addr
+ 2);
1749 port_offset
= XHCI_EXT_PORT_OFF(temp
);
1750 port_count
= XHCI_EXT_PORT_COUNT(temp
);
1751 xhci_dbg(xhci
, "Ext Cap %p, port offset = %u, "
1752 "count = %u, revision = 0x%x\n",
1753 addr
, port_offset
, port_count
, major_revision
);
1754 /* Port count includes the current port offset */
1755 if (port_offset
== 0 || (port_offset
+ port_count
- 1) > num_ports
)
1756 /* WTF? "Valid values are ‘1’ to MaxPorts" */
1759 for (i
= port_offset
; i
< (port_offset
+ port_count
); i
++) {
1760 /* Duplicate entry. Ignore the port if the revisions differ. */
1761 if (xhci
->port_array
[i
] != 0) {
1762 xhci_warn(xhci
, "Duplicate port entry, Ext Cap %p,"
1763 " port %u\n", addr
, i
);
1764 xhci_warn(xhci
, "Port was marked as USB %u, "
1765 "duplicated as USB %u\n",
1766 xhci
->port_array
[i
], major_revision
);
1767 /* Only adjust the roothub port counts if we haven't
1768 * found a similar duplicate.
1770 if (xhci
->port_array
[i
] != major_revision
&&
1771 xhci
->port_array
[i
] != DUPLICATE_ENTRY
) {
1772 if (xhci
->port_array
[i
] == 0x03)
1773 xhci
->num_usb3_ports
--;
1775 xhci
->num_usb2_ports
--;
1776 xhci
->port_array
[i
] = DUPLICATE_ENTRY
;
1778 /* FIXME: Should we disable the port? */
1781 xhci
->port_array
[i
] = major_revision
;
1782 if (major_revision
== 0x03)
1783 xhci
->num_usb3_ports
++;
1785 xhci
->num_usb2_ports
++;
1787 /* FIXME: Should we disable ports not in the Extended Capabilities? */
1791 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
1792 * specify what speeds each port is supposed to be. We can't count on the port
1793 * speed bits in the PORTSC register being correct until a device is connected,
1794 * but we need to set up the two fake roothubs with the correct number of USB
1795 * 3.0 and USB 2.0 ports at host controller initialization time.
1797 static int xhci_setup_port_arrays(struct xhci_hcd
*xhci
, gfp_t flags
)
1799 __le32 __iomem
*addr
;
1801 unsigned int num_ports
;
1804 addr
= &xhci
->cap_regs
->hcc_params
;
1805 offset
= XHCI_HCC_EXT_CAPS(xhci_readl(xhci
, addr
));
1807 xhci_err(xhci
, "No Extended Capability registers, "
1808 "unable to set up roothub.\n");
1812 num_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1813 xhci
->port_array
= kzalloc(sizeof(*xhci
->port_array
)*num_ports
, flags
);
1814 if (!xhci
->port_array
)
1818 * For whatever reason, the first capability offset is from the
1819 * capability register base, not from the HCCPARAMS register.
1820 * See section 5.3.6 for offset calculation.
1822 addr
= &xhci
->cap_regs
->hc_capbase
+ offset
;
1826 cap_id
= xhci_readl(xhci
, addr
);
1827 if (XHCI_EXT_CAPS_ID(cap_id
) == XHCI_EXT_CAPS_PROTOCOL
)
1828 xhci_add_in_port(xhci
, num_ports
, addr
,
1829 (u8
) XHCI_EXT_PORT_MAJOR(cap_id
));
1830 offset
= XHCI_EXT_CAPS_NEXT(cap_id
);
1831 if (!offset
|| (xhci
->num_usb2_ports
+ xhci
->num_usb3_ports
)
1835 * Once you're into the Extended Capabilities, the offset is
1836 * always relative to the register holding the offset.
1841 if (xhci
->num_usb2_ports
== 0 && xhci
->num_usb3_ports
== 0) {
1842 xhci_warn(xhci
, "No ports on the roothubs?\n");
1845 xhci_dbg(xhci
, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
1846 xhci
->num_usb2_ports
, xhci
->num_usb3_ports
);
1848 /* Place limits on the number of roothub ports so that the hub
1849 * descriptors aren't longer than the USB core will allocate.
1851 if (xhci
->num_usb3_ports
> 15) {
1852 xhci_dbg(xhci
, "Limiting USB 3.0 roothub ports to 15.\n");
1853 xhci
->num_usb3_ports
= 15;
1855 if (xhci
->num_usb2_ports
> USB_MAXCHILDREN
) {
1856 xhci_dbg(xhci
, "Limiting USB 2.0 roothub ports to %u.\n",
1858 xhci
->num_usb2_ports
= USB_MAXCHILDREN
;
1862 * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
1863 * Not sure how the USB core will handle a hub with no ports...
1865 if (xhci
->num_usb2_ports
) {
1866 xhci
->usb2_ports
= kmalloc(sizeof(*xhci
->usb2_ports
)*
1867 xhci
->num_usb2_ports
, flags
);
1868 if (!xhci
->usb2_ports
)
1872 for (i
= 0; i
< num_ports
; i
++) {
1873 if (xhci
->port_array
[i
] == 0x03 ||
1874 xhci
->port_array
[i
] == 0 ||
1875 xhci
->port_array
[i
] == DUPLICATE_ENTRY
)
1878 xhci
->usb2_ports
[port_index
] =
1879 &xhci
->op_regs
->port_status_base
+
1881 xhci_dbg(xhci
, "USB 2.0 port at index %u, "
1883 xhci
->usb2_ports
[port_index
]);
1885 if (port_index
== xhci
->num_usb2_ports
)
1889 if (xhci
->num_usb3_ports
) {
1890 xhci
->usb3_ports
= kmalloc(sizeof(*xhci
->usb3_ports
)*
1891 xhci
->num_usb3_ports
, flags
);
1892 if (!xhci
->usb3_ports
)
1896 for (i
= 0; i
< num_ports
; i
++)
1897 if (xhci
->port_array
[i
] == 0x03) {
1898 xhci
->usb3_ports
[port_index
] =
1899 &xhci
->op_regs
->port_status_base
+
1901 xhci_dbg(xhci
, "USB 3.0 port at index %u, "
1903 xhci
->usb3_ports
[port_index
]);
1905 if (port_index
== xhci
->num_usb3_ports
)
1912 int xhci_mem_init(struct xhci_hcd
*xhci
, gfp_t flags
)
1915 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
1916 unsigned int val
, val2
;
1918 struct xhci_segment
*seg
;
1922 page_size
= xhci_readl(xhci
, &xhci
->op_regs
->page_size
);
1923 xhci_dbg(xhci
, "Supported page size register = 0x%x\n", page_size
);
1924 for (i
= 0; i
< 16; i
++) {
1925 if ((0x1 & page_size
) != 0)
1927 page_size
= page_size
>> 1;
1930 xhci_dbg(xhci
, "Supported page size of %iK\n", (1 << (i
+12)) / 1024);
1932 xhci_warn(xhci
, "WARN: no supported page size\n");
1933 /* Use 4K pages, since that's common and the minimum the HC supports */
1934 xhci
->page_shift
= 12;
1935 xhci
->page_size
= 1 << xhci
->page_shift
;
1936 xhci_dbg(xhci
, "HCD page size set to %iK\n", xhci
->page_size
/ 1024);
1939 * Program the Number of Device Slots Enabled field in the CONFIG
1940 * register with the max value of slots the HC can handle.
1942 val
= HCS_MAX_SLOTS(xhci_readl(xhci
, &xhci
->cap_regs
->hcs_params1
));
1943 xhci_dbg(xhci
, "// xHC can handle at most %d device slots.\n",
1944 (unsigned int) val
);
1945 val2
= xhci_readl(xhci
, &xhci
->op_regs
->config_reg
);
1946 val
|= (val2
& ~HCS_SLOTS_MASK
);
1947 xhci_dbg(xhci
, "// Setting Max device slots reg = 0x%x.\n",
1948 (unsigned int) val
);
1949 xhci_writel(xhci
, val
, &xhci
->op_regs
->config_reg
);
1952 * Section 5.4.8 - doorbell array must be
1953 * "physically contiguous and 64-byte (cache line) aligned".
1955 xhci
->dcbaa
= pci_alloc_consistent(to_pci_dev(dev
),
1956 sizeof(*xhci
->dcbaa
), &dma
);
1959 memset(xhci
->dcbaa
, 0, sizeof *(xhci
->dcbaa
));
1960 xhci
->dcbaa
->dma
= dma
;
1961 xhci_dbg(xhci
, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
1962 (unsigned long long)xhci
->dcbaa
->dma
, xhci
->dcbaa
);
1963 xhci_write_64(xhci
, dma
, &xhci
->op_regs
->dcbaa_ptr
);
1966 * Initialize the ring segment pool. The ring must be a contiguous
1967 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
1968 * however, the command ring segment needs 64-byte aligned segments,
1969 * so we pick the greater alignment need.
1971 xhci
->segment_pool
= dma_pool_create("xHCI ring segments", dev
,
1972 SEGMENT_SIZE
, 64, xhci
->page_size
);
1974 /* See Table 46 and Note on Figure 55 */
1975 xhci
->device_pool
= dma_pool_create("xHCI input/output contexts", dev
,
1976 2112, 64, xhci
->page_size
);
1977 if (!xhci
->segment_pool
|| !xhci
->device_pool
)
1980 /* Linear stream context arrays don't have any boundary restrictions,
1981 * and only need to be 16-byte aligned.
1983 xhci
->small_streams_pool
=
1984 dma_pool_create("xHCI 256 byte stream ctx arrays",
1985 dev
, SMALL_STREAM_ARRAY_SIZE
, 16, 0);
1986 xhci
->medium_streams_pool
=
1987 dma_pool_create("xHCI 1KB stream ctx arrays",
1988 dev
, MEDIUM_STREAM_ARRAY_SIZE
, 16, 0);
1989 /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
1990 * will be allocated with pci_alloc_consistent()
1993 if (!xhci
->small_streams_pool
|| !xhci
->medium_streams_pool
)
1996 /* Set up the command ring to have one segments for now. */
1997 xhci
->cmd_ring
= xhci_ring_alloc(xhci
, 1, true, flags
);
1998 if (!xhci
->cmd_ring
)
2000 xhci_dbg(xhci
, "Allocated command ring at %p\n", xhci
->cmd_ring
);
2001 xhci_dbg(xhci
, "First segment DMA is 0x%llx\n",
2002 (unsigned long long)xhci
->cmd_ring
->first_seg
->dma
);
2004 /* Set the address in the Command Ring Control register */
2005 val_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
2006 val_64
= (val_64
& (u64
) CMD_RING_RSVD_BITS
) |
2007 (xhci
->cmd_ring
->first_seg
->dma
& (u64
) ~CMD_RING_RSVD_BITS
) |
2008 xhci
->cmd_ring
->cycle_state
;
2009 xhci_dbg(xhci
, "// Setting command ring address to 0x%x\n", val
);
2010 xhci_write_64(xhci
, val_64
, &xhci
->op_regs
->cmd_ring
);
2011 xhci_dbg_cmd_ptrs(xhci
);
2013 val
= xhci_readl(xhci
, &xhci
->cap_regs
->db_off
);
2015 xhci_dbg(xhci
, "// Doorbell array is located at offset 0x%x"
2016 " from cap regs base addr\n", val
);
2017 xhci
->dba
= (void __iomem
*) xhci
->cap_regs
+ val
;
2018 xhci_dbg_regs(xhci
);
2019 xhci_print_run_regs(xhci
);
2020 /* Set ir_set to interrupt register set 0 */
2021 xhci
->ir_set
= &xhci
->run_regs
->ir_set
[0];
2024 * Event ring setup: Allocate a normal ring, but also setup
2025 * the event ring segment table (ERST). Section 4.9.3.
2027 xhci_dbg(xhci
, "// Allocating event ring\n");
2028 xhci
->event_ring
= xhci_ring_alloc(xhci
, ERST_NUM_SEGS
, false, flags
);
2029 if (!xhci
->event_ring
)
2031 if (xhci_check_trb_in_td_math(xhci
, flags
) < 0)
2034 xhci
->erst
.entries
= pci_alloc_consistent(to_pci_dev(dev
),
2035 sizeof(struct xhci_erst_entry
)*ERST_NUM_SEGS
, &dma
);
2036 if (!xhci
->erst
.entries
)
2038 xhci_dbg(xhci
, "// Allocated event ring segment table at 0x%llx\n",
2039 (unsigned long long)dma
);
2041 memset(xhci
->erst
.entries
, 0, sizeof(struct xhci_erst_entry
)*ERST_NUM_SEGS
);
2042 xhci
->erst
.num_entries
= ERST_NUM_SEGS
;
2043 xhci
->erst
.erst_dma_addr
= dma
;
2044 xhci_dbg(xhci
, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
2045 xhci
->erst
.num_entries
,
2047 (unsigned long long)xhci
->erst
.erst_dma_addr
);
2049 /* set ring base address and size for each segment table entry */
2050 for (val
= 0, seg
= xhci
->event_ring
->first_seg
; val
< ERST_NUM_SEGS
; val
++) {
2051 struct xhci_erst_entry
*entry
= &xhci
->erst
.entries
[val
];
2052 entry
->seg_addr
= cpu_to_le64(seg
->dma
);
2053 entry
->seg_size
= cpu_to_le32(TRBS_PER_SEGMENT
);
2058 /* set ERST count with the number of entries in the segment table */
2059 val
= xhci_readl(xhci
, &xhci
->ir_set
->erst_size
);
2060 val
&= ERST_SIZE_MASK
;
2061 val
|= ERST_NUM_SEGS
;
2062 xhci_dbg(xhci
, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
2064 xhci_writel(xhci
, val
, &xhci
->ir_set
->erst_size
);
2066 xhci_dbg(xhci
, "// Set ERST entries to point to event ring.\n");
2067 /* set the segment table base address */
2068 xhci_dbg(xhci
, "// Set ERST base address for ir_set 0 = 0x%llx\n",
2069 (unsigned long long)xhci
->erst
.erst_dma_addr
);
2070 val_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_base
);
2071 val_64
&= ERST_PTR_MASK
;
2072 val_64
|= (xhci
->erst
.erst_dma_addr
& (u64
) ~ERST_PTR_MASK
);
2073 xhci_write_64(xhci
, val_64
, &xhci
->ir_set
->erst_base
);
2075 /* Set the event ring dequeue address */
2076 xhci_set_hc_event_deq(xhci
);
2077 xhci_dbg(xhci
, "Wrote ERST address to ir_set 0.\n");
2078 xhci_print_ir_set(xhci
, 0);
2081 * XXX: Might need to set the Interrupter Moderation Register to
2082 * something other than the default (~1ms minimum between interrupts).
2083 * See section 5.5.1.2.
2085 init_completion(&xhci
->addr_dev
);
2086 for (i
= 0; i
< MAX_HC_SLOTS
; ++i
)
2087 xhci
->devs
[i
] = NULL
;
2088 for (i
= 0; i
< USB_MAXCHILDREN
; ++i
) {
2089 xhci
->bus_state
[0].resume_done
[i
] = 0;
2090 xhci
->bus_state
[1].resume_done
[i
] = 0;
2093 if (scratchpad_alloc(xhci
, flags
))
2095 if (xhci_setup_port_arrays(xhci
, flags
))
2101 xhci_warn(xhci
, "Couldn't initialize memory\n");
2102 xhci_mem_cleanup(xhci
);