2 * arch/s390/kernel/entry64.S
3 * S390 low-level entry points.
5 * Copyright (C) IBM Corp. 1999,2010
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Hartmut Penner (hp@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 * Heiko Carstens <heiko.carstens@de.ibm.com>
12 #include <linux/linkage.h>
13 #include <linux/init.h>
14 #include <asm/cache.h>
15 #include <asm/errno.h>
16 #include <asm/ptrace.h>
17 #include <asm/thread_info.h>
18 #include <asm/asm-offsets.h>
19 #include <asm/unistd.h>
23 * Stack layout for the system_call stack entry.
24 * The first few entries are identical to the user_regs_struct.
26 SP_PTREGS = STACK_FRAME_OVERHEAD
27 SP_ARGS = STACK_FRAME_OVERHEAD + __PT_ARGS
28 SP_PSW = STACK_FRAME_OVERHEAD + __PT_PSW
29 SP_R0 = STACK_FRAME_OVERHEAD + __PT_GPRS
30 SP_R1 = STACK_FRAME_OVERHEAD + __PT_GPRS + 8
31 SP_R2 = STACK_FRAME_OVERHEAD + __PT_GPRS + 16
32 SP_R3 = STACK_FRAME_OVERHEAD + __PT_GPRS + 24
33 SP_R4 = STACK_FRAME_OVERHEAD + __PT_GPRS + 32
34 SP_R5 = STACK_FRAME_OVERHEAD + __PT_GPRS + 40
35 SP_R6 = STACK_FRAME_OVERHEAD + __PT_GPRS + 48
36 SP_R7 = STACK_FRAME_OVERHEAD + __PT_GPRS + 56
37 SP_R8 = STACK_FRAME_OVERHEAD + __PT_GPRS + 64
38 SP_R9 = STACK_FRAME_OVERHEAD + __PT_GPRS + 72
39 SP_R10 = STACK_FRAME_OVERHEAD + __PT_GPRS + 80
40 SP_R11 = STACK_FRAME_OVERHEAD + __PT_GPRS + 88
41 SP_R12 = STACK_FRAME_OVERHEAD + __PT_GPRS + 96
42 SP_R13 = STACK_FRAME_OVERHEAD + __PT_GPRS + 104
43 SP_R14 = STACK_FRAME_OVERHEAD + __PT_GPRS + 112
44 SP_R15 = STACK_FRAME_OVERHEAD + __PT_GPRS + 120
45 SP_ORIG_R2 = STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2
46 SP_ILC = STACK_FRAME_OVERHEAD + __PT_ILC
47 SP_SVCNR = STACK_FRAME_OVERHEAD + __PT_SVCNR
48 SP_SIZE = STACK_FRAME_OVERHEAD + __PT_SIZE
50 STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
51 STACK_SIZE = 1 << STACK_SHIFT
53 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
54 _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP )
55 _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
57 _TIF_SYSCALL = (_TIF_SYSCALL_TRACE>>8 | _TIF_SYSCALL_AUDIT>>8 | \
58 _TIF_SECCOMP>>8 | _TIF_SYSCALL_TRACEPOINT>>8)
60 #define BASED(name) name-system_call(%r13)
62 .macro HANDLE_SIE_INTERCEPT
63 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
72 #ifdef CONFIG_TRACE_IRQFLAGS
75 brasl %r14,trace_hardirqs_on_caller
80 brasl %r14,trace_hardirqs_off_caller
84 #define TRACE_IRQS_OFF
88 .macro LOCKDEP_SYS_EXIT
89 tm SP_PSW+1(%r15),0x01 # returning to user ?
91 brasl %r14,lockdep_sys_exit
95 #define LOCKDEP_SYS_EXIT
98 .macro UPDATE_VTIME lc_from,lc_to,lc_sum
106 * Register usage in interrupt handlers:
107 * R9 - pointer to current task structure
108 * R13 - pointer to literal pool
109 * R14 - return register for function calls
110 * R15 - kernel stack pointer
113 .macro SAVE_ALL_SVC psworg,savearea
114 stmg %r11,%r15,\savearea
115 lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
116 aghi %r15,-SP_SIZE # make room for registers & psw
117 lg %r11,__LC_LAST_BREAK
120 .macro SAVE_ALL_PGM psworg,savearea
121 stmg %r11,%r15,\savearea
122 tm \psworg+1,0x01 # test problem state bit
123 #ifdef CONFIG_CHECK_STACK
125 tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
132 1: lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
133 2: aghi %r15,-SP_SIZE # make room for registers & psw
134 larl %r13,system_call
135 lg %r11,__LC_LAST_BREAK
138 .macro SAVE_ALL_ASYNC psworg,savearea
139 stmg %r11,%r15,\savearea
140 larl %r13,system_call
141 lg %r11,__LC_LAST_BREAK
143 tm \psworg+1,0x01 # test problem state bit
144 jnz 1f # from user -> load kernel stack
145 clc \psworg+8(8),BASED(.Lcritical_end)
147 clc \psworg+8(8),BASED(.Lcritical_start)
149 brasl %r14,cleanup_critical
150 tm 1(%r12),0x01 # retest problem state after cleanup
152 0: lg %r14,__LC_ASYNC_STACK # are we already on the async. stack ?
154 srag %r14,%r14,STACK_SHIFT
155 #ifdef CONFIG_CHECK_STACK
157 tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
163 1: lg %r15,__LC_ASYNC_STACK # load async stack
164 2: aghi %r15,-SP_SIZE # make room for registers & psw
167 .macro CREATE_STACK_FRAME savearea
168 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
169 stg %r2,SP_ORIG_R2(%r15) # store original content of gpr 2
170 mvc SP_R11(40,%r15),\savearea # move %r11-%r15 to stack
171 stmg %r0,%r10,SP_R0(%r15) # store gprs %r0-%r10 to kernel stack
174 .macro RESTORE_ALL psworg,sync
175 mvc \psworg(16),SP_PSW(%r15) # move user PSW to lowcore
177 ni \psworg+1,0xfd # clear wait state bit
179 lg %r14,__LC_VDSO_PER_CPU
180 lmg %r0,%r13,SP_R0(%r15) # load gprs 0-13 of user
182 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
183 lmg %r14,%r15,SP_R14(%r15) # load grps 14-15 of user
184 lpswe \psworg # back to caller
190 stg %r11,__TI_last_break(%r12)
195 mvc __SF_EMPTY(1,%r15),SP_PSW(%r15)
196 ni __SF_EMPTY(%r15),0xbf
201 * Scheduler resume function, called by switch_to
202 * gpr2 = (task_struct *) prev
203 * gpr3 = (task_struct *) next
209 tm __THREAD_per+4(%r3),0xe8 # is the new process using per ?
210 jz __switch_to_noper # if not we're fine
211 stctg %c9,%c11,__SF_EMPTY(%r15)# We are using per stuff
212 clc __THREAD_per(24,%r3),__SF_EMPTY(%r15)
213 je __switch_to_noper # we got away without bashing TLB's
214 lctlg %c9,%c11,__THREAD_per(%r3) # Nope we didn't
216 lg %r4,__THREAD_info(%r2) # get thread_info of prev
217 tm __TI_flags+7(%r4),_TIF_MCCK_PENDING # machine check pending?
218 jz __switch_to_no_mcck
219 ni __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev
220 lg %r4,__THREAD_info(%r3) # get thread_info of next
221 oi __TI_flags+7(%r4),_TIF_MCCK_PENDING # set it in next
223 stmg %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task
224 stg %r15,__THREAD_ksp(%r2) # store kernel stack to prev->tss.ksp
225 lg %r15,__THREAD_ksp(%r3) # load kernel stack from next->tss.ksp
226 lmg %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task
227 stg %r3,__LC_CURRENT # __LC_CURRENT = current task struct
228 lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4
229 lg %r3,__THREAD_info(%r3) # load thread_info from task struct
230 stg %r3,__LC_THREAD_INFO
232 stg %r3,__LC_KERNEL_STACK # __LC_KERNEL_STACK = new kernel stack
237 * SVC interrupt handler routine. System calls are synchronous events and
238 * are executed with interrupts enabled.
243 stpt __LC_SYNC_ENTER_TIMER
245 SAVE_ALL_SVC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
246 CREATE_STACK_FRAME __LC_SAVE_AREA
247 mvc SP_PSW(16,%r15),__LC_SVC_OLD_PSW
248 mvc SP_ILC(4,%r15),__LC_SVC_ILC
249 lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct
251 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
253 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
255 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
258 llgh %r7,SP_SVCNR(%r15)
259 slag %r7,%r7,2 # shift and test for svc 0
261 # svc 0: system call number in %r1
262 llgfr %r1,%r1 # clear high word in r1
265 sth %r1,SP_SVCNR(%r15)
266 slag %r7,%r1,2 # shift and test for svc 0
268 larl %r10,sys_call_table
270 tm __TI_flags+5(%r12),(_TIF_31BIT>>16) # running in 31 bit mode ?
272 larl %r10,sys_call_table_emu # use 31 bit emulation system calls
275 tm __TI_flags+6(%r12),_TIF_SYSCALL
276 mvc SP_ARGS(8,%r15),SP_R7(%r15)
277 lgf %r8,0(%r7,%r10) # load address of system call routine
279 basr %r14,%r8 # call sys_xxxx
280 stg %r2,SP_R2(%r15) # store return value (change R2 on stack)
285 tm __TI_flags+7(%r12),_TIF_WORK_SVC
286 jnz sysc_work # there is work to do (signals etc.)
288 RESTORE_ALL __LC_RETURN_PSW,1
292 # There is work to do, but first we need to check if we return to userspace.
295 tm SP_PSW+1(%r15),0x01 # returning to user ?
299 # One of the work bits is on. Find out which one.
302 tm __TI_flags+7(%r12),_TIF_MCCK_PENDING
304 tm __TI_flags+7(%r12),_TIF_NEED_RESCHED
306 tm __TI_flags+7(%r12),_TIF_SIGPENDING
308 tm __TI_flags+7(%r12),_TIF_NOTIFY_RESUME
309 jo sysc_notify_resume
310 tm __TI_flags+7(%r12),_TIF_RESTART_SVC
312 tm __TI_flags+7(%r12),_TIF_SINGLE_STEP
314 j sysc_return # beware of critical section cleanup
317 # _TIF_NEED_RESCHED is set, call schedule
320 larl %r14,sysc_return
321 jg schedule # return point is sysc_return
324 # _TIF_MCCK_PENDING is set, call handler
327 larl %r14,sysc_return
328 jg s390_handle_mcck # TIF bit will be cleared by handler
331 # _TIF_SIGPENDING is set, call do_signal
334 ni __TI_flags+7(%r12),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
335 la %r2,SP_PTREGS(%r15) # load pt_regs
336 brasl %r14,do_signal # call do_signal
337 tm __TI_flags+7(%r12),_TIF_RESTART_SVC
339 tm __TI_flags+7(%r12),_TIF_SINGLE_STEP
344 # _TIF_NOTIFY_RESUME is set, call do_notify_resume
347 la %r2,SP_PTREGS(%r15) # load pt_regs
348 larl %r14,sysc_return
349 jg do_notify_resume # call do_notify_resume
352 # _TIF_RESTART_SVC is set, set up registers and restart svc
355 ni __TI_flags+7(%r12),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC
356 lg %r7,SP_R2(%r15) # load new svc number
357 mvc SP_R2(8,%r15),SP_ORIG_R2(%r15) # restore first argument
358 lmg %r2,%r6,SP_R2(%r15) # load svc arguments
359 sth %r7,SP_SVCNR(%r15)
361 j sysc_nr_ok # restart svc
364 # _TIF_SINGLE_STEP is set, call do_single_step
367 ni __TI_flags+7(%r12),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
368 xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number
369 la %r2,SP_PTREGS(%r15) # address of register-save area
370 larl %r14,sysc_return # load adr. of system return
371 jg do_single_step # branch to do_sigtrap
374 # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
375 # and after the system call
378 la %r2,SP_PTREGS(%r15) # load pt_regs
380 llgh %r0,SP_SVCNR(%r15)
382 brasl %r14,do_syscall_trace_enter
386 sllg %r7,%r2,2 # svc number *4
389 lmg %r3,%r6,SP_R3(%r15)
390 mvc SP_ARGS(8,%r15),SP_R7(%r15)
391 lg %r2,SP_ORIG_R2(%r15)
392 basr %r14,%r8 # call sys_xxx
393 stg %r2,SP_R2(%r15) # store return value
395 tm __TI_flags+6(%r12),_TIF_SYSCALL
397 la %r2,SP_PTREGS(%r15) # load pt_regs
398 larl %r14,sysc_return # return point is sysc_return
399 jg do_syscall_trace_exit
402 # a new process exits the kernel with ret_from_fork
406 lg %r13,__LC_SVC_NEW_PSW+8
407 lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct
408 tm SP_PSW+1(%r15),0x01 # forking a kernel thread ?
410 stg %r15,SP_R15(%r15) # store stack pointer for new kthread
411 0: brasl %r14,schedule_tail
413 stosm 24(%r15),0x03 # reenable interrupts
417 # kernel_execve function needs to deal with pt_regs that is not
422 stmg %r12,%r15,96(%r15)
425 stg %r14,__SF_BACKCHAIN(%r15)
426 la %r12,SP_PTREGS(%r15)
427 xc 0(__PT_SIZE,%r12),0(%r12)
433 lmg %r12,%r15,96(%r15)
436 0: stnsm __SF_EMPTY(%r15),0xfc # disable interrupts
437 lg %r15,__LC_KERNEL_STACK # load ksp
438 aghi %r15,-SP_SIZE # make room for registers & psw
439 lg %r13,__LC_SVC_NEW_PSW+8
440 mvc SP_PTREGS(__PT_SIZE,%r15),0(%r12) # copy pt_regs
441 lg %r12,__LC_THREAD_INFO
442 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
443 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
444 brasl %r14,execve_tail
448 * Program check handler routine
451 .globl pgm_check_handler
454 * First we need to check for a special case:
455 * Single stepping an instruction that disables the PER event mask will
456 * cause a PER event AFTER the mask has been set. Example: SVC or LPSW.
457 * For a single stepped SVC the program check handler gets control after
458 * the SVC new PSW has been loaded. But we want to execute the SVC first and
459 * then handle the PER event. Therefore we update the SVC old PSW to point
460 * to the pgm_check_handler and branch to the SVC handler after we checked
461 * if we have to load the kernel stack register.
462 * For every other possible cause for PER event without the PER mask set
463 * we just ignore the PER event (FIXME: is there anything we have to do
466 stpt __LC_SYNC_ENTER_TIMER
467 tm __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception
468 jnz pgm_per # got per exception -> special case
469 SAVE_ALL_PGM __LC_PGM_OLD_PSW,__LC_SAVE_AREA
470 CREATE_STACK_FRAME __LC_SAVE_AREA
471 xc SP_ILC(4,%r15),SP_ILC(%r15)
472 mvc SP_PSW(16,%r15),__LC_PGM_OLD_PSW
473 lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct
474 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
476 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
477 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
478 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
482 stg %r11,SP_ARGS(%r15)
483 lgf %r3,__LC_PGM_ILC # load program interruption code
484 lg %r4,__LC_TRANS_EXC_CODE
489 larl %r1,pgm_check_table
490 lg %r1,0(%r8,%r1) # load address of handler routine
491 la %r2,SP_PTREGS(%r15) # address of register-save area
492 basr %r14,%r1 # branch to interrupt-handler
497 # handle per exception
500 tm __LC_PGM_OLD_PSW,0x40 # test if per event recording is on
501 jnz pgm_per_std # ok, normal per event from user space
502 # ok its one of the special cases, now we need to find out which one
503 clc __LC_PGM_OLD_PSW(16),__LC_SVC_NEW_PSW
505 # no interesting special case, ignore PER event
506 lpswe __LC_PGM_OLD_PSW
509 # Normal per exception
512 SAVE_ALL_PGM __LC_PGM_OLD_PSW,__LC_SAVE_AREA
513 CREATE_STACK_FRAME __LC_SAVE_AREA
514 mvc SP_PSW(16,%r15),__LC_PGM_OLD_PSW
515 lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct
516 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
518 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
519 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
520 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
524 lg %r1,__TI_task(%r12)
525 tm SP_PSW+1(%r15),0x01 # kernel per event ?
527 mvc __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
528 mvc __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
529 mvc __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
530 oi __TI_flags+7(%r12),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
531 lgf %r3,__LC_PGM_ILC # load program interruption code
532 lg %r4,__LC_TRANS_EXC_CODE
535 ngr %r8,%r3 # clear per-event-bit and ilc
538 larl %r1,pgm_check_table
539 lg %r1,0(%r8,%r1) # load address of handler routine
540 la %r2,SP_PTREGS(%r15) # address of register-save area
541 basr %r14,%r1 # branch to interrupt-handler
546 # it was a single stepped SVC that is causing all the trouble
549 SAVE_ALL_PGM __LC_SVC_OLD_PSW,__LC_SAVE_AREA
550 CREATE_STACK_FRAME __LC_SAVE_AREA
551 mvc SP_PSW(16,%r15),__LC_SVC_OLD_PSW
552 mvc SP_ILC(4,%r15),__LC_SVC_ILC
553 lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct
554 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
555 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
556 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
558 lg %r8,__TI_task(%r12)
559 mvc __THREAD_per+__PER_atmid(2,%r8),__LC_PER_ATMID
560 mvc __THREAD_per+__PER_address(8,%r8),__LC_PER_ADDRESS
561 mvc __THREAD_per+__PER_access_id(1,%r8),__LC_PER_ACCESS_ID
562 oi __TI_flags+7(%r12),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
563 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
564 lmg %r2,%r6,SP_R2(%r15) # load svc arguments
568 # per was called from kernel, must be kprobes
572 xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number
573 la %r2,SP_PTREGS(%r15) # address of register-save area
574 brasl %r14,do_single_step
578 * IO interrupt handler routine
580 .globl io_int_handler
583 stpt __LC_ASYNC_ENTER_TIMER
584 SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+40
585 CREATE_STACK_FRAME __LC_SAVE_AREA+40
586 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
587 lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct
588 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
590 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
591 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
592 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
597 la %r2,SP_PTREGS(%r15) # address of register-save area
598 brasl %r14,do_IRQ # call standard irq handler
603 tm __TI_flags+7(%r12),_TIF_WORK_INT
604 jnz io_work # there is work to do (signals etc.)
606 RESTORE_ALL __LC_RETURN_PSW,0
610 # There is work todo, find out in which context we have been interrupted:
611 # 1) if we return to user space we can do all _TIF_WORK_INT work
612 # 2) if we return to kernel code and kvm is enabled check if we need to
613 # modify the psw to leave SIE
614 # 3) if we return to kernel code and preemptive scheduling is enabled check
615 # the preemption counter and if it is zero call preempt_schedule_irq
616 # Before any work can be done, a switch to the kernel stack is required.
619 tm SP_PSW+1(%r15),0x01 # returning to user ?
620 jo io_work_user # yes -> do resched & signal
621 #ifdef CONFIG_PREEMPT
622 # check for preemptive scheduling
623 icm %r0,15,__TI_precount(%r12)
624 jnz io_restore # preemption is disabled
625 tm __TI_flags+7(%r12),_TIF_NEED_RESCHED
627 # switch to kernel stack
630 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
631 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
633 # TRACE_IRQS_ON already done at io_return, call
634 # TRACE_IRQS_OFF to keep things symmetrical
636 brasl %r14,preempt_schedule_irq
643 # Need to do work before returning to userspace, switch to kernel stack
646 lg %r1,__LC_KERNEL_STACK
648 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
649 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
653 # One of the work bits is on. Find out which one.
654 # Checked are: _TIF_SIGPENDING, _TIF_NOTIFY_RESUME, _TIF_NEED_RESCHED
655 # and _TIF_MCCK_PENDING
658 tm __TI_flags+7(%r12),_TIF_MCCK_PENDING
660 tm __TI_flags+7(%r12),_TIF_NEED_RESCHED
662 tm __TI_flags+7(%r12),_TIF_SIGPENDING
664 tm __TI_flags+7(%r12),_TIF_NOTIFY_RESUME
666 j io_return # beware of critical section cleanup
669 # _TIF_MCCK_PENDING is set, call handler
672 # TRACE_IRQS_ON already done at io_return
673 brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler
678 # _TIF_NEED_RESCHED is set, call schedule
681 # TRACE_IRQS_ON already done at io_return
682 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
683 brasl %r14,schedule # call scheduler
684 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
689 # _TIF_SIGPENDING or is set, call do_signal
692 # TRACE_IRQS_ON already done at io_return
693 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
694 la %r2,SP_PTREGS(%r15) # load pt_regs
695 brasl %r14,do_signal # call do_signal
696 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
701 # _TIF_NOTIFY_RESUME or is set, call do_notify_resume
704 # TRACE_IRQS_ON already done at io_return
705 stosm __SF_EMPTY(%r15),0x03 # reenable interrupts
706 la %r2,SP_PTREGS(%r15) # load pt_regs
707 brasl %r14,do_notify_resume # call do_notify_resume
708 stnsm __SF_EMPTY(%r15),0xfc # disable I/O and ext. interrupts
713 * External interrupt handler routine
715 .globl ext_int_handler
718 stpt __LC_ASYNC_ENTER_TIMER
719 SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+40
720 CREATE_STACK_FRAME __LC_SAVE_AREA+40
721 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
722 lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct
723 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
725 UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
726 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
727 mvc __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
733 la %r2,SP_PTREGS(%r15) # address of register-save area
734 llgf %r3,__LC_CPU_ADDRESS # get cpu address + interruption code
735 llgf %r4,__LC_EXT_PARAMS # get external parameter
736 lg %r5,__LC_EXT_PARAMS2-4096(%r1) # get 64 bit external parameter
743 * Machine check handler routines
745 .globl mcck_int_handler
748 la %r1,4095 # revalidate r1
749 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer
750 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs
751 stmg %r11,%r15,__LC_SAVE_AREA+80
752 larl %r13,system_call
753 lg %r11,__LC_LAST_BREAK
754 la %r12,__LC_MCK_OLD_PSW
755 tm __LC_MCCK_CODE,0x80 # system damage?
756 jo mcck_int_main # yes -> rest of mcck code invalid
758 mvc __LC_MCCK_ENTER_TIMER(8),__LC_CPU_TIMER_SAVE_AREA-4095(%r14)
759 tm __LC_MCCK_CODE+5,0x02 # stored cpu timer value valid?
761 la %r14,__LC_SYNC_ENTER_TIMER
762 clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
764 la %r14,__LC_ASYNC_ENTER_TIMER
765 0: clc 0(8,%r14),__LC_EXIT_TIMER
767 la %r14,__LC_EXIT_TIMER
768 0: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
770 la %r14,__LC_LAST_UPDATE_TIMER
772 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
773 1: tm __LC_MCCK_CODE+2,0x09 # mwp + ia of old psw valid?
774 jno mcck_int_main # no -> skip cleanup critical
775 tm __LC_MCK_OLD_PSW+1,0x01 # test problem state bit
776 jnz mcck_int_main # from user -> load kernel stack
777 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_end)
779 clc __LC_MCK_OLD_PSW+8(8),BASED(.Lcritical_start)
781 brasl %r14,cleanup_critical
783 lg %r14,__LC_PANIC_STACK # are we already on the panic stack?
785 srag %r14,%r14,PAGE_SHIFT
787 lg %r15,__LC_PANIC_STACK # load panic stack
788 0: aghi %r15,-SP_SIZE # make room for registers & psw
789 CREATE_STACK_FRAME __LC_SAVE_AREA+80
790 mvc SP_PSW(16,%r15),0(%r12)
791 lg %r12,__LC_THREAD_INFO # load pointer to thread_info struct
792 tm __LC_MCCK_CODE+2,0x08 # mwp of old psw valid?
793 jno mcck_no_vtime # no -> no timer update
794 tm SP_PSW+1(%r15),0x01 # interrupting from user ?
796 UPDATE_VTIME __LC_EXIT_TIMER,__LC_MCCK_ENTER_TIMER,__LC_USER_TIMER
797 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
798 mvc __LC_LAST_UPDATE_TIMER(8),__LC_MCCK_ENTER_TIMER
801 la %r2,SP_PTREGS(%r15) # load pt_regs
802 brasl %r14,s390_do_machine_check
803 tm SP_PSW+1(%r15),0x01 # returning to user ?
805 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
807 mvc SP_PTREGS(__PT_SIZE,%r1),SP_PTREGS(%r15)
808 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1) # clear back chain
810 stosm __SF_EMPTY(%r15),0x04 # turn dat on
811 tm __TI_flags+7(%r12),_TIF_MCCK_PENDING
815 brasl %r14,s390_handle_mcck
818 mvc __LC_RETURN_MCCK_PSW(16),SP_PSW(%r15) # move return PSW
819 ni __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit
820 lmg %r0,%r15,SP_R0(%r15) # load gprs 0-15
821 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
824 0: lpswe __LC_RETURN_MCCK_PSW # back to caller
828 * Restart interruption handler, kick starter for additional CPUs
832 .globl restart_int_handler
836 spt restart_vtime-restart_base(%r1)
837 stck __LC_LAST_UPDATE_CLOCK
838 mvc __LC_LAST_UPDATE_TIMER(8),restart_vtime-restart_base(%r1)
839 mvc __LC_EXIT_TIMER(8),restart_vtime-restart_base(%r1)
840 lg %r15,__LC_SAVE_AREA+120 # load ksp
841 lghi %r10,__LC_CREGS_SAVE_AREA
842 lctlg %c0,%c15,0(%r10) # get new ctl regs
843 lghi %r10,__LC_AREGS_SAVE_AREA
845 lmg %r6,%r15,__SF_GPRS(%r15) # load registers from clone
846 lg %r1,__LC_THREAD_INFO
847 mvc __LC_USER_TIMER(8),__TI_user_timer(%r1)
848 mvc __LC_SYSTEM_TIMER(8),__TI_system_timer(%r1)
849 xc __LC_STEAL_TIMER(8),__LC_STEAL_TIMER
850 stosm __SF_EMPTY(%r15),0x04 # now we can turn dat on
854 .long 0x7fffffff,0xffffffff
858 * If we do not run with SMP enabled, let the new CPU crash ...
860 .globl restart_int_handler
864 lpswe restart_crash-restart_base(%r1)
867 .long 0x000a0000,0x00000000,0x00000000,0x00000000
871 #ifdef CONFIG_CHECK_STACK
873 * The synchronous or the asynchronous stack overflowed. We are dead.
874 * No need to properly save the registers, we are going to panic anyway.
875 * Setup a pt_regs so that show_trace can provide a good call trace.
878 lg %r15,__LC_PANIC_STACK # change to panic stack
880 mvc SP_PSW(16,%r15),0(%r12) # move user PSW to stack
881 stmg %r0,%r10,SP_R0(%r15) # store gprs %r0-%r10 to kernel stack
882 la %r1,__LC_SAVE_AREA
883 chi %r12,__LC_SVC_OLD_PSW
885 chi %r12,__LC_PGM_OLD_PSW
887 la %r1,__LC_SAVE_AREA+40
888 0: mvc SP_R11(40,%r15),0(%r1) # move %r11-%r15 to stack
889 mvc SP_ARGS(8,%r15),__LC_LAST_BREAK
890 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) # clear back chain
891 la %r2,SP_PTREGS(%r15) # load pt_regs
892 jg kernel_stack_overflow
895 cleanup_table_system_call:
896 .quad system_call, sysc_do_svc
897 cleanup_table_sysc_tif:
898 .quad sysc_tif, sysc_restore
899 cleanup_table_sysc_restore:
900 .quad sysc_restore, sysc_done
901 cleanup_table_io_tif:
902 .quad io_tif, io_restore
903 cleanup_table_io_restore:
904 .quad io_restore, io_done
907 clc 8(8,%r12),BASED(cleanup_table_system_call)
909 clc 8(8,%r12),BASED(cleanup_table_system_call+8)
910 jl cleanup_system_call
912 clc 8(8,%r12),BASED(cleanup_table_sysc_tif)
914 clc 8(8,%r12),BASED(cleanup_table_sysc_tif+8)
917 clc 8(8,%r12),BASED(cleanup_table_sysc_restore)
919 clc 8(8,%r12),BASED(cleanup_table_sysc_restore+8)
920 jl cleanup_sysc_restore
922 clc 8(8,%r12),BASED(cleanup_table_io_tif)
924 clc 8(8,%r12),BASED(cleanup_table_io_tif+8)
927 clc 8(8,%r12),BASED(cleanup_table_io_restore)
929 clc 8(8,%r12),BASED(cleanup_table_io_restore+8)
930 jl cleanup_io_restore
935 mvc __LC_RETURN_PSW(16),0(%r12)
936 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+8)
938 mvc __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
939 cghi %r12,__LC_MCK_OLD_PSW
941 mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
942 0: cghi %r12,__LC_MCK_OLD_PSW
943 la %r12,__LC_SAVE_AREA+80
945 la %r12,__LC_SAVE_AREA+40
946 0: clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+16)
948 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn)
950 mvc __LC_SAVE_AREA(40),0(%r12)
951 0: lg %r15,__LC_KERNEL_STACK # problem state -> load ksp
952 aghi %r15,-SP_SIZE # make room for registers & psw
955 CREATE_STACK_FRAME __LC_SAVE_AREA
956 mvc SP_PSW(16,%r15),__LC_SVC_OLD_PSW
957 mvc SP_ILC(4,%r15),__LC_SVC_ILC
958 mvc 8(8,%r12),__LC_THREAD_INFO
960 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+24)
962 UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
964 clc __LC_RETURN_PSW+8(8),BASED(cleanup_system_call_insn+32)
966 UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
968 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
970 lg %r12,__LC_THREAD_INFO
972 stg %r11,__TI_last_break(%r12)
973 0: mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_system_call+8)
974 la %r12,__LC_RETURN_PSW
976 cleanup_system_call_insn:
984 mvc __LC_RETURN_PSW(8),0(%r12)
985 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_sysc_tif)
986 la %r12,__LC_RETURN_PSW
989 cleanup_sysc_restore:
990 clc 8(8,%r12),BASED(cleanup_sysc_restore_insn)
992 clc 8(8,%r12),BASED(cleanup_sysc_restore_insn+8)
994 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
995 cghi %r12,__LC_MCK_OLD_PSW
997 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
998 0: mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
999 cghi %r12,__LC_MCK_OLD_PSW
1000 la %r12,__LC_SAVE_AREA+80
1002 la %r12,__LC_SAVE_AREA+40
1003 1: mvc 0(40,%r12),SP_R11(%r15)
1004 lmg %r0,%r10,SP_R0(%r15)
1005 lg %r15,SP_R15(%r15)
1006 2: la %r12,__LC_RETURN_PSW
1008 cleanup_sysc_restore_insn:
1010 .quad sysc_done - 16
1013 mvc __LC_RETURN_PSW(8),0(%r12)
1014 mvc __LC_RETURN_PSW+8(8),BASED(cleanup_table_io_tif)
1015 la %r12,__LC_RETURN_PSW
1019 clc 8(8,%r12),BASED(cleanup_io_restore_insn)
1021 clc 8(8,%r12),BASED(cleanup_io_restore_insn+8)
1023 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
1024 0: mvc __LC_RETURN_PSW(16),SP_PSW(%r15)
1025 mvc __LC_SAVE_AREA+80(40),SP_R11(%r15)
1026 lmg %r0,%r10,SP_R0(%r15)
1027 lg %r15,SP_R15(%r15)
1028 1: la %r12,__LC_RETURN_PSW
1030 cleanup_io_restore_insn:
1039 .quad __critical_start
1041 .quad __critical_end
1043 .section .rodata, "a"
1044 #define SYSCALL(esa,esame,emu) .long esame
1045 .globl sys_call_table
1047 #include "syscalls.S"
1050 #ifdef CONFIG_COMPAT
1052 #define SYSCALL(esa,esame,emu) .long emu
1054 #include "syscalls.S"