?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[media] DiBxxxx: Codingstype updates
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / media / dvb / frontends / dib9000.c
blob43fb6e45424a7297de37786d17c9a1813c257e8d
1 /*
2 * Linux-DVB Driver for DiBcom's DiB9000 and demodulator-family.
3 *
4 * Copyright (C) 2005-10 DiBcom (http://www.dibcom.fr/)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation, version 2.
9 */
10 #include <linux/kernel.h>
11 #include <linux/i2c.h>
12 #include <linux/mutex.h>
13
14 #include "dvb_math.h"
15 #include "dvb_frontend.h"
16
17 #include "dib9000.h"
18 #include "dibx000_common.h"
19
20 static int debug;
21 module_param(debug, int, 0644);
22 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
23
24 #define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB9000: "); printk(args); printk("\n"); } } while (0)
25 #define MAX_NUMBER_OF_FRONTENDS 6
26
27 struct i2c_device {
28 struct i2c_adapter *i2c_adap;
29 u8 i2c_addr;
30 };
31
32 /* lock */
33 #define DIB_LOCK struct mutex
34 #define DibAcquireLock(lock) do { if (mutex_lock_interruptible(lock) < 0) dprintk("could not get the lock"); } while (0)
35 #define DibReleaseLock(lock) mutex_unlock(lock)
36 #define DibInitLock(lock) mutex_init(lock)
37 #define DibFreeLock(lock)
38
39 struct dib9000_state {
40 struct i2c_device i2c;
41
42 struct dibx000_i2c_master i2c_master;
43 struct i2c_adapter tuner_adap;
44 struct i2c_adapter component_bus;
45
46 u16 revision;
47 u8 reg_offs;
48
49 enum frontend_tune_state tune_state;
50 u32 status;
51 struct dvb_frontend_parametersContext channel_status;
52
53 u8 fe_id;
54
55 #define DIB9000_GPIO_DEFAULT_DIRECTIONS 0xffff
56 u16 gpio_dir;
57 #define DIB9000_GPIO_DEFAULT_VALUES 0x0000
58 u16 gpio_val;
59 #define DIB9000_GPIO_DEFAULT_PWM_POS 0xffff
60 u16 gpio_pwm_pos;
61
62 union { /* common for all chips */
63 struct {
64 u8 mobile_mode:1;
65 } host;
66
67 struct {
68 struct dib9000_fe_memory_map {
69 u16 addr;
70 u16 size;
71 } fe_mm[18];
72 u8 memcmd;
73
74 DIB_LOCK mbx_if_lock; /* to protect read/write operations */
75 DIB_LOCK mbx_lock; /* to protect the whole mailbox handling */
76
77 DIB_LOCK mem_lock; /* to protect the memory accesses */
78 DIB_LOCK mem_mbx_lock; /* to protect the memory-based mailbox */
79
80 #define MBX_MAX_WORDS (256 - 200 - 2)
81 #define DIB9000_MSG_CACHE_SIZE 2
82 u16 message_cache[DIB9000_MSG_CACHE_SIZE][MBX_MAX_WORDS];
83 u8 fw_is_running;
84 } risc;
85 } platform;
86
87 union { /* common for all platforms */
88 struct {
89 struct dib9000_config cfg;
90 } d9;
91 } chip;
92
93 struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
94 u16 component_bus_speed;
95 };
96
97 u32 fe_info[44] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
98 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
99 0, 0, 0
100 };
101
102 enum dib9000_power_mode {
103 DIB9000_POWER_ALL = 0,
104
105 DIB9000_POWER_NO,
106 DIB9000_POWER_INTERF_ANALOG_AGC,
107 DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD,
108 DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD,
109 DIB9000_POWER_INTERFACE_ONLY,
110 };
111
112 enum dib9000_out_messages {
113 OUT_MSG_HBM_ACK,
114 OUT_MSG_HOST_BUF_FAIL,
115 OUT_MSG_REQ_VERSION,
116 OUT_MSG_BRIDGE_I2C_W,
117 OUT_MSG_BRIDGE_I2C_R,
118 OUT_MSG_BRIDGE_APB_W,
119 OUT_MSG_BRIDGE_APB_R,
120 OUT_MSG_SCAN_CHANNEL,
121 OUT_MSG_MONIT_DEMOD,
122 OUT_MSG_CONF_GPIO,
123 OUT_MSG_DEBUG_HELP,
124 OUT_MSG_SUBBAND_SEL,
125 OUT_MSG_ENABLE_TIME_SLICE,
126 OUT_MSG_FE_FW_DL,
127 OUT_MSG_FE_CHANNEL_SEARCH,
128 OUT_MSG_FE_CHANNEL_TUNE,
129 OUT_MSG_FE_SLEEP,
130 OUT_MSG_FE_SYNC,
131 OUT_MSG_CTL_MONIT,
132
133 OUT_MSG_CONF_SVC,
134 OUT_MSG_SET_HBM,
135 OUT_MSG_INIT_DEMOD,
136 OUT_MSG_ENABLE_DIVERSITY,
137 OUT_MSG_SET_OUTPUT_MODE,
138 OUT_MSG_SET_PRIORITARY_CHANNEL,
139 OUT_MSG_ACK_FRG,
140 OUT_MSG_INIT_PMU,
141 };
142
143 enum dib9000_in_messages {
144 IN_MSG_DATA,
145 IN_MSG_FRAME_INFO,
146 IN_MSG_CTL_MONIT,
147 IN_MSG_ACK_FREE_ITEM,
148 IN_MSG_DEBUG_BUF,
149 IN_MSG_MPE_MONITOR,
150 IN_MSG_RAWTS_MONITOR,
151 IN_MSG_END_BRIDGE_I2C_RW,
152 IN_MSG_END_BRIDGE_APB_RW,
153 IN_MSG_VERSION,
154 IN_MSG_END_OF_SCAN,
155 IN_MSG_MONIT_DEMOD,
156 IN_MSG_ERROR,
157 IN_MSG_FE_FW_DL_DONE,
158 IN_MSG_EVENT,
159 IN_MSG_ACK_CHANGE_SVC,
160 IN_MSG_HBM_PROF,
161 };
162
163 /* memory_access requests */
164 #define FE_MM_W_CHANNEL 0
165 #define FE_MM_W_FE_INFO 1
166 #define FE_MM_RW_SYNC 2
167
168 #define FE_SYNC_CHANNEL 1
169 #define FE_SYNC_W_GENERIC_MONIT 2
170 #define FE_SYNC_COMPONENT_ACCESS 3
171
172 #define FE_MM_R_CHANNEL_SEARCH_STATE 3
173 #define FE_MM_R_CHANNEL_UNION_CONTEXT 4
174 #define FE_MM_R_FE_INFO 5
175 #define FE_MM_R_FE_MONITOR 6
176
177 #define FE_MM_W_CHANNEL_HEAD 7
178 #define FE_MM_W_CHANNEL_UNION 8
179 #define FE_MM_W_CHANNEL_CONTEXT 9
180 #define FE_MM_R_CHANNEL_UNION 10
181 #define FE_MM_R_CHANNEL_CONTEXT 11
182 #define FE_MM_R_CHANNEL_TUNE_STATE 12
183
184 #define FE_MM_R_GENERIC_MONITORING_SIZE 13
185 #define FE_MM_W_GENERIC_MONITORING 14
186 #define FE_MM_R_GENERIC_MONITORING 15
187
188 #define FE_MM_W_COMPONENT_ACCESS 16
189 #define FE_MM_RW_COMPONENT_ACCESS_BUFFER 17
190 static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len);
191 static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len);
192
193 static u16 to_fw_output_mode(u16 mode)
194 {
195 switch (mode) {
196 case OUTMODE_HIGH_Z:
197 return 0;
198 case OUTMODE_MPEG2_PAR_GATED_CLK:
199 return 4;
200 case OUTMODE_MPEG2_PAR_CONT_CLK:
201 return 8;
202 case OUTMODE_MPEG2_SERIAL:
203 return 16;
204 case OUTMODE_DIVERSITY:
205 return 128;
206 case OUTMODE_MPEG2_FIFO:
207 return 2;
208 case OUTMODE_ANALOG_ADC:
209 return 1;
210 default:
211 return 0;
212 }
213 }
214
215 static u16 dib9000_read16_attr(struct dib9000_state *state, u16 reg, u8 * b, u32 len, u16 attribute)
216 {
217 u32 chunk_size = 126;
218 u32 l;
219 int ret;
220 u8 wb[2] = { reg >> 8, reg & 0xff };
221 struct i2c_msg msg[2] = {
222 {.addr = state->i2c.i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2},
223 {.addr = state->i2c.i2c_addr >> 1, .flags = I2C_M_RD, .buf = b, .len = len},
224 };
225
226 if (state->platform.risc.fw_is_running && (reg < 1024))
227 return dib9000_risc_apb_access_read(state, reg, attribute, NULL, 0, b, len);
228
229 if (attribute & DATA_BUS_ACCESS_MODE_8BIT)
230 wb[0] |= (1 << 5);
231 if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
232 wb[0] |= (1 << 4);
233
234 do {
235 l = len < chunk_size ? len : chunk_size;
236 msg[1].len = l;
237 msg[1].buf = b;
238 ret = i2c_transfer(state->i2c.i2c_adap, msg, 2) != 2 ? -EREMOTEIO : 0;
239 if (ret != 0) {
240 dprintk("i2c read error on %d", reg);
241 return -EREMOTEIO;
242 }
243
244 b += l;
245 len -= l;
246
247 if (!(attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT))
248 reg += l / 2;
249 } while ((ret == 0) && len);
250
251 return 0;
252 }
253
254 static u16 dib9000_i2c_read16(struct i2c_device *i2c, u16 reg)
255 {
256 u8 b[2];
257 u8 wb[2] = { reg >> 8, reg & 0xff };
258 struct i2c_msg msg[2] = {
259 {.addr = i2c->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2},
260 {.addr = i2c->i2c_addr >> 1, .flags = I2C_M_RD, .buf = b, .len = 2},
261 };
262
263 if (i2c_transfer(i2c->i2c_adap, msg, 2) != 2) {
264 dprintk("read register %x error", reg);
265 return 0;
266 }
267
268 return (b[0] << 8) | b[1];
269 }
270
271 static inline u16 dib9000_read_word(struct dib9000_state *state, u16 reg)
272 {
273 u8 b[2];
274 if (dib9000_read16_attr(state, reg, b, 2, 0) != 0)
275 return 0;
276 return (b[0] << 8 | b[1]);
277 }
278
279 static inline u16 dib9000_read_word_attr(struct dib9000_state *state, u16 reg, u16 attribute)
280 {
281 u8 b[2];
282 if (dib9000_read16_attr(state, reg, b, 2, attribute) != 0)
283 return 0;
284 return (b[0] << 8 | b[1]);
285 }
286
287 #define dib9000_read16_noinc_attr(state, reg, b, len, attribute) dib9000_read16_attr(state, reg, b, len, (attribute) | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
288
289 static u16 dib9000_write16_attr(struct dib9000_state *state, u16 reg, const u8 * buf, u32 len, u16 attribute)
290 {
291 u8 b[255];
292 u32 chunk_size = 126;
293 u32 l;
294 int ret;
295
296 struct i2c_msg msg = {
297 .addr = state->i2c.i2c_addr >> 1, .flags = 0, .buf = b, .len = len + 2
298 };
299
300 if (state->platform.risc.fw_is_running && (reg < 1024)) {
301 if (dib9000_risc_apb_access_write
302 (state, reg, DATA_BUS_ACCESS_MODE_16BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | attribute, buf, len) != 0)
303 return -EINVAL;
304 return 0;
305 }
306
307 b[0] = (reg >> 8) & 0xff;
308 b[1] = (reg) & 0xff;
309
310 if (attribute & DATA_BUS_ACCESS_MODE_8BIT)
311 b[0] |= (1 << 5);
312 if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
313 b[0] |= (1 << 4);
314
315 do {
316 l = len < chunk_size ? len : chunk_size;
317 msg.len = l + 2;
318 memcpy(&b[2], buf, l);
319
320 ret = i2c_transfer(state->i2c.i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
321
322 buf += l;
323 len -= l;
324
325 if (!(attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT))
326 reg += l / 2;
327 } while ((ret == 0) && len);
328
329 return ret;
330 }
331
332 static int dib9000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val)
333 {
334 u8 b[4] = { (reg >> 8) & 0xff, reg & 0xff, (val >> 8) & 0xff, val & 0xff };
335 struct i2c_msg msg = {
336 .addr = i2c->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4
337 };
338
339 return i2c_transfer(i2c->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
340 }
341
342 static inline int dib9000_write_word(struct dib9000_state *state, u16 reg, u16 val)
343 {
344 u8 b[2] = { val >> 8, val & 0xff };
345 return dib9000_write16_attr(state, reg, b, 2, 0);
346 }
347
348 static inline int dib9000_write_word_attr(struct dib9000_state *state, u16 reg, u16 val, u16 attribute)
349 {
350 u8 b[2] = { val >> 8, val & 0xff };
351 return dib9000_write16_attr(state, reg, b, 2, attribute);
352 }
353
354 #define dib9000_write(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, 0)
355 #define dib9000_write16_noinc(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
356 #define dib9000_write16_noinc_attr(state, reg, buf, len, attribute) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | (attribute))
357
358 #define dib9000_mbx_send(state, id, data, len) dib9000_mbx_send_attr(state, id, data, len, 0)
359 #define dib9000_mbx_get_message(state, id, msg, len) dib9000_mbx_get_message_attr(state, id, msg, len, 0)
360
361 #define MAC_IRQ (1 << 1)
362 #define IRQ_POL_MSK (1 << 4)
363
364 #define dib9000_risc_mem_read_chunks(state, b, len) dib9000_read16_attr(state, 1063, b, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
365 #define dib9000_risc_mem_write_chunks(state, buf, len) dib9000_write16_attr(state, 1063, buf, len, DATA_BUS_ACCESS_MODE_8BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
366
367 static void dib9000_risc_mem_setup_cmd(struct dib9000_state *state, u32 addr, u32 len, u8 reading)
368 {
369 u8 b[14] = { 0 };
370
371 /* dprintk("%d memcmd: %d %d %d\n", state->fe_id, addr, addr+len, len); */
372 /* b[0] = 0 << 7; */
373 b[1] = 1;
374
375 /* b[2] = 0; */
376 /* b[3] = 0; */
377 b[4] = (u8) (addr >> 8);
378 b[5] = (u8) (addr & 0xff);
379
380 /* b[10] = 0; */
381 /* b[11] = 0; */
382 b[12] = (u8) (addr >> 8);
383 b[13] = (u8) (addr & 0xff);
384
385 addr += len;
386 /* b[6] = 0; */
387 /* b[7] = 0; */
388 b[8] = (u8) (addr >> 8);
389 b[9] = (u8) (addr & 0xff);
390
391 dib9000_write(state, 1056, b, 14);
392 if (reading)
393 dib9000_write_word(state, 1056, (1 << 15) | 1);
394 state->platform.risc.memcmd = -1; /* if it was called directly reset it - to force a future setup-call to set it */
395 }
396
397 static void dib9000_risc_mem_setup(struct dib9000_state *state, u8 cmd)
398 {
399 struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd & 0x7f];
400 /* decide whether we need to "refresh" the memory controller */
401 if (state->platform.risc.memcmd == cmd && /* same command */
402 !(cmd & 0x80 && m->size < 67)) /* and we do not want to read something with less than 67 bytes looping - working around a bug in the memory controller */
403 return;
404 dib9000_risc_mem_setup_cmd(state, m->addr, m->size, cmd & 0x80);
405 state->platform.risc.memcmd = cmd;
406 }
407
408 static int dib9000_risc_mem_read(struct dib9000_state *state, u8 cmd, u8 * b, u16 len)
409 {
410 if (!state->platform.risc.fw_is_running)
411 return -EIO;
412
413 DibAcquireLock(&state->platform.risc.mem_lock);
414 dib9000_risc_mem_setup(state, cmd | 0x80);
415 dib9000_risc_mem_read_chunks(state, b, len);
416 DibReleaseLock(&state->platform.risc.mem_lock);
417 return 0;
418 }
419
420 static int dib9000_risc_mem_write(struct dib9000_state *state, u8 cmd, const u8 * b)
421 {
422 struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[cmd];
423 if (!state->platform.risc.fw_is_running)
424 return -EIO;
425
426 DibAcquireLock(&state->platform.risc.mem_lock);
427 dib9000_risc_mem_setup(state, cmd);
428 dib9000_risc_mem_write_chunks(state, b, m->size);
429 DibReleaseLock(&state->platform.risc.mem_lock);
430 return 0;
431 }
432
433 static int dib9000_firmware_download(struct dib9000_state *state, u8 risc_id, u16 key, const u8 * code, u32 len)
434 {
435 u16 offs;
436
437 if (risc_id == 1)
438 offs = 16;
439 else
440 offs = 0;
441
442 /* config crtl reg */
443 dib9000_write_word(state, 1024 + offs, 0x000f);
444 dib9000_write_word(state, 1025 + offs, 0);
445 dib9000_write_word(state, 1031 + offs, key);
446
447 dprintk("going to download %dB of microcode", len);
448 if (dib9000_write16_noinc(state, 1026 + offs, (u8 *) code, (u16) len) != 0) {
449 dprintk("error while downloading microcode for RISC %c", 'A' + risc_id);
450 return -EIO;
451 }
452
453 dprintk("Microcode for RISC %c loaded", 'A' + risc_id);
454
455 return 0;
456 }
457
458 static int dib9000_mbx_host_init(struct dib9000_state *state, u8 risc_id)
459 {
460 u16 mbox_offs;
461 u16 reset_reg;
462 u16 tries = 1000;
463
464 if (risc_id == 1)
465 mbox_offs = 16;
466 else
467 mbox_offs = 0;
468
469 /* Reset mailbox */
470 dib9000_write_word(state, 1027 + mbox_offs, 0x8000);
471
472 /* Read reset status */
473 do {
474 reset_reg = dib9000_read_word(state, 1027 + mbox_offs);
475 msleep(100);
476 } while ((reset_reg & 0x8000) && --tries);
477
478 if (reset_reg & 0x8000) {
479 dprintk("MBX: init ERROR, no response from RISC %c", 'A' + risc_id);
480 return -EIO;
481 }
482 dprintk("MBX: initialized");
483 return 0;
484 }
485
486 #define MAX_MAILBOX_TRY 100
487 static int dib9000_mbx_send_attr(struct dib9000_state *state, u8 id, u16 * data, u8 len, u16 attr)
488 {
489 u8 ret = 0, *d, b[2];
490 u16 tmp;
491 u16 size;
492 u32 i;
493
494 if (!state->platform.risc.fw_is_running)
495 return -EINVAL;
496
497 DibAcquireLock(&state->platform.risc.mbx_if_lock);
498 tmp = MAX_MAILBOX_TRY;
499 do {
500 size = dib9000_read_word_attr(state, 1043, attr) & 0xff;
501 if ((size + len + 1) > MBX_MAX_WORDS && --tmp) {
502 dprintk("MBX: RISC mbx full, retrying");
503 msleep(100);
504 } else
505 break;
506 } while (1);
507
508 /*dprintk( "MBX: size: %d", size); */
509
510 if (tmp == 0) {
511 ret = -EINVAL;
512 goto out;
513 }
514 #ifdef DUMP_MSG
515 dprintk("--> %02x %d ", id, len + 1);
516 for (i = 0; i < len; i++)
517 dprintk("%04x ", data[i]);
518 dprintk("\n");
519 #endif
520
521 /* byte-order conversion - works on big (where it is not necessary) or little endian */
522 d = (u8 *) data;
523 for (i = 0; i < len; i++) {
524 tmp = data[i];
525 *d++ = tmp >> 8;
526 *d++ = tmp & 0xff;
527 }
528
529 /* write msg */
530 b[0] = id;
531 b[1] = len + 1;
532 if (dib9000_write16_noinc_attr(state, 1045, b, 2, attr) != 0 || dib9000_write16_noinc_attr(state, 1045, (u8 *) data, len * 2, attr) != 0) {
533 ret = -EIO;
534 goto out;
535 }
536
537 /* update register nb_mes_in_RX */
538 ret = (u8) dib9000_write_word_attr(state, 1043, 1 << 14, attr);
539
540 out:
541 DibReleaseLock(&state->platform.risc.mbx_if_lock);
542
543 return ret;
544 }
545
546 static u8 dib9000_mbx_read(struct dib9000_state *state, u16 * data, u8 risc_id, u16 attr)
547 {
548 #ifdef DUMP_MSG
549 u16 *d = data;
550 #endif
551
552 u16 tmp, i;
553 u8 size;
554 u8 mc_base;
555
556 if (!state->platform.risc.fw_is_running)
557 return 0;
558
559 DibAcquireLock(&state->platform.risc.mbx_if_lock);
560 if (risc_id == 1)
561 mc_base = 16;
562 else
563 mc_base = 0;
564
565 /* Length and type in the first word */
566 *data = dib9000_read_word_attr(state, 1029 + mc_base, attr);
567
568 size = *data & 0xff;
569 if (size <= MBX_MAX_WORDS) {
570 data++;
571 size--; /* Initial word already read */
572
573 dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, size * 2, attr);
574
575 /* to word conversion */
576 for (i = 0; i < size; i++) {
577 tmp = *data;
578 *data = (tmp >> 8) | (tmp << 8);
579 data++;
580 }
581
582 #ifdef DUMP_MSG
583 dprintk("<-- ");
584 for (i = 0; i < size + 1; i++)
585 dprintk("%04x ", d[i]);
586 dprintk("\n");
587 #endif
588 } else {
589 dprintk("MBX: message is too big for message cache (%d), flushing message", size);
590 size--; /* Initial word already read */
591 while (size--)
592 dib9000_read16_noinc_attr(state, 1029 + mc_base, (u8 *) data, 2, attr);
593 }
594 /* Update register nb_mes_in_TX */
595 dib9000_write_word_attr(state, 1028 + mc_base, 1 << 14, attr);
596
597 DibReleaseLock(&state->platform.risc.mbx_if_lock);
598
599 return size + 1;
600 }
601
602 static int dib9000_risc_debug_buf(struct dib9000_state *state, u16 * data, u8 size)
603 {
604 u32 ts = data[1] << 16 | data[0];
605 char *b = (char *)&data[2];
606
607 b[2 * (size - 2) - 1] = '\0'; /* Bullet proof the buffer */
608 if (*b == '~') {
609 b++;
610 dprintk(b);
611 } else
612 dprintk("RISC%d: %d.%04d %s", state->fe_id, ts / 10000, ts % 10000, *b ? b : "<emtpy>");
613 return 1;
614 }
615
616 static int dib9000_mbx_fetch_to_cache(struct dib9000_state *state, u16 attr)
617 {
618 int i;
619 u8 size;
620 u16 *block;
621 /* find a free slot */
622 for (i = 0; i < DIB9000_MSG_CACHE_SIZE; i++) {
623 block = state->platform.risc.message_cache[i];
624 if (*block == 0) {
625 size = dib9000_mbx_read(state, block, 1, attr);
626
627 /* dprintk( "MBX: fetched %04x message to cache", *block); */
628
629 switch (*block >> 8) {
630 case IN_MSG_DEBUG_BUF:
631 dib9000_risc_debug_buf(state, block + 1, size); /* debug-messages are going to be printed right away */
632 *block = 0; /* free the block */
633 break;
634 #if 0
635 case IN_MSG_DATA: /* FE-TRACE */
636 dib9000_risc_data_process(state, block + 1, size);
637 *block = 0;
638 break;
639 #endif
640 default:
641 break;
642 }
643
644 return 1;
645 }
646 }
647 dprintk("MBX: no free cache-slot found for new message...");
648 return -1;
649 }
650
651 static u8 dib9000_mbx_count(struct dib9000_state *state, u8 risc_id, u16 attr)
652 {
653 if (risc_id == 0)
654 return (u8) (dib9000_read_word_attr(state, 1028, attr) >> 10) & 0x1f; /* 5 bit field */
655 else
656 return (u8) (dib9000_read_word_attr(state, 1044, attr) >> 8) & 0x7f; /* 7 bit field */
657 }
658
659 static int dib9000_mbx_process(struct dib9000_state *state, u16 attr)
660 {
661 int ret = 0;
662 u16 tmp;
663
664 if (!state->platform.risc.fw_is_running)
665 return -1;
666
667 DibAcquireLock(&state->platform.risc.mbx_lock);
668
669 if (dib9000_mbx_count(state, 1, attr)) /* 1=RiscB */
670 ret = dib9000_mbx_fetch_to_cache(state, attr);
671
672 tmp = dib9000_read_word_attr(state, 1229, attr); /* Clear the IRQ */
673 /* if (tmp) */
674 /* dprintk( "cleared IRQ: %x", tmp); */
675 DibReleaseLock(&state->platform.risc.mbx_lock);
676
677 return ret;
678 }
679
680 static int dib9000_mbx_get_message_attr(struct dib9000_state *state, u16 id, u16 * msg, u8 * size, u16 attr)
681 {
682 u8 i;
683 u16 *block;
684 u16 timeout = 30;
685
686 *msg = 0;
687 do {
688 /* dib9000_mbx_get_from_cache(); */
689 for (i = 0; i < DIB9000_MSG_CACHE_SIZE; i++) {
690 block = state->platform.risc.message_cache[i];
691 if ((*block >> 8) == id) {
692 *size = (*block & 0xff) - 1;
693 memcpy(msg, block + 1, (*size) * 2);
694 *block = 0; /* free the block */
695 i = 0; /* signal that we found a message */
696 break;
697 }
698 }
699
700 if (i == 0)
701 break;
702
703 if (dib9000_mbx_process(state, attr) == -1) /* try to fetch one message - if any */
704 return -1;
705
706 } while (--timeout);
707
708 if (timeout == 0) {
709 dprintk("waiting for message %d timed out", id);
710 return -1;
711 }
712
713 return i == 0;
714 }
715
716 static int dib9000_risc_check_version(struct dib9000_state *state)
717 {
718 u8 r[4];
719 u8 size;
720 u16 fw_version = 0;
721
722 if (dib9000_mbx_send(state, OUT_MSG_REQ_VERSION, &fw_version, 1) != 0)
723 return -EIO;
724
725 if (dib9000_mbx_get_message(state, IN_MSG_VERSION, (u16 *) r, &size) < 0)
726 return -EIO;
727
728 fw_version = (r[0] << 8) | r[1];
729 dprintk("RISC: ver: %d.%02d (IC: %d)", fw_version >> 10, fw_version & 0x3ff, (r[2] << 8) | r[3]);
730
731 if ((fw_version >> 10) != 7)
732 return -EINVAL;
733
734 switch (fw_version & 0x3ff) {
735 case 11:
736 case 12:
737 case 14:
738 case 15:
739 case 16:
740 case 17:
741 break;
742 default:
743 dprintk("RISC: invalid firmware version");
744 return -EINVAL;
745 }
746
747 dprintk("RISC: valid firmware version");
748 return 0;
749 }
750
751 static int dib9000_fw_boot(struct dib9000_state *state, const u8 * codeA, u32 lenA, const u8 * codeB, u32 lenB)
752 {
753 /* Reconfig pool mac ram */
754 dib9000_write_word(state, 1225, 0x02); /* A: 8k C, 4 k D - B: 32k C 6 k D - IRAM 96k */
755 dib9000_write_word(state, 1226, 0x05);
756
757 /* Toggles IP crypto to Host APB interface. */
758 dib9000_write_word(state, 1542, 1);
759
760 /* Set jump and no jump in the dma box */
761 dib9000_write_word(state, 1074, 0);
762 dib9000_write_word(state, 1075, 0);
763
764 /* Set MAC as APB Master. */
765 dib9000_write_word(state, 1237, 0);
766
767 /* Reset the RISCs */
768 if (codeA != NULL)
769 dib9000_write_word(state, 1024, 2);
770 else
771 dib9000_write_word(state, 1024, 15);
772 if (codeB != NULL)
773 dib9000_write_word(state, 1040, 2);
774
775 if (codeA != NULL)
776 dib9000_firmware_download(state, 0, 0x1234, codeA, lenA);
777 if (codeB != NULL)
778 dib9000_firmware_download(state, 1, 0x1234, codeB, lenB);
779
780 /* Run the RISCs */
781 if (codeA != NULL)
782 dib9000_write_word(state, 1024, 0);
783 if (codeB != NULL)
784 dib9000_write_word(state, 1040, 0);
785
786 if (codeA != NULL)
787 if (dib9000_mbx_host_init(state, 0) != 0)
788 return -EIO;
789 if (codeB != NULL)
790 if (dib9000_mbx_host_init(state, 1) != 0)
791 return -EIO;
792
793 msleep(100);
794 state->platform.risc.fw_is_running = 1;
795
796 if (dib9000_risc_check_version(state) != 0)
797 return -EINVAL;
798
799 state->platform.risc.memcmd = 0xff;
800 return 0;
801 }
802
803 static u16 dib9000_identify(struct i2c_device *client)
804 {
805 u16 value;
806
807 value = dib9000_i2c_read16(client, 896);
808 if (value != 0x01b3) {
809 dprintk("wrong Vendor ID (0x%x)", value);
810 return 0;
811 }
812
813 value = dib9000_i2c_read16(client, 897);
814 if (value != 0x4000 && value != 0x4001 && value != 0x4002 && value != 0x4003 && value != 0x4004 && value != 0x4005) {
815 dprintk("wrong Device ID (0x%x)", value);
816 return 0;
817 }
818
819 /* protect this driver to be used with 7000PC */
820 if (value == 0x4000 && dib9000_i2c_read16(client, 769) == 0x4000) {
821 dprintk("this driver does not work with DiB7000PC");
822 return 0;
823 }
824
825 switch (value) {
826 case 0x4000:
827 dprintk("found DiB7000MA/PA/MB/PB");
828 break;
829 case 0x4001:
830 dprintk("found DiB7000HC");
831 break;
832 case 0x4002:
833 dprintk("found DiB7000MC");
834 break;
835 case 0x4003:
836 dprintk("found DiB9000A");
837 break;
838 case 0x4004:
839 dprintk("found DiB9000H");
840 break;
841 case 0x4005:
842 dprintk("found DiB9000M");
843 break;
844 }
845
846 return value;
847 }
848
849 static void dib9000_set_power_mode(struct dib9000_state *state, enum dib9000_power_mode mode)
850 {
851 /* by default everything is going to be powered off */
852 u16 reg_903 = 0x3fff, reg_904 = 0xffff, reg_905 = 0xffff, reg_906;
853 u8 offset;
854
855 if (state->revision == 0x4003 || state->revision == 0x4004 || state->revision == 0x4005)
856 offset = 1;
857 else
858 offset = 0;
859
860 reg_906 = dib9000_read_word(state, 906 + offset) | 0x3; /* keep settings for RISC */
861
862 /* now, depending on the requested mode, we power on */
863 switch (mode) {
864 /* power up everything in the demod */
865 case DIB9000_POWER_ALL:
866 reg_903 = 0x0000;
867 reg_904 = 0x0000;
868 reg_905 = 0x0000;
869 reg_906 = 0x0000;
870 break;
871
872 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO or SRAM) */
873 case DIB9000_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C or SRAM */
874 reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 2));
875 break;
876
877 case DIB9000_POWER_INTERF_ANALOG_AGC:
878 reg_903 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10));
879 reg_905 &= ~((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | (1 << 2));
880 reg_906 &= ~((1 << 0));
881 break;
882
883 case DIB9000_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD:
884 reg_903 = 0x0000;
885 reg_904 = 0x801f;
886 reg_905 = 0x0000;
887 reg_906 &= ~((1 << 0));
888 break;
889
890 case DIB9000_POWER_COR4_CRY_ESRAM_MOUT_NUD:
891 reg_903 = 0x0000;
892 reg_904 = 0x8000;
893 reg_905 = 0x010b;
894 reg_906 &= ~((1 << 0));
895 break;
896 default:
897 case DIB9000_POWER_NO:
898 break;
899 }
900
901 /* always power down unused parts */
902 if (!state->platform.host.mobile_mode)
903 reg_904 |= (1 << 7) | (1 << 6) | (1 << 4) | (1 << 2) | (1 << 1);
904
905 /* P_sdio_select_clk = 0 on MC and after */
906 if (state->revision != 0x4000)
907 reg_906 <<= 1;
908
909 dib9000_write_word(state, 903 + offset, reg_903);
910 dib9000_write_word(state, 904 + offset, reg_904);
911 dib9000_write_word(state, 905 + offset, reg_905);
912 dib9000_write_word(state, 906 + offset, reg_906);
913 }
914
915 static int dib9000_fw_reset(struct dvb_frontend *fe)
916 {
917 struct dib9000_state *state = fe->demodulator_priv;
918
919 dib9000_write_word(state, 1817, 0x0003);
920
921 dib9000_write_word(state, 1227, 1);
922 dib9000_write_word(state, 1227, 0);
923
924 switch ((state->revision = dib9000_identify(&state->i2c))) {
925 case 0x4003:
926 case 0x4004:
927 case 0x4005:
928 state->reg_offs = 1;
929 break;
930 default:
931 return -EINVAL;
932 }
933
934 /* reset the i2c-master to use the host interface */
935 dibx000_reset_i2c_master(&state->i2c_master);
936
937 dib9000_set_power_mode(state, DIB9000_POWER_ALL);
938
939 /* unforce divstr regardless whether i2c enumeration was done or not */
940 dib9000_write_word(state, 1794, dib9000_read_word(state, 1794) & ~(1 << 1));
941 dib9000_write_word(state, 1796, 0);
942 dib9000_write_word(state, 1805, 0x805);
943
944 /* restart all parts */
945 dib9000_write_word(state, 898, 0xffff);
946 dib9000_write_word(state, 899, 0xffff);
947 dib9000_write_word(state, 900, 0x0001);
948 dib9000_write_word(state, 901, 0xff19);
949 dib9000_write_word(state, 902, 0x003c);
950
951 dib9000_write_word(state, 898, 0);
952 dib9000_write_word(state, 899, 0);
953 dib9000_write_word(state, 900, 0);
954 dib9000_write_word(state, 901, 0);
955 dib9000_write_word(state, 902, 0);
956
957 dib9000_write_word(state, 911, state->chip.d9.cfg.if_drives);
958
959 dib9000_set_power_mode(state, DIB9000_POWER_INTERFACE_ONLY);
960
961 return 0;
962 }
963
964 static int dib9000_risc_apb_access_read(struct dib9000_state *state, u32 address, u16 attribute, const u8 * tx, u32 txlen, u8 * b, u32 len)
965 {
966 u16 mb[10];
967 u8 i, s;
968
969 if (address >= 1024 || !state->platform.risc.fw_is_running)
970 return -EINVAL;
971
972 /* dprintk( "APB access thru rd fw %d %x", address, attribute); */
973
974 mb[0] = (u16) address;
975 mb[1] = len / 2;
976 dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_R, mb, 2, attribute);
977 switch (dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute)) {
978 case 1:
979 s--;
980 for (i = 0; i < s; i++) {
981 b[i * 2] = (mb[i + 1] >> 8) & 0xff;
982 b[i * 2 + 1] = (mb[i + 1]) & 0xff;
983 }
984 return 0;
985 default:
986 return -EIO;
987 }
988 return -EIO;
989 }
990
991 static int dib9000_risc_apb_access_write(struct dib9000_state *state, u32 address, u16 attribute, const u8 * b, u32 len)
992 {
993 u16 mb[10];
994 u8 s, i;
995
996 if (address >= 1024 || !state->platform.risc.fw_is_running)
997 return -EINVAL;
998
999 /* dprintk( "APB access thru wr fw %d %x", address, attribute); */
1000
1001 mb[0] = (unsigned short)address;
1002 for (i = 0; i < len && i < 20; i += 2)
1003 mb[1 + (i / 2)] = (b[i] << 8 | b[i + 1]);
1004
1005 dib9000_mbx_send_attr(state, OUT_MSG_BRIDGE_APB_W, mb, 1 + len / 2, attribute);
1006 return dib9000_mbx_get_message_attr(state, IN_MSG_END_BRIDGE_APB_RW, mb, &s, attribute) == 1 ? 0 : -EINVAL;
1007 }
1008
1009 static int dib9000_fw_memmbx_sync(struct dib9000_state *state, u8 i)
1010 {
1011 u8 index_loop = 10;
1012
1013 if (!state->platform.risc.fw_is_running)
1014 return 0;
1015 dib9000_risc_mem_write(state, FE_MM_RW_SYNC, &i);
1016 do {
1017 dib9000_risc_mem_read(state, FE_MM_RW_SYNC, &i, 1);
1018 } while (i && index_loop--);
1019
1020 if (index_loop > 0)
1021 return 0;
1022 return -EIO;
1023 }
1024
1025 static int dib9000_fw_init(struct dib9000_state *state)
1026 {
1027 struct dibGPIOFunction *f;
1028 u16 b[40] = { 0 };
1029 u8 i;
1030 u8 size;
1031
1032 if (dib9000_fw_boot(state, NULL, 0, state->chip.d9.cfg.microcode_B_fe_buffer, state->chip.d9.cfg.microcode_B_fe_size) != 0)
1033 return -EIO;
1034
1035 /* initialize the firmware */
1036 for (i = 0; i < ARRAY_SIZE(state->chip.d9.cfg.gpio_function); i++) {
1037 f = &state->chip.d9.cfg.gpio_function[i];
1038 if (f->mask) {
1039 switch (f->function) {
1040 case BOARD_GPIO_FUNCTION_COMPONENT_ON:
1041 b[0] = (u16) f->mask;
1042 b[1] = (u16) f->direction;
1043 b[2] = (u16) f->value;
1044 break;
1045 case BOARD_GPIO_FUNCTION_COMPONENT_OFF:
1046 b[3] = (u16) f->mask;
1047 b[4] = (u16) f->direction;
1048 b[5] = (u16) f->value;
1049 break;
1050 }
1051 }
1052 }
1053 if (dib9000_mbx_send(state, OUT_MSG_CONF_GPIO, b, 15) != 0)
1054 return -EIO;
1055
1056 /* subband */
1057 b[0] = state->chip.d9.cfg.subband.size; /* type == 0 -> GPIO - PWM not yet supported */
1058 for (i = 0; i < state->chip.d9.cfg.subband.size; i++) {
1059 b[1 + i * 4] = state->chip.d9.cfg.subband.subband[i].f_mhz;
1060 b[2 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.mask;
1061 b[3 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.direction;
1062 b[4 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.value;
1063 }
1064 b[1 + i * 4] = 0; /* fe_id */
1065 if (dib9000_mbx_send(state, OUT_MSG_SUBBAND_SEL, b, 2 + 4 * i) != 0)
1066 return -EIO;
1067
1068 /* 0 - id, 1 - no_of_frontends */
1069 b[0] = (0 << 8) | 1;
1070 /* 0 = i2c-address demod, 0 = tuner */
1071 b[1] = (0 << 8) | (0);
1072 b[2] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000) >> 16) & 0xffff);
1073 b[3] = (u16) (((state->chip.d9.cfg.xtal_clock_khz * 1000)) & 0xffff);
1074 b[4] = (u16) ((state->chip.d9.cfg.vcxo_timer >> 16) & 0xffff);
1075 b[5] = (u16) ((state->chip.d9.cfg.vcxo_timer) & 0xffff);
1076 b[6] = (u16) ((state->chip.d9.cfg.timing_frequency >> 16) & 0xffff);
1077 b[7] = (u16) ((state->chip.d9.cfg.timing_frequency) & 0xffff);
1078 b[29] = state->chip.d9.cfg.if_drives;
1079 if (dib9000_mbx_send(state, OUT_MSG_INIT_DEMOD, b, ARRAY_SIZE(b)) != 0)
1080 return -EIO;
1081
1082 if (dib9000_mbx_send(state, OUT_MSG_FE_FW_DL, NULL, 0) != 0)
1083 return -EIO;
1084
1085 if (dib9000_mbx_get_message(state, IN_MSG_FE_FW_DL_DONE, b, &size) < 0)
1086 return -EIO;
1087
1088 if (size > ARRAY_SIZE(b)) {
1089 dprintk("error : firmware returned %dbytes needed but the used buffer has only %dbytes\n Firmware init ABORTED", size,
1090 (int)ARRAY_SIZE(b));
1091 return -EINVAL;
1092 }
1093
1094 for (i = 0; i < size; i += 2) {
1095 state->platform.risc.fe_mm[i / 2].addr = b[i + 0];
1096 state->platform.risc.fe_mm[i / 2].size = b[i + 1];
1097 }
1098
1099 return 0;
1100 }
1101
1102 static void dib9000_fw_set_channel_head(struct dib9000_state *state, struct dvb_frontend_parameters *ch)
1103 {
1104 u8 b[9];
1105 u32 freq = state->fe[0]->dtv_property_cache.frequency / 1000;
1106 if (state->fe_id % 2)
1107 freq += 101;
1108
1109 b[0] = (u8) ((freq >> 0) & 0xff);
1110 b[1] = (u8) ((freq >> 8) & 0xff);
1111 b[2] = (u8) ((freq >> 16) & 0xff);
1112 b[3] = (u8) ((freq >> 24) & 0xff);
1113 b[4] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 0) & 0xff);
1114 b[5] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 8) & 0xff);
1115 b[6] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 16) & 0xff);
1116 b[7] = (u8) ((state->fe[0]->dtv_property_cache.bandwidth_hz / 1000 >> 24) & 0xff);
1117 b[8] = 0x80; /* do not wait for CELL ID when doing autosearch */
1118 if (state->fe[0]->dtv_property_cache.delivery_system == SYS_DVBT)
1119 b[8] |= 1;
1120 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_HEAD, b);
1121 }
1122
1123 static int dib9000_fw_get_channel(struct dvb_frontend *fe, struct dvb_frontend_parameters *channel)
1124 {
1125 struct dib9000_state *state = fe->demodulator_priv;
1126 struct dibDVBTChannel {
1127 s8 spectrum_inversion;
1128
1129 s8 nfft;
1130 s8 guard;
1131 s8 constellation;
1132
1133 s8 hrch;
1134 s8 alpha;
1135 s8 code_rate_hp;
1136 s8 code_rate_lp;
1137 s8 select_hp;
1138
1139 s8 intlv_native;
1140 };
1141 struct dibDVBTChannel ch;
1142 int ret = 0;
1143
1144 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
1145 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) {
1146 goto error;
1147 ret = -EIO;
1148 }
1149
1150 dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_UNION, (u8 *) &ch, sizeof(struct dibDVBTChannel));
1151
1152 switch (ch.spectrum_inversion & 0x7) {
1153 case 1:
1154 state->fe[0]->dtv_property_cache.inversion = INVERSION_ON;
1155 break;
1156 case 0:
1157 state->fe[0]->dtv_property_cache.inversion = INVERSION_OFF;
1158 break;
1159 default:
1160 case -1:
1161 state->fe[0]->dtv_property_cache.inversion = INVERSION_AUTO;
1162 break;
1163 }
1164 switch (ch.nfft) {
1165 case 0:
1166 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_2K;
1167 break;
1168 case 2:
1169 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_4K;
1170 break;
1171 case 1:
1172 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
1173 break;
1174 default:
1175 case -1:
1176 state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_AUTO;
1177 break;
1178 }
1179 switch (ch.guard) {
1180 case 0:
1181 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_32;
1182 break;
1183 case 1:
1184 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_16;
1185 break;
1186 case 2:
1187 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
1188 break;
1189 case 3:
1190 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_4;
1191 break;
1192 default:
1193 case -1:
1194 state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_AUTO;
1195 break;
1196 }
1197 switch (ch.constellation) {
1198 case 2:
1199 state->fe[0]->dtv_property_cache.modulation = QAM_64;
1200 break;
1201 case 1:
1202 state->fe[0]->dtv_property_cache.modulation = QAM_16;
1203 break;
1204 case 0:
1205 state->fe[0]->dtv_property_cache.modulation = QPSK;
1206 break;
1207 default:
1208 case -1:
1209 state->fe[0]->dtv_property_cache.modulation = QAM_AUTO;
1210 break;
1211 }
1212 switch (ch.hrch) {
1213 case 0:
1214 state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_NONE;
1215 break;
1216 case 1:
1217 state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_1;
1218 break;
1219 default:
1220 case -1:
1221 state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_AUTO;
1222 break;
1223 }
1224 switch (ch.code_rate_hp) {
1225 case 1:
1226 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_1_2;
1227 break;
1228 case 2:
1229 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_2_3;
1230 break;
1231 case 3:
1232 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_3_4;
1233 break;
1234 case 5:
1235 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_5_6;
1236 break;
1237 case 7:
1238 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_7_8;
1239 break;
1240 default:
1241 case -1:
1242 state->fe[0]->dtv_property_cache.code_rate_HP = FEC_AUTO;
1243 break;
1244 }
1245 switch (ch.code_rate_lp) {
1246 case 1:
1247 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_1_2;
1248 break;
1249 case 2:
1250 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_2_3;
1251 break;
1252 case 3:
1253 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_3_4;
1254 break;
1255 case 5:
1256 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_5_6;
1257 break;
1258 case 7:
1259 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_7_8;
1260 break;
1261 default:
1262 case -1:
1263 state->fe[0]->dtv_property_cache.code_rate_LP = FEC_AUTO;
1264 break;
1265 }
1266
1267 error:
1268 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
1269 return ret;
1270 }
1271
1272 static int dib9000_fw_set_channel_union(struct dvb_frontend *fe, struct dvb_frontend_parameters *channel)
1273 {
1274 struct dib9000_state *state = fe->demodulator_priv;
1275 struct dibDVBTChannel {
1276 s8 spectrum_inversion;
1277
1278 s8 nfft;
1279 s8 guard;
1280 s8 constellation;
1281
1282 s8 hrch;
1283 s8 alpha;
1284 s8 code_rate_hp;
1285 s8 code_rate_lp;
1286 s8 select_hp;
1287
1288 s8 intlv_native;
1289 };
1290 struct dibDVBTChannel ch;
1291
1292 switch (state->fe[0]->dtv_property_cache.inversion) {
1293 case INVERSION_ON:
1294 ch.spectrum_inversion = 1;
1295 break;
1296 case INVERSION_OFF:
1297 ch.spectrum_inversion = 0;
1298 break;
1299 default:
1300 case INVERSION_AUTO:
1301 ch.spectrum_inversion = -1;
1302 break;
1303 }
1304 switch (state->fe[0]->dtv_property_cache.transmission_mode) {
1305 case TRANSMISSION_MODE_2K:
1306 ch.nfft = 0;
1307 break;
1308 case TRANSMISSION_MODE_4K:
1309 ch.nfft = 2;
1310 break;
1311 case TRANSMISSION_MODE_8K:
1312 ch.nfft = 1;
1313 break;
1314 default:
1315 case TRANSMISSION_MODE_AUTO:
1316 ch.nfft = 1;
1317 break;
1318 }
1319 switch (state->fe[0]->dtv_property_cache.guard_interval) {
1320 case GUARD_INTERVAL_1_32:
1321 ch.guard = 0;
1322 break;
1323 case GUARD_INTERVAL_1_16:
1324 ch.guard = 1;
1325 break;
1326 case GUARD_INTERVAL_1_8:
1327 ch.guard = 2;
1328 break;
1329 case GUARD_INTERVAL_1_4:
1330 ch.guard = 3;
1331 break;
1332 default:
1333 case GUARD_INTERVAL_AUTO:
1334 ch.guard = -1;
1335 break;
1336 }
1337 switch (state->fe[0]->dtv_property_cache.modulation) {
1338 case QAM_64:
1339 ch.constellation = 2;
1340 break;
1341 case QAM_16:
1342 ch.constellation = 1;
1343 break;
1344 case QPSK:
1345 ch.constellation = 0;
1346 break;
1347 default:
1348 case QAM_AUTO:
1349 ch.constellation = -1;
1350 break;
1351 }
1352 switch (state->fe[0]->dtv_property_cache.hierarchy) {
1353 case HIERARCHY_NONE:
1354 ch.hrch = 0;
1355 break;
1356 case HIERARCHY_1:
1357 case HIERARCHY_2:
1358 case HIERARCHY_4:
1359 ch.hrch = 1;
1360 break;
1361 default:
1362 case HIERARCHY_AUTO:
1363 ch.hrch = -1;
1364 break;
1365 }
1366 ch.alpha = 1;
1367 switch (state->fe[0]->dtv_property_cache.code_rate_HP) {
1368 case FEC_1_2:
1369 ch.code_rate_hp = 1;
1370 break;
1371 case FEC_2_3:
1372 ch.code_rate_hp = 2;
1373 break;
1374 case FEC_3_4:
1375 ch.code_rate_hp = 3;
1376 break;
1377 case FEC_5_6:
1378 ch.code_rate_hp = 5;
1379 break;
1380 case FEC_7_8:
1381 ch.code_rate_hp = 7;
1382 break;
1383 default:
1384 case FEC_AUTO:
1385 ch.code_rate_hp = -1;
1386 break;
1387 }
1388 switch (state->fe[0]->dtv_property_cache.code_rate_LP) {
1389 case FEC_1_2:
1390 ch.code_rate_lp = 1;
1391 break;
1392 case FEC_2_3:
1393 ch.code_rate_lp = 2;
1394 break;
1395 case FEC_3_4:
1396 ch.code_rate_lp = 3;
1397 break;
1398 case FEC_5_6:
1399 ch.code_rate_lp = 5;
1400 break;
1401 case FEC_7_8:
1402 ch.code_rate_lp = 7;
1403 break;
1404 default:
1405 case FEC_AUTO:
1406 ch.code_rate_lp = -1;
1407 break;
1408 }
1409 ch.select_hp = 1;
1410 ch.intlv_native = 1;
1411
1412 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_UNION, (u8 *) &ch);
1413
1414 return 0;
1415 }
1416
1417 static int dib9000_fw_tune(struct dvb_frontend *fe, struct dvb_frontend_parameters *ch)
1418 {
1419 struct dib9000_state *state = fe->demodulator_priv;
1420 int ret = 10, search = state->channel_status.status == CHANNEL_STATUS_PARAMETERS_UNKNOWN;
1421 s8 i;
1422
1423 switch (state->tune_state) {
1424 case CT_DEMOD_START:
1425 dib9000_fw_set_channel_head(state, ch);
1426
1427 /* write the channel context - a channel is initialized to 0, so it is OK */
1428 dib9000_risc_mem_write(state, FE_MM_W_CHANNEL_CONTEXT, (u8 *) fe_info);
1429 dib9000_risc_mem_write(state, FE_MM_W_FE_INFO, (u8 *) fe_info);
1430
1431 if (search)
1432 dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_SEARCH, NULL, 0);
1433 else {
1434 dib9000_fw_set_channel_union(fe, ch);
1435 dib9000_mbx_send(state, OUT_MSG_FE_CHANNEL_TUNE, NULL, 0);
1436 }
1437 state->tune_state = CT_DEMOD_STEP_1;
1438 break;
1439 case CT_DEMOD_STEP_1:
1440 if (search)
1441 dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_SEARCH_STATE, (u8 *) &i, 1);
1442 else
1443 dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_TUNE_STATE, (u8 *) &i, 1);
1444 switch (i) { /* something happened */
1445 case 0:
1446 break;
1447 case -2: /* tps locks are "slower" than MPEG locks -> even in autosearch data is OK here */
1448 if (search)
1449 state->status = FE_STATUS_DEMOD_SUCCESS;
1450 else {
1451 state->tune_state = CT_DEMOD_STOP;
1452 state->status = FE_STATUS_LOCKED;
1453 }
1454 break;
1455 default:
1456 state->status = FE_STATUS_TUNE_FAILED;
1457 state->tune_state = CT_DEMOD_STOP;
1458 break;
1459 }
1460 break;
1461 default:
1462 ret = FE_CALLBACK_TIME_NEVER;
1463 break;
1464 }
1465
1466 return ret;
1467 }
1468
1469 static int dib9000_fw_set_diversity_in(struct dvb_frontend *fe, int onoff)
1470 {
1471 struct dib9000_state *state = fe->demodulator_priv;
1472 u16 mode = (u16) onoff;
1473 return dib9000_mbx_send(state, OUT_MSG_ENABLE_DIVERSITY, &mode, 1);
1474 }
1475
1476 static int dib9000_fw_set_output_mode(struct dvb_frontend *fe, int mode)
1477 {
1478 struct dib9000_state *state = fe->demodulator_priv;
1479 u16 outreg, smo_mode;
1480
1481 dprintk("setting output mode for demod %p to %d", fe, mode);
1482
1483 switch (mode) {
1484 case OUTMODE_MPEG2_PAR_GATED_CLK:
1485 outreg = (1 << 10); /* 0x0400 */
1486 break;
1487 case OUTMODE_MPEG2_PAR_CONT_CLK:
1488 outreg = (1 << 10) | (1 << 6); /* 0x0440 */
1489 break;
1490 case OUTMODE_MPEG2_SERIAL:
1491 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */
1492 break;
1493 case OUTMODE_DIVERSITY:
1494 outreg = (1 << 10) | (4 << 6); /* 0x0500 */
1495 break;
1496 case OUTMODE_MPEG2_FIFO:
1497 outreg = (1 << 10) | (5 << 6);
1498 break;
1499 case OUTMODE_HIGH_Z:
1500 outreg = 0;
1501 break;
1502 default:
1503 dprintk("Unhandled output_mode passed to be set for demod %p", &state->fe[0]);
1504 return -EINVAL;
1505 }
1506
1507 dib9000_write_word(state, 1795, outreg);
1508
1509 switch (mode) {
1510 case OUTMODE_MPEG2_PAR_GATED_CLK:
1511 case OUTMODE_MPEG2_PAR_CONT_CLK:
1512 case OUTMODE_MPEG2_SERIAL:
1513 case OUTMODE_MPEG2_FIFO:
1514 smo_mode = (dib9000_read_word(state, 295) & 0x0010) | (1 << 1);
1515 if (state->chip.d9.cfg.output_mpeg2_in_188_bytes)
1516 smo_mode |= (1 << 5);
1517 dib9000_write_word(state, 295, smo_mode);
1518 break;
1519 }
1520
1521 outreg = to_fw_output_mode(mode);
1522 return dib9000_mbx_send(state, OUT_MSG_SET_OUTPUT_MODE, &outreg, 1);
1523 }
1524
1525 static int dib9000_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1526 {
1527 struct dib9000_state *state = i2c_get_adapdata(i2c_adap);
1528 u16 i, len, t, index_msg;
1529
1530 for (index_msg = 0; index_msg < num; index_msg++) {
1531 if (msg[index_msg].flags & I2C_M_RD) { /* read */
1532 len = msg[index_msg].len;
1533 if (len > 16)
1534 len = 16;
1535
1536 if (dib9000_read_word(state, 790) != 0)
1537 dprintk("TunerITF: read busy");
1538
1539 dib9000_write_word(state, 784, (u16) (msg[index_msg].addr));
1540 dib9000_write_word(state, 787, (len / 2) - 1);
1541 dib9000_write_word(state, 786, 1); /* start read */
1542
1543 i = 1000;
1544 while (dib9000_read_word(state, 790) != (len / 2) && i)
1545 i--;
1546
1547 if (i == 0)
1548 dprintk("TunerITF: read failed");
1549
1550 for (i = 0; i < len; i += 2) {
1551 t = dib9000_read_word(state, 785);
1552 msg[index_msg].buf[i] = (t >> 8) & 0xff;
1553 msg[index_msg].buf[i + 1] = (t) & 0xff;
1554 }
1555 if (dib9000_read_word(state, 790) != 0)
1556 dprintk("TunerITF: read more data than expected");
1557 } else {
1558 i = 1000;
1559 while (dib9000_read_word(state, 789) && i)
1560 i--;
1561 if (i == 0)
1562 dprintk("TunerITF: write busy");
1563
1564 len = msg[index_msg].len;
1565 if (len > 16)
1566 len = 16;
1567
1568 for (i = 0; i < len; i += 2)
1569 dib9000_write_word(state, 785, (msg[index_msg].buf[i] << 8) | msg[index_msg].buf[i + 1]);
1570 dib9000_write_word(state, 784, (u16) msg[index_msg].addr);
1571 dib9000_write_word(state, 787, (len / 2) - 1);
1572 dib9000_write_word(state, 786, 0); /* start write */
1573
1574 i = 1000;
1575 while (dib9000_read_word(state, 791) > 0 && i)
1576 i--;
1577 if (i == 0)
1578 dprintk("TunerITF: write failed");
1579 }
1580 }
1581 return num;
1582 }
1583
1584 int dib9000_fw_set_component_bus_speed(struct dvb_frontend *fe, u16 speed)
1585 {
1586 struct dib9000_state *state = fe->demodulator_priv;
1587
1588 state->component_bus_speed = speed;
1589 return 0;
1590 }
1591 EXPORT_SYMBOL(dib9000_fw_set_component_bus_speed);
1592
1593 static int dib9000_fw_component_bus_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1594 {
1595 struct dib9000_state *state = i2c_get_adapdata(i2c_adap);
1596 u8 type = 0; /* I2C */
1597 u8 port = DIBX000_I2C_INTERFACE_GPIO_3_4;
1598 u16 scl = state->component_bus_speed; /* SCL frequency */
1599 struct dib9000_fe_memory_map *m = &state->platform.risc.fe_mm[FE_MM_RW_COMPONENT_ACCESS_BUFFER];
1600 u8 p[13] = { 0 };
1601
1602 p[0] = type;
1603 p[1] = port;
1604 p[2] = msg[0].addr << 1;
1605
1606 p[3] = (u8) scl & 0xff; /* scl */
1607 p[4] = (u8) (scl >> 8);
1608
1609 p[7] = 0;
1610 p[8] = 0;
1611
1612 p[9] = (u8) (msg[0].len);
1613 p[10] = (u8) (msg[0].len >> 8);
1614 if ((num > 1) && (msg[1].flags & I2C_M_RD)) {
1615 p[11] = (u8) (msg[1].len);
1616 p[12] = (u8) (msg[1].len >> 8);
1617 } else {
1618 p[11] = 0;
1619 p[12] = 0;
1620 }
1621
1622 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
1623
1624 dib9000_risc_mem_write(state, FE_MM_W_COMPONENT_ACCESS, p);
1625
1626 { /* write-part */
1627 dib9000_risc_mem_setup_cmd(state, m->addr, msg[0].len, 0);
1628 dib9000_risc_mem_write_chunks(state, msg[0].buf, msg[0].len);
1629 }
1630
1631 /* do the transaction */
1632 if (dib9000_fw_memmbx_sync(state, FE_SYNC_COMPONENT_ACCESS) < 0) {
1633 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
1634 return 0;
1635 }
1636
1637 /* read back any possible result */
1638 if ((num > 1) && (msg[1].flags & I2C_M_RD))
1639 dib9000_risc_mem_read(state, FE_MM_RW_COMPONENT_ACCESS_BUFFER, msg[1].buf, msg[1].len);
1640
1641 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
1642
1643 return num;
1644 }
1645
1646 static u32 dib9000_i2c_func(struct i2c_adapter *adapter)
1647 {
1648 return I2C_FUNC_I2C;
1649 }
1650
1651 static struct i2c_algorithm dib9000_tuner_algo = {
1652 .master_xfer = dib9000_tuner_xfer,
1653 .functionality = dib9000_i2c_func,
1654 };
1655
1656 static struct i2c_algorithm dib9000_component_bus_algo = {
1657 .master_xfer = dib9000_fw_component_bus_xfer,
1658 .functionality = dib9000_i2c_func,
1659 };
1660
1661 struct i2c_adapter *dib9000_get_tuner_interface(struct dvb_frontend *fe)
1662 {
1663 struct dib9000_state *st = fe->demodulator_priv;
1664 return &st->tuner_adap;
1665 }
1666 EXPORT_SYMBOL(dib9000_get_tuner_interface);
1667
1668 struct i2c_adapter *dib9000_get_component_bus_interface(struct dvb_frontend *fe)
1669 {
1670 struct dib9000_state *st = fe->demodulator_priv;
1671 return &st->component_bus;
1672 }
1673 EXPORT_SYMBOL(dib9000_get_component_bus_interface);
1674
1675 struct i2c_adapter *dib9000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
1676 {
1677 struct dib9000_state *st = fe->demodulator_priv;
1678 return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
1679 }
1680 EXPORT_SYMBOL(dib9000_get_i2c_master);
1681
1682 int dib9000_set_i2c_adapter(struct dvb_frontend *fe, struct i2c_adapter *i2c)
1683 {
1684 struct dib9000_state *st = fe->demodulator_priv;
1685
1686 st->i2c.i2c_adap = i2c;
1687 return 0;
1688 }
1689 EXPORT_SYMBOL(dib9000_set_i2c_adapter);
1690
1691 static int dib9000_cfg_gpio(struct dib9000_state *st, u8 num, u8 dir, u8 val)
1692 {
1693 st->gpio_dir = dib9000_read_word(st, 773);
1694 st->gpio_dir &= ~(1 << num); /* reset the direction bit */
1695 st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */
1696 dib9000_write_word(st, 773, st->gpio_dir);
1697
1698 st->gpio_val = dib9000_read_word(st, 774);
1699 st->gpio_val &= ~(1 << num); /* reset the direction bit */
1700 st->gpio_val |= (val & 0x01) << num; /* set the new value */
1701 dib9000_write_word(st, 774, st->gpio_val);
1702
1703 dprintk("gpio dir: %04x: gpio val: %04x", st->gpio_dir, st->gpio_val);
1704
1705 return 0;
1706 }
1707
1708 int dib9000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
1709 {
1710 struct dib9000_state *state = fe->demodulator_priv;
1711 return dib9000_cfg_gpio(state, num, dir, val);
1712 }
1713 EXPORT_SYMBOL(dib9000_set_gpio);
1714
1715 int dib9000_fw_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
1716 {
1717 struct dib9000_state *state = fe->demodulator_priv;
1718 u16 val = dib9000_read_word(state, 294 + 1) & 0xffef;
1719 val |= (onoff & 0x1) << 4;
1720
1721 dprintk("PID filter enabled %d", onoff);
1722 return dib9000_write_word(state, 294 + 1, val);
1723 }
1724 EXPORT_SYMBOL(dib9000_fw_pid_filter_ctrl);
1725
1726 int dib9000_fw_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
1727 {
1728 struct dib9000_state *state = fe->demodulator_priv;
1729 dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
1730 return dib9000_write_word(state, 300 + 1 + id, onoff ? (1 << 13) | pid : 0);
1731 }
1732 EXPORT_SYMBOL(dib9000_fw_pid_filter);
1733
1734 int dib9000_firmware_post_pll_init(struct dvb_frontend *fe)
1735 {
1736 struct dib9000_state *state = fe->demodulator_priv;
1737 return dib9000_fw_init(state);
1738 }
1739 EXPORT_SYMBOL(dib9000_firmware_post_pll_init);
1740
1741 static void dib9000_release(struct dvb_frontend *demod)
1742 {
1743 struct dib9000_state *st = demod->demodulator_priv;
1744 u8 index_frontend;
1745
1746 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
1747 dvb_frontend_detach(st->fe[index_frontend]);
1748
1749 DibFreeLock(&state->platform.risc.mbx_if_lock);
1750 DibFreeLock(&state->platform.risc.mbx_lock);
1751 DibFreeLock(&state->platform.risc.mem_lock);
1752 DibFreeLock(&state->platform.risc.mem_mbx_lock);
1753 dibx000_exit_i2c_master(&st->i2c_master);
1754
1755 i2c_del_adapter(&st->tuner_adap);
1756 i2c_del_adapter(&st->component_bus);
1757 kfree(st->fe[0]);
1758 kfree(st);
1759 }
1760
1761 static int dib9000_wakeup(struct dvb_frontend *fe)
1762 {
1763 return 0;
1764 }
1765
1766 static int dib9000_sleep(struct dvb_frontend *fe)
1767 {
1768 struct dib9000_state *state = fe->demodulator_priv;
1769 u8 index_frontend;
1770 int ret;
1771
1772 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1773 ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
1774 if (ret < 0)
1775 return ret;
1776 }
1777 return dib9000_mbx_send(state, OUT_MSG_FE_SLEEP, NULL, 0);
1778 }
1779
1780 static int dib9000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
1781 {
1782 tune->min_delay_ms = 1000;
1783 return 0;
1784 }
1785
1786 static int dib9000_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
1787 {
1788 struct dib9000_state *state = fe->demodulator_priv;
1789 u8 index_frontend, sub_index_frontend;
1790 fe_status_t stat;
1791 int ret;
1792
1793 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1794 state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
1795 if (stat & FE_HAS_SYNC) {
1796 dprintk("TPS lock on the slave%i", index_frontend);
1797
1798 /* synchronize the cache with the other frontends */
1799 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend], fep);
1800 for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL);
1801 sub_index_frontend++) {
1802 if (sub_index_frontend != index_frontend) {
1803 state->fe[sub_index_frontend]->dtv_property_cache.modulation =
1804 state->fe[index_frontend]->dtv_property_cache.modulation;
1805 state->fe[sub_index_frontend]->dtv_property_cache.inversion =
1806 state->fe[index_frontend]->dtv_property_cache.inversion;
1807 state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode =
1808 state->fe[index_frontend]->dtv_property_cache.transmission_mode;
1809 state->fe[sub_index_frontend]->dtv_property_cache.guard_interval =
1810 state->fe[index_frontend]->dtv_property_cache.guard_interval;
1811 state->fe[sub_index_frontend]->dtv_property_cache.hierarchy =
1812 state->fe[index_frontend]->dtv_property_cache.hierarchy;
1813 state->fe[sub_index_frontend]->dtv_property_cache.code_rate_HP =
1814 state->fe[index_frontend]->dtv_property_cache.code_rate_HP;
1815 state->fe[sub_index_frontend]->dtv_property_cache.code_rate_LP =
1816 state->fe[index_frontend]->dtv_property_cache.code_rate_LP;
1817 state->fe[sub_index_frontend]->dtv_property_cache.rolloff =
1818 state->fe[index_frontend]->dtv_property_cache.rolloff;
1819 }
1820 }
1821 return 0;
1822 }
1823 }
1824
1825 /* get the channel from master chip */
1826 ret = dib9000_fw_get_channel(fe, fep);
1827 if (ret != 0)
1828 return ret;
1829
1830 /* synchronize the cache with the other frontends */
1831 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1832 state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion;
1833 state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode;
1834 state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interval;
1835 state->fe[index_frontend]->dtv_property_cache.modulation = fe->dtv_property_cache.modulation;
1836 state->fe[index_frontend]->dtv_property_cache.hierarchy = fe->dtv_property_cache.hierarchy;
1837 state->fe[index_frontend]->dtv_property_cache.code_rate_HP = fe->dtv_property_cache.code_rate_HP;
1838 state->fe[index_frontend]->dtv_property_cache.code_rate_LP = fe->dtv_property_cache.code_rate_LP;
1839 state->fe[index_frontend]->dtv_property_cache.rolloff = fe->dtv_property_cache.rolloff;
1840 }
1841
1842 return 0;
1843 }
1844
1845 static int dib9000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
1846 {
1847 struct dib9000_state *state = fe->demodulator_priv;
1848 state->tune_state = tune_state;
1849 if (tune_state == CT_DEMOD_START)
1850 state->status = FE_STATUS_TUNE_PENDING;
1851
1852 return 0;
1853 }
1854
1855 static u32 dib9000_get_status(struct dvb_frontend *fe)
1856 {
1857 struct dib9000_state *state = fe->demodulator_priv;
1858 return state->status;
1859 }
1860
1861 static int dib9000_set_channel_status(struct dvb_frontend *fe, struct dvb_frontend_parametersContext *channel_status)
1862 {
1863 struct dib9000_state *state = fe->demodulator_priv;
1864
1865 memcpy(&state->channel_status, channel_status, sizeof(struct dvb_frontend_parametersContext));
1866 return 0;
1867 }
1868
1869 static int dib9000_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
1870 {
1871 struct dib9000_state *state = fe->demodulator_priv;
1872 int sleep_time, sleep_time_slave;
1873 u32 frontend_status;
1874 u8 nbr_pending, exit_condition, index_frontend, index_frontend_success;
1875 struct dvb_frontend_parametersContext channel_status;
1876
1877 /* check that the correct parameters are set */
1878 if (state->fe[0]->dtv_property_cache.frequency == 0) {
1879 dprintk("dib9000: must specify frequency ");
1880 return 0;
1881 }
1882
1883 if (state->fe[0]->dtv_property_cache.bandwidth_hz == 0) {
1884 dprintk("dib9000: must specify bandwidth ");
1885 return 0;
1886 }
1887 fe->dtv_property_cache.delivery_system = SYS_DVBT;
1888
1889 /* set the master status */
1890 if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ||
1891 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || fep->u.ofdm.constellation == QAM_AUTO || fep->u.ofdm.code_rate_HP == FEC_AUTO) {
1892 /* no channel specified, autosearch the channel */
1893 state->channel_status.status = CHANNEL_STATUS_PARAMETERS_UNKNOWN;
1894 } else
1895 state->channel_status.status = CHANNEL_STATUS_PARAMETERS_SET;
1896
1897 /* set mode and status for the different frontends */
1898 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1899 dib9000_fw_set_diversity_in(state->fe[index_frontend], 1);
1900
1901 /* synchronization of the cache */
1902 memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
1903
1904 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_DVBT;
1905 dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_HIGH_Z);
1906
1907 dib9000_set_channel_status(state->fe[index_frontend], &state->channel_status);
1908 dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
1909 }
1910
1911 /* actual tune */
1912 exit_condition = 0; /* 0: tune pending; 1: tune failed; 2:tune success */
1913 index_frontend_success = 0;
1914 do {
1915 sleep_time = dib9000_fw_tune(state->fe[0], NULL);
1916 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1917 sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend], NULL);
1918 if (sleep_time == FE_CALLBACK_TIME_NEVER)
1919 sleep_time = sleep_time_slave;
1920 else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time))
1921 sleep_time = sleep_time_slave;
1922 }
1923 if (sleep_time != FE_CALLBACK_TIME_NEVER)
1924 msleep(sleep_time / 10);
1925 else
1926 break;
1927
1928 nbr_pending = 0;
1929 exit_condition = 0;
1930 index_frontend_success = 0;
1931 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1932 frontend_status = -dib9000_get_status(state->fe[index_frontend]);
1933 if (frontend_status > -FE_STATUS_TUNE_PENDING) {
1934 exit_condition = 2; /* tune success */
1935 index_frontend_success = index_frontend;
1936 break;
1937 }
1938 if (frontend_status == -FE_STATUS_TUNE_PENDING)
1939 nbr_pending++; /* some frontends are still tuning */
1940 }
1941 if ((exit_condition != 2) && (nbr_pending == 0))
1942 exit_condition = 1; /* if all tune are done and no success, exit: tune failed */
1943
1944 } while (exit_condition == 0);
1945
1946 /* check the tune result */
1947 if (exit_condition == 1) { /* tune failed */
1948 dprintk("tune failed");
1949 return 0;
1950 }
1951
1952 dprintk("tune success on frontend%i", index_frontend_success);
1953
1954 /* synchronize all the channel cache */
1955 dib9000_get_frontend(state->fe[0], fep);
1956
1957 /* retune the other frontends with the found channel */
1958 channel_status.status = CHANNEL_STATUS_PARAMETERS_SET;
1959 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1960 /* only retune the frontends which was not tuned success */
1961 if (index_frontend != index_frontend_success) {
1962 dib9000_set_channel_status(state->fe[index_frontend], &channel_status);
1963 dib9000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
1964 }
1965 }
1966 do {
1967 sleep_time = FE_CALLBACK_TIME_NEVER;
1968 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1969 if (index_frontend != index_frontend_success) {
1970 sleep_time_slave = dib9000_fw_tune(state->fe[index_frontend], NULL);
1971 if (sleep_time == FE_CALLBACK_TIME_NEVER)
1972 sleep_time = sleep_time_slave;
1973 else if ((sleep_time_slave != FE_CALLBACK_TIME_NEVER) && (sleep_time_slave > sleep_time))
1974 sleep_time = sleep_time_slave;
1975 }
1976 }
1977 if (sleep_time != FE_CALLBACK_TIME_NEVER)
1978 msleep(sleep_time / 10);
1979 else
1980 break;
1981
1982 nbr_pending = 0;
1983 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
1984 if (index_frontend != index_frontend_success) {
1985 frontend_status = -dib9000_get_status(state->fe[index_frontend]);
1986 if ((index_frontend != index_frontend_success) && (frontend_status == -FE_STATUS_TUNE_PENDING))
1987 nbr_pending++; /* some frontends are still tuning */
1988 }
1989 }
1990 } while (nbr_pending != 0);
1991
1992 /* set the output mode */
1993 dib9000_fw_set_output_mode(state->fe[0], state->chip.d9.cfg.output_mode);
1994 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
1995 dib9000_fw_set_output_mode(state->fe[index_frontend], OUTMODE_DIVERSITY);
1996
1997 /* turn off the diversity for the last frontend */
1998 dib9000_fw_set_diversity_in(state->fe[index_frontend - 1], 0);
1999
2000 return 0;
2001 }
2002
2003 static u16 dib9000_read_lock(struct dvb_frontend *fe)
2004 {
2005 struct dib9000_state *state = fe->demodulator_priv;
2006
2007 return dib9000_read_word(state, 535);
2008 }
2009
2010 static int dib9000_read_status(struct dvb_frontend *fe, fe_status_t * stat)
2011 {
2012 struct dib9000_state *state = fe->demodulator_priv;
2013 u8 index_frontend;
2014 u16 lock = 0, lock_slave = 0;
2015
2016 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2017 lock_slave |= dib9000_read_lock(state->fe[index_frontend]);
2018
2019 lock = dib9000_read_word(state, 535);
2020
2021 *stat = 0;
2022
2023 if ((lock & 0x8000) || (lock_slave & 0x8000))
2024 *stat |= FE_HAS_SIGNAL;
2025 if ((lock & 0x3000) || (lock_slave & 0x3000))
2026 *stat |= FE_HAS_CARRIER;
2027 if ((lock & 0x0100) || (lock_slave & 0x0100))
2028 *stat |= FE_HAS_VITERBI;
2029 if (((lock & 0x0038) == 0x38) || ((lock_slave & 0x0038) == 0x38))
2030 *stat |= FE_HAS_SYNC;
2031 if ((lock & 0x0008) || (lock_slave & 0x0008))
2032 *stat |= FE_HAS_LOCK;
2033
2034 return 0;
2035 }
2036
2037 static int dib9000_read_ber(struct dvb_frontend *fe, u32 * ber)
2038 {
2039 struct dib9000_state *state = fe->demodulator_priv;
2040 u16 c[16];
2041
2042 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
2043 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
2044 return -EIO;
2045 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
2046 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
2047
2048 *ber = c[10] << 16 | c[11];
2049 return 0;
2050 }
2051
2052 static int dib9000_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2053 {
2054 struct dib9000_state *state = fe->demodulator_priv;
2055 u8 index_frontend;
2056 u16 c[16];
2057 u16 val;
2058
2059 *strength = 0;
2060 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
2061 state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
2062 if (val > 65535 - *strength)
2063 *strength = 65535;
2064 else
2065 *strength += val;
2066 }
2067
2068 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
2069 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
2070 return -EIO;
2071 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
2072 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
2073
2074 val = 65535 - c[4];
2075 if (val > 65535 - *strength)
2076 *strength = 65535;
2077 else
2078 *strength += val;
2079 return 0;
2080 }
2081
2082 static u32 dib9000_get_snr(struct dvb_frontend *fe)
2083 {
2084 struct dib9000_state *state = fe->demodulator_priv;
2085 u16 c[16];
2086 u32 n, s, exp;
2087 u16 val;
2088
2089 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
2090 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
2091 return -EIO;
2092 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
2093 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
2094
2095 val = c[7];
2096 n = (val >> 4) & 0xff;
2097 exp = ((val & 0xf) << 2);
2098 val = c[8];
2099 exp += ((val >> 14) & 0x3);
2100 if ((exp & 0x20) != 0)
2101 exp -= 0x40;
2102 n <<= exp + 16;
2103
2104 s = (val >> 6) & 0xFF;
2105 exp = (val & 0x3F);
2106 if ((exp & 0x20) != 0)
2107 exp -= 0x40;
2108 s <<= exp + 16;
2109
2110 if (n > 0) {
2111 u32 t = (s / n) << 16;
2112 return t + ((s << 16) - n * t) / n;
2113 }
2114 return 0xffffffff;
2115 }
2116
2117 static int dib9000_read_snr(struct dvb_frontend *fe, u16 * snr)
2118 {
2119 struct dib9000_state *state = fe->demodulator_priv;
2120 u8 index_frontend;
2121 u32 snr_master;
2122
2123 snr_master = dib9000_get_snr(fe);
2124 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
2125 snr_master += dib9000_get_snr(state->fe[index_frontend]);
2126
2127 if ((snr_master >> 16) != 0) {
2128 snr_master = 10 * intlog10(snr_master >> 16);
2129 *snr = snr_master / ((1 << 24) / 10);
2130 } else
2131 *snr = 0;
2132
2133 return 0;
2134 }
2135
2136 static int dib9000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
2137 {
2138 struct dib9000_state *state = fe->demodulator_priv;
2139 u16 c[16];
2140
2141 DibAcquireLock(&state->platform.risc.mem_mbx_lock);
2142 if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
2143 return -EIO;
2144 dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
2145 DibReleaseLock(&state->platform.risc.mem_mbx_lock);
2146
2147 *unc = c[12];
2148 return 0;
2149 }
2150
2151 int dib9000_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, u8 first_addr)
2152 {
2153 int k = 0;
2154 u8 new_addr = 0;
2155 struct i2c_device client = {.i2c_adap = i2c };
2156
2157 client.i2c_addr = default_addr + 16;
2158 dib9000_i2c_write16(&client, 1796, 0x0);
2159
2160 for (k = no_of_demods - 1; k >= 0; k--) {
2161 /* designated i2c address */
2162 new_addr = first_addr + (k << 1);
2163 client.i2c_addr = default_addr;
2164
2165 dib9000_i2c_write16(&client, 1817, 3);
2166 dib9000_i2c_write16(&client, 1796, 0);
2167 dib9000_i2c_write16(&client, 1227, 1);
2168 dib9000_i2c_write16(&client, 1227, 0);
2169
2170 client.i2c_addr = new_addr;
2171 dib9000_i2c_write16(&client, 1817, 3);
2172 dib9000_i2c_write16(&client, 1796, 0);
2173 dib9000_i2c_write16(&client, 1227, 1);
2174 dib9000_i2c_write16(&client, 1227, 0);
2175
2176 if (dib9000_identify(&client) == 0) {
2177 client.i2c_addr = default_addr;
2178 if (dib9000_identify(&client) == 0) {
2179 dprintk("DiB9000 #%d: not identified", k);
2180 return -EIO;
2181 }
2182 }
2183
2184 dib9000_i2c_write16(&client, 1795, (1 << 10) | (4 << 6));
2185 dib9000_i2c_write16(&client, 1794, (new_addr << 2) | 2);
2186
2187 dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
2188 }
2189
2190 for (k = 0; k < no_of_demods; k++) {
2191 new_addr = first_addr | (k << 1);
2192 client.i2c_addr = new_addr;
2193
2194 dib9000_i2c_write16(&client, 1794, (new_addr << 2));
2195 dib9000_i2c_write16(&client, 1795, 0);
2196 }
2197
2198 return 0;
2199 }
2200 EXPORT_SYMBOL(dib9000_i2c_enumeration);
2201
2202 int dib9000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
2203 {
2204 struct dib9000_state *state = fe->demodulator_priv;
2205 u8 index_frontend = 1;
2206
2207 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
2208 index_frontend++;
2209 if (index_frontend < MAX_NUMBER_OF_FRONTENDS) {
2210 dprintk("set slave fe %p to index %i", fe_slave, index_frontend);
2211 state->fe[index_frontend] = fe_slave;
2212 return 0;
2213 }
2214
2215 dprintk("too many slave frontend");
2216 return -ENOMEM;
2217 }
2218 EXPORT_SYMBOL(dib9000_set_slave_frontend);
2219
2220 int dib9000_remove_slave_frontend(struct dvb_frontend *fe)
2221 {
2222 struct dib9000_state *state = fe->demodulator_priv;
2223 u8 index_frontend = 1;
2224
2225 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
2226 index_frontend++;
2227 if (index_frontend != 1) {
2228 dprintk("remove slave fe %p (index %i)", state->fe[index_frontend - 1], index_frontend - 1);
2229 state->fe[index_frontend] = NULL;
2230 return 0;
2231 }
2232
2233 dprintk("no frontend to be removed");
2234 return -ENODEV;
2235 }
2236 EXPORT_SYMBOL(dib9000_remove_slave_frontend);
2237
2238 struct dvb_frontend *dib9000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
2239 {
2240 struct dib9000_state *state = fe->demodulator_priv;
2241
2242 if (slave_index >= MAX_NUMBER_OF_FRONTENDS)
2243 return NULL;
2244 return state->fe[slave_index];
2245 }
2246 EXPORT_SYMBOL(dib9000_get_slave_frontend);
2247
2248 static struct dvb_frontend_ops dib9000_ops;
2249 struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, const struct dib9000_config *cfg)
2250 {
2251 struct dvb_frontend *fe;
2252 struct dib9000_state *st;
2253 st = kzalloc(sizeof(struct dib9000_state), GFP_KERNEL);
2254 if (st == NULL)
2255 return NULL;
2256 fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL);
2257 if (fe == NULL)
2258 return NULL;
2259
2260 memcpy(&st->chip.d9.cfg, cfg, sizeof(struct dib9000_config));
2261 st->i2c.i2c_adap = i2c_adap;
2262 st->i2c.i2c_addr = i2c_addr;
2263
2264 st->gpio_dir = DIB9000_GPIO_DEFAULT_DIRECTIONS;
2265 st->gpio_val = DIB9000_GPIO_DEFAULT_VALUES;
2266 st->gpio_pwm_pos = DIB9000_GPIO_DEFAULT_PWM_POS;
2267
2268 DibInitLock(&st->platform.risc.mbx_if_lock);
2269 DibInitLock(&st->platform.risc.mbx_lock);
2270 DibInitLock(&st->platform.risc.mem_lock);
2271 DibInitLock(&st->platform.risc.mem_mbx_lock);
2272
2273 st->fe[0] = fe;
2274 fe->demodulator_priv = st;
2275 memcpy(&st->fe[0]->ops, &dib9000_ops, sizeof(struct dvb_frontend_ops));
2276
2277 /* Ensure the output mode remains at the previous default if it's
2278 * not specifically set by the caller.
2279 */
2280 if ((st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
2281 st->chip.d9.cfg.output_mode = OUTMODE_MPEG2_FIFO;
2282
2283 if (dib9000_identify(&st->i2c) == 0)
2284 goto error;
2285
2286 dibx000_init_i2c_master(&st->i2c_master, DIB7000MC, st->i2c.i2c_adap, st->i2c.i2c_addr);
2287
2288 st->tuner_adap.dev.parent = i2c_adap->dev.parent;
2289 strncpy(st->tuner_adap.name, "DIB9000_FW TUNER ACCESS", sizeof(st->tuner_adap.name));
2290 st->tuner_adap.algo = &dib9000_tuner_algo;
2291 st->tuner_adap.algo_data = NULL;
2292 i2c_set_adapdata(&st->tuner_adap, st);
2293 if (i2c_add_adapter(&st->tuner_adap) < 0)
2294 goto error;
2295
2296 st->component_bus.dev.parent = i2c_adap->dev.parent;
2297 strncpy(st->component_bus.name, "DIB9000_FW COMPONENT BUS ACCESS", sizeof(st->component_bus.name));
2298 st->component_bus.algo = &dib9000_component_bus_algo;
2299 st->component_bus.algo_data = NULL;
2300 st->component_bus_speed = 340;
2301 i2c_set_adapdata(&st->component_bus, st);
2302 if (i2c_add_adapter(&st->component_bus) < 0)
2303 goto component_bus_add_error;
2304
2305 dib9000_fw_reset(fe);
2306
2307 return fe;
2308
2309 component_bus_add_error:
2310 i2c_del_adapter(&st->tuner_adap);
2311 error:
2312 kfree(st);
2313 return NULL;
2314 }
2315 EXPORT_SYMBOL(dib9000_attach);
2316
2317 static struct dvb_frontend_ops dib9000_ops = {
2318 .info = {
2319 .name = "DiBcom 9000",
2320 .type = FE_OFDM,
2321 .frequency_min = 44250000,
2322 .frequency_max = 867250000,
2323 .frequency_stepsize = 62500,
2324 .caps = FE_CAN_INVERSION_AUTO |
2325 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2326 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2327 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
2328 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
2329 },
2330
2331 .release = dib9000_release,
2332
2333 .init = dib9000_wakeup,
2334 .sleep = dib9000_sleep,
2335
2336 .set_frontend = dib9000_set_frontend,
2337 .get_tune_settings = dib9000_fe_get_tune_settings,
2338 .get_frontend = dib9000_get_frontend,
2339
2340 .read_status = dib9000_read_status,
2341 .read_ber = dib9000_read_ber,
2342 .read_signal_strength = dib9000_read_signal_strength,
2343 .read_snr = dib9000_read_snr,
2344 .read_ucblocks = dib9000_read_unc_blocks,
2345 };
2346
2347 MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
2348 MODULE_AUTHOR("Olivier Grenie <ogrenie@dibcom.fr>");
2349 MODULE_DESCRIPTION("Driver for the DiBcom 9000 COFDM demodulator");
2350 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree