4 * Copyright (C) 2009 Renesas Solutions Corp.
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * Based on SH7723 Setup
9 * Copyright (C) 2008 Paul Mundt
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
15 #include <linux/platform_device.h>
16 #include <linux/init.h>
17 #include <linux/serial.h>
19 #include <linux/serial_sci.h>
20 #include <linux/uio_driver.h>
21 #include <linux/sh_timer.h>
23 #include <asm/clock.h>
24 #include <asm/mmzone.h>
27 static struct plat_sci_port sci_platform_data
[] = {
29 .mapbase
= 0xffe00000,
30 .flags
= UPF_BOOT_AUTOCONF
,
32 .irqs
= { 80, 80, 80, 80 },
35 .mapbase
= 0xffe10000,
36 .flags
= UPF_BOOT_AUTOCONF
,
38 .irqs
= { 81, 81, 81, 81 },
41 .mapbase
= 0xffe20000,
42 .flags
= UPF_BOOT_AUTOCONF
,
44 .irqs
= { 82, 82, 82, 82 },
47 .mapbase
= 0xa4e30000,
48 .flags
= UPF_BOOT_AUTOCONF
,
50 .irqs
= { 56, 56, 56, 56 },
53 .mapbase
= 0xa4e40000,
54 .flags
= UPF_BOOT_AUTOCONF
,
56 .irqs
= { 88, 88, 88, 88 },
59 .mapbase
= 0xa4e50000,
60 .flags
= UPF_BOOT_AUTOCONF
,
62 .irqs
= { 109, 109, 109, 109 },
69 static struct platform_device sci_device
= {
73 .platform_data
= sci_platform_data
,
78 static struct resource rtc_resources
[] = {
81 .end
= 0xa465fec0 + 0x58 - 1,
82 .flags
= IORESOURCE_IO
,
87 .flags
= IORESOURCE_IRQ
,
92 .flags
= IORESOURCE_IRQ
,
97 .flags
= IORESOURCE_IRQ
,
101 static struct platform_device rtc_device
= {
104 .num_resources
= ARRAY_SIZE(rtc_resources
),
105 .resource
= rtc_resources
,
109 static struct resource iic0_resources
[] = {
113 .end
= 0x04470018 - 1,
114 .flags
= IORESOURCE_MEM
,
119 .flags
= IORESOURCE_IRQ
,
123 static struct platform_device iic0_device
= {
124 .name
= "i2c-sh_mobile",
125 .id
= 0, /* "i2c0" clock */
126 .num_resources
= ARRAY_SIZE(iic0_resources
),
127 .resource
= iic0_resources
,
131 static struct resource iic1_resources
[] = {
135 .end
= 0x04750018 - 1,
136 .flags
= IORESOURCE_MEM
,
141 .flags
= IORESOURCE_IRQ
,
145 static struct platform_device iic1_device
= {
146 .name
= "i2c-sh_mobile",
147 .id
= 1, /* "i2c1" clock */
148 .num_resources
= ARRAY_SIZE(iic1_resources
),
149 .resource
= iic1_resources
,
153 static struct uio_info vpu_platform_data
= {
159 static struct resource vpu_resources
[] = {
164 .flags
= IORESOURCE_MEM
,
167 /* place holder for contiguous memory */
171 static struct platform_device vpu_device
= {
172 .name
= "uio_pdrv_genirq",
175 .platform_data
= &vpu_platform_data
,
177 .resource
= vpu_resources
,
178 .num_resources
= ARRAY_SIZE(vpu_resources
),
182 static struct uio_info veu0_platform_data
= {
188 static struct resource veu0_resources
[] = {
192 .end
= 0xfe9200cb - 1,
193 .flags
= IORESOURCE_MEM
,
196 /* place holder for contiguous memory */
200 static struct platform_device veu0_device
= {
201 .name
= "uio_pdrv_genirq",
204 .platform_data
= &veu0_platform_data
,
206 .resource
= veu0_resources
,
207 .num_resources
= ARRAY_SIZE(veu0_resources
),
211 static struct uio_info veu1_platform_data
= {
217 static struct resource veu1_resources
[] = {
221 .end
= 0xfe9240cb - 1,
222 .flags
= IORESOURCE_MEM
,
225 /* place holder for contiguous memory */
229 static struct platform_device veu1_device
= {
230 .name
= "uio_pdrv_genirq",
233 .platform_data
= &veu1_platform_data
,
235 .resource
= veu1_resources
,
236 .num_resources
= ARRAY_SIZE(veu1_resources
),
239 static struct sh_timer_config cmt_platform_data
= {
241 .channel_offset
= 0x60,
244 .clockevent_rating
= 125,
245 .clocksource_rating
= 200,
248 static struct resource cmt_resources
[] = {
253 .flags
= IORESOURCE_MEM
,
257 .flags
= IORESOURCE_IRQ
,
261 static struct platform_device cmt_device
= {
265 .platform_data
= &cmt_platform_data
,
267 .resource
= cmt_resources
,
268 .num_resources
= ARRAY_SIZE(cmt_resources
),
271 static struct sh_timer_config tmu0_platform_data
= {
273 .channel_offset
= 0x04,
276 .clockevent_rating
= 200,
279 static struct resource tmu0_resources
[] = {
284 .flags
= IORESOURCE_MEM
,
288 .flags
= IORESOURCE_IRQ
,
292 static struct platform_device tmu0_device
= {
296 .platform_data
= &tmu0_platform_data
,
298 .resource
= tmu0_resources
,
299 .num_resources
= ARRAY_SIZE(tmu0_resources
),
302 static struct sh_timer_config tmu1_platform_data
= {
304 .channel_offset
= 0x10,
307 .clocksource_rating
= 200,
310 static struct resource tmu1_resources
[] = {
315 .flags
= IORESOURCE_MEM
,
319 .flags
= IORESOURCE_IRQ
,
323 static struct platform_device tmu1_device
= {
327 .platform_data
= &tmu1_platform_data
,
329 .resource
= tmu1_resources
,
330 .num_resources
= ARRAY_SIZE(tmu1_resources
),
333 static struct sh_timer_config tmu2_platform_data
= {
335 .channel_offset
= 0x1c,
340 static struct resource tmu2_resources
[] = {
345 .flags
= IORESOURCE_MEM
,
349 .flags
= IORESOURCE_IRQ
,
353 static struct platform_device tmu2_device
= {
357 .platform_data
= &tmu2_platform_data
,
359 .resource
= tmu2_resources
,
360 .num_resources
= ARRAY_SIZE(tmu2_resources
),
364 static struct sh_timer_config tmu3_platform_data
= {
366 .channel_offset
= 0x04,
371 static struct resource tmu3_resources
[] = {
376 .flags
= IORESOURCE_MEM
,
380 .flags
= IORESOURCE_IRQ
,
384 static struct platform_device tmu3_device
= {
388 .platform_data
= &tmu3_platform_data
,
390 .resource
= tmu3_resources
,
391 .num_resources
= ARRAY_SIZE(tmu3_resources
),
394 static struct sh_timer_config tmu4_platform_data
= {
396 .channel_offset
= 0x10,
401 static struct resource tmu4_resources
[] = {
406 .flags
= IORESOURCE_MEM
,
410 .flags
= IORESOURCE_IRQ
,
414 static struct platform_device tmu4_device
= {
418 .platform_data
= &tmu4_platform_data
,
420 .resource
= tmu4_resources
,
421 .num_resources
= ARRAY_SIZE(tmu4_resources
),
424 static struct sh_timer_config tmu5_platform_data
= {
426 .channel_offset
= 0x1c,
431 static struct resource tmu5_resources
[] = {
436 .flags
= IORESOURCE_MEM
,
440 .flags
= IORESOURCE_IRQ
,
444 static struct platform_device tmu5_device
= {
448 .platform_data
= &tmu5_platform_data
,
450 .resource
= tmu5_resources
,
451 .num_resources
= ARRAY_SIZE(tmu5_resources
),
454 static struct platform_device
*sh7724_devices
[] __initdata
= {
471 static int __init
sh7724_devices_setup(void)
473 platform_resource_setup_memory(&vpu_device
, "vpu", 2 << 20);
474 platform_resource_setup_memory(&veu0_device
, "veu0", 2 << 20);
475 platform_resource_setup_memory(&veu1_device
, "veu1", 2 << 20);
477 return platform_add_devices(sh7724_devices
,
478 ARRAY_SIZE(sh7724_devices
));
480 device_initcall(sh7724_devices_setup
);
482 static struct platform_device
*sh7724_early_devices
[] __initdata
= {
492 void __init
plat_early_device_setup(void)
494 early_platform_add_devices(sh7724_early_devices
,
495 ARRAY_SIZE(sh7724_early_devices
));
498 #define RAMCR_CACHE_L2FC 0x0002
499 #define RAMCR_CACHE_L2E 0x0001
500 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
501 void __uses_jump_to_uncached
l2_cache_init(void)
503 /* Enable L2 cache */
504 ctrl_outl(L2_CACHE_ENABLE
, RAMCR
);
510 /* interrupt sources */
511 IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
,
513 DMAC1A_DEI0
, DMAC1A_DEI1
, DMAC1A_DEI2
, DMAC1A_DEI3
,
514 _2DG_TRI
, _2DG_INI
, _2DG_CEI
, _2DG_BRK
,
515 DMAC0A_DEI0
, DMAC0A_DEI1
, DMAC0A_DEI2
, DMAC0A_DEI3
,
516 VIO_CEU20I
, VIO_BEU20I
, VIO_VEU3F1
, VIO_VOUI
,
524 RTC_ATI
, RTC_PRI
, RTC_CUI
,
525 DMAC1B_DEI4
, DMAC1B_DEI5
, DMAC1B_DADERR
,
526 DMAC0B_DEI4
, DMAC0B_DEI5
, DMAC0B_DADERR
,
528 SCIF_SCIF0
, SCIF_SCIF1
, SCIF_SCIF2
,
530 MSIOF_MSIOFI0
, MSIOF_MSIOFI1
,
531 SPU_SPUI0
, SPU_SPUI1
,
535 I2C1_ALI
, I2C1_TACKI
, I2C1_WAITI
, I2C1_DTEI
,
536 I2C0_ALI
, I2C0_TACKI
, I2C0_WAITI
, I2C0_DTEI
,
537 SDHI0_SDHII0
, SDHI0_SDHII1
, SDHI0_SDHII2
,
543 TMU0_TUNI0
, TMU0_TUNI1
, TMU0_TUNI2
,
545 SDHI1_SDHII0
, SDHI1_SDHII1
, SDHI1_SDHII2
,
547 MMC_MMCI0
, MMC_MMCI1
, MMC_MMCI2
,
549 TMU1_TUNI0
, TMU1_TUNI1
, TMU1_TUNI2
,
551 /* interrupt groups */
552 DMAC1A
, _2DG
, DMAC0A
, VIO
, RTC
,
553 DMAC1B
, DMAC0B
, I2C0
, I2C1
, SDHI0
, SDHI1
, SPU
, MMC
,
556 static struct intc_vect vectors
[] __initdata
= {
557 INTC_VECT(IRQ0
, 0x600), INTC_VECT(IRQ1
, 0x620),
558 INTC_VECT(IRQ2
, 0x640), INTC_VECT(IRQ3
, 0x660),
559 INTC_VECT(IRQ4
, 0x680), INTC_VECT(IRQ5
, 0x6a0),
560 INTC_VECT(IRQ6
, 0x6c0), INTC_VECT(IRQ7
, 0x6e0),
562 INTC_VECT(DMAC1A_DEI0
, 0x700),
563 INTC_VECT(DMAC1A_DEI1
, 0x720),
564 INTC_VECT(DMAC1A_DEI2
, 0x740),
565 INTC_VECT(DMAC1A_DEI3
, 0x760),
567 INTC_VECT(_2DG_TRI
, 0x780),
568 INTC_VECT(_2DG_INI
, 0x7A0),
569 INTC_VECT(_2DG_CEI
, 0x7C0),
570 INTC_VECT(_2DG_BRK
, 0x7E0),
572 INTC_VECT(DMAC0A_DEI0
, 0x800),
573 INTC_VECT(DMAC0A_DEI1
, 0x820),
574 INTC_VECT(DMAC0A_DEI2
, 0x840),
575 INTC_VECT(DMAC0A_DEI3
, 0x860),
577 INTC_VECT(VIO_CEU20I
, 0x880),
578 INTC_VECT(VIO_BEU20I
, 0x8A0),
579 INTC_VECT(VIO_VEU3F1
, 0x8C0),
580 INTC_VECT(VIO_VOUI
, 0x8E0),
582 INTC_VECT(SCIFA_SCIFA0
, 0x900),
583 INTC_VECT(VPU_VPUI
, 0x980),
584 INTC_VECT(TPU_TPUI
, 0x9A0),
585 INTC_VECT(CEU21I
, 0x9E0),
586 INTC_VECT(BEU21I
, 0xA00),
587 INTC_VECT(USB_USI0
, 0xA20),
588 INTC_VECT(ATAPI
, 0xA60),
590 INTC_VECT(RTC_ATI
, 0xA80),
591 INTC_VECT(RTC_PRI
, 0xAA0),
592 INTC_VECT(RTC_CUI
, 0xAC0),
594 INTC_VECT(DMAC1B_DEI4
, 0xB00),
595 INTC_VECT(DMAC1B_DEI5
, 0xB20),
596 INTC_VECT(DMAC1B_DADERR
, 0xB40),
598 INTC_VECT(DMAC0B_DEI4
, 0xB80),
599 INTC_VECT(DMAC0B_DEI5
, 0xBA0),
600 INTC_VECT(DMAC0B_DADERR
, 0xBC0),
602 INTC_VECT(KEYSC_KEYI
, 0xBE0),
603 INTC_VECT(SCIF_SCIF0
, 0xC00),
604 INTC_VECT(SCIF_SCIF1
, 0xC20),
605 INTC_VECT(SCIF_SCIF2
, 0xC40),
606 INTC_VECT(VEU3F0I
, 0xC60),
607 INTC_VECT(MSIOF_MSIOFI0
, 0xC80),
608 INTC_VECT(MSIOF_MSIOFI1
, 0xCA0),
609 INTC_VECT(SPU_SPUI0
, 0xCC0),
610 INTC_VECT(SPU_SPUI1
, 0xCE0),
611 INTC_VECT(SCIFA_SCIFA1
, 0xD00),
613 /* INTC_VECT(ICB_ICBI, 0xD20), */
614 INTC_VECT(ETHI
, 0xD60),
616 INTC_VECT(I2C1_ALI
, 0xD80),
617 INTC_VECT(I2C1_TACKI
, 0xDA0),
618 INTC_VECT(I2C1_WAITI
, 0xDC0),
619 INTC_VECT(I2C1_DTEI
, 0xDE0),
621 INTC_VECT(I2C0_ALI
, 0xE00),
622 INTC_VECT(I2C0_TACKI
, 0xE20),
623 INTC_VECT(I2C0_WAITI
, 0xE40),
624 INTC_VECT(I2C0_DTEI
, 0xE60),
626 INTC_VECT(SDHI0_SDHII0
, 0xE80),
627 INTC_VECT(SDHI0_SDHII1
, 0xEA0),
628 INTC_VECT(SDHI0_SDHII2
, 0xEC0),
630 INTC_VECT(CMT_CMTI
, 0xF00),
631 INTC_VECT(TSIF_TSIFI
, 0xF20),
632 /* INTC_VECT(ICB_LMBI, 0xF60), */
633 INTC_VECT(FSI_FSI
, 0xF80),
634 INTC_VECT(SCIFA_SCIFA2
, 0xFA0),
636 INTC_VECT(TMU0_TUNI0
, 0x400),
637 INTC_VECT(TMU0_TUNI1
, 0x420),
638 INTC_VECT(TMU0_TUNI2
, 0x440),
640 INTC_VECT(IRDA_IRDAI
, 0x480),
642 INTC_VECT(SDHI1_SDHII0
, 0x4E0),
643 INTC_VECT(SDHI1_SDHII1
, 0x500),
644 INTC_VECT(SDHI1_SDHII2
, 0x520),
646 INTC_VECT(JPU_JPUI
, 0x560),
648 INTC_VECT(MMC_MMCI0
, 0x580),
649 INTC_VECT(MMC_MMCI1
, 0x5A0),
650 INTC_VECT(MMC_MMCI2
, 0x5C0),
652 INTC_VECT(LCDC_LCDCI
, 0xF40),
654 INTC_VECT(TMU1_TUNI0
, 0x920),
655 INTC_VECT(TMU1_TUNI1
, 0x940),
656 INTC_VECT(TMU1_TUNI2
, 0x960),
659 static struct intc_group groups
[] __initdata
= {
660 INTC_GROUP(DMAC1A
, DMAC1A_DEI0
, DMAC1A_DEI1
, DMAC1A_DEI2
, DMAC1A_DEI3
),
661 INTC_GROUP(_2DG
, _2DG_TRI
, _2DG_INI
, _2DG_CEI
, _2DG_BRK
),
662 INTC_GROUP(DMAC0A
, DMAC0A_DEI0
, DMAC0A_DEI1
, DMAC0A_DEI2
, DMAC0A_DEI3
),
663 INTC_GROUP(VIO
, VIO_CEU20I
, VIO_BEU20I
, VIO_VEU3F1
, VIO_VOUI
),
664 INTC_GROUP(RTC
, RTC_ATI
, RTC_PRI
, RTC_CUI
),
665 INTC_GROUP(DMAC1B
, DMAC1B_DEI4
, DMAC1B_DEI5
, DMAC1B_DADERR
),
666 INTC_GROUP(DMAC0B
, DMAC0B_DEI4
, DMAC0B_DEI5
, DMAC0B_DADERR
),
667 INTC_GROUP(I2C0
, I2C0_ALI
, I2C0_TACKI
, I2C0_WAITI
, I2C0_DTEI
),
668 INTC_GROUP(I2C1
, I2C1_ALI
, I2C1_TACKI
, I2C1_WAITI
, I2C1_DTEI
),
669 INTC_GROUP(SDHI0
, SDHI0_SDHII0
, SDHI0_SDHII1
, SDHI0_SDHII2
),
670 INTC_GROUP(SDHI1
, SDHI1_SDHII0
, SDHI1_SDHII1
, SDHI1_SDHII2
),
671 INTC_GROUP(SPU
, SPU_SPUI0
, SPU_SPUI1
),
672 INTC_GROUP(MMC
, MMC_MMCI0
, MMC_MMCI1
, MMC_MMCI2
),
675 /* FIXMEEEEEEEEEEEEEEEEEEE !!!!! */
676 /* very bad manual !! */
677 static struct intc_mask_reg mask_registers
[] __initdata
= {
678 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
679 { 0, TMU1_TUNI2
, TMU1_TUNI1
, TMU1_TUNI0
,
680 /*SDHII3?*/0, SDHI1_SDHII2
, SDHI1_SDHII1
, SDHI1_SDHII0
} },
681 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
682 { VIO_VOUI
, VIO_VEU3F1
, VIO_BEU20I
, VIO_CEU20I
,
683 DMAC0A_DEI3
, DMAC0A_DEI2
, DMAC0A_DEI1
, DMAC0A_DEI0
} },
684 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
685 { 0, 0, 0, VPU_VPUI
, ATAPI
, ETHI
, 0, /*SCIFA3*/SCIFA_SCIFA0
} },
686 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
687 { DMAC1A_DEI3
, DMAC1A_DEI2
, DMAC1A_DEI1
, DMAC1A_DEI0
,
688 SPU_SPUI1
, SPU_SPUI0
, BEU21I
, IRDA_IRDAI
} },
689 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
690 { 0, TMU0_TUNI2
, TMU0_TUNI1
, TMU0_TUNI0
,
691 JPU_JPUI
, 0, 0, LCDC_LCDCI
} },
692 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
693 { KEYSC_KEYI
, DMAC0B_DADERR
, DMAC0B_DEI5
, DMAC0B_DEI4
,
694 VEU3F0I
, SCIF_SCIF2
, SCIF_SCIF1
, SCIF_SCIF0
} },
695 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
696 { 0, 0, /*ICB_ICBI*/0, /*SCIFA4*/SCIFA_SCIFA1
,
697 CEU21I
, 0, MSIOF_MSIOFI1
, MSIOF_MSIOFI0
} },
698 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
699 { I2C0_DTEI
, I2C0_WAITI
, I2C0_TACKI
, I2C0_ALI
,
700 I2C1_DTEI
, I2C1_WAITI
, I2C1_TACKI
, I2C1_ALI
} },
701 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
702 { /*SDHII3*/0, SDHI0_SDHII2
, SDHI0_SDHII1
, SDHI0_SDHII0
,
703 0, 0, /*SCIFA5*/SCIFA_SCIFA2
, FSI_FSI
} },
704 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
705 { 0, 0, 0, CMT_CMTI
, 0, /*USB1*/0, USB_USI0
, 0 } },
706 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
707 { 0, DMAC1B_DADERR
, DMAC1B_DEI5
, DMAC1B_DEI4
,
708 0, RTC_ATI
, RTC_PRI
, RTC_CUI
} },
709 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
710 { _2DG_BRK
, _2DG_CEI
, _2DG_INI
, _2DG_TRI
,
711 0, TPU_TPUI
, /*ICB_LMBI*/0, TSIF_TSIFI
} },
712 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
713 { 0, 0, 0, 0, 0, 0, 0, 0/*2DDMAC*/ } },
714 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
715 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
718 static struct intc_prio_reg prio_registers
[] __initdata
= {
719 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0
, TMU0_TUNI1
,
720 TMU0_TUNI2
, IRDA_IRDAI
} },
721 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU_JPUI
, LCDC_LCDCI
,
723 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0
, TMU1_TUNI1
,
725 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMC
, 0, ATAPI
} },
726 { 0xa4080010, 0, 16, 4, /* IPRE */
727 { DMAC0A
, /*BEU?VEU?*/VIO
, /*SCIFA3*/SCIFA_SCIFA0
, /*VPU5F*/
729 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI
, DMAC0B
,
730 USB_USI0
, CMT_CMTI
} },
731 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0
, SCIF_SCIF1
,
732 SCIF_SCIF2
, VEU3F0I
} },
733 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0
, MSIOF_MSIOFI1
,
735 { 0xa4080020, 0, 16, 4, /* IPRI */ { /*SCIFA4*/SCIFA_SCIFA1
, /*ICB*/0,
736 TSIF_TSIFI
, _2DG
/*ICB?*/ } },
737 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU21I
, ETHI
, FSI_FSI
, SDHI1
} },
738 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC
, DMAC1B
, /*ICB?*/0, SDHI0
} },
739 { 0xa408002c, 0, 16, 4, /* IPRL */ { /*SCIFA5*/SCIFA_SCIFA2
, 0,
740 TPU_TPUI
, /*2DDMAC*/0 } },
741 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
742 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
745 static struct intc_sense_reg sense_registers
[] __initdata
= {
746 { 0xa414001c, 16, 2, /* ICR1 */
747 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
750 static struct intc_mask_reg ack_registers
[] __initdata
= {
751 { 0xa4140024, 0, 8, /* INTREQ00 */
752 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
755 static DECLARE_INTC_DESC_ACK(intc_desc
, "sh7724", vectors
, groups
,
756 mask_registers
, prio_registers
, sense_registers
,
759 void __init
plat_irq_setup(void)
761 register_intc_controller(&intc_desc
);