2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
16 #include <linux/kvm_host.h>
20 #include "kvm_cache_regs.h"
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
31 #include <asm/virtext.h>
33 #define __ex(x) __kvm_handle_fault_on_reboot(x)
35 MODULE_AUTHOR("Qumranet");
36 MODULE_LICENSE("GPL");
38 #define IOPM_ALLOC_ORDER 2
39 #define MSRPM_ALLOC_ORDER 1
41 #define SEG_TYPE_LDT 2
42 #define SEG_TYPE_BUSY_TSS16 3
44 #define SVM_FEATURE_NPT (1 << 0)
45 #define SVM_FEATURE_LBRV (1 << 1)
46 #define SVM_FEATURE_SVML (1 << 2)
48 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
50 /* Turn on to get debugging output*/
51 /* #define NESTED_DEBUG */
54 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
56 #define nsvm_printk(fmt, args...) do {} while(0)
59 static const u32 host_save_user_msrs
[] = {
61 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
64 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
67 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
74 unsigned long vmcb_pa
;
75 struct svm_cpu_data
*svm_data
;
76 uint64_t asid_generation
;
77 uint64_t sysenter_esp
;
78 uint64_t sysenter_eip
;
82 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
91 /* These are the merged vectors */
94 /* gpa pointers to the real vectors */
95 u64 nested_vmcb_msrpm
;
98 /* enable NPT for AMD64 and X86 with PAE */
99 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
100 static bool npt_enabled
= true;
102 static bool npt_enabled
= false;
106 module_param(npt
, int, S_IRUGO
);
108 static int nested
= 0;
109 module_param(nested
, int, S_IRUGO
);
111 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
113 static int nested_svm_exit_handled(struct vcpu_svm
*svm
, bool kvm_override
);
114 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
115 static int nested_svm_vmsave(struct vcpu_svm
*svm
, void *nested_vmcb
,
116 void *arg2
, void *opaque
);
117 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
118 bool has_error_code
, u32 error_code
);
120 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
122 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
125 static inline bool is_nested(struct vcpu_svm
*svm
)
127 return svm
->nested_vmcb
;
130 static unsigned long iopm_base
;
132 struct kvm_ldttss_desc
{
135 unsigned base1
: 8, type
: 5, dpl
: 2, p
: 1;
136 unsigned limit1
: 4, zero0
: 3, g
: 1, base2
: 8;
139 } __attribute__((packed
));
141 struct svm_cpu_data
{
147 struct kvm_ldttss_desc
*tss_desc
;
149 struct page
*save_area
;
152 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
153 static uint32_t svm_features
;
155 struct svm_init_data
{
160 static u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
162 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
163 #define MSRS_RANGE_SIZE 2048
164 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
166 #define MAX_INST_SIZE 15
168 static inline u32
svm_has(u32 feat
)
170 return svm_features
& feat
;
173 static inline void clgi(void)
175 asm volatile (__ex(SVM_CLGI
));
178 static inline void stgi(void)
180 asm volatile (__ex(SVM_STGI
));
183 static inline void invlpga(unsigned long addr
, u32 asid
)
185 asm volatile (__ex(SVM_INVLPGA
) :: "a"(addr
), "c"(asid
));
188 static inline void force_new_asid(struct kvm_vcpu
*vcpu
)
190 to_svm(vcpu
)->asid_generation
--;
193 static inline void flush_guest_tlb(struct kvm_vcpu
*vcpu
)
195 force_new_asid(vcpu
);
198 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
200 if (!npt_enabled
&& !(efer
& EFER_LMA
))
203 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
204 vcpu
->arch
.shadow_efer
= efer
;
207 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
208 bool has_error_code
, u32 error_code
)
210 struct vcpu_svm
*svm
= to_svm(vcpu
);
212 /* If we are within a nested VM we'd better #VMEXIT and let the
213 guest handle the exception */
214 if (nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
217 svm
->vmcb
->control
.event_inj
= nr
219 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
220 | SVM_EVTINJ_TYPE_EXEPT
;
221 svm
->vmcb
->control
.event_inj_err
= error_code
;
224 static int is_external_interrupt(u32 info
)
226 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
227 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
230 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
232 struct vcpu_svm
*svm
= to_svm(vcpu
);
235 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
236 ret
|= X86_SHADOW_INT_STI
| X86_SHADOW_INT_MOV_SS
;
240 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
242 struct vcpu_svm
*svm
= to_svm(vcpu
);
245 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
247 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
251 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
253 struct vcpu_svm
*svm
= to_svm(vcpu
);
255 if (!svm
->next_rip
) {
256 if (emulate_instruction(vcpu
, vcpu
->run
, 0, 0, EMULTYPE_SKIP
) !=
258 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
261 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
262 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
263 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
265 kvm_rip_write(vcpu
, svm
->next_rip
);
266 svm_set_interrupt_shadow(vcpu
, 0);
269 static int has_svm(void)
273 if (!cpu_has_svm(&msg
)) {
274 printk(KERN_INFO
"has_svm: %s\n", msg
);
281 static void svm_hardware_disable(void *garbage
)
286 static void svm_hardware_enable(void *garbage
)
289 struct svm_cpu_data
*svm_data
;
291 struct desc_ptr gdt_descr
;
292 struct desc_struct
*gdt
;
293 int me
= raw_smp_processor_id();
296 printk(KERN_ERR
"svm_cpu_init: err EOPNOTSUPP on %d\n", me
);
299 svm_data
= per_cpu(svm_data
, me
);
302 printk(KERN_ERR
"svm_cpu_init: svm_data is NULL on %d\n",
307 svm_data
->asid_generation
= 1;
308 svm_data
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
309 svm_data
->next_asid
= svm_data
->max_asid
+ 1;
311 asm volatile ("sgdt %0" : "=m"(gdt_descr
));
312 gdt
= (struct desc_struct
*)gdt_descr
.address
;
313 svm_data
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
315 rdmsrl(MSR_EFER
, efer
);
316 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
318 wrmsrl(MSR_VM_HSAVE_PA
,
319 page_to_pfn(svm_data
->save_area
) << PAGE_SHIFT
);
322 static void svm_cpu_uninit(int cpu
)
324 struct svm_cpu_data
*svm_data
325 = per_cpu(svm_data
, raw_smp_processor_id());
330 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
331 __free_page(svm_data
->save_area
);
335 static int svm_cpu_init(int cpu
)
337 struct svm_cpu_data
*svm_data
;
340 svm_data
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
344 svm_data
->save_area
= alloc_page(GFP_KERNEL
);
346 if (!svm_data
->save_area
)
349 per_cpu(svm_data
, cpu
) = svm_data
;
359 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
364 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
365 if (msr
>= msrpm_ranges
[i
] &&
366 msr
< msrpm_ranges
[i
] + MSRS_IN_RANGE
) {
367 u32 msr_offset
= (i
* MSRS_IN_RANGE
+ msr
-
368 msrpm_ranges
[i
]) * 2;
370 u32
*base
= msrpm
+ (msr_offset
/ 32);
371 u32 msr_shift
= msr_offset
% 32;
372 u32 mask
= ((write
) ? 0 : 2) | ((read
) ? 0 : 1);
373 *base
= (*base
& ~(0x3 << msr_shift
)) |
381 static void svm_vcpu_init_msrpm(u32
*msrpm
)
383 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
386 set_msr_interception(msrpm
, MSR_GS_BASE
, 1, 1);
387 set_msr_interception(msrpm
, MSR_FS_BASE
, 1, 1);
388 set_msr_interception(msrpm
, MSR_KERNEL_GS_BASE
, 1, 1);
389 set_msr_interception(msrpm
, MSR_LSTAR
, 1, 1);
390 set_msr_interception(msrpm
, MSR_CSTAR
, 1, 1);
391 set_msr_interception(msrpm
, MSR_SYSCALL_MASK
, 1, 1);
393 set_msr_interception(msrpm
, MSR_K6_STAR
, 1, 1);
394 set_msr_interception(msrpm
, MSR_IA32_SYSENTER_CS
, 1, 1);
397 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
399 u32
*msrpm
= svm
->msrpm
;
401 svm
->vmcb
->control
.lbr_ctl
= 1;
402 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
403 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
404 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
405 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
408 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
410 u32
*msrpm
= svm
->msrpm
;
412 svm
->vmcb
->control
.lbr_ctl
= 0;
413 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
414 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
415 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
416 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
419 static __init
int svm_hardware_setup(void)
422 struct page
*iopm_pages
;
426 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
431 iopm_va
= page_address(iopm_pages
);
432 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
433 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
435 if (boot_cpu_has(X86_FEATURE_NX
))
436 kvm_enable_efer_bits(EFER_NX
);
438 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
439 kvm_enable_efer_bits(EFER_FFXSR
);
442 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
443 kvm_enable_efer_bits(EFER_SVME
);
446 for_each_online_cpu(cpu
) {
447 r
= svm_cpu_init(cpu
);
452 svm_features
= cpuid_edx(SVM_CPUID_FUNC
);
454 if (!svm_has(SVM_FEATURE_NPT
))
457 if (npt_enabled
&& !npt
) {
458 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
463 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
471 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
476 static __exit
void svm_hardware_unsetup(void)
480 for_each_online_cpu(cpu
)
483 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
487 static void init_seg(struct vmcb_seg
*seg
)
490 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
491 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
496 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
499 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
504 static void init_vmcb(struct vcpu_svm
*svm
)
506 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
507 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
509 control
->intercept_cr_read
= INTERCEPT_CR0_MASK
|
513 control
->intercept_cr_write
= INTERCEPT_CR0_MASK
|
518 control
->intercept_dr_read
= INTERCEPT_DR0_MASK
|
523 control
->intercept_dr_write
= INTERCEPT_DR0_MASK
|
530 control
->intercept_exceptions
= (1 << PF_VECTOR
) |
535 control
->intercept
= (1ULL << INTERCEPT_INTR
) |
536 (1ULL << INTERCEPT_NMI
) |
537 (1ULL << INTERCEPT_SMI
) |
538 (1ULL << INTERCEPT_CPUID
) |
539 (1ULL << INTERCEPT_INVD
) |
540 (1ULL << INTERCEPT_HLT
) |
541 (1ULL << INTERCEPT_INVLPG
) |
542 (1ULL << INTERCEPT_INVLPGA
) |
543 (1ULL << INTERCEPT_IOIO_PROT
) |
544 (1ULL << INTERCEPT_MSR_PROT
) |
545 (1ULL << INTERCEPT_TASK_SWITCH
) |
546 (1ULL << INTERCEPT_SHUTDOWN
) |
547 (1ULL << INTERCEPT_VMRUN
) |
548 (1ULL << INTERCEPT_VMMCALL
) |
549 (1ULL << INTERCEPT_VMLOAD
) |
550 (1ULL << INTERCEPT_VMSAVE
) |
551 (1ULL << INTERCEPT_STGI
) |
552 (1ULL << INTERCEPT_CLGI
) |
553 (1ULL << INTERCEPT_SKINIT
) |
554 (1ULL << INTERCEPT_WBINVD
) |
555 (1ULL << INTERCEPT_MONITOR
) |
556 (1ULL << INTERCEPT_MWAIT
);
558 control
->iopm_base_pa
= iopm_base
;
559 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
560 control
->tsc_offset
= 0;
561 control
->int_ctl
= V_INTR_MASKING_MASK
;
569 save
->cs
.selector
= 0xf000;
570 /* Executable/Readable Code Segment */
571 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
572 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
573 save
->cs
.limit
= 0xffff;
575 * cs.base should really be 0xffff0000, but vmx can't handle that, so
576 * be consistent with it.
578 * Replace when we have real mode working for vmx.
580 save
->cs
.base
= 0xf0000;
582 save
->gdtr
.limit
= 0xffff;
583 save
->idtr
.limit
= 0xffff;
585 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
586 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
588 save
->efer
= EFER_SVME
;
589 save
->dr6
= 0xffff0ff0;
592 save
->rip
= 0x0000fff0;
593 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
596 * cr0 val on cpu init should be 0x60000010, we enable cpu
597 * cache by default. the orderly way is to enable cache in bios.
599 save
->cr0
= 0x00000010 | X86_CR0_PG
| X86_CR0_WP
;
600 save
->cr4
= X86_CR4_PAE
;
604 /* Setup VMCB for Nested Paging */
605 control
->nested_ctl
= 1;
606 control
->intercept
&= ~((1ULL << INTERCEPT_TASK_SWITCH
) |
607 (1ULL << INTERCEPT_INVLPG
));
608 control
->intercept_exceptions
&= ~(1 << PF_VECTOR
);
609 control
->intercept_cr_read
&= ~(INTERCEPT_CR0_MASK
|
611 control
->intercept_cr_write
&= ~(INTERCEPT_CR0_MASK
|
613 save
->g_pat
= 0x0007040600070406ULL
;
614 /* enable caching because the QEMU Bios doesn't enable it */
615 save
->cr0
= X86_CR0_ET
;
619 force_new_asid(&svm
->vcpu
);
621 svm
->nested_vmcb
= 0;
622 svm
->vcpu
.arch
.hflags
= HF_GIF_MASK
;
625 static int svm_vcpu_reset(struct kvm_vcpu
*vcpu
)
627 struct vcpu_svm
*svm
= to_svm(vcpu
);
631 if (!kvm_vcpu_is_bsp(vcpu
)) {
632 kvm_rip_write(vcpu
, 0);
633 svm
->vmcb
->save
.cs
.base
= svm
->vcpu
.arch
.sipi_vector
<< 12;
634 svm
->vmcb
->save
.cs
.selector
= svm
->vcpu
.arch
.sipi_vector
<< 8;
636 vcpu
->arch
.regs_avail
= ~0;
637 vcpu
->arch
.regs_dirty
= ~0;
642 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
644 struct vcpu_svm
*svm
;
646 struct page
*msrpm_pages
;
647 struct page
*hsave_page
;
648 struct page
*nested_msrpm_pages
;
651 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
657 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
661 page
= alloc_page(GFP_KERNEL
);
668 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
672 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
673 if (!nested_msrpm_pages
)
676 svm
->msrpm
= page_address(msrpm_pages
);
677 svm_vcpu_init_msrpm(svm
->msrpm
);
679 hsave_page
= alloc_page(GFP_KERNEL
);
682 svm
->hsave
= page_address(hsave_page
);
684 svm
->nested_msrpm
= page_address(nested_msrpm_pages
);
686 svm
->vmcb
= page_address(page
);
687 clear_page(svm
->vmcb
);
688 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
689 svm
->asid_generation
= 0;
693 svm
->vcpu
.fpu_active
= 1;
694 svm
->vcpu
.arch
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
695 if (kvm_vcpu_is_bsp(&svm
->vcpu
))
696 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
701 kvm_vcpu_uninit(&svm
->vcpu
);
703 kmem_cache_free(kvm_vcpu_cache
, svm
);
708 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
710 struct vcpu_svm
*svm
= to_svm(vcpu
);
712 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
713 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
714 __free_page(virt_to_page(svm
->hsave
));
715 __free_pages(virt_to_page(svm
->nested_msrpm
), MSRPM_ALLOC_ORDER
);
716 kvm_vcpu_uninit(vcpu
);
717 kmem_cache_free(kvm_vcpu_cache
, svm
);
720 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
722 struct vcpu_svm
*svm
= to_svm(vcpu
);
725 if (unlikely(cpu
!= vcpu
->cpu
)) {
729 * Make sure that the guest sees a monotonically
733 delta
= vcpu
->arch
.host_tsc
- tsc_this
;
734 svm
->vmcb
->control
.tsc_offset
+= delta
;
736 kvm_migrate_timers(vcpu
);
737 svm
->asid_generation
= 0;
740 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
741 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
744 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
746 struct vcpu_svm
*svm
= to_svm(vcpu
);
749 ++vcpu
->stat
.host_state_reload
;
750 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
751 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
753 rdtscll(vcpu
->arch
.host_tsc
);
756 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
758 return to_svm(vcpu
)->vmcb
->save
.rflags
;
761 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
763 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
766 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
769 case VCPU_EXREG_PDPTR
:
770 BUG_ON(!npt_enabled
);
771 load_pdptrs(vcpu
, vcpu
->arch
.cr3
);
778 static void svm_set_vintr(struct vcpu_svm
*svm
)
780 svm
->vmcb
->control
.intercept
|= 1ULL << INTERCEPT_VINTR
;
783 static void svm_clear_vintr(struct vcpu_svm
*svm
)
785 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_VINTR
);
788 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
790 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
793 case VCPU_SREG_CS
: return &save
->cs
;
794 case VCPU_SREG_DS
: return &save
->ds
;
795 case VCPU_SREG_ES
: return &save
->es
;
796 case VCPU_SREG_FS
: return &save
->fs
;
797 case VCPU_SREG_GS
: return &save
->gs
;
798 case VCPU_SREG_SS
: return &save
->ss
;
799 case VCPU_SREG_TR
: return &save
->tr
;
800 case VCPU_SREG_LDTR
: return &save
->ldtr
;
806 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
808 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
813 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
814 struct kvm_segment
*var
, int seg
)
816 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
819 var
->limit
= s
->limit
;
820 var
->selector
= s
->selector
;
821 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
822 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
823 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
824 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
825 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
826 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
827 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
828 var
->g
= (s
->attrib
>> SVM_SELECTOR_G_SHIFT
) & 1;
830 /* AMD's VMCB does not have an explicit unusable field, so emulate it
831 * for cross vendor migration purposes by "not present"
833 var
->unusable
= !var
->present
|| (var
->type
== 0);
838 * SVM always stores 0 for the 'G' bit in the CS selector in
839 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
840 * Intel's VMENTRY has a check on the 'G' bit.
842 var
->g
= s
->limit
> 0xfffff;
846 * Work around a bug where the busy flag in the tr selector
856 * The accessed bit must always be set in the segment
857 * descriptor cache, although it can be cleared in the
858 * descriptor, the cached bit always remains at 1. Since
859 * Intel has a check on this, set it here to support
860 * cross-vendor migration.
866 /* On AMD CPUs sometimes the DB bit in the segment
867 * descriptor is left as 1, although the whole segment has
868 * been made unusable. Clear it here to pass an Intel VMX
869 * entry check when cross vendor migrating.
877 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
879 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
884 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
886 struct vcpu_svm
*svm
= to_svm(vcpu
);
888 dt
->limit
= svm
->vmcb
->save
.idtr
.limit
;
889 dt
->base
= svm
->vmcb
->save
.idtr
.base
;
892 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
894 struct vcpu_svm
*svm
= to_svm(vcpu
);
896 svm
->vmcb
->save
.idtr
.limit
= dt
->limit
;
897 svm
->vmcb
->save
.idtr
.base
= dt
->base
;
900 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
902 struct vcpu_svm
*svm
= to_svm(vcpu
);
904 dt
->limit
= svm
->vmcb
->save
.gdtr
.limit
;
905 dt
->base
= svm
->vmcb
->save
.gdtr
.base
;
908 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
910 struct vcpu_svm
*svm
= to_svm(vcpu
);
912 svm
->vmcb
->save
.gdtr
.limit
= dt
->limit
;
913 svm
->vmcb
->save
.gdtr
.base
= dt
->base
;
916 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
920 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
922 struct vcpu_svm
*svm
= to_svm(vcpu
);
925 if (vcpu
->arch
.shadow_efer
& EFER_LME
) {
926 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
927 vcpu
->arch
.shadow_efer
|= EFER_LMA
;
928 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
931 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
932 vcpu
->arch
.shadow_efer
&= ~EFER_LMA
;
933 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
940 if ((vcpu
->arch
.cr0
& X86_CR0_TS
) && !(cr0
& X86_CR0_TS
)) {
941 svm
->vmcb
->control
.intercept_exceptions
&= ~(1 << NM_VECTOR
);
942 vcpu
->fpu_active
= 1;
945 vcpu
->arch
.cr0
= cr0
;
946 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
947 if (!vcpu
->fpu_active
) {
948 svm
->vmcb
->control
.intercept_exceptions
|= (1 << NM_VECTOR
);
953 * re-enable caching here because the QEMU bios
954 * does not do it - this results in some delay at
957 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
958 svm
->vmcb
->save
.cr0
= cr0
;
961 static void svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
963 unsigned long host_cr4_mce
= read_cr4() & X86_CR4_MCE
;
964 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
966 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
967 force_new_asid(vcpu
);
969 vcpu
->arch
.cr4
= cr4
;
973 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
976 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
977 struct kvm_segment
*var
, int seg
)
979 struct vcpu_svm
*svm
= to_svm(vcpu
);
980 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
983 s
->limit
= var
->limit
;
984 s
->selector
= var
->selector
;
988 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
989 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
990 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
991 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
992 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
993 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
994 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
995 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
997 if (seg
== VCPU_SREG_CS
)
999 = (svm
->vmcb
->save
.cs
.attrib
1000 >> SVM_SELECTOR_DPL_SHIFT
) & 3;
1004 static void update_db_intercept(struct kvm_vcpu
*vcpu
)
1006 struct vcpu_svm
*svm
= to_svm(vcpu
);
1008 svm
->vmcb
->control
.intercept_exceptions
&=
1009 ~((1 << DB_VECTOR
) | (1 << BP_VECTOR
));
1011 if (vcpu
->arch
.singlestep
)
1012 svm
->vmcb
->control
.intercept_exceptions
|= (1 << DB_VECTOR
);
1014 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1015 if (vcpu
->guest_debug
&
1016 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
1017 svm
->vmcb
->control
.intercept_exceptions
|=
1019 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1020 svm
->vmcb
->control
.intercept_exceptions
|=
1023 vcpu
->guest_debug
= 0;
1026 static int svm_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1028 int old_debug
= vcpu
->guest_debug
;
1029 struct vcpu_svm
*svm
= to_svm(vcpu
);
1031 vcpu
->guest_debug
= dbg
->control
;
1033 update_db_intercept(vcpu
);
1035 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1036 svm
->vmcb
->save
.dr7
= dbg
->arch
.debugreg
[7];
1038 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1040 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
1041 svm
->vmcb
->save
.rflags
|= X86_EFLAGS_TF
| X86_EFLAGS_RF
;
1042 else if (old_debug
& KVM_GUESTDBG_SINGLESTEP
)
1043 svm
->vmcb
->save
.rflags
&= ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1048 static void load_host_msrs(struct kvm_vcpu
*vcpu
)
1050 #ifdef CONFIG_X86_64
1051 wrmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1055 static void save_host_msrs(struct kvm_vcpu
*vcpu
)
1057 #ifdef CONFIG_X86_64
1058 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1062 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*svm_data
)
1064 if (svm_data
->next_asid
> svm_data
->max_asid
) {
1065 ++svm_data
->asid_generation
;
1066 svm_data
->next_asid
= 1;
1067 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1070 svm
->asid_generation
= svm_data
->asid_generation
;
1071 svm
->vmcb
->control
.asid
= svm_data
->next_asid
++;
1074 static unsigned long svm_get_dr(struct kvm_vcpu
*vcpu
, int dr
)
1076 struct vcpu_svm
*svm
= to_svm(vcpu
);
1081 val
= vcpu
->arch
.db
[dr
];
1084 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1085 val
= vcpu
->arch
.dr6
;
1087 val
= svm
->vmcb
->save
.dr6
;
1090 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1091 val
= vcpu
->arch
.dr7
;
1093 val
= svm
->vmcb
->save
.dr7
;
1099 KVMTRACE_2D(DR_READ
, vcpu
, (u32
)dr
, (u32
)val
, handler
);
1103 static void svm_set_dr(struct kvm_vcpu
*vcpu
, int dr
, unsigned long value
,
1106 struct vcpu_svm
*svm
= to_svm(vcpu
);
1108 KVMTRACE_2D(DR_WRITE
, vcpu
, (u32
)dr
, (u32
)value
, handler
);
1114 vcpu
->arch
.db
[dr
] = value
;
1115 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
))
1116 vcpu
->arch
.eff_db
[dr
] = value
;
1119 if (vcpu
->arch
.cr4
& X86_CR4_DE
)
1120 *exception
= UD_VECTOR
;
1123 if (value
& 0xffffffff00000000ULL
) {
1124 *exception
= GP_VECTOR
;
1127 vcpu
->arch
.dr6
= (value
& DR6_VOLATILE
) | DR6_FIXED_1
;
1130 if (value
& 0xffffffff00000000ULL
) {
1131 *exception
= GP_VECTOR
;
1134 vcpu
->arch
.dr7
= (value
& DR7_VOLATILE
) | DR7_FIXED_1
;
1135 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)) {
1136 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1137 vcpu
->arch
.switch_db_regs
= (value
& DR7_BP_EN_MASK
);
1141 /* FIXME: Possible case? */
1142 printk(KERN_DEBUG
"%s: unexpected dr %u\n",
1144 *exception
= UD_VECTOR
;
1149 static int pf_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1154 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1155 error_code
= svm
->vmcb
->control
.exit_info_1
;
1158 KVMTRACE_3D(PAGE_FAULT
, &svm
->vcpu
, error_code
,
1159 (u32
)fault_address
, (u32
)(fault_address
>> 32),
1162 KVMTRACE_3D(TDP_FAULT
, &svm
->vcpu
, error_code
,
1163 (u32
)fault_address
, (u32
)(fault_address
>> 32),
1166 * FIXME: Tis shouldn't be necessary here, but there is a flush
1167 * missing in the MMU code. Until we find this bug, flush the
1168 * complete TLB here on an NPF
1171 svm_flush_tlb(&svm
->vcpu
);
1173 if (kvm_event_needs_reinjection(&svm
->vcpu
))
1174 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1176 return kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
);
1179 static int db_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1181 if (!(svm
->vcpu
.guest_debug
&
1182 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1183 !svm
->vcpu
.arch
.singlestep
) {
1184 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1188 if (svm
->vcpu
.arch
.singlestep
) {
1189 svm
->vcpu
.arch
.singlestep
= false;
1190 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
1191 svm
->vmcb
->save
.rflags
&=
1192 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1193 update_db_intercept(&svm
->vcpu
);
1196 if (svm
->vcpu
.guest_debug
&
1197 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)){
1198 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1199 kvm_run
->debug
.arch
.pc
=
1200 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1201 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1208 static int bp_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1210 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1211 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1212 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1216 static int ud_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1220 er
= emulate_instruction(&svm
->vcpu
, kvm_run
, 0, 0, EMULTYPE_TRAP_UD
);
1221 if (er
!= EMULATE_DONE
)
1222 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1226 static int nm_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1228 svm
->vmcb
->control
.intercept_exceptions
&= ~(1 << NM_VECTOR
);
1229 if (!(svm
->vcpu
.arch
.cr0
& X86_CR0_TS
))
1230 svm
->vmcb
->save
.cr0
&= ~X86_CR0_TS
;
1231 svm
->vcpu
.fpu_active
= 1;
1236 static int mc_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1239 * On an #MC intercept the MCE handler is not called automatically in
1240 * the host. So do it by hand here.
1244 /* not sure if we ever come back to this point */
1249 static int shutdown_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1252 * VMCB is undefined after a SHUTDOWN intercept
1253 * so reinitialize it.
1255 clear_page(svm
->vmcb
);
1258 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1262 static int io_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1264 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1265 int size
, in
, string
;
1268 ++svm
->vcpu
.stat
.io_exits
;
1270 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1272 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1275 if (emulate_instruction(&svm
->vcpu
,
1276 kvm_run
, 0, 0, 0) == EMULATE_DO_MMIO
)
1281 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1282 port
= io_info
>> 16;
1283 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1285 skip_emulated_instruction(&svm
->vcpu
);
1286 return kvm_emulate_pio(&svm
->vcpu
, kvm_run
, in
, size
, port
);
1289 static int nmi_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1291 KVMTRACE_0D(NMI
, &svm
->vcpu
, handler
);
1295 static int intr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1297 ++svm
->vcpu
.stat
.irq_exits
;
1298 KVMTRACE_0D(INTR
, &svm
->vcpu
, handler
);
1302 static int nop_on_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1307 static int halt_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1309 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1310 skip_emulated_instruction(&svm
->vcpu
);
1311 return kvm_emulate_halt(&svm
->vcpu
);
1314 static int vmmcall_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1316 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1317 skip_emulated_instruction(&svm
->vcpu
);
1318 kvm_emulate_hypercall(&svm
->vcpu
);
1322 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
1324 if (!(svm
->vcpu
.arch
.shadow_efer
& EFER_SVME
)
1325 || !is_paging(&svm
->vcpu
)) {
1326 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1330 if (svm
->vmcb
->save
.cpl
) {
1331 kvm_inject_gp(&svm
->vcpu
, 0);
1338 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
1339 bool has_error_code
, u32 error_code
)
1341 if (is_nested(svm
)) {
1342 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
1343 svm
->vmcb
->control
.exit_code_hi
= 0;
1344 svm
->vmcb
->control
.exit_info_1
= error_code
;
1345 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
1346 if (nested_svm_exit_handled(svm
, false)) {
1347 nsvm_printk("VMexit -> EXCP 0x%x\n", nr
);
1349 nested_svm_vmexit(svm
);
1357 static inline int nested_svm_intr(struct vcpu_svm
*svm
)
1359 if (is_nested(svm
)) {
1360 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1363 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
1366 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
1368 if (nested_svm_exit_handled(svm
, false)) {
1369 nsvm_printk("VMexit -> INTR\n");
1370 nested_svm_vmexit(svm
);
1378 static struct page
*nested_svm_get_page(struct vcpu_svm
*svm
, u64 gpa
)
1382 down_read(¤t
->mm
->mmap_sem
);
1383 page
= gfn_to_page(svm
->vcpu
.kvm
, gpa
>> PAGE_SHIFT
);
1384 up_read(¤t
->mm
->mmap_sem
);
1386 if (is_error_page(page
)) {
1387 printk(KERN_INFO
"%s: could not find page at 0x%llx\n",
1389 kvm_release_page_clean(page
);
1390 kvm_inject_gp(&svm
->vcpu
, 0);
1396 static int nested_svm_do(struct vcpu_svm
*svm
,
1397 u64 arg1_gpa
, u64 arg2_gpa
, void *opaque
,
1398 int (*handler
)(struct vcpu_svm
*svm
,
1403 struct page
*arg1_page
;
1404 struct page
*arg2_page
= NULL
;
1409 arg1_page
= nested_svm_get_page(svm
, arg1_gpa
);
1410 if(arg1_page
== NULL
)
1414 arg2_page
= nested_svm_get_page(svm
, arg2_gpa
);
1415 if(arg2_page
== NULL
) {
1416 kvm_release_page_clean(arg1_page
);
1421 arg1
= kmap_atomic(arg1_page
, KM_USER0
);
1423 arg2
= kmap_atomic(arg2_page
, KM_USER1
);
1425 retval
= handler(svm
, arg1
, arg2
, opaque
);
1427 kunmap_atomic(arg1
, KM_USER0
);
1429 kunmap_atomic(arg2
, KM_USER1
);
1431 kvm_release_page_dirty(arg1_page
);
1433 kvm_release_page_dirty(arg2_page
);
1438 static int nested_svm_exit_handled_real(struct vcpu_svm
*svm
,
1443 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1444 bool kvm_overrides
= *(bool *)opaque
;
1445 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1447 if (kvm_overrides
) {
1448 switch (exit_code
) {
1452 /* For now we are always handling NPFs when using them */
1457 /* When we're shadowing, trap PFs */
1458 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
1467 switch (exit_code
) {
1468 case SVM_EXIT_READ_CR0
... SVM_EXIT_READ_CR8
: {
1469 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_READ_CR0
);
1470 if (nested_vmcb
->control
.intercept_cr_read
& cr_bits
)
1474 case SVM_EXIT_WRITE_CR0
... SVM_EXIT_WRITE_CR8
: {
1475 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_CR0
);
1476 if (nested_vmcb
->control
.intercept_cr_write
& cr_bits
)
1480 case SVM_EXIT_READ_DR0
... SVM_EXIT_READ_DR7
: {
1481 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_READ_DR0
);
1482 if (nested_vmcb
->control
.intercept_dr_read
& dr_bits
)
1486 case SVM_EXIT_WRITE_DR0
... SVM_EXIT_WRITE_DR7
: {
1487 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_DR0
);
1488 if (nested_vmcb
->control
.intercept_dr_write
& dr_bits
)
1492 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
1493 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
1494 if (nested_vmcb
->control
.intercept_exceptions
& excp_bits
)
1499 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
1500 nsvm_printk("exit code: 0x%x\n", exit_code
);
1501 if (nested_vmcb
->control
.intercept
& exit_bits
)
1509 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
,
1510 void *arg1
, void *arg2
,
1513 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1514 u8
*msrpm
= (u8
*)arg2
;
1516 u32 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
1517 u32 param
= svm
->vmcb
->control
.exit_info_1
& 1;
1519 if (!(nested_vmcb
->control
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
1527 case 0xc0000000 ... 0xc0001fff:
1528 t0
= (8192 + msr
- 0xc0000000) * 2;
1532 case 0xc0010000 ... 0xc0011fff:
1533 t0
= (16384 + msr
- 0xc0010000) * 2;
1541 if (msrpm
[t1
] & ((1 << param
) << t0
))
1547 static int nested_svm_exit_handled(struct vcpu_svm
*svm
, bool kvm_override
)
1549 bool k
= kvm_override
;
1551 switch (svm
->vmcb
->control
.exit_code
) {
1553 return nested_svm_do(svm
, svm
->nested_vmcb
,
1554 svm
->nested_vmcb_msrpm
, NULL
,
1555 nested_svm_exit_handled_msr
);
1559 return nested_svm_do(svm
, svm
->nested_vmcb
, 0, &k
,
1560 nested_svm_exit_handled_real
);
1563 static int nested_svm_vmexit_real(struct vcpu_svm
*svm
, void *arg1
,
1564 void *arg2
, void *opaque
)
1566 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1567 struct vmcb
*hsave
= svm
->hsave
;
1568 u64 nested_save
[] = { nested_vmcb
->save
.cr0
,
1569 nested_vmcb
->save
.cr3
,
1570 nested_vmcb
->save
.cr4
,
1571 nested_vmcb
->save
.efer
,
1572 nested_vmcb
->control
.intercept_cr_read
,
1573 nested_vmcb
->control
.intercept_cr_write
,
1574 nested_vmcb
->control
.intercept_dr_read
,
1575 nested_vmcb
->control
.intercept_dr_write
,
1576 nested_vmcb
->control
.intercept_exceptions
,
1577 nested_vmcb
->control
.intercept
,
1578 nested_vmcb
->control
.msrpm_base_pa
,
1579 nested_vmcb
->control
.iopm_base_pa
,
1580 nested_vmcb
->control
.tsc_offset
};
1582 /* Give the current vmcb to the guest */
1583 memcpy(nested_vmcb
, svm
->vmcb
, sizeof(struct vmcb
));
1584 nested_vmcb
->save
.cr0
= nested_save
[0];
1586 nested_vmcb
->save
.cr3
= nested_save
[1];
1587 nested_vmcb
->save
.cr4
= nested_save
[2];
1588 nested_vmcb
->save
.efer
= nested_save
[3];
1589 nested_vmcb
->control
.intercept_cr_read
= nested_save
[4];
1590 nested_vmcb
->control
.intercept_cr_write
= nested_save
[5];
1591 nested_vmcb
->control
.intercept_dr_read
= nested_save
[6];
1592 nested_vmcb
->control
.intercept_dr_write
= nested_save
[7];
1593 nested_vmcb
->control
.intercept_exceptions
= nested_save
[8];
1594 nested_vmcb
->control
.intercept
= nested_save
[9];
1595 nested_vmcb
->control
.msrpm_base_pa
= nested_save
[10];
1596 nested_vmcb
->control
.iopm_base_pa
= nested_save
[11];
1597 nested_vmcb
->control
.tsc_offset
= nested_save
[12];
1599 /* We always set V_INTR_MASKING and remember the old value in hflags */
1600 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1601 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
1603 if ((nested_vmcb
->control
.int_ctl
& V_IRQ_MASK
) &&
1604 (nested_vmcb
->control
.int_vector
)) {
1605 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1606 nested_vmcb
->control
.int_vector
);
1609 /* Restore the original control entries */
1610 svm
->vmcb
->control
= hsave
->control
;
1612 /* Kill any pending exceptions */
1613 if (svm
->vcpu
.arch
.exception
.pending
== true)
1614 nsvm_printk("WARNING: Pending Exception\n");
1615 svm
->vcpu
.arch
.exception
.pending
= false;
1617 /* Restore selected save entries */
1618 svm
->vmcb
->save
.es
= hsave
->save
.es
;
1619 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
1620 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
1621 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
1622 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
1623 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
1624 svm
->vmcb
->save
.rflags
= hsave
->save
.rflags
;
1625 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
1626 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
1627 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
1629 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
1630 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
1632 kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
1634 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
1635 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
1636 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
1637 svm
->vmcb
->save
.dr7
= 0;
1638 svm
->vmcb
->save
.cpl
= 0;
1639 svm
->vmcb
->control
.exit_int_info
= 0;
1641 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
1642 /* Exit nested SVM mode */
1643 svm
->nested_vmcb
= 0;
1648 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
1650 nsvm_printk("VMexit\n");
1651 if (nested_svm_do(svm
, svm
->nested_vmcb
, 0,
1652 NULL
, nested_svm_vmexit_real
))
1655 kvm_mmu_reset_context(&svm
->vcpu
);
1656 kvm_mmu_load(&svm
->vcpu
);
1661 static int nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
, void *arg1
,
1662 void *arg2
, void *opaque
)
1665 u32
*nested_msrpm
= (u32
*)arg1
;
1666 for (i
=0; i
< PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
) / 4; i
++)
1667 svm
->nested_msrpm
[i
] = svm
->msrpm
[i
] | nested_msrpm
[i
];
1668 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested_msrpm
);
1673 static int nested_svm_vmrun(struct vcpu_svm
*svm
, void *arg1
,
1674 void *arg2
, void *opaque
)
1676 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1677 struct vmcb
*hsave
= svm
->hsave
;
1679 /* nested_vmcb is our indicator if nested SVM is activated */
1680 svm
->nested_vmcb
= svm
->vmcb
->save
.rax
;
1682 /* Clear internal status */
1683 svm
->vcpu
.arch
.exception
.pending
= false;
1685 /* Save the old vmcb, so we don't need to pick what we save, but
1686 can restore everything when a VMEXIT occurs */
1687 memcpy(hsave
, svm
->vmcb
, sizeof(struct vmcb
));
1688 /* We need to remember the original CR3 in the SPT case */
1690 hsave
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
1691 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
1692 hsave
->save
.rip
= svm
->next_rip
;
1694 if (svm
->vmcb
->save
.rflags
& X86_EFLAGS_IF
)
1695 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
1697 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
1699 /* Load the nested guest state */
1700 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
1701 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
1702 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
1703 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
1704 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
1705 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
1706 svm
->vmcb
->save
.rflags
= nested_vmcb
->save
.rflags
;
1707 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
1708 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
1709 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
1711 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
1712 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
1714 kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
1715 kvm_mmu_reset_context(&svm
->vcpu
);
1717 svm
->vmcb
->save
.cr2
= nested_vmcb
->save
.cr2
;
1718 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
1719 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
1720 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
1721 /* In case we don't even reach vcpu_run, the fields are not updated */
1722 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
1723 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
1724 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
1725 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
1726 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
1727 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
1729 /* We don't want a nested guest to be more powerful than the guest,
1730 so all intercepts are ORed */
1731 svm
->vmcb
->control
.intercept_cr_read
|=
1732 nested_vmcb
->control
.intercept_cr_read
;
1733 svm
->vmcb
->control
.intercept_cr_write
|=
1734 nested_vmcb
->control
.intercept_cr_write
;
1735 svm
->vmcb
->control
.intercept_dr_read
|=
1736 nested_vmcb
->control
.intercept_dr_read
;
1737 svm
->vmcb
->control
.intercept_dr_write
|=
1738 nested_vmcb
->control
.intercept_dr_write
;
1739 svm
->vmcb
->control
.intercept_exceptions
|=
1740 nested_vmcb
->control
.intercept_exceptions
;
1742 svm
->vmcb
->control
.intercept
|= nested_vmcb
->control
.intercept
;
1744 svm
->nested_vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
;
1746 force_new_asid(&svm
->vcpu
);
1747 svm
->vmcb
->control
.exit_int_info
= nested_vmcb
->control
.exit_int_info
;
1748 svm
->vmcb
->control
.exit_int_info_err
= nested_vmcb
->control
.exit_int_info_err
;
1749 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
1750 if (nested_vmcb
->control
.int_ctl
& V_IRQ_MASK
) {
1751 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1752 nested_vmcb
->control
.int_ctl
);
1754 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
1755 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
1757 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
1759 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1760 nested_vmcb
->control
.exit_int_info
,
1761 nested_vmcb
->control
.int_state
);
1763 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
1764 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
1765 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
1766 if (nested_vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
)
1767 nsvm_printk("Injecting Event: 0x%x\n",
1768 nested_vmcb
->control
.event_inj
);
1769 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
1770 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
1772 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
1777 static int nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
1779 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
1780 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
1781 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
1782 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
1783 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
1784 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
1785 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
1786 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
1787 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
1788 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
1789 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
1790 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
1795 static int nested_svm_vmload(struct vcpu_svm
*svm
, void *nested_vmcb
,
1796 void *arg2
, void *opaque
)
1798 return nested_svm_vmloadsave((struct vmcb
*)nested_vmcb
, svm
->vmcb
);
1801 static int nested_svm_vmsave(struct vcpu_svm
*svm
, void *nested_vmcb
,
1802 void *arg2
, void *opaque
)
1804 return nested_svm_vmloadsave(svm
->vmcb
, (struct vmcb
*)nested_vmcb
);
1807 static int vmload_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1809 if (nested_svm_check_permissions(svm
))
1812 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1813 skip_emulated_instruction(&svm
->vcpu
);
1815 nested_svm_do(svm
, svm
->vmcb
->save
.rax
, 0, NULL
, nested_svm_vmload
);
1820 static int vmsave_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1822 if (nested_svm_check_permissions(svm
))
1825 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1826 skip_emulated_instruction(&svm
->vcpu
);
1828 nested_svm_do(svm
, svm
->vmcb
->save
.rax
, 0, NULL
, nested_svm_vmsave
);
1833 static int vmrun_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1835 nsvm_printk("VMrun\n");
1836 if (nested_svm_check_permissions(svm
))
1839 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1840 skip_emulated_instruction(&svm
->vcpu
);
1842 if (nested_svm_do(svm
, svm
->vmcb
->save
.rax
, 0,
1843 NULL
, nested_svm_vmrun
))
1846 if (nested_svm_do(svm
, svm
->nested_vmcb_msrpm
, 0,
1847 NULL
, nested_svm_vmrun_msrpm
))
1853 static int stgi_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1855 if (nested_svm_check_permissions(svm
))
1858 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1859 skip_emulated_instruction(&svm
->vcpu
);
1861 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
1866 static int clgi_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1868 if (nested_svm_check_permissions(svm
))
1871 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1872 skip_emulated_instruction(&svm
->vcpu
);
1874 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
1876 /* After a CLGI no interrupts should come */
1877 svm_clear_vintr(svm
);
1878 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
1883 static int invalid_op_interception(struct vcpu_svm
*svm
,
1884 struct kvm_run
*kvm_run
)
1886 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1890 static int task_switch_interception(struct vcpu_svm
*svm
,
1891 struct kvm_run
*kvm_run
)
1895 int int_type
= svm
->vmcb
->control
.exit_int_info
&
1896 SVM_EXITINTINFO_TYPE_MASK
;
1897 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
1899 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
1901 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
1903 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
1905 if (svm
->vmcb
->control
.exit_info_2
&
1906 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
1907 reason
= TASK_SWITCH_IRET
;
1908 else if (svm
->vmcb
->control
.exit_info_2
&
1909 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
1910 reason
= TASK_SWITCH_JMP
;
1912 reason
= TASK_SWITCH_GATE
;
1914 reason
= TASK_SWITCH_CALL
;
1916 if (reason
== TASK_SWITCH_GATE
) {
1918 case SVM_EXITINTINFO_TYPE_NMI
:
1919 svm
->vcpu
.arch
.nmi_injected
= false;
1921 case SVM_EXITINTINFO_TYPE_EXEPT
:
1922 kvm_clear_exception_queue(&svm
->vcpu
);
1924 case SVM_EXITINTINFO_TYPE_INTR
:
1925 kvm_clear_interrupt_queue(&svm
->vcpu
);
1932 if (reason
!= TASK_SWITCH_GATE
||
1933 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
1934 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
1935 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
1936 skip_emulated_instruction(&svm
->vcpu
);
1938 return kvm_task_switch(&svm
->vcpu
, tss_selector
, reason
);
1941 static int cpuid_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1943 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
1944 kvm_emulate_cpuid(&svm
->vcpu
);
1948 static int iret_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1950 ++svm
->vcpu
.stat
.nmi_window_exits
;
1951 svm
->vmcb
->control
.intercept
&= ~(1UL << INTERCEPT_IRET
);
1952 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
1956 static int invlpg_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1958 if (emulate_instruction(&svm
->vcpu
, kvm_run
, 0, 0, 0) != EMULATE_DONE
)
1959 pr_unimpl(&svm
->vcpu
, "%s: failed\n", __func__
);
1963 static int emulate_on_interception(struct vcpu_svm
*svm
,
1964 struct kvm_run
*kvm_run
)
1966 if (emulate_instruction(&svm
->vcpu
, NULL
, 0, 0, 0) != EMULATE_DONE
)
1967 pr_unimpl(&svm
->vcpu
, "%s: failed\n", __func__
);
1971 static int cr8_write_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1973 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
1974 /* instruction emulation calls kvm_set_cr8() */
1975 emulate_instruction(&svm
->vcpu
, NULL
, 0, 0, 0);
1976 if (irqchip_in_kernel(svm
->vcpu
.kvm
)) {
1977 svm
->vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR8_MASK
;
1980 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
1982 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
1986 static int svm_get_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64
*data
)
1988 struct vcpu_svm
*svm
= to_svm(vcpu
);
1991 case MSR_IA32_TSC
: {
1995 *data
= svm
->vmcb
->control
.tsc_offset
+ tsc
;
1999 *data
= svm
->vmcb
->save
.star
;
2001 #ifdef CONFIG_X86_64
2003 *data
= svm
->vmcb
->save
.lstar
;
2006 *data
= svm
->vmcb
->save
.cstar
;
2008 case MSR_KERNEL_GS_BASE
:
2009 *data
= svm
->vmcb
->save
.kernel_gs_base
;
2011 case MSR_SYSCALL_MASK
:
2012 *data
= svm
->vmcb
->save
.sfmask
;
2015 case MSR_IA32_SYSENTER_CS
:
2016 *data
= svm
->vmcb
->save
.sysenter_cs
;
2018 case MSR_IA32_SYSENTER_EIP
:
2019 *data
= svm
->sysenter_eip
;
2021 case MSR_IA32_SYSENTER_ESP
:
2022 *data
= svm
->sysenter_esp
;
2024 /* Nobody will change the following 5 values in the VMCB so
2025 we can safely return them on rdmsr. They will always be 0
2026 until LBRV is implemented. */
2027 case MSR_IA32_DEBUGCTLMSR
:
2028 *data
= svm
->vmcb
->save
.dbgctl
;
2030 case MSR_IA32_LASTBRANCHFROMIP
:
2031 *data
= svm
->vmcb
->save
.br_from
;
2033 case MSR_IA32_LASTBRANCHTOIP
:
2034 *data
= svm
->vmcb
->save
.br_to
;
2036 case MSR_IA32_LASTINTFROMIP
:
2037 *data
= svm
->vmcb
->save
.last_excp_from
;
2039 case MSR_IA32_LASTINTTOIP
:
2040 *data
= svm
->vmcb
->save
.last_excp_to
;
2042 case MSR_VM_HSAVE_PA
:
2043 *data
= svm
->hsave_msr
;
2048 case MSR_IA32_UCODE_REV
:
2052 return kvm_get_msr_common(vcpu
, ecx
, data
);
2057 static int rdmsr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
2059 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2062 if (svm_get_msr(&svm
->vcpu
, ecx
, &data
))
2063 kvm_inject_gp(&svm
->vcpu
, 0);
2065 KVMTRACE_3D(MSR_READ
, &svm
->vcpu
, ecx
, (u32
)data
,
2066 (u32
)(data
>> 32), handler
);
2068 svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] = data
& 0xffffffff;
2069 svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = data
>> 32;
2070 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2071 skip_emulated_instruction(&svm
->vcpu
);
2076 static int svm_set_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64 data
)
2078 struct vcpu_svm
*svm
= to_svm(vcpu
);
2081 case MSR_IA32_TSC
: {
2085 svm
->vmcb
->control
.tsc_offset
= data
- tsc
;
2089 svm
->vmcb
->save
.star
= data
;
2091 #ifdef CONFIG_X86_64
2093 svm
->vmcb
->save
.lstar
= data
;
2096 svm
->vmcb
->save
.cstar
= data
;
2098 case MSR_KERNEL_GS_BASE
:
2099 svm
->vmcb
->save
.kernel_gs_base
= data
;
2101 case MSR_SYSCALL_MASK
:
2102 svm
->vmcb
->save
.sfmask
= data
;
2105 case MSR_IA32_SYSENTER_CS
:
2106 svm
->vmcb
->save
.sysenter_cs
= data
;
2108 case MSR_IA32_SYSENTER_EIP
:
2109 svm
->sysenter_eip
= data
;
2110 svm
->vmcb
->save
.sysenter_eip
= data
;
2112 case MSR_IA32_SYSENTER_ESP
:
2113 svm
->sysenter_esp
= data
;
2114 svm
->vmcb
->save
.sysenter_esp
= data
;
2116 case MSR_IA32_DEBUGCTLMSR
:
2117 if (!svm_has(SVM_FEATURE_LBRV
)) {
2118 pr_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2122 if (data
& DEBUGCTL_RESERVED_BITS
)
2125 svm
->vmcb
->save
.dbgctl
= data
;
2126 if (data
& (1ULL<<0))
2127 svm_enable_lbrv(svm
);
2129 svm_disable_lbrv(svm
);
2131 case MSR_VM_HSAVE_PA
:
2132 svm
->hsave_msr
= data
;
2135 return kvm_set_msr_common(vcpu
, ecx
, data
);
2140 static int wrmsr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
2142 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2143 u64 data
= (svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] & -1u)
2144 | ((u64
)(svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2146 KVMTRACE_3D(MSR_WRITE
, &svm
->vcpu
, ecx
, (u32
)data
, (u32
)(data
>> 32),
2149 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2150 if (svm_set_msr(&svm
->vcpu
, ecx
, data
))
2151 kvm_inject_gp(&svm
->vcpu
, 0);
2153 skip_emulated_instruction(&svm
->vcpu
);
2157 static int msr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
2159 if (svm
->vmcb
->control
.exit_info_1
)
2160 return wrmsr_interception(svm
, kvm_run
);
2162 return rdmsr_interception(svm
, kvm_run
);
2165 static int interrupt_window_interception(struct vcpu_svm
*svm
,
2166 struct kvm_run
*kvm_run
)
2168 KVMTRACE_0D(PEND_INTR
, &svm
->vcpu
, handler
);
2170 svm_clear_vintr(svm
);
2171 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2173 * If the user space waits to inject interrupts, exit as soon as
2176 if (!irqchip_in_kernel(svm
->vcpu
.kvm
) &&
2177 kvm_run
->request_interrupt_window
&&
2178 !kvm_cpu_has_interrupt(&svm
->vcpu
)) {
2179 ++svm
->vcpu
.stat
.irq_window_exits
;
2180 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2187 static int (*svm_exit_handlers
[])(struct vcpu_svm
*svm
,
2188 struct kvm_run
*kvm_run
) = {
2189 [SVM_EXIT_READ_CR0
] = emulate_on_interception
,
2190 [SVM_EXIT_READ_CR3
] = emulate_on_interception
,
2191 [SVM_EXIT_READ_CR4
] = emulate_on_interception
,
2192 [SVM_EXIT_READ_CR8
] = emulate_on_interception
,
2194 [SVM_EXIT_WRITE_CR0
] = emulate_on_interception
,
2195 [SVM_EXIT_WRITE_CR3
] = emulate_on_interception
,
2196 [SVM_EXIT_WRITE_CR4
] = emulate_on_interception
,
2197 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
2198 [SVM_EXIT_READ_DR0
] = emulate_on_interception
,
2199 [SVM_EXIT_READ_DR1
] = emulate_on_interception
,
2200 [SVM_EXIT_READ_DR2
] = emulate_on_interception
,
2201 [SVM_EXIT_READ_DR3
] = emulate_on_interception
,
2202 [SVM_EXIT_WRITE_DR0
] = emulate_on_interception
,
2203 [SVM_EXIT_WRITE_DR1
] = emulate_on_interception
,
2204 [SVM_EXIT_WRITE_DR2
] = emulate_on_interception
,
2205 [SVM_EXIT_WRITE_DR3
] = emulate_on_interception
,
2206 [SVM_EXIT_WRITE_DR5
] = emulate_on_interception
,
2207 [SVM_EXIT_WRITE_DR7
] = emulate_on_interception
,
2208 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
2209 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
2210 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
2211 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
2212 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
2213 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
2214 [SVM_EXIT_INTR
] = intr_interception
,
2215 [SVM_EXIT_NMI
] = nmi_interception
,
2216 [SVM_EXIT_SMI
] = nop_on_interception
,
2217 [SVM_EXIT_INIT
] = nop_on_interception
,
2218 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
2219 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2220 [SVM_EXIT_CPUID
] = cpuid_interception
,
2221 [SVM_EXIT_IRET
] = iret_interception
,
2222 [SVM_EXIT_INVD
] = emulate_on_interception
,
2223 [SVM_EXIT_HLT
] = halt_interception
,
2224 [SVM_EXIT_INVLPG
] = invlpg_interception
,
2225 [SVM_EXIT_INVLPGA
] = invalid_op_interception
,
2226 [SVM_EXIT_IOIO
] = io_interception
,
2227 [SVM_EXIT_MSR
] = msr_interception
,
2228 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
2229 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
2230 [SVM_EXIT_VMRUN
] = vmrun_interception
,
2231 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
2232 [SVM_EXIT_VMLOAD
] = vmload_interception
,
2233 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
2234 [SVM_EXIT_STGI
] = stgi_interception
,
2235 [SVM_EXIT_CLGI
] = clgi_interception
,
2236 [SVM_EXIT_SKINIT
] = invalid_op_interception
,
2237 [SVM_EXIT_WBINVD
] = emulate_on_interception
,
2238 [SVM_EXIT_MONITOR
] = invalid_op_interception
,
2239 [SVM_EXIT_MWAIT
] = invalid_op_interception
,
2240 [SVM_EXIT_NPF
] = pf_interception
,
2243 static int handle_exit(struct kvm_run
*kvm_run
, struct kvm_vcpu
*vcpu
)
2245 struct vcpu_svm
*svm
= to_svm(vcpu
);
2246 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2248 KVMTRACE_3D(VMEXIT
, vcpu
, exit_code
, (u32
)svm
->vmcb
->save
.rip
,
2249 (u32
)((u64
)svm
->vmcb
->save
.rip
>> 32), entryexit
);
2251 if (is_nested(svm
)) {
2252 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2253 exit_code
, svm
->vmcb
->control
.exit_info_1
,
2254 svm
->vmcb
->control
.exit_info_2
, svm
->vmcb
->save
.rip
);
2255 if (nested_svm_exit_handled(svm
, true)) {
2256 nested_svm_vmexit(svm
);
2257 nsvm_printk("-> #VMEXIT\n");
2264 if ((vcpu
->arch
.cr0
^ svm
->vmcb
->save
.cr0
) & X86_CR0_PG
) {
2265 svm_set_cr0(vcpu
, svm
->vmcb
->save
.cr0
);
2268 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
2269 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
2271 kvm_mmu_reset_context(vcpu
);
2277 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
2278 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
2279 kvm_run
->fail_entry
.hardware_entry_failure_reason
2280 = svm
->vmcb
->control
.exit_code
;
2284 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
2285 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
2286 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
)
2287 printk(KERN_ERR
"%s: unexpected exit_ini_info 0x%x "
2289 __func__
, svm
->vmcb
->control
.exit_int_info
,
2292 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
2293 || !svm_exit_handlers
[exit_code
]) {
2294 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
2295 kvm_run
->hw
.hardware_exit_reason
= exit_code
;
2299 return svm_exit_handlers
[exit_code
](svm
, kvm_run
);
2302 static void reload_tss(struct kvm_vcpu
*vcpu
)
2304 int cpu
= raw_smp_processor_id();
2306 struct svm_cpu_data
*svm_data
= per_cpu(svm_data
, cpu
);
2307 svm_data
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
2311 static void pre_svm_run(struct vcpu_svm
*svm
)
2313 int cpu
= raw_smp_processor_id();
2315 struct svm_cpu_data
*svm_data
= per_cpu(svm_data
, cpu
);
2317 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
2318 /* FIXME: handle wraparound of asid_generation */
2319 if (svm
->asid_generation
!= svm_data
->asid_generation
)
2320 new_asid(svm
, svm_data
);
2323 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
2325 struct vcpu_svm
*svm
= to_svm(vcpu
);
2327 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
2328 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
2329 svm
->vmcb
->control
.intercept
|= (1UL << INTERCEPT_IRET
);
2330 ++vcpu
->stat
.nmi_injections
;
2333 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
2335 struct vmcb_control_area
*control
;
2337 KVMTRACE_1D(INJ_VIRQ
, &svm
->vcpu
, (u32
)irq
, handler
);
2339 ++svm
->vcpu
.stat
.irq_injections
;
2340 control
= &svm
->vmcb
->control
;
2341 control
->int_vector
= irq
;
2342 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
2343 control
->int_ctl
|= V_IRQ_MASK
|
2344 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
2347 static void svm_queue_irq(struct kvm_vcpu
*vcpu
, unsigned nr
)
2349 struct vcpu_svm
*svm
= to_svm(vcpu
);
2351 svm
->vmcb
->control
.event_inj
= nr
|
2352 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
2355 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
2357 struct vcpu_svm
*svm
= to_svm(vcpu
);
2359 nested_svm_intr(svm
);
2361 svm_queue_irq(vcpu
, vcpu
->arch
.interrupt
.nr
);
2364 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
2366 struct vcpu_svm
*svm
= to_svm(vcpu
);
2372 svm
->vmcb
->control
.intercept_cr_write
|= INTERCEPT_CR8_MASK
;
2375 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
2377 struct vcpu_svm
*svm
= to_svm(vcpu
);
2378 struct vmcb
*vmcb
= svm
->vmcb
;
2379 return !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
2380 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
2383 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
2385 struct vcpu_svm
*svm
= to_svm(vcpu
);
2386 struct vmcb
*vmcb
= svm
->vmcb
;
2387 return (vmcb
->save
.rflags
& X86_EFLAGS_IF
) &&
2388 !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
2389 (svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
2392 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
2394 svm_set_vintr(to_svm(vcpu
));
2395 svm_inject_irq(to_svm(vcpu
), 0x0);
2398 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
2400 struct vcpu_svm
*svm
= to_svm(vcpu
);
2402 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
2404 return; /* IRET will cause a vm exit */
2406 /* Something prevents NMI from been injected. Single step over
2407 possible problem (IRET or exception injection or interrupt
2409 vcpu
->arch
.singlestep
= true;
2410 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
2411 update_db_intercept(vcpu
);
2414 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
2419 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
2421 force_new_asid(vcpu
);
2424 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
2428 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
2430 struct vcpu_svm
*svm
= to_svm(vcpu
);
2432 if (!(svm
->vmcb
->control
.intercept_cr_write
& INTERCEPT_CR8_MASK
)) {
2433 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
2434 kvm_set_cr8(vcpu
, cr8
);
2438 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
2440 struct vcpu_svm
*svm
= to_svm(vcpu
);
2443 cr8
= kvm_get_cr8(vcpu
);
2444 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
2445 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
2448 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
2452 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
2454 if (svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
2455 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
2457 svm
->vcpu
.arch
.nmi_injected
= false;
2458 kvm_clear_exception_queue(&svm
->vcpu
);
2459 kvm_clear_interrupt_queue(&svm
->vcpu
);
2461 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
2464 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
2465 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
2468 case SVM_EXITINTINFO_TYPE_NMI
:
2469 svm
->vcpu
.arch
.nmi_injected
= true;
2471 case SVM_EXITINTINFO_TYPE_EXEPT
:
2472 /* In case of software exception do not reinject an exception
2473 vector, but re-execute and instruction instead */
2474 if (kvm_exception_is_soft(vector
))
2476 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
2477 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
2478 kvm_queue_exception_e(&svm
->vcpu
, vector
, err
);
2481 kvm_queue_exception(&svm
->vcpu
, vector
);
2483 case SVM_EXITINTINFO_TYPE_INTR
:
2484 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
2491 #ifdef CONFIG_X86_64
2497 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2499 struct vcpu_svm
*svm
= to_svm(vcpu
);
2504 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
2505 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
2506 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
2510 sync_lapic_to_cr8(vcpu
);
2512 save_host_msrs(vcpu
);
2513 fs_selector
= kvm_read_fs();
2514 gs_selector
= kvm_read_gs();
2515 ldt_selector
= kvm_read_ldt();
2516 if (!is_nested(svm
))
2517 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
2518 /* required for live migration with NPT */
2520 svm
->vmcb
->save
.cr3
= vcpu
->arch
.cr3
;
2527 "push %%"R
"bp; \n\t"
2528 "mov %c[rbx](%[svm]), %%"R
"bx \n\t"
2529 "mov %c[rcx](%[svm]), %%"R
"cx \n\t"
2530 "mov %c[rdx](%[svm]), %%"R
"dx \n\t"
2531 "mov %c[rsi](%[svm]), %%"R
"si \n\t"
2532 "mov %c[rdi](%[svm]), %%"R
"di \n\t"
2533 "mov %c[rbp](%[svm]), %%"R
"bp \n\t"
2534 #ifdef CONFIG_X86_64
2535 "mov %c[r8](%[svm]), %%r8 \n\t"
2536 "mov %c[r9](%[svm]), %%r9 \n\t"
2537 "mov %c[r10](%[svm]), %%r10 \n\t"
2538 "mov %c[r11](%[svm]), %%r11 \n\t"
2539 "mov %c[r12](%[svm]), %%r12 \n\t"
2540 "mov %c[r13](%[svm]), %%r13 \n\t"
2541 "mov %c[r14](%[svm]), %%r14 \n\t"
2542 "mov %c[r15](%[svm]), %%r15 \n\t"
2545 /* Enter guest mode */
2547 "mov %c[vmcb](%[svm]), %%"R
"ax \n\t"
2548 __ex(SVM_VMLOAD
) "\n\t"
2549 __ex(SVM_VMRUN
) "\n\t"
2550 __ex(SVM_VMSAVE
) "\n\t"
2553 /* Save guest registers, load host registers */
2554 "mov %%"R
"bx, %c[rbx](%[svm]) \n\t"
2555 "mov %%"R
"cx, %c[rcx](%[svm]) \n\t"
2556 "mov %%"R
"dx, %c[rdx](%[svm]) \n\t"
2557 "mov %%"R
"si, %c[rsi](%[svm]) \n\t"
2558 "mov %%"R
"di, %c[rdi](%[svm]) \n\t"
2559 "mov %%"R
"bp, %c[rbp](%[svm]) \n\t"
2560 #ifdef CONFIG_X86_64
2561 "mov %%r8, %c[r8](%[svm]) \n\t"
2562 "mov %%r9, %c[r9](%[svm]) \n\t"
2563 "mov %%r10, %c[r10](%[svm]) \n\t"
2564 "mov %%r11, %c[r11](%[svm]) \n\t"
2565 "mov %%r12, %c[r12](%[svm]) \n\t"
2566 "mov %%r13, %c[r13](%[svm]) \n\t"
2567 "mov %%r14, %c[r14](%[svm]) \n\t"
2568 "mov %%r15, %c[r15](%[svm]) \n\t"
2573 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
2574 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
2575 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
2576 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
2577 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
2578 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
2579 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
2580 #ifdef CONFIG_X86_64
2581 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
2582 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
2583 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
2584 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
2585 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
2586 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
2587 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
2588 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
2591 , R
"bx", R
"cx", R
"dx", R
"si", R
"di"
2592 #ifdef CONFIG_X86_64
2593 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2597 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
2598 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
2599 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
2600 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
2602 kvm_load_fs(fs_selector
);
2603 kvm_load_gs(gs_selector
);
2604 kvm_load_ldt(ldt_selector
);
2605 load_host_msrs(vcpu
);
2609 local_irq_disable();
2613 sync_cr8_to_lapic(vcpu
);
2618 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
2619 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
2622 svm_complete_interrupts(svm
);
2627 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
2629 struct vcpu_svm
*svm
= to_svm(vcpu
);
2632 svm
->vmcb
->control
.nested_cr3
= root
;
2633 force_new_asid(vcpu
);
2637 svm
->vmcb
->save
.cr3
= root
;
2638 force_new_asid(vcpu
);
2640 if (vcpu
->fpu_active
) {
2641 svm
->vmcb
->control
.intercept_exceptions
|= (1 << NM_VECTOR
);
2642 svm
->vmcb
->save
.cr0
|= X86_CR0_TS
;
2643 vcpu
->fpu_active
= 0;
2647 static int is_disabled(void)
2651 rdmsrl(MSR_VM_CR
, vm_cr
);
2652 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
2659 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
2662 * Patch in the VMMCALL instruction:
2664 hypercall
[0] = 0x0f;
2665 hypercall
[1] = 0x01;
2666 hypercall
[2] = 0xd9;
2669 static void svm_check_processor_compat(void *rtn
)
2674 static bool svm_cpu_has_accelerated_tpr(void)
2679 static int get_npt_level(void)
2681 #ifdef CONFIG_X86_64
2682 return PT64_ROOT_LEVEL
;
2684 return PT32E_ROOT_LEVEL
;
2688 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
2693 static struct kvm_x86_ops svm_x86_ops
= {
2694 .cpu_has_kvm_support
= has_svm
,
2695 .disabled_by_bios
= is_disabled
,
2696 .hardware_setup
= svm_hardware_setup
,
2697 .hardware_unsetup
= svm_hardware_unsetup
,
2698 .check_processor_compatibility
= svm_check_processor_compat
,
2699 .hardware_enable
= svm_hardware_enable
,
2700 .hardware_disable
= svm_hardware_disable
,
2701 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
2703 .vcpu_create
= svm_create_vcpu
,
2704 .vcpu_free
= svm_free_vcpu
,
2705 .vcpu_reset
= svm_vcpu_reset
,
2707 .prepare_guest_switch
= svm_prepare_guest_switch
,
2708 .vcpu_load
= svm_vcpu_load
,
2709 .vcpu_put
= svm_vcpu_put
,
2711 .set_guest_debug
= svm_guest_debug
,
2712 .get_msr
= svm_get_msr
,
2713 .set_msr
= svm_set_msr
,
2714 .get_segment_base
= svm_get_segment_base
,
2715 .get_segment
= svm_get_segment
,
2716 .set_segment
= svm_set_segment
,
2717 .get_cpl
= svm_get_cpl
,
2718 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
2719 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
2720 .set_cr0
= svm_set_cr0
,
2721 .set_cr3
= svm_set_cr3
,
2722 .set_cr4
= svm_set_cr4
,
2723 .set_efer
= svm_set_efer
,
2724 .get_idt
= svm_get_idt
,
2725 .set_idt
= svm_set_idt
,
2726 .get_gdt
= svm_get_gdt
,
2727 .set_gdt
= svm_set_gdt
,
2728 .get_dr
= svm_get_dr
,
2729 .set_dr
= svm_set_dr
,
2730 .cache_reg
= svm_cache_reg
,
2731 .get_rflags
= svm_get_rflags
,
2732 .set_rflags
= svm_set_rflags
,
2734 .tlb_flush
= svm_flush_tlb
,
2736 .run
= svm_vcpu_run
,
2737 .handle_exit
= handle_exit
,
2738 .skip_emulated_instruction
= skip_emulated_instruction
,
2739 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
2740 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
2741 .patch_hypercall
= svm_patch_hypercall
,
2742 .set_irq
= svm_set_irq
,
2743 .set_nmi
= svm_inject_nmi
,
2744 .queue_exception
= svm_queue_exception
,
2745 .interrupt_allowed
= svm_interrupt_allowed
,
2746 .nmi_allowed
= svm_nmi_allowed
,
2747 .enable_nmi_window
= enable_nmi_window
,
2748 .enable_irq_window
= enable_irq_window
,
2749 .update_cr8_intercept
= update_cr8_intercept
,
2751 .set_tss_addr
= svm_set_tss_addr
,
2752 .get_tdp_level
= get_npt_level
,
2753 .get_mt_mask
= svm_get_mt_mask
,
2756 static int __init
svm_init(void)
2758 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
2762 static void __exit
svm_exit(void)
2767 module_init(svm_init
)
2768 module_exit(svm_exit
)