2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
);
41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
51 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
);
52 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
54 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
55 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
56 struct drm_i915_gem_pwrite
*args
,
57 struct drm_file
*file_priv
);
58 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
60 static LIST_HEAD(shrink_list
);
61 static DEFINE_SPINLOCK(shrink_list_lock
);
64 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj_priv
)
66 return obj_priv
->gtt_space
&&
68 obj_priv
->pin_count
== 0;
71 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
74 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
77 (start
& (PAGE_SIZE
- 1)) != 0 ||
78 (end
& (PAGE_SIZE
- 1)) != 0) {
82 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
85 dev
->gtt_total
= (uint32_t) (end
- start
);
91 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
92 struct drm_file
*file_priv
)
94 struct drm_i915_gem_init
*args
= data
;
97 mutex_lock(&dev
->struct_mutex
);
98 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
99 mutex_unlock(&dev
->struct_mutex
);
105 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
106 struct drm_file
*file_priv
)
108 struct drm_i915_gem_get_aperture
*args
= data
;
110 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
113 args
->aper_size
= dev
->gtt_total
;
114 args
->aper_available_size
= (args
->aper_size
-
115 atomic_read(&dev
->pin_memory
));
122 * Creates a new mm object and returns a handle to it.
125 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
126 struct drm_file
*file_priv
)
128 struct drm_i915_gem_create
*args
= data
;
129 struct drm_gem_object
*obj
;
133 args
->size
= roundup(args
->size
, PAGE_SIZE
);
135 /* Allocate the new object */
136 obj
= i915_gem_alloc_object(dev
, args
->size
);
140 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
142 drm_gem_object_unreference_unlocked(obj
);
146 /* Sink the floating reference from kref_init(handlecount) */
147 drm_gem_object_handle_unreference_unlocked(obj
);
149 args
->handle
= handle
;
154 fast_shmem_read(struct page
**pages
,
155 loff_t page_base
, int page_offset
,
162 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
165 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
166 kunmap_atomic(vaddr
, KM_USER0
);
174 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
176 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
177 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
179 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
180 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
184 slow_shmem_copy(struct page
*dst_page
,
186 struct page
*src_page
,
190 char *dst_vaddr
, *src_vaddr
;
192 dst_vaddr
= kmap(dst_page
);
193 src_vaddr
= kmap(src_page
);
195 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
202 slow_shmem_bit17_copy(struct page
*gpu_page
,
204 struct page
*cpu_page
,
209 char *gpu_vaddr
, *cpu_vaddr
;
211 /* Use the unswizzled path if this page isn't affected. */
212 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
214 return slow_shmem_copy(cpu_page
, cpu_offset
,
215 gpu_page
, gpu_offset
, length
);
217 return slow_shmem_copy(gpu_page
, gpu_offset
,
218 cpu_page
, cpu_offset
, length
);
221 gpu_vaddr
= kmap(gpu_page
);
222 cpu_vaddr
= kmap(cpu_page
);
224 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
225 * XORing with the other bits (A9 for Y, A9 and A10 for X)
228 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
229 int this_length
= min(cacheline_end
- gpu_offset
, length
);
230 int swizzled_gpu_offset
= gpu_offset
^ 64;
233 memcpy(cpu_vaddr
+ cpu_offset
,
234 gpu_vaddr
+ swizzled_gpu_offset
,
237 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
238 cpu_vaddr
+ cpu_offset
,
241 cpu_offset
+= this_length
;
242 gpu_offset
+= this_length
;
243 length
-= this_length
;
251 * This is the fast shmem pread path, which attempts to copy_from_user directly
252 * from the backing pages of the object to the user's address space. On a
253 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
256 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
257 struct drm_i915_gem_pread
*args
,
258 struct drm_file
*file_priv
)
260 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
262 loff_t offset
, page_base
;
263 char __user
*user_data
;
264 int page_offset
, page_length
;
267 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
270 mutex_lock(&dev
->struct_mutex
);
272 ret
= i915_gem_object_get_pages(obj
, 0);
276 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
281 obj_priv
= to_intel_bo(obj
);
282 offset
= args
->offset
;
285 /* Operation in this page
287 * page_base = page offset within aperture
288 * page_offset = offset within page
289 * page_length = bytes to copy for this page
291 page_base
= (offset
& ~(PAGE_SIZE
-1));
292 page_offset
= offset
& (PAGE_SIZE
-1);
293 page_length
= remain
;
294 if ((page_offset
+ remain
) > PAGE_SIZE
)
295 page_length
= PAGE_SIZE
- page_offset
;
297 ret
= fast_shmem_read(obj_priv
->pages
,
298 page_base
, page_offset
,
299 user_data
, page_length
);
303 remain
-= page_length
;
304 user_data
+= page_length
;
305 offset
+= page_length
;
309 i915_gem_object_put_pages(obj
);
311 mutex_unlock(&dev
->struct_mutex
);
317 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
321 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
323 /* If we've insufficient memory to map in the pages, attempt
324 * to make some space by throwing out some old buffers.
326 if (ret
== -ENOMEM
) {
327 struct drm_device
*dev
= obj
->dev
;
329 ret
= i915_gem_evict_something(dev
, obj
->size
,
330 i915_gem_get_gtt_alignment(obj
));
334 ret
= i915_gem_object_get_pages(obj
, 0);
341 * This is the fallback shmem pread path, which allocates temporary storage
342 * in kernel space to copy_to_user into outside of the struct_mutex, so we
343 * can copy out of the object's backing pages while holding the struct mutex
344 * and not take page faults.
347 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
348 struct drm_i915_gem_pread
*args
,
349 struct drm_file
*file_priv
)
351 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
352 struct mm_struct
*mm
= current
->mm
;
353 struct page
**user_pages
;
355 loff_t offset
, pinned_pages
, i
;
356 loff_t first_data_page
, last_data_page
, num_pages
;
357 int shmem_page_index
, shmem_page_offset
;
358 int data_page_index
, data_page_offset
;
361 uint64_t data_ptr
= args
->data_ptr
;
362 int do_bit17_swizzling
;
366 /* Pin the user pages containing the data. We can't fault while
367 * holding the struct mutex, yet we want to hold it while
368 * dereferencing the user data.
370 first_data_page
= data_ptr
/ PAGE_SIZE
;
371 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
372 num_pages
= last_data_page
- first_data_page
+ 1;
374 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
375 if (user_pages
== NULL
)
378 down_read(&mm
->mmap_sem
);
379 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
380 num_pages
, 1, 0, user_pages
, NULL
);
381 up_read(&mm
->mmap_sem
);
382 if (pinned_pages
< num_pages
) {
384 goto fail_put_user_pages
;
387 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
389 mutex_lock(&dev
->struct_mutex
);
391 ret
= i915_gem_object_get_pages_or_evict(obj
);
395 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
400 obj_priv
= to_intel_bo(obj
);
401 offset
= args
->offset
;
404 /* Operation in this page
406 * shmem_page_index = page number within shmem file
407 * shmem_page_offset = offset within page in shmem file
408 * data_page_index = page number in get_user_pages return
409 * data_page_offset = offset with data_page_index page.
410 * page_length = bytes to copy for this page
412 shmem_page_index
= offset
/ PAGE_SIZE
;
413 shmem_page_offset
= offset
& ~PAGE_MASK
;
414 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
415 data_page_offset
= data_ptr
& ~PAGE_MASK
;
417 page_length
= remain
;
418 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
419 page_length
= PAGE_SIZE
- shmem_page_offset
;
420 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
421 page_length
= PAGE_SIZE
- data_page_offset
;
423 if (do_bit17_swizzling
) {
424 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
426 user_pages
[data_page_index
],
431 slow_shmem_copy(user_pages
[data_page_index
],
433 obj_priv
->pages
[shmem_page_index
],
438 remain
-= page_length
;
439 data_ptr
+= page_length
;
440 offset
+= page_length
;
444 i915_gem_object_put_pages(obj
);
446 mutex_unlock(&dev
->struct_mutex
);
448 for (i
= 0; i
< pinned_pages
; i
++) {
449 SetPageDirty(user_pages
[i
]);
450 page_cache_release(user_pages
[i
]);
452 drm_free_large(user_pages
);
458 * Reads data from the object referenced by handle.
460 * On error, the contents of *data are undefined.
463 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
464 struct drm_file
*file_priv
)
466 struct drm_i915_gem_pread
*args
= data
;
467 struct drm_gem_object
*obj
;
468 struct drm_i915_gem_object
*obj_priv
;
471 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
474 obj_priv
= to_intel_bo(obj
);
476 /* Bounds check source.
478 * XXX: This could use review for overflow issues...
480 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
481 args
->offset
+ args
->size
> obj
->size
) {
482 drm_gem_object_unreference_unlocked(obj
);
486 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
487 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
489 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
491 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
495 drm_gem_object_unreference_unlocked(obj
);
500 /* This is the fast write path which cannot handle
501 * page faults in the source data
505 fast_user_write(struct io_mapping
*mapping
,
506 loff_t page_base
, int page_offset
,
507 char __user
*user_data
,
511 unsigned long unwritten
;
513 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
, KM_USER0
);
514 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
516 io_mapping_unmap_atomic(vaddr_atomic
, KM_USER0
);
522 /* Here's the write path which can sleep for
527 slow_kernel_write(struct io_mapping
*mapping
,
528 loff_t gtt_base
, int gtt_offset
,
529 struct page
*user_page
, int user_offset
,
532 char __iomem
*dst_vaddr
;
535 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
536 src_vaddr
= kmap(user_page
);
538 memcpy_toio(dst_vaddr
+ gtt_offset
,
539 src_vaddr
+ user_offset
,
543 io_mapping_unmap(dst_vaddr
);
547 fast_shmem_write(struct page
**pages
,
548 loff_t page_base
, int page_offset
,
553 unsigned long unwritten
;
555 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
558 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
559 kunmap_atomic(vaddr
, KM_USER0
);
567 * This is the fast pwrite path, where we copy the data directly from the
568 * user into the GTT, uncached.
571 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
572 struct drm_i915_gem_pwrite
*args
,
573 struct drm_file
*file_priv
)
575 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
576 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
578 loff_t offset
, page_base
;
579 char __user
*user_data
;
580 int page_offset
, page_length
;
583 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
585 if (!access_ok(VERIFY_READ
, user_data
, remain
))
589 mutex_lock(&dev
->struct_mutex
);
590 ret
= i915_gem_object_pin(obj
, 0);
592 mutex_unlock(&dev
->struct_mutex
);
595 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
599 obj_priv
= to_intel_bo(obj
);
600 offset
= obj_priv
->gtt_offset
+ args
->offset
;
603 /* Operation in this page
605 * page_base = page offset within aperture
606 * page_offset = offset within page
607 * page_length = bytes to copy for this page
609 page_base
= (offset
& ~(PAGE_SIZE
-1));
610 page_offset
= offset
& (PAGE_SIZE
-1);
611 page_length
= remain
;
612 if ((page_offset
+ remain
) > PAGE_SIZE
)
613 page_length
= PAGE_SIZE
- page_offset
;
615 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
616 page_offset
, user_data
, page_length
);
618 /* If we get a fault while copying data, then (presumably) our
619 * source page isn't available. Return the error and we'll
620 * retry in the slow path.
625 remain
-= page_length
;
626 user_data
+= page_length
;
627 offset
+= page_length
;
631 i915_gem_object_unpin(obj
);
632 mutex_unlock(&dev
->struct_mutex
);
638 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
639 * the memory and maps it using kmap_atomic for copying.
641 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
642 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
645 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
646 struct drm_i915_gem_pwrite
*args
,
647 struct drm_file
*file_priv
)
649 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
650 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
652 loff_t gtt_page_base
, offset
;
653 loff_t first_data_page
, last_data_page
, num_pages
;
654 loff_t pinned_pages
, i
;
655 struct page
**user_pages
;
656 struct mm_struct
*mm
= current
->mm
;
657 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
659 uint64_t data_ptr
= args
->data_ptr
;
663 /* Pin the user pages containing the data. We can't fault while
664 * holding the struct mutex, and all of the pwrite implementations
665 * want to hold it while dereferencing the user data.
667 first_data_page
= data_ptr
/ PAGE_SIZE
;
668 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
669 num_pages
= last_data_page
- first_data_page
+ 1;
671 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
672 if (user_pages
== NULL
)
675 down_read(&mm
->mmap_sem
);
676 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
677 num_pages
, 0, 0, user_pages
, NULL
);
678 up_read(&mm
->mmap_sem
);
679 if (pinned_pages
< num_pages
) {
681 goto out_unpin_pages
;
684 mutex_lock(&dev
->struct_mutex
);
685 ret
= i915_gem_object_pin(obj
, 0);
689 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
691 goto out_unpin_object
;
693 obj_priv
= to_intel_bo(obj
);
694 offset
= obj_priv
->gtt_offset
+ args
->offset
;
697 /* Operation in this page
699 * gtt_page_base = page offset within aperture
700 * gtt_page_offset = offset within page in aperture
701 * data_page_index = page number in get_user_pages return
702 * data_page_offset = offset with data_page_index page.
703 * page_length = bytes to copy for this page
705 gtt_page_base
= offset
& PAGE_MASK
;
706 gtt_page_offset
= offset
& ~PAGE_MASK
;
707 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
708 data_page_offset
= data_ptr
& ~PAGE_MASK
;
710 page_length
= remain
;
711 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
712 page_length
= PAGE_SIZE
- gtt_page_offset
;
713 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
714 page_length
= PAGE_SIZE
- data_page_offset
;
716 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
717 gtt_page_base
, gtt_page_offset
,
718 user_pages
[data_page_index
],
722 remain
-= page_length
;
723 offset
+= page_length
;
724 data_ptr
+= page_length
;
728 i915_gem_object_unpin(obj
);
730 mutex_unlock(&dev
->struct_mutex
);
732 for (i
= 0; i
< pinned_pages
; i
++)
733 page_cache_release(user_pages
[i
]);
734 drm_free_large(user_pages
);
740 * This is the fast shmem pwrite path, which attempts to directly
741 * copy_from_user into the kmapped pages backing the object.
744 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
745 struct drm_i915_gem_pwrite
*args
,
746 struct drm_file
*file_priv
)
748 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
750 loff_t offset
, page_base
;
751 char __user
*user_data
;
752 int page_offset
, page_length
;
755 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
758 mutex_lock(&dev
->struct_mutex
);
760 ret
= i915_gem_object_get_pages(obj
, 0);
764 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
768 obj_priv
= to_intel_bo(obj
);
769 offset
= args
->offset
;
773 /* Operation in this page
775 * page_base = page offset within aperture
776 * page_offset = offset within page
777 * page_length = bytes to copy for this page
779 page_base
= (offset
& ~(PAGE_SIZE
-1));
780 page_offset
= offset
& (PAGE_SIZE
-1);
781 page_length
= remain
;
782 if ((page_offset
+ remain
) > PAGE_SIZE
)
783 page_length
= PAGE_SIZE
- page_offset
;
785 ret
= fast_shmem_write(obj_priv
->pages
,
786 page_base
, page_offset
,
787 user_data
, page_length
);
791 remain
-= page_length
;
792 user_data
+= page_length
;
793 offset
+= page_length
;
797 i915_gem_object_put_pages(obj
);
799 mutex_unlock(&dev
->struct_mutex
);
805 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
806 * the memory and maps it using kmap_atomic for copying.
808 * This avoids taking mmap_sem for faulting on the user's address while the
809 * struct_mutex is held.
812 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
813 struct drm_i915_gem_pwrite
*args
,
814 struct drm_file
*file_priv
)
816 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
817 struct mm_struct
*mm
= current
->mm
;
818 struct page
**user_pages
;
820 loff_t offset
, pinned_pages
, i
;
821 loff_t first_data_page
, last_data_page
, num_pages
;
822 int shmem_page_index
, shmem_page_offset
;
823 int data_page_index
, data_page_offset
;
826 uint64_t data_ptr
= args
->data_ptr
;
827 int do_bit17_swizzling
;
831 /* Pin the user pages containing the data. We can't fault while
832 * holding the struct mutex, and all of the pwrite implementations
833 * want to hold it while dereferencing the user data.
835 first_data_page
= data_ptr
/ PAGE_SIZE
;
836 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
837 num_pages
= last_data_page
- first_data_page
+ 1;
839 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
840 if (user_pages
== NULL
)
843 down_read(&mm
->mmap_sem
);
844 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
845 num_pages
, 0, 0, user_pages
, NULL
);
846 up_read(&mm
->mmap_sem
);
847 if (pinned_pages
< num_pages
) {
849 goto fail_put_user_pages
;
852 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
854 mutex_lock(&dev
->struct_mutex
);
856 ret
= i915_gem_object_get_pages_or_evict(obj
);
860 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
864 obj_priv
= to_intel_bo(obj
);
865 offset
= args
->offset
;
869 /* Operation in this page
871 * shmem_page_index = page number within shmem file
872 * shmem_page_offset = offset within page in shmem file
873 * data_page_index = page number in get_user_pages return
874 * data_page_offset = offset with data_page_index page.
875 * page_length = bytes to copy for this page
877 shmem_page_index
= offset
/ PAGE_SIZE
;
878 shmem_page_offset
= offset
& ~PAGE_MASK
;
879 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
880 data_page_offset
= data_ptr
& ~PAGE_MASK
;
882 page_length
= remain
;
883 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
884 page_length
= PAGE_SIZE
- shmem_page_offset
;
885 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
886 page_length
= PAGE_SIZE
- data_page_offset
;
888 if (do_bit17_swizzling
) {
889 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
891 user_pages
[data_page_index
],
896 slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
898 user_pages
[data_page_index
],
903 remain
-= page_length
;
904 data_ptr
+= page_length
;
905 offset
+= page_length
;
909 i915_gem_object_put_pages(obj
);
911 mutex_unlock(&dev
->struct_mutex
);
913 for (i
= 0; i
< pinned_pages
; i
++)
914 page_cache_release(user_pages
[i
]);
915 drm_free_large(user_pages
);
921 * Writes data to the object referenced by handle.
923 * On error, the contents of the buffer that were to be modified are undefined.
926 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
927 struct drm_file
*file_priv
)
929 struct drm_i915_gem_pwrite
*args
= data
;
930 struct drm_gem_object
*obj
;
931 struct drm_i915_gem_object
*obj_priv
;
934 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
937 obj_priv
= to_intel_bo(obj
);
939 /* Bounds check destination.
941 * XXX: This could use review for overflow issues...
943 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
944 args
->offset
+ args
->size
> obj
->size
) {
945 drm_gem_object_unreference_unlocked(obj
);
949 /* We can only do the GTT pwrite on untiled buffers, as otherwise
950 * it would end up going through the fenced access, and we'll get
951 * different detiling behavior between reading and writing.
952 * pread/pwrite currently are reading and writing from the CPU
953 * perspective, requiring manual detiling by the client.
955 if (obj_priv
->phys_obj
)
956 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
957 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
958 dev
->gtt_total
!= 0 &&
959 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
960 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
961 if (ret
== -EFAULT
) {
962 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
965 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
966 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
968 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
969 if (ret
== -EFAULT
) {
970 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
977 DRM_INFO("pwrite failed %d\n", ret
);
980 drm_gem_object_unreference_unlocked(obj
);
986 * Called when user space prepares to use an object with the CPU, either
987 * through the mmap ioctl's mapping or a GTT mapping.
990 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
991 struct drm_file
*file_priv
)
993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
994 struct drm_i915_gem_set_domain
*args
= data
;
995 struct drm_gem_object
*obj
;
996 struct drm_i915_gem_object
*obj_priv
;
997 uint32_t read_domains
= args
->read_domains
;
998 uint32_t write_domain
= args
->write_domain
;
1001 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1004 /* Only handle setting domains to types used by the CPU. */
1005 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1008 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1011 /* Having something in the write domain implies it's in the read
1012 * domain, and only that read domain. Enforce that in the request.
1014 if (write_domain
!= 0 && read_domains
!= write_domain
)
1017 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1020 obj_priv
= to_intel_bo(obj
);
1022 mutex_lock(&dev
->struct_mutex
);
1024 intel_mark_busy(dev
, obj
);
1027 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1028 obj
, obj
->size
, read_domains
, write_domain
);
1030 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1031 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1033 /* Update the LRU on the fence for the CPU access that's
1036 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1037 struct drm_i915_fence_reg
*reg
=
1038 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1039 list_move_tail(®
->lru_list
,
1040 &dev_priv
->mm
.fence_list
);
1043 /* Silently promote "you're not bound, there was nothing to do"
1044 * to success, since the client was just asking us to
1045 * make sure everything was done.
1050 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1054 /* Maintain LRU order of "inactive" objects */
1055 if (ret
== 0 && i915_gem_object_is_inactive(obj_priv
))
1056 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1058 drm_gem_object_unreference(obj
);
1059 mutex_unlock(&dev
->struct_mutex
);
1064 * Called when user space has done writes to this buffer
1067 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1068 struct drm_file
*file_priv
)
1070 struct drm_i915_gem_sw_finish
*args
= data
;
1071 struct drm_gem_object
*obj
;
1072 struct drm_i915_gem_object
*obj_priv
;
1075 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1078 mutex_lock(&dev
->struct_mutex
);
1079 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1081 mutex_unlock(&dev
->struct_mutex
);
1086 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1087 __func__
, args
->handle
, obj
, obj
->size
);
1089 obj_priv
= to_intel_bo(obj
);
1091 /* Pinned buffers may be scanout, so flush the cache */
1092 if (obj_priv
->pin_count
)
1093 i915_gem_object_flush_cpu_write_domain(obj
);
1095 drm_gem_object_unreference(obj
);
1096 mutex_unlock(&dev
->struct_mutex
);
1101 * Maps the contents of an object, returning the address it is mapped
1104 * While the mapping holds a reference on the contents of the object, it doesn't
1105 * imply a ref on the object itself.
1108 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1109 struct drm_file
*file_priv
)
1111 struct drm_i915_gem_mmap
*args
= data
;
1112 struct drm_gem_object
*obj
;
1116 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1119 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1123 offset
= args
->offset
;
1125 down_write(¤t
->mm
->mmap_sem
);
1126 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1127 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1129 up_write(¤t
->mm
->mmap_sem
);
1130 drm_gem_object_unreference_unlocked(obj
);
1131 if (IS_ERR((void *)addr
))
1134 args
->addr_ptr
= (uint64_t) addr
;
1140 * i915_gem_fault - fault a page into the GTT
1141 * vma: VMA in question
1144 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1145 * from userspace. The fault handler takes care of binding the object to
1146 * the GTT (if needed), allocating and programming a fence register (again,
1147 * only if needed based on whether the old reg is still valid or the object
1148 * is tiled) and inserting a new PTE into the faulting process.
1150 * Note that the faulting process may involve evicting existing objects
1151 * from the GTT and/or fence registers to make room. So performance may
1152 * suffer if the GTT working set is large or there are few fence registers
1155 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1157 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1158 struct drm_device
*dev
= obj
->dev
;
1159 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1160 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1161 pgoff_t page_offset
;
1164 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1166 /* We don't use vmf->pgoff since that has the fake offset */
1167 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1170 /* Now bind it into the GTT if needed */
1171 mutex_lock(&dev
->struct_mutex
);
1172 if (!obj_priv
->gtt_space
) {
1173 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1177 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1182 /* Need a new fence register? */
1183 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1184 ret
= i915_gem_object_get_fence_reg(obj
);
1189 if (i915_gem_object_is_inactive(obj_priv
))
1190 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1192 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1195 /* Finally, remap it using the new GTT offset */
1196 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1198 mutex_unlock(&dev
->struct_mutex
);
1203 return VM_FAULT_NOPAGE
;
1206 return VM_FAULT_OOM
;
1208 return VM_FAULT_SIGBUS
;
1213 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1214 * @obj: obj in question
1216 * GEM memory mapping works by handing back to userspace a fake mmap offset
1217 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1218 * up the object based on the offset and sets up the various memory mapping
1221 * This routine allocates and attaches a fake offset for @obj.
1224 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1226 struct drm_device
*dev
= obj
->dev
;
1227 struct drm_gem_mm
*mm
= dev
->mm_private
;
1228 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1229 struct drm_map_list
*list
;
1230 struct drm_local_map
*map
;
1233 /* Set the object up for mmap'ing */
1234 list
= &obj
->map_list
;
1235 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1240 map
->type
= _DRM_GEM
;
1241 map
->size
= obj
->size
;
1244 /* Get a DRM GEM mmap offset allocated... */
1245 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1246 obj
->size
/ PAGE_SIZE
, 0, 0);
1247 if (!list
->file_offset_node
) {
1248 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1253 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1254 obj
->size
/ PAGE_SIZE
, 0);
1255 if (!list
->file_offset_node
) {
1260 list
->hash
.key
= list
->file_offset_node
->start
;
1261 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
1262 DRM_ERROR("failed to add to map hash\n");
1267 /* By now we should be all set, any drm_mmap request on the offset
1268 * below will get to our mmap & fault handler */
1269 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1274 drm_mm_put_block(list
->file_offset_node
);
1282 * i915_gem_release_mmap - remove physical page mappings
1283 * @obj: obj in question
1285 * Preserve the reservation of the mmapping with the DRM core code, but
1286 * relinquish ownership of the pages back to the system.
1288 * It is vital that we remove the page mapping if we have mapped a tiled
1289 * object through the GTT and then lose the fence register due to
1290 * resource pressure. Similarly if the object has been moved out of the
1291 * aperture, than pages mapped into userspace must be revoked. Removing the
1292 * mapping will then trigger a page fault on the next user access, allowing
1293 * fixup by i915_gem_fault().
1296 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1298 struct drm_device
*dev
= obj
->dev
;
1299 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1301 if (dev
->dev_mapping
)
1302 unmap_mapping_range(dev
->dev_mapping
,
1303 obj_priv
->mmap_offset
, obj
->size
, 1);
1307 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1309 struct drm_device
*dev
= obj
->dev
;
1310 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1311 struct drm_gem_mm
*mm
= dev
->mm_private
;
1312 struct drm_map_list
*list
;
1314 list
= &obj
->map_list
;
1315 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1317 if (list
->file_offset_node
) {
1318 drm_mm_put_block(list
->file_offset_node
);
1319 list
->file_offset_node
= NULL
;
1327 obj_priv
->mmap_offset
= 0;
1331 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1332 * @obj: object to check
1334 * Return the required GTT alignment for an object, taking into account
1335 * potential fence register mapping if needed.
1338 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1340 struct drm_device
*dev
= obj
->dev
;
1341 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1345 * Minimum alignment is 4k (GTT page size), but might be greater
1346 * if a fence register is needed for the object.
1348 if (IS_I965G(dev
) || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1352 * Previous chips need to be aligned to the size of the smallest
1353 * fence register that can contain the object.
1360 for (i
= start
; i
< obj
->size
; i
<<= 1)
1367 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1369 * @data: GTT mapping ioctl data
1370 * @file_priv: GEM object info
1372 * Simply returns the fake offset to userspace so it can mmap it.
1373 * The mmap call will end up in drm_gem_mmap(), which will set things
1374 * up so we can get faults in the handler above.
1376 * The fault handler will take care of binding the object into the GTT
1377 * (since it may have been evicted to make room for something), allocating
1378 * a fence register, and mapping the appropriate aperture address into
1382 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1383 struct drm_file
*file_priv
)
1385 struct drm_i915_gem_mmap_gtt
*args
= data
;
1386 struct drm_gem_object
*obj
;
1387 struct drm_i915_gem_object
*obj_priv
;
1390 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1393 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1397 mutex_lock(&dev
->struct_mutex
);
1399 obj_priv
= to_intel_bo(obj
);
1401 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1402 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1403 drm_gem_object_unreference(obj
);
1404 mutex_unlock(&dev
->struct_mutex
);
1409 if (!obj_priv
->mmap_offset
) {
1410 ret
= i915_gem_create_mmap_offset(obj
);
1412 drm_gem_object_unreference(obj
);
1413 mutex_unlock(&dev
->struct_mutex
);
1418 args
->offset
= obj_priv
->mmap_offset
;
1421 * Pull it into the GTT so that we have a page list (makes the
1422 * initial fault faster and any subsequent flushing possible).
1424 if (!obj_priv
->agp_mem
) {
1425 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1427 drm_gem_object_unreference(obj
);
1428 mutex_unlock(&dev
->struct_mutex
);
1433 drm_gem_object_unreference(obj
);
1434 mutex_unlock(&dev
->struct_mutex
);
1440 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1442 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1443 int page_count
= obj
->size
/ PAGE_SIZE
;
1446 BUG_ON(obj_priv
->pages_refcount
== 0);
1447 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1449 if (--obj_priv
->pages_refcount
!= 0)
1452 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1453 i915_gem_object_save_bit_17_swizzle(obj
);
1455 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1456 obj_priv
->dirty
= 0;
1458 for (i
= 0; i
< page_count
; i
++) {
1459 if (obj_priv
->dirty
)
1460 set_page_dirty(obj_priv
->pages
[i
]);
1462 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1463 mark_page_accessed(obj_priv
->pages
[i
]);
1465 page_cache_release(obj_priv
->pages
[i
]);
1467 obj_priv
->dirty
= 0;
1469 drm_free_large(obj_priv
->pages
);
1470 obj_priv
->pages
= NULL
;
1474 i915_gem_next_request_seqno(struct drm_device
*dev
,
1475 struct intel_ring_buffer
*ring
)
1477 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1479 ring
->outstanding_lazy_request
= true;
1481 return dev_priv
->next_seqno
;
1485 i915_gem_object_move_to_active(struct drm_gem_object
*obj
,
1486 struct intel_ring_buffer
*ring
)
1488 struct drm_device
*dev
= obj
->dev
;
1489 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1490 uint32_t seqno
= i915_gem_next_request_seqno(dev
, ring
);
1492 BUG_ON(ring
== NULL
);
1493 obj_priv
->ring
= ring
;
1495 /* Add a reference if we're newly entering the active list. */
1496 if (!obj_priv
->active
) {
1497 drm_gem_object_reference(obj
);
1498 obj_priv
->active
= 1;
1501 /* Move from whatever list we were on to the tail of execution. */
1502 list_move_tail(&obj_priv
->list
, &ring
->active_list
);
1503 obj_priv
->last_rendering_seqno
= seqno
;
1507 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1509 struct drm_device
*dev
= obj
->dev
;
1510 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1511 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1513 BUG_ON(!obj_priv
->active
);
1514 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1515 obj_priv
->last_rendering_seqno
= 0;
1518 /* Immediately discard the backing storage */
1520 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1522 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1523 struct inode
*inode
;
1525 /* Our goal here is to return as much of the memory as
1526 * is possible back to the system as we are called from OOM.
1527 * To do this we must instruct the shmfs to drop all of its
1528 * backing pages, *now*. Here we mirror the actions taken
1529 * when by shmem_delete_inode() to release the backing store.
1531 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1532 truncate_inode_pages(inode
->i_mapping
, 0);
1533 if (inode
->i_op
->truncate_range
)
1534 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1536 obj_priv
->madv
= __I915_MADV_PURGED
;
1540 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1542 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1546 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1548 struct drm_device
*dev
= obj
->dev
;
1549 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1550 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1552 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1553 if (obj_priv
->pin_count
!= 0)
1554 list_del_init(&obj_priv
->list
);
1556 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1558 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1560 obj_priv
->last_rendering_seqno
= 0;
1561 obj_priv
->ring
= NULL
;
1562 if (obj_priv
->active
) {
1563 obj_priv
->active
= 0;
1564 drm_gem_object_unreference(obj
);
1566 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1570 i915_gem_process_flushing_list(struct drm_device
*dev
,
1571 uint32_t flush_domains
,
1572 struct intel_ring_buffer
*ring
)
1574 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1575 struct drm_i915_gem_object
*obj_priv
, *next
;
1577 list_for_each_entry_safe(obj_priv
, next
,
1578 &dev_priv
->mm
.gpu_write_list
,
1580 struct drm_gem_object
*obj
= &obj_priv
->base
;
1582 if ((obj
->write_domain
& flush_domains
) ==
1583 obj
->write_domain
&&
1584 obj_priv
->ring
->ring_flag
== ring
->ring_flag
) {
1585 uint32_t old_write_domain
= obj
->write_domain
;
1587 obj
->write_domain
= 0;
1588 list_del_init(&obj_priv
->gpu_write_list
);
1589 i915_gem_object_move_to_active(obj
, ring
);
1591 /* update the fence lru list */
1592 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1593 struct drm_i915_fence_reg
*reg
=
1594 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1595 list_move_tail(®
->lru_list
,
1596 &dev_priv
->mm
.fence_list
);
1599 trace_i915_gem_object_change_domain(obj
,
1607 i915_add_request(struct drm_device
*dev
,
1608 struct drm_file
*file_priv
,
1609 struct drm_i915_gem_request
*request
,
1610 struct intel_ring_buffer
*ring
)
1612 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1613 struct drm_i915_file_private
*i915_file_priv
= NULL
;
1617 if (file_priv
!= NULL
)
1618 i915_file_priv
= file_priv
->driver_priv
;
1620 if (request
== NULL
) {
1621 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1622 if (request
== NULL
)
1626 seqno
= ring
->add_request(dev
, ring
, file_priv
, 0);
1628 request
->seqno
= seqno
;
1629 request
->ring
= ring
;
1630 request
->emitted_jiffies
= jiffies
;
1631 was_empty
= list_empty(&ring
->request_list
);
1632 list_add_tail(&request
->list
, &ring
->request_list
);
1634 if (i915_file_priv
) {
1635 list_add_tail(&request
->client_list
,
1636 &i915_file_priv
->mm
.request_list
);
1638 INIT_LIST_HEAD(&request
->client_list
);
1641 if (!dev_priv
->mm
.suspended
) {
1642 mod_timer(&dev_priv
->hangcheck_timer
,
1643 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1645 queue_delayed_work(dev_priv
->wq
,
1646 &dev_priv
->mm
.retire_work
, HZ
);
1652 * Command execution barrier
1654 * Ensures that all commands in the ring are finished
1655 * before signalling the CPU
1658 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1660 uint32_t flush_domains
= 0;
1662 /* The sampler always gets flushed on i965 (sigh) */
1664 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1666 ring
->flush(dev
, ring
,
1667 I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1671 * Moves buffers associated only with the given active seqno from the active
1672 * to inactive list, potentially freeing them.
1675 i915_gem_retire_request(struct drm_device
*dev
,
1676 struct drm_i915_gem_request
*request
)
1678 trace_i915_gem_request_retire(dev
, request
->seqno
);
1680 /* Move any buffers on the active list that are no longer referenced
1681 * by the ringbuffer to the flushing/inactive lists as appropriate.
1683 while (!list_empty(&request
->ring
->active_list
)) {
1684 struct drm_gem_object
*obj
;
1685 struct drm_i915_gem_object
*obj_priv
;
1687 obj_priv
= list_first_entry(&request
->ring
->active_list
,
1688 struct drm_i915_gem_object
,
1690 obj
= &obj_priv
->base
;
1692 /* If the seqno being retired doesn't match the oldest in the
1693 * list, then the oldest in the list must still be newer than
1696 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
1700 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1701 __func__
, request
->seqno
, obj
);
1704 if (obj
->write_domain
!= 0)
1705 i915_gem_object_move_to_flushing(obj
);
1707 i915_gem_object_move_to_inactive(obj
);
1712 * Returns true if seq1 is later than seq2.
1715 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1717 return (int32_t)(seq1
- seq2
) >= 0;
1721 i915_get_gem_seqno(struct drm_device
*dev
,
1722 struct intel_ring_buffer
*ring
)
1724 return ring
->get_gem_seqno(dev
, ring
);
1728 * This function clears the request list as sequence numbers are passed.
1731 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1732 struct intel_ring_buffer
*ring
)
1734 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1737 if (!ring
->status_page
.page_addr
1738 || list_empty(&ring
->request_list
))
1741 seqno
= i915_get_gem_seqno(dev
, ring
);
1743 while (!list_empty(&ring
->request_list
)) {
1744 struct drm_i915_gem_request
*request
;
1745 uint32_t retiring_seqno
;
1747 request
= list_first_entry(&ring
->request_list
,
1748 struct drm_i915_gem_request
,
1750 retiring_seqno
= request
->seqno
;
1752 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
1753 atomic_read(&dev_priv
->mm
.wedged
)) {
1754 i915_gem_retire_request(dev
, request
);
1756 list_del(&request
->list
);
1757 list_del(&request
->client_list
);
1763 if (unlikely (dev_priv
->trace_irq_seqno
&&
1764 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1766 ring
->user_irq_put(dev
, ring
);
1767 dev_priv
->trace_irq_seqno
= 0;
1772 i915_gem_retire_requests(struct drm_device
*dev
)
1774 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1776 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1777 struct drm_i915_gem_object
*obj_priv
, *tmp
;
1779 /* We must be careful that during unbind() we do not
1780 * accidentally infinitely recurse into retire requests.
1782 * retire -> free -> unbind -> wait -> retire_ring
1784 list_for_each_entry_safe(obj_priv
, tmp
,
1785 &dev_priv
->mm
.deferred_free_list
,
1787 i915_gem_free_object_tail(&obj_priv
->base
);
1790 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
1792 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
1796 i915_gem_retire_work_handler(struct work_struct
*work
)
1798 drm_i915_private_t
*dev_priv
;
1799 struct drm_device
*dev
;
1801 dev_priv
= container_of(work
, drm_i915_private_t
,
1802 mm
.retire_work
.work
);
1803 dev
= dev_priv
->dev
;
1805 mutex_lock(&dev
->struct_mutex
);
1806 i915_gem_retire_requests(dev
);
1808 if (!dev_priv
->mm
.suspended
&&
1809 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
1811 !list_empty(&dev_priv
->bsd_ring
.request_list
))))
1812 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1813 mutex_unlock(&dev
->struct_mutex
);
1817 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1818 bool interruptible
, struct intel_ring_buffer
*ring
)
1820 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1826 if (seqno
== dev_priv
->next_seqno
) {
1827 seqno
= i915_add_request(dev
, NULL
, NULL
, ring
);
1832 if (atomic_read(&dev_priv
->mm
.wedged
))
1835 if (!i915_seqno_passed(ring
->get_gem_seqno(dev
, ring
), seqno
)) {
1836 if (HAS_PCH_SPLIT(dev
))
1837 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1839 ier
= I915_READ(IER
);
1841 DRM_ERROR("something (likely vbetool) disabled "
1842 "interrupts, re-enabling\n");
1843 i915_driver_irq_preinstall(dev
);
1844 i915_driver_irq_postinstall(dev
);
1847 trace_i915_gem_request_wait_begin(dev
, seqno
);
1849 ring
->waiting_gem_seqno
= seqno
;
1850 ring
->user_irq_get(dev
, ring
);
1852 ret
= wait_event_interruptible(ring
->irq_queue
,
1854 ring
->get_gem_seqno(dev
, ring
), seqno
)
1855 || atomic_read(&dev_priv
->mm
.wedged
));
1857 wait_event(ring
->irq_queue
,
1859 ring
->get_gem_seqno(dev
, ring
), seqno
)
1860 || atomic_read(&dev_priv
->mm
.wedged
));
1862 ring
->user_irq_put(dev
, ring
);
1863 ring
->waiting_gem_seqno
= 0;
1865 trace_i915_gem_request_wait_end(dev
, seqno
);
1867 if (atomic_read(&dev_priv
->mm
.wedged
))
1870 if (ret
&& ret
!= -ERESTARTSYS
)
1871 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
1872 __func__
, ret
, seqno
, ring
->get_gem_seqno(dev
, ring
),
1873 dev_priv
->next_seqno
);
1875 /* Directly dispatch request retiring. While we have the work queue
1876 * to handle this, the waiter on a request often wants an associated
1877 * buffer to have made it to the inactive list, and we would need
1878 * a separate wait queue to handle that.
1881 i915_gem_retire_requests_ring(dev
, ring
);
1887 * Waits for a sequence number to be signaled, and cleans up the
1888 * request and object lists appropriately for that event.
1891 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1892 struct intel_ring_buffer
*ring
)
1894 return i915_do_wait_request(dev
, seqno
, 1, ring
);
1898 i915_gem_flush(struct drm_device
*dev
,
1899 uint32_t invalidate_domains
,
1900 uint32_t flush_domains
)
1902 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1904 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1905 drm_agp_chipset_flush(dev
);
1907 dev_priv
->render_ring
.flush(dev
, &dev_priv
->render_ring
,
1912 dev_priv
->bsd_ring
.flush(dev
, &dev_priv
->bsd_ring
,
1918 * Ensures that all rendering to the object has completed and the object is
1919 * safe to unbind from the GTT or access from the CPU.
1922 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
)
1924 struct drm_device
*dev
= obj
->dev
;
1925 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1928 /* This function only exists to support waiting for existing rendering,
1929 * not for emitting required flushes.
1931 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1933 /* If there is rendering queued on the buffer being evicted, wait for
1936 if (obj_priv
->active
) {
1938 DRM_INFO("%s: object %p wait for seqno %08x\n",
1939 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1941 ret
= i915_wait_request(dev
,
1942 obj_priv
->last_rendering_seqno
,
1952 * Unbinds an object from the GTT aperture.
1955 i915_gem_object_unbind(struct drm_gem_object
*obj
)
1957 struct drm_device
*dev
= obj
->dev
;
1958 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1962 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
1963 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
1965 if (obj_priv
->gtt_space
== NULL
)
1968 if (obj_priv
->pin_count
!= 0) {
1969 DRM_ERROR("Attempting to unbind pinned buffer\n");
1973 /* blow away mappings if mapped through GTT */
1974 i915_gem_release_mmap(obj
);
1976 /* Move the object to the CPU domain to ensure that
1977 * any possible CPU writes while it's not in the GTT
1978 * are flushed when we go to remap it. This will
1979 * also ensure that all pending GPU writes are finished
1982 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1983 if (ret
== -ERESTARTSYS
)
1985 /* Continue on if we fail due to EIO, the GPU is hung so we
1986 * should be safe and we need to cleanup or else we might
1987 * cause memory corruption through use-after-free.
1990 /* release the fence reg _after_ flushing */
1991 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
1992 i915_gem_clear_fence_reg(obj
);
1994 if (obj_priv
->agp_mem
!= NULL
) {
1995 drm_unbind_agp(obj_priv
->agp_mem
);
1996 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
1997 obj_priv
->agp_mem
= NULL
;
2000 i915_gem_object_put_pages(obj
);
2001 BUG_ON(obj_priv
->pages_refcount
);
2003 if (obj_priv
->gtt_space
) {
2004 atomic_dec(&dev
->gtt_count
);
2005 atomic_sub(obj
->size
, &dev
->gtt_memory
);
2007 drm_mm_put_block(obj_priv
->gtt_space
);
2008 obj_priv
->gtt_space
= NULL
;
2011 /* Remove ourselves from the LRU list if present. */
2012 if (!list_empty(&obj_priv
->list
))
2013 list_del_init(&obj_priv
->list
);
2015 if (i915_gem_object_is_purgeable(obj_priv
))
2016 i915_gem_object_truncate(obj
);
2018 trace_i915_gem_object_unbind(obj
);
2024 i915_gpu_idle(struct drm_device
*dev
)
2026 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2030 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2031 list_empty(&dev_priv
->render_ring
.active_list
) &&
2033 list_empty(&dev_priv
->bsd_ring
.active_list
)));
2037 /* Flush everything onto the inactive list. */
2038 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2040 ret
= i915_wait_request(dev
,
2041 i915_gem_next_request_seqno(dev
, &dev_priv
->render_ring
),
2042 &dev_priv
->render_ring
);
2047 ret
= i915_wait_request(dev
,
2048 i915_gem_next_request_seqno(dev
, &dev_priv
->bsd_ring
),
2049 &dev_priv
->bsd_ring
);
2058 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2061 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2063 struct address_space
*mapping
;
2064 struct inode
*inode
;
2067 BUG_ON(obj_priv
->pages_refcount
2068 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT
);
2070 if (obj_priv
->pages_refcount
++ != 0)
2073 /* Get the list of pages out of our struct file. They'll be pinned
2074 * at this point until we release them.
2076 page_count
= obj
->size
/ PAGE_SIZE
;
2077 BUG_ON(obj_priv
->pages
!= NULL
);
2078 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2079 if (obj_priv
->pages
== NULL
) {
2080 obj_priv
->pages_refcount
--;
2084 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2085 mapping
= inode
->i_mapping
;
2086 for (i
= 0; i
< page_count
; i
++) {
2087 page
= read_cache_page_gfp(mapping
, i
,
2095 obj_priv
->pages
[i
] = page
;
2098 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2099 i915_gem_object_do_bit_17_swizzle(obj
);
2105 page_cache_release(obj_priv
->pages
[i
]);
2107 drm_free_large(obj_priv
->pages
);
2108 obj_priv
->pages
= NULL
;
2109 obj_priv
->pages_refcount
--;
2110 return PTR_ERR(page
);
2113 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2115 struct drm_gem_object
*obj
= reg
->obj
;
2116 struct drm_device
*dev
= obj
->dev
;
2117 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2118 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2119 int regnum
= obj_priv
->fence_reg
;
2122 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2124 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2125 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2126 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2128 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2129 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2130 val
|= I965_FENCE_REG_VALID
;
2132 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2135 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2137 struct drm_gem_object
*obj
= reg
->obj
;
2138 struct drm_device
*dev
= obj
->dev
;
2139 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2140 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2141 int regnum
= obj_priv
->fence_reg
;
2144 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2146 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2147 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2148 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2149 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2150 val
|= I965_FENCE_REG_VALID
;
2152 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2155 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2157 struct drm_gem_object
*obj
= reg
->obj
;
2158 struct drm_device
*dev
= obj
->dev
;
2159 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2160 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2161 int regnum
= obj_priv
->fence_reg
;
2163 uint32_t fence_reg
, val
;
2166 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2167 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2168 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2169 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2173 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2174 HAS_128_BYTE_Y_TILING(dev
))
2179 /* Note: pitch better be a power of two tile widths */
2180 pitch_val
= obj_priv
->stride
/ tile_width
;
2181 pitch_val
= ffs(pitch_val
) - 1;
2183 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2184 HAS_128_BYTE_Y_TILING(dev
))
2185 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2187 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2189 val
= obj_priv
->gtt_offset
;
2190 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2191 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2192 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2193 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2194 val
|= I830_FENCE_REG_VALID
;
2197 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2199 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2200 I915_WRITE(fence_reg
, val
);
2203 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2205 struct drm_gem_object
*obj
= reg
->obj
;
2206 struct drm_device
*dev
= obj
->dev
;
2207 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2208 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2209 int regnum
= obj_priv
->fence_reg
;
2212 uint32_t fence_size_bits
;
2214 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2215 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2216 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2217 __func__
, obj_priv
->gtt_offset
);
2221 pitch_val
= obj_priv
->stride
/ 128;
2222 pitch_val
= ffs(pitch_val
) - 1;
2223 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2225 val
= obj_priv
->gtt_offset
;
2226 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2227 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2228 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2229 WARN_ON(fence_size_bits
& ~0x00000f00);
2230 val
|= fence_size_bits
;
2231 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2232 val
|= I830_FENCE_REG_VALID
;
2234 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2237 static int i915_find_fence_reg(struct drm_device
*dev
)
2239 struct drm_i915_fence_reg
*reg
= NULL
;
2240 struct drm_i915_gem_object
*obj_priv
= NULL
;
2241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2242 struct drm_gem_object
*obj
= NULL
;
2245 /* First try to find a free reg */
2247 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2248 reg
= &dev_priv
->fence_regs
[i
];
2252 obj_priv
= to_intel_bo(reg
->obj
);
2253 if (!obj_priv
->pin_count
)
2260 /* None available, try to steal one or wait for a user to finish */
2261 i
= I915_FENCE_REG_NONE
;
2262 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2265 obj_priv
= to_intel_bo(obj
);
2267 if (obj_priv
->pin_count
)
2271 i
= obj_priv
->fence_reg
;
2275 BUG_ON(i
== I915_FENCE_REG_NONE
);
2277 /* We only have a reference on obj from the active list. put_fence_reg
2278 * might drop that one, causing a use-after-free in it. So hold a
2279 * private reference to obj like the other callers of put_fence_reg
2280 * (set_tiling ioctl) do. */
2281 drm_gem_object_reference(obj
);
2282 ret
= i915_gem_object_put_fence_reg(obj
);
2283 drm_gem_object_unreference(obj
);
2291 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2292 * @obj: object to map through a fence reg
2294 * When mapping objects through the GTT, userspace wants to be able to write
2295 * to them without having to worry about swizzling if the object is tiled.
2297 * This function walks the fence regs looking for a free one for @obj,
2298 * stealing one if it can't find any.
2300 * It then sets up the reg based on the object's properties: address, pitch
2301 * and tiling format.
2304 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
)
2306 struct drm_device
*dev
= obj
->dev
;
2307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2308 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2309 struct drm_i915_fence_reg
*reg
= NULL
;
2312 /* Just update our place in the LRU if our fence is getting used. */
2313 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2314 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2315 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2319 switch (obj_priv
->tiling_mode
) {
2320 case I915_TILING_NONE
:
2321 WARN(1, "allocating a fence for non-tiled object?\n");
2324 if (!obj_priv
->stride
)
2326 WARN((obj_priv
->stride
& (512 - 1)),
2327 "object 0x%08x is X tiled but has non-512B pitch\n",
2328 obj_priv
->gtt_offset
);
2331 if (!obj_priv
->stride
)
2333 WARN((obj_priv
->stride
& (128 - 1)),
2334 "object 0x%08x is Y tiled but has non-128B pitch\n",
2335 obj_priv
->gtt_offset
);
2339 ret
= i915_find_fence_reg(dev
);
2343 obj_priv
->fence_reg
= ret
;
2344 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2345 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2350 sandybridge_write_fence_reg(reg
);
2351 else if (IS_I965G(dev
))
2352 i965_write_fence_reg(reg
);
2353 else if (IS_I9XX(dev
))
2354 i915_write_fence_reg(reg
);
2356 i830_write_fence_reg(reg
);
2358 trace_i915_gem_object_get_fence(obj
, obj_priv
->fence_reg
,
2359 obj_priv
->tiling_mode
);
2365 * i915_gem_clear_fence_reg - clear out fence register info
2366 * @obj: object to clear
2368 * Zeroes out the fence register itself and clears out the associated
2369 * data structures in dev_priv and obj_priv.
2372 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2374 struct drm_device
*dev
= obj
->dev
;
2375 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2376 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2377 struct drm_i915_fence_reg
*reg
=
2378 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2381 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2382 (obj_priv
->fence_reg
* 8), 0);
2383 } else if (IS_I965G(dev
)) {
2384 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2388 if (obj_priv
->fence_reg
< 8)
2389 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2391 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
-
2394 I915_WRITE(fence_reg
, 0);
2398 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2399 list_del_init(®
->lru_list
);
2403 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2404 * to the buffer to finish, and then resets the fence register.
2405 * @obj: tiled object holding a fence register.
2407 * Zeroes out the fence register itself and clears out the associated
2408 * data structures in dev_priv and obj_priv.
2411 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
)
2413 struct drm_device
*dev
= obj
->dev
;
2414 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2416 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2419 /* If we've changed tiling, GTT-mappings of the object
2420 * need to re-fault to ensure that the correct fence register
2421 * setup is in place.
2423 i915_gem_release_mmap(obj
);
2425 /* On the i915, GPU access to tiled buffers is via a fence,
2426 * therefore we must wait for any outstanding access to complete
2427 * before clearing the fence.
2429 if (!IS_I965G(dev
)) {
2432 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2437 i915_gem_object_flush_gtt_write_domain(obj
);
2438 i915_gem_clear_fence_reg (obj
);
2444 * Finds free space in the GTT aperture and binds the object there.
2447 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2449 struct drm_device
*dev
= obj
->dev
;
2450 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2451 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2452 struct drm_mm_node
*free_space
;
2453 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2456 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2457 DRM_ERROR("Attempting to bind a purgeable object\n");
2462 alignment
= i915_gem_get_gtt_alignment(obj
);
2463 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2464 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2468 /* If the object is bigger than the entire aperture, reject it early
2469 * before evicting everything in a vain attempt to find space.
2471 if (obj
->size
> dev
->gtt_total
) {
2472 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2477 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2478 obj
->size
, alignment
, 0);
2479 if (free_space
!= NULL
) {
2480 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2482 if (obj_priv
->gtt_space
!= NULL
)
2483 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2485 if (obj_priv
->gtt_space
== NULL
) {
2486 /* If the gtt is empty and we're still having trouble
2487 * fitting our object in, we're out of memory.
2490 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
2492 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2500 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2501 obj
->size
, obj_priv
->gtt_offset
);
2503 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2505 drm_mm_put_block(obj_priv
->gtt_space
);
2506 obj_priv
->gtt_space
= NULL
;
2508 if (ret
== -ENOMEM
) {
2509 /* first try to clear up some space from the GTT */
2510 ret
= i915_gem_evict_something(dev
, obj
->size
,
2513 /* now try to shrink everyone else */
2528 /* Create an AGP memory structure pointing at our pages, and bind it
2531 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2533 obj
->size
>> PAGE_SHIFT
,
2534 obj_priv
->gtt_offset
,
2535 obj_priv
->agp_type
);
2536 if (obj_priv
->agp_mem
== NULL
) {
2537 i915_gem_object_put_pages(obj
);
2538 drm_mm_put_block(obj_priv
->gtt_space
);
2539 obj_priv
->gtt_space
= NULL
;
2541 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2547 atomic_inc(&dev
->gtt_count
);
2548 atomic_add(obj
->size
, &dev
->gtt_memory
);
2550 /* keep track of bounds object by adding it to the inactive list */
2551 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
2553 /* Assert that the object is not currently in any GPU domain. As it
2554 * wasn't in the GTT, there shouldn't be any way it could have been in
2557 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2558 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2560 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2566 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2568 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2570 /* If we don't have a page list set up, then we're not pinned
2571 * to GPU, and we can ignore the cache flush because it'll happen
2572 * again at bind time.
2574 if (obj_priv
->pages
== NULL
)
2577 trace_i915_gem_object_clflush(obj
);
2579 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2582 /** Flushes any GPU write domain for the object if it's dirty. */
2584 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
2587 struct drm_device
*dev
= obj
->dev
;
2588 uint32_t old_write_domain
;
2590 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2593 /* Queue the GPU write cache flushing we need. */
2594 old_write_domain
= obj
->write_domain
;
2595 i915_gem_flush(dev
, 0, obj
->write_domain
);
2597 trace_i915_gem_object_change_domain(obj
,
2604 return i915_gem_object_wait_rendering(obj
);
2607 /** Flushes the GTT write domain for the object if it's dirty. */
2609 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2611 uint32_t old_write_domain
;
2613 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2616 /* No actual flushing is required for the GTT write domain. Writes
2617 * to it immediately go to main memory as far as we know, so there's
2618 * no chipset flush. It also doesn't land in render cache.
2620 old_write_domain
= obj
->write_domain
;
2621 obj
->write_domain
= 0;
2623 trace_i915_gem_object_change_domain(obj
,
2628 /** Flushes the CPU write domain for the object if it's dirty. */
2630 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2632 struct drm_device
*dev
= obj
->dev
;
2633 uint32_t old_write_domain
;
2635 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2638 i915_gem_clflush_object(obj
);
2639 drm_agp_chipset_flush(dev
);
2640 old_write_domain
= obj
->write_domain
;
2641 obj
->write_domain
= 0;
2643 trace_i915_gem_object_change_domain(obj
,
2649 i915_gem_object_flush_write_domain(struct drm_gem_object
*obj
)
2653 switch (obj
->write_domain
) {
2654 case I915_GEM_DOMAIN_GTT
:
2655 i915_gem_object_flush_gtt_write_domain(obj
);
2657 case I915_GEM_DOMAIN_CPU
:
2658 i915_gem_object_flush_cpu_write_domain(obj
);
2661 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2669 * Moves a single object to the GTT read, and possibly write domain.
2671 * This function returns when the move is complete, including waiting on
2675 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2677 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2678 uint32_t old_write_domain
, old_read_domains
;
2681 /* Not valid to be called on unbound objects. */
2682 if (obj_priv
->gtt_space
== NULL
)
2685 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2689 old_write_domain
= obj
->write_domain
;
2690 old_read_domains
= obj
->read_domains
;
2692 /* If we're writing through the GTT domain, then CPU and GPU caches
2693 * will need to be invalidated at next use.
2696 ret
= i915_gem_object_wait_rendering(obj
);
2700 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2703 i915_gem_object_flush_cpu_write_domain(obj
);
2705 /* It should now be out of any other write domains, and we can update
2706 * the domain values for our changes.
2708 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2709 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2711 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2712 obj_priv
->dirty
= 1;
2715 trace_i915_gem_object_change_domain(obj
,
2723 * Prepare buffer for display plane. Use uninterruptible for possible flush
2724 * wait, as in modesetting process we're not supposed to be interrupted.
2727 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
)
2729 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2730 uint32_t old_read_domains
;
2733 /* Not valid to be called on unbound objects. */
2734 if (obj_priv
->gtt_space
== NULL
)
2737 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2741 i915_gem_object_flush_cpu_write_domain(obj
);
2743 old_read_domains
= obj
->read_domains
;
2744 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2746 trace_i915_gem_object_change_domain(obj
,
2754 * Moves a single object to the CPU read, and possibly write domain.
2756 * This function returns when the move is complete, including waiting on
2760 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2762 uint32_t old_write_domain
, old_read_domains
;
2765 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2769 i915_gem_object_flush_gtt_write_domain(obj
);
2771 /* If we have a partially-valid cache of the object in the CPU,
2772 * finish invalidating it and free the per-page flags.
2774 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2776 old_write_domain
= obj
->write_domain
;
2777 old_read_domains
= obj
->read_domains
;
2779 /* Flush the CPU cache if it's still invalid. */
2780 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2781 i915_gem_clflush_object(obj
);
2783 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2786 /* It should now be out of any other write domains, and we can update
2787 * the domain values for our changes.
2789 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2791 /* If we're writing through the CPU, then the GPU read domains will
2792 * need to be invalidated at next use.
2795 ret
= i915_gem_object_wait_rendering(obj
);
2799 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
2800 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2803 trace_i915_gem_object_change_domain(obj
,
2811 * Set the next domain for the specified object. This
2812 * may not actually perform the necessary flushing/invaliding though,
2813 * as that may want to be batched with other set_domain operations
2815 * This is (we hope) the only really tricky part of gem. The goal
2816 * is fairly simple -- track which caches hold bits of the object
2817 * and make sure they remain coherent. A few concrete examples may
2818 * help to explain how it works. For shorthand, we use the notation
2819 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2820 * a pair of read and write domain masks.
2822 * Case 1: the batch buffer
2828 * 5. Unmapped from GTT
2831 * Let's take these a step at a time
2834 * Pages allocated from the kernel may still have
2835 * cache contents, so we set them to (CPU, CPU) always.
2836 * 2. Written by CPU (using pwrite)
2837 * The pwrite function calls set_domain (CPU, CPU) and
2838 * this function does nothing (as nothing changes)
2840 * This function asserts that the object is not
2841 * currently in any GPU-based read or write domains
2843 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2844 * As write_domain is zero, this function adds in the
2845 * current read domains (CPU+COMMAND, 0).
2846 * flush_domains is set to CPU.
2847 * invalidate_domains is set to COMMAND
2848 * clflush is run to get data out of the CPU caches
2849 * then i915_dev_set_domain calls i915_gem_flush to
2850 * emit an MI_FLUSH and drm_agp_chipset_flush
2851 * 5. Unmapped from GTT
2852 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2853 * flush_domains and invalidate_domains end up both zero
2854 * so no flushing/invalidating happens
2858 * Case 2: The shared render buffer
2862 * 3. Read/written by GPU
2863 * 4. set_domain to (CPU,CPU)
2864 * 5. Read/written by CPU
2865 * 6. Read/written by GPU
2868 * Same as last example, (CPU, CPU)
2870 * Nothing changes (assertions find that it is not in the GPU)
2871 * 3. Read/written by GPU
2872 * execbuffer calls set_domain (RENDER, RENDER)
2873 * flush_domains gets CPU
2874 * invalidate_domains gets GPU
2876 * MI_FLUSH and drm_agp_chipset_flush
2877 * 4. set_domain (CPU, CPU)
2878 * flush_domains gets GPU
2879 * invalidate_domains gets CPU
2880 * wait_rendering (obj) to make sure all drawing is complete.
2881 * This will include an MI_FLUSH to get the data from GPU
2883 * clflush (obj) to invalidate the CPU cache
2884 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2885 * 5. Read/written by CPU
2886 * cache lines are loaded and dirtied
2887 * 6. Read written by GPU
2888 * Same as last GPU access
2890 * Case 3: The constant buffer
2895 * 4. Updated (written) by CPU again
2904 * flush_domains = CPU
2905 * invalidate_domains = RENDER
2908 * drm_agp_chipset_flush
2909 * 4. Updated (written) by CPU again
2911 * flush_domains = 0 (no previous write domain)
2912 * invalidate_domains = 0 (no new read domains)
2915 * flush_domains = CPU
2916 * invalidate_domains = RENDER
2919 * drm_agp_chipset_flush
2922 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
2924 struct drm_device
*dev
= obj
->dev
;
2925 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2926 uint32_t invalidate_domains
= 0;
2927 uint32_t flush_domains
= 0;
2928 uint32_t old_read_domains
;
2930 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
2931 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
2933 intel_mark_busy(dev
, obj
);
2936 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2938 obj
->read_domains
, obj
->pending_read_domains
,
2939 obj
->write_domain
, obj
->pending_write_domain
);
2942 * If the object isn't moving to a new write domain,
2943 * let the object stay in multiple read domains
2945 if (obj
->pending_write_domain
== 0)
2946 obj
->pending_read_domains
|= obj
->read_domains
;
2948 obj_priv
->dirty
= 1;
2951 * Flush the current write domain if
2952 * the new read domains don't match. Invalidate
2953 * any read domains which differ from the old
2956 if (obj
->write_domain
&&
2957 obj
->write_domain
!= obj
->pending_read_domains
) {
2958 flush_domains
|= obj
->write_domain
;
2959 invalidate_domains
|=
2960 obj
->pending_read_domains
& ~obj
->write_domain
;
2963 * Invalidate any read caches which may have
2964 * stale data. That is, any new read domains.
2966 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
2967 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
2969 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2970 __func__
, flush_domains
, invalidate_domains
);
2972 i915_gem_clflush_object(obj
);
2975 old_read_domains
= obj
->read_domains
;
2977 /* The actual obj->write_domain will be updated with
2978 * pending_write_domain after we emit the accumulated flush for all
2979 * of our domain changes in execbuffers (which clears objects'
2980 * write_domains). So if we have a current write domain that we
2981 * aren't changing, set pending_write_domain to that.
2983 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
2984 obj
->pending_write_domain
= obj
->write_domain
;
2985 obj
->read_domains
= obj
->pending_read_domains
;
2987 dev
->invalidate_domains
|= invalidate_domains
;
2988 dev
->flush_domains
|= flush_domains
;
2990 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2992 obj
->read_domains
, obj
->write_domain
,
2993 dev
->invalidate_domains
, dev
->flush_domains
);
2996 trace_i915_gem_object_change_domain(obj
,
3002 * Moves the object from a partially CPU read to a full one.
3004 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3005 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3008 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3010 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3012 if (!obj_priv
->page_cpu_valid
)
3015 /* If we're partially in the CPU read domain, finish moving it in.
3017 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3020 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3021 if (obj_priv
->page_cpu_valid
[i
])
3023 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3027 /* Free the page_cpu_valid mappings which are now stale, whether
3028 * or not we've got I915_GEM_DOMAIN_CPU.
3030 kfree(obj_priv
->page_cpu_valid
);
3031 obj_priv
->page_cpu_valid
= NULL
;
3035 * Set the CPU read domain on a range of the object.
3037 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3038 * not entirely valid. The page_cpu_valid member of the object flags which
3039 * pages have been flushed, and will be respected by
3040 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3041 * of the whole object.
3043 * This function returns when the move is complete, including waiting on
3047 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3048 uint64_t offset
, uint64_t size
)
3050 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3051 uint32_t old_read_domains
;
3054 if (offset
== 0 && size
== obj
->size
)
3055 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3057 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3060 i915_gem_object_flush_gtt_write_domain(obj
);
3062 /* If we're already fully in the CPU read domain, we're done. */
3063 if (obj_priv
->page_cpu_valid
== NULL
&&
3064 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3067 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3068 * newly adding I915_GEM_DOMAIN_CPU
3070 if (obj_priv
->page_cpu_valid
== NULL
) {
3071 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3073 if (obj_priv
->page_cpu_valid
== NULL
)
3075 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3076 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3078 /* Flush the cache on any pages that are still invalid from the CPU's
3081 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3083 if (obj_priv
->page_cpu_valid
[i
])
3086 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3088 obj_priv
->page_cpu_valid
[i
] = 1;
3091 /* It should now be out of any other write domains, and we can update
3092 * the domain values for our changes.
3094 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3096 old_read_domains
= obj
->read_domains
;
3097 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3099 trace_i915_gem_object_change_domain(obj
,
3107 * Pin an object to the GTT and evaluate the relocations landing in it.
3110 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3111 struct drm_file
*file_priv
,
3112 struct drm_i915_gem_exec_object2
*entry
,
3113 struct drm_i915_gem_relocation_entry
*relocs
)
3115 struct drm_device
*dev
= obj
->dev
;
3116 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3117 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3119 void __iomem
*reloc_page
;
3122 need_fence
= entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3123 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3125 /* Check fence reg constraints and rebind if necessary */
3127 !i915_gem_object_fence_offset_ok(obj
,
3128 obj_priv
->tiling_mode
)) {
3129 ret
= i915_gem_object_unbind(obj
);
3134 /* Choose the GTT offset for our buffer and put it there. */
3135 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3140 * Pre-965 chips need a fence register set up in order to
3141 * properly handle blits to/from tiled surfaces.
3144 ret
= i915_gem_object_get_fence_reg(obj
);
3146 i915_gem_object_unpin(obj
);
3151 entry
->offset
= obj_priv
->gtt_offset
;
3153 /* Apply the relocations, using the GTT aperture to avoid cache
3154 * flushing requirements.
3156 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3157 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
3158 struct drm_gem_object
*target_obj
;
3159 struct drm_i915_gem_object
*target_obj_priv
;
3160 uint32_t reloc_val
, reloc_offset
;
3161 uint32_t __iomem
*reloc_entry
;
3163 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3164 reloc
->target_handle
);
3165 if (target_obj
== NULL
) {
3166 i915_gem_object_unpin(obj
);
3169 target_obj_priv
= to_intel_bo(target_obj
);
3172 DRM_INFO("%s: obj %p offset %08x target %d "
3173 "read %08x write %08x gtt %08x "
3174 "presumed %08x delta %08x\n",
3177 (int) reloc
->offset
,
3178 (int) reloc
->target_handle
,
3179 (int) reloc
->read_domains
,
3180 (int) reloc
->write_domain
,
3181 (int) target_obj_priv
->gtt_offset
,
3182 (int) reloc
->presumed_offset
,
3186 /* The target buffer should have appeared before us in the
3187 * exec_object list, so it should have a GTT space bound by now.
3189 if (target_obj_priv
->gtt_space
== NULL
) {
3190 DRM_ERROR("No GTT space found for object %d\n",
3191 reloc
->target_handle
);
3192 drm_gem_object_unreference(target_obj
);
3193 i915_gem_object_unpin(obj
);
3197 /* Validate that the target is in a valid r/w GPU domain */
3198 if (reloc
->write_domain
& (reloc
->write_domain
- 1)) {
3199 DRM_ERROR("reloc with multiple write domains: "
3200 "obj %p target %d offset %d "
3201 "read %08x write %08x",
3202 obj
, reloc
->target_handle
,
3203 (int) reloc
->offset
,
3204 reloc
->read_domains
,
3205 reloc
->write_domain
);
3208 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3209 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3210 DRM_ERROR("reloc with read/write CPU domains: "
3211 "obj %p target %d offset %d "
3212 "read %08x write %08x",
3213 obj
, reloc
->target_handle
,
3214 (int) reloc
->offset
,
3215 reloc
->read_domains
,
3216 reloc
->write_domain
);
3217 drm_gem_object_unreference(target_obj
);
3218 i915_gem_object_unpin(obj
);
3221 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3222 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3223 DRM_ERROR("Write domain conflict: "
3224 "obj %p target %d offset %d "
3225 "new %08x old %08x\n",
3226 obj
, reloc
->target_handle
,
3227 (int) reloc
->offset
,
3228 reloc
->write_domain
,
3229 target_obj
->pending_write_domain
);
3230 drm_gem_object_unreference(target_obj
);
3231 i915_gem_object_unpin(obj
);
3235 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3236 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3238 /* If the relocation already has the right value in it, no
3239 * more work needs to be done.
3241 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3242 drm_gem_object_unreference(target_obj
);
3246 /* Check that the relocation address is valid... */
3247 if (reloc
->offset
> obj
->size
- 4) {
3248 DRM_ERROR("Relocation beyond object bounds: "
3249 "obj %p target %d offset %d size %d.\n",
3250 obj
, reloc
->target_handle
,
3251 (int) reloc
->offset
, (int) obj
->size
);
3252 drm_gem_object_unreference(target_obj
);
3253 i915_gem_object_unpin(obj
);
3256 if (reloc
->offset
& 3) {
3257 DRM_ERROR("Relocation not 4-byte aligned: "
3258 "obj %p target %d offset %d.\n",
3259 obj
, reloc
->target_handle
,
3260 (int) reloc
->offset
);
3261 drm_gem_object_unreference(target_obj
);
3262 i915_gem_object_unpin(obj
);
3266 /* and points to somewhere within the target object. */
3267 if (reloc
->delta
>= target_obj
->size
) {
3268 DRM_ERROR("Relocation beyond target object bounds: "
3269 "obj %p target %d delta %d size %d.\n",
3270 obj
, reloc
->target_handle
,
3271 (int) reloc
->delta
, (int) target_obj
->size
);
3272 drm_gem_object_unreference(target_obj
);
3273 i915_gem_object_unpin(obj
);
3277 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3279 drm_gem_object_unreference(target_obj
);
3280 i915_gem_object_unpin(obj
);
3284 /* Map the page containing the relocation we're going to
3287 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3288 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3292 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3293 (reloc_offset
& (PAGE_SIZE
- 1)));
3294 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3297 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3298 obj
, (unsigned int) reloc
->offset
,
3299 readl(reloc_entry
), reloc_val
);
3301 writel(reloc_val
, reloc_entry
);
3302 io_mapping_unmap_atomic(reloc_page
, KM_USER0
);
3304 /* The updated presumed offset for this entry will be
3305 * copied back out to the user.
3307 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3309 drm_gem_object_unreference(target_obj
);
3314 i915_gem_dump_object(obj
, 128, __func__
, ~0);
3319 /* Throttle our rendering by waiting until the ring has completed our requests
3320 * emitted over 20 msec ago.
3322 * Note that if we were to use the current jiffies each time around the loop,
3323 * we wouldn't escape the function with any frames outstanding if the time to
3324 * render a frame was over 20ms.
3326 * This should get us reasonable parallelism between CPU and GPU but also
3327 * relatively low latency when blocking on a particular request to finish.
3330 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
3332 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
3334 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3336 mutex_lock(&dev
->struct_mutex
);
3337 while (!list_empty(&i915_file_priv
->mm
.request_list
)) {
3338 struct drm_i915_gem_request
*request
;
3340 request
= list_first_entry(&i915_file_priv
->mm
.request_list
,
3341 struct drm_i915_gem_request
,
3344 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3347 ret
= i915_wait_request(dev
, request
->seqno
, request
->ring
);
3351 mutex_unlock(&dev
->struct_mutex
);
3357 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2
*exec_list
,
3358 uint32_t buffer_count
,
3359 struct drm_i915_gem_relocation_entry
**relocs
)
3361 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3365 for (i
= 0; i
< buffer_count
; i
++) {
3366 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3368 reloc_count
+= exec_list
[i
].relocation_count
;
3371 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3372 if (*relocs
== NULL
) {
3373 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count
);
3377 for (i
= 0; i
< buffer_count
; i
++) {
3378 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3380 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3382 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3384 exec_list
[i
].relocation_count
*
3387 drm_free_large(*relocs
);
3392 reloc_index
+= exec_list
[i
].relocation_count
;
3399 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2
*exec_list
,
3400 uint32_t buffer_count
,
3401 struct drm_i915_gem_relocation_entry
*relocs
)
3403 uint32_t reloc_count
= 0, i
;
3409 for (i
= 0; i
< buffer_count
; i
++) {
3410 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3413 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3415 unwritten
= copy_to_user(user_relocs
,
3416 &relocs
[reloc_count
],
3417 exec_list
[i
].relocation_count
*
3425 reloc_count
+= exec_list
[i
].relocation_count
;
3429 drm_free_large(relocs
);
3435 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2
*exec
,
3436 uint64_t exec_offset
)
3438 uint32_t exec_start
, exec_len
;
3440 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3441 exec_len
= (uint32_t) exec
->batch_len
;
3443 if ((exec_start
| exec_len
) & 0x7)
3453 i915_gem_wait_for_pending_flip(struct drm_device
*dev
,
3454 struct drm_gem_object
**object_list
,
3457 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3458 struct drm_i915_gem_object
*obj_priv
;
3463 prepare_to_wait(&dev_priv
->pending_flip_queue
,
3464 &wait
, TASK_INTERRUPTIBLE
);
3465 for (i
= 0; i
< count
; i
++) {
3466 obj_priv
= to_intel_bo(object_list
[i
]);
3467 if (atomic_read(&obj_priv
->pending_flip
) > 0)
3473 if (!signal_pending(current
)) {
3474 mutex_unlock(&dev
->struct_mutex
);
3476 mutex_lock(&dev
->struct_mutex
);
3482 finish_wait(&dev_priv
->pending_flip_queue
, &wait
);
3488 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3489 struct drm_file
*file_priv
,
3490 struct drm_i915_gem_execbuffer2
*args
,
3491 struct drm_i915_gem_exec_object2
*exec_list
)
3493 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3494 struct drm_gem_object
**object_list
= NULL
;
3495 struct drm_gem_object
*batch_obj
;
3496 struct drm_i915_gem_object
*obj_priv
;
3497 struct drm_clip_rect
*cliprects
= NULL
;
3498 struct drm_i915_gem_relocation_entry
*relocs
= NULL
;
3499 struct drm_i915_gem_request
*request
= NULL
;
3500 int ret
= 0, ret2
, i
, pinned
= 0;
3501 uint64_t exec_offset
;
3502 uint32_t seqno
, reloc_index
;
3503 int pin_tries
, flips
;
3505 struct intel_ring_buffer
*ring
= NULL
;
3508 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3509 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3511 if (args
->flags
& I915_EXEC_BSD
) {
3512 if (!HAS_BSD(dev
)) {
3513 DRM_ERROR("execbuf with wrong flag\n");
3516 ring
= &dev_priv
->bsd_ring
;
3518 ring
= &dev_priv
->render_ring
;
3521 if (args
->buffer_count
< 1) {
3522 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3525 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3526 if (object_list
== NULL
) {
3527 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3528 args
->buffer_count
);
3533 if (args
->num_cliprects
!= 0) {
3534 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3536 if (cliprects
== NULL
) {
3541 ret
= copy_from_user(cliprects
,
3542 (struct drm_clip_rect __user
*)
3543 (uintptr_t) args
->cliprects_ptr
,
3544 sizeof(*cliprects
) * args
->num_cliprects
);
3546 DRM_ERROR("copy %d cliprects failed: %d\n",
3547 args
->num_cliprects
, ret
);
3553 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3554 if (request
== NULL
) {
3559 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3564 mutex_lock(&dev
->struct_mutex
);
3566 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3568 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3569 mutex_unlock(&dev
->struct_mutex
);
3574 if (dev_priv
->mm
.suspended
) {
3575 mutex_unlock(&dev
->struct_mutex
);
3580 /* Look up object handles */
3582 for (i
= 0; i
< args
->buffer_count
; i
++) {
3583 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3584 exec_list
[i
].handle
);
3585 if (object_list
[i
] == NULL
) {
3586 DRM_ERROR("Invalid object handle %d at index %d\n",
3587 exec_list
[i
].handle
, i
);
3588 /* prevent error path from reading uninitialized data */
3589 args
->buffer_count
= i
+ 1;
3594 obj_priv
= to_intel_bo(object_list
[i
]);
3595 if (obj_priv
->in_execbuffer
) {
3596 DRM_ERROR("Object %p appears more than once in object list\n",
3598 /* prevent error path from reading uninitialized data */
3599 args
->buffer_count
= i
+ 1;
3603 obj_priv
->in_execbuffer
= true;
3604 flips
+= atomic_read(&obj_priv
->pending_flip
);
3608 ret
= i915_gem_wait_for_pending_flip(dev
, object_list
,
3609 args
->buffer_count
);
3614 /* Pin and relocate */
3615 for (pin_tries
= 0; ; pin_tries
++) {
3619 for (i
= 0; i
< args
->buffer_count
; i
++) {
3620 object_list
[i
]->pending_read_domains
= 0;
3621 object_list
[i
]->pending_write_domain
= 0;
3622 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3625 &relocs
[reloc_index
]);
3629 reloc_index
+= exec_list
[i
].relocation_count
;
3635 /* error other than GTT full, or we've already tried again */
3636 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3637 if (ret
!= -ERESTARTSYS
) {
3638 unsigned long long total_size
= 0;
3640 for (i
= 0; i
< args
->buffer_count
; i
++) {
3641 obj_priv
= to_intel_bo(object_list
[i
]);
3643 total_size
+= object_list
[i
]->size
;
3645 exec_list
[i
].flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3646 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3648 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3649 pinned
+1, args
->buffer_count
,
3650 total_size
, num_fences
,
3652 DRM_ERROR("%d objects [%d pinned], "
3653 "%d object bytes [%d pinned], "
3654 "%d/%d gtt bytes\n",
3655 atomic_read(&dev
->object_count
),
3656 atomic_read(&dev
->pin_count
),
3657 atomic_read(&dev
->object_memory
),
3658 atomic_read(&dev
->pin_memory
),
3659 atomic_read(&dev
->gtt_memory
),
3665 /* unpin all of our buffers */
3666 for (i
= 0; i
< pinned
; i
++)
3667 i915_gem_object_unpin(object_list
[i
]);
3670 /* evict everyone we can from the aperture */
3671 ret
= i915_gem_evict_everything(dev
);
3672 if (ret
&& ret
!= -ENOSPC
)
3676 /* Set the pending read domains for the batch buffer to COMMAND */
3677 batch_obj
= object_list
[args
->buffer_count
-1];
3678 if (batch_obj
->pending_write_domain
) {
3679 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3683 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3685 /* Sanity check the batch buffer, prior to moving objects */
3686 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3687 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3689 DRM_ERROR("execbuf with invalid offset/length\n");
3693 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3695 /* Zero the global flush/invalidate flags. These
3696 * will be modified as new domains are computed
3699 dev
->invalidate_domains
= 0;
3700 dev
->flush_domains
= 0;
3702 for (i
= 0; i
< args
->buffer_count
; i
++) {
3703 struct drm_gem_object
*obj
= object_list
[i
];
3705 /* Compute new gpu domains and update invalidate/flush */
3706 i915_gem_object_set_to_gpu_domain(obj
);
3709 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3711 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3713 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3715 dev
->invalidate_domains
,
3716 dev
->flush_domains
);
3719 dev
->invalidate_domains
,
3720 dev
->flush_domains
);
3723 if (dev_priv
->render_ring
.outstanding_lazy_request
) {
3724 (void)i915_add_request(dev
, file_priv
, NULL
, &dev_priv
->render_ring
);
3725 dev_priv
->render_ring
.outstanding_lazy_request
= false;
3727 if (dev_priv
->bsd_ring
.outstanding_lazy_request
) {
3728 (void)i915_add_request(dev
, file_priv
, NULL
, &dev_priv
->bsd_ring
);
3729 dev_priv
->bsd_ring
.outstanding_lazy_request
= false;
3732 for (i
= 0; i
< args
->buffer_count
; i
++) {
3733 struct drm_gem_object
*obj
= object_list
[i
];
3734 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3735 uint32_t old_write_domain
= obj
->write_domain
;
3737 obj
->write_domain
= obj
->pending_write_domain
;
3738 if (obj
->write_domain
)
3739 list_move_tail(&obj_priv
->gpu_write_list
,
3740 &dev_priv
->mm
.gpu_write_list
);
3742 list_del_init(&obj_priv
->gpu_write_list
);
3744 trace_i915_gem_object_change_domain(obj
,
3749 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3752 for (i
= 0; i
< args
->buffer_count
; i
++) {
3753 i915_gem_object_check_coherency(object_list
[i
],
3754 exec_list
[i
].handle
);
3759 i915_gem_dump_object(batch_obj
,
3765 /* Exec the batchbuffer */
3766 ret
= ring
->dispatch_gem_execbuffer(dev
, ring
, args
,
3767 cliprects
, exec_offset
);
3769 DRM_ERROR("dispatch failed %d\n", ret
);
3774 * Ensure that the commands in the batch buffer are
3775 * finished before the interrupt fires
3777 i915_retire_commands(dev
, ring
);
3779 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3781 for (i
= 0; i
< args
->buffer_count
; i
++) {
3782 struct drm_gem_object
*obj
= object_list
[i
];
3783 obj_priv
= to_intel_bo(obj
);
3785 i915_gem_object_move_to_active(obj
, ring
);
3787 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
3792 * Get a seqno representing the execution of the current buffer,
3793 * which we can wait on. We would like to mitigate these interrupts,
3794 * likely by only creating seqnos occasionally (so that we have
3795 * *some* interrupts representing completion of buffers that we can
3796 * wait on when trying to clear up gtt space).
3798 seqno
= i915_add_request(dev
, file_priv
, request
, ring
);
3802 i915_dump_lru(dev
, __func__
);
3805 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3808 for (i
= 0; i
< pinned
; i
++)
3809 i915_gem_object_unpin(object_list
[i
]);
3811 for (i
= 0; i
< args
->buffer_count
; i
++) {
3812 if (object_list
[i
]) {
3813 obj_priv
= to_intel_bo(object_list
[i
]);
3814 obj_priv
->in_execbuffer
= false;
3816 drm_gem_object_unreference(object_list
[i
]);
3819 mutex_unlock(&dev
->struct_mutex
);
3822 /* Copy the updated relocations out regardless of current error
3823 * state. Failure to update the relocs would mean that the next
3824 * time userland calls execbuf, it would do so with presumed offset
3825 * state that didn't match the actual object state.
3827 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
3830 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
3836 drm_free_large(object_list
);
3844 * Legacy execbuffer just creates an exec2 list from the original exec object
3845 * list array and passes it to the real function.
3848 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3849 struct drm_file
*file_priv
)
3851 struct drm_i915_gem_execbuffer
*args
= data
;
3852 struct drm_i915_gem_execbuffer2 exec2
;
3853 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3854 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3858 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3859 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3862 if (args
->buffer_count
< 1) {
3863 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3867 /* Copy in the exec list from userland */
3868 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
3869 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3870 if (exec_list
== NULL
|| exec2_list
== NULL
) {
3871 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3872 args
->buffer_count
);
3873 drm_free_large(exec_list
);
3874 drm_free_large(exec2_list
);
3877 ret
= copy_from_user(exec_list
,
3878 (struct drm_i915_relocation_entry __user
*)
3879 (uintptr_t) args
->buffers_ptr
,
3880 sizeof(*exec_list
) * args
->buffer_count
);
3882 DRM_ERROR("copy %d exec entries failed %d\n",
3883 args
->buffer_count
, ret
);
3884 drm_free_large(exec_list
);
3885 drm_free_large(exec2_list
);
3889 for (i
= 0; i
< args
->buffer_count
; i
++) {
3890 exec2_list
[i
].handle
= exec_list
[i
].handle
;
3891 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
3892 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
3893 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
3894 exec2_list
[i
].offset
= exec_list
[i
].offset
;
3896 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
3898 exec2_list
[i
].flags
= 0;
3901 exec2
.buffers_ptr
= args
->buffers_ptr
;
3902 exec2
.buffer_count
= args
->buffer_count
;
3903 exec2
.batch_start_offset
= args
->batch_start_offset
;
3904 exec2
.batch_len
= args
->batch_len
;
3905 exec2
.DR1
= args
->DR1
;
3906 exec2
.DR4
= args
->DR4
;
3907 exec2
.num_cliprects
= args
->num_cliprects
;
3908 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
3909 exec2
.flags
= I915_EXEC_RENDER
;
3911 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
3913 /* Copy the new buffer offsets back to the user's exec list. */
3914 for (i
= 0; i
< args
->buffer_count
; i
++)
3915 exec_list
[i
].offset
= exec2_list
[i
].offset
;
3916 /* ... and back out to userspace */
3917 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
3918 (uintptr_t) args
->buffers_ptr
,
3920 sizeof(*exec_list
) * args
->buffer_count
);
3923 DRM_ERROR("failed to copy %d exec entries "
3924 "back to user (%d)\n",
3925 args
->buffer_count
, ret
);
3929 drm_free_large(exec_list
);
3930 drm_free_large(exec2_list
);
3935 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3936 struct drm_file
*file_priv
)
3938 struct drm_i915_gem_execbuffer2
*args
= data
;
3939 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3943 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3944 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3947 if (args
->buffer_count
< 1) {
3948 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
3952 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3953 if (exec2_list
== NULL
) {
3954 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3955 args
->buffer_count
);
3958 ret
= copy_from_user(exec2_list
,
3959 (struct drm_i915_relocation_entry __user
*)
3960 (uintptr_t) args
->buffers_ptr
,
3961 sizeof(*exec2_list
) * args
->buffer_count
);
3963 DRM_ERROR("copy %d exec entries failed %d\n",
3964 args
->buffer_count
, ret
);
3965 drm_free_large(exec2_list
);
3969 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
3971 /* Copy the new buffer offsets back to the user's exec list. */
3972 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
3973 (uintptr_t) args
->buffers_ptr
,
3975 sizeof(*exec2_list
) * args
->buffer_count
);
3978 DRM_ERROR("failed to copy %d exec entries "
3979 "back to user (%d)\n",
3980 args
->buffer_count
, ret
);
3984 drm_free_large(exec2_list
);
3989 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
3991 struct drm_device
*dev
= obj
->dev
;
3992 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3995 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
3997 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3999 if (obj_priv
->gtt_space
!= NULL
) {
4001 alignment
= i915_gem_get_gtt_alignment(obj
);
4002 if (obj_priv
->gtt_offset
& (alignment
- 1)) {
4003 WARN(obj_priv
->pin_count
,
4004 "bo is already pinned with incorrect alignment:"
4005 " offset=%x, req.alignment=%x\n",
4006 obj_priv
->gtt_offset
, alignment
);
4007 ret
= i915_gem_object_unbind(obj
);
4013 if (obj_priv
->gtt_space
== NULL
) {
4014 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4019 obj_priv
->pin_count
++;
4021 /* If the object is not active and not pending a flush,
4022 * remove it from the inactive list
4024 if (obj_priv
->pin_count
== 1) {
4025 atomic_inc(&dev
->pin_count
);
4026 atomic_add(obj
->size
, &dev
->pin_memory
);
4027 if (!obj_priv
->active
&&
4028 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4029 list_del_init(&obj_priv
->list
);
4031 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4037 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4039 struct drm_device
*dev
= obj
->dev
;
4040 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4041 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4043 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4044 obj_priv
->pin_count
--;
4045 BUG_ON(obj_priv
->pin_count
< 0);
4046 BUG_ON(obj_priv
->gtt_space
== NULL
);
4048 /* If the object is no longer pinned, and is
4049 * neither active nor being flushed, then stick it on
4052 if (obj_priv
->pin_count
== 0) {
4053 if (!obj_priv
->active
&&
4054 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4055 list_move_tail(&obj_priv
->list
,
4056 &dev_priv
->mm
.inactive_list
);
4057 atomic_dec(&dev
->pin_count
);
4058 atomic_sub(obj
->size
, &dev
->pin_memory
);
4060 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4064 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4065 struct drm_file
*file_priv
)
4067 struct drm_i915_gem_pin
*args
= data
;
4068 struct drm_gem_object
*obj
;
4069 struct drm_i915_gem_object
*obj_priv
;
4072 mutex_lock(&dev
->struct_mutex
);
4074 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4076 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4078 mutex_unlock(&dev
->struct_mutex
);
4081 obj_priv
= to_intel_bo(obj
);
4083 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4084 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4085 drm_gem_object_unreference(obj
);
4086 mutex_unlock(&dev
->struct_mutex
);
4090 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4091 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4093 drm_gem_object_unreference(obj
);
4094 mutex_unlock(&dev
->struct_mutex
);
4098 obj_priv
->user_pin_count
++;
4099 obj_priv
->pin_filp
= file_priv
;
4100 if (obj_priv
->user_pin_count
== 1) {
4101 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4103 drm_gem_object_unreference(obj
);
4104 mutex_unlock(&dev
->struct_mutex
);
4109 /* XXX - flush the CPU caches for pinned objects
4110 * as the X server doesn't manage domains yet
4112 i915_gem_object_flush_cpu_write_domain(obj
);
4113 args
->offset
= obj_priv
->gtt_offset
;
4114 drm_gem_object_unreference(obj
);
4115 mutex_unlock(&dev
->struct_mutex
);
4121 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4122 struct drm_file
*file_priv
)
4124 struct drm_i915_gem_pin
*args
= data
;
4125 struct drm_gem_object
*obj
;
4126 struct drm_i915_gem_object
*obj_priv
;
4128 mutex_lock(&dev
->struct_mutex
);
4130 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4132 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4134 mutex_unlock(&dev
->struct_mutex
);
4138 obj_priv
= to_intel_bo(obj
);
4139 if (obj_priv
->pin_filp
!= file_priv
) {
4140 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4142 drm_gem_object_unreference(obj
);
4143 mutex_unlock(&dev
->struct_mutex
);
4146 obj_priv
->user_pin_count
--;
4147 if (obj_priv
->user_pin_count
== 0) {
4148 obj_priv
->pin_filp
= NULL
;
4149 i915_gem_object_unpin(obj
);
4152 drm_gem_object_unreference(obj
);
4153 mutex_unlock(&dev
->struct_mutex
);
4158 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4159 struct drm_file
*file_priv
)
4161 struct drm_i915_gem_busy
*args
= data
;
4162 struct drm_gem_object
*obj
;
4163 struct drm_i915_gem_object
*obj_priv
;
4165 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4167 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4172 mutex_lock(&dev
->struct_mutex
);
4174 /* Count all active objects as busy, even if they are currently not used
4175 * by the gpu. Users of this interface expect objects to eventually
4176 * become non-busy without any further actions, therefore emit any
4177 * necessary flushes here.
4179 obj_priv
= to_intel_bo(obj
);
4180 args
->busy
= obj_priv
->active
;
4182 /* Unconditionally flush objects, even when the gpu still uses this
4183 * object. Userspace calling this function indicates that it wants to
4184 * use this buffer rather sooner than later, so issuing the required
4185 * flush earlier is beneficial.
4187 if (obj
->write_domain
) {
4188 i915_gem_flush(dev
, 0, obj
->write_domain
);
4189 (void)i915_add_request(dev
, file_priv
, NULL
, obj_priv
->ring
);
4192 /* Update the active list for the hardware's current position.
4193 * Otherwise this only updates on a delayed timer or when irqs
4194 * are actually unmasked, and our working set ends up being
4195 * larger than required.
4197 i915_gem_retire_requests_ring(dev
, obj_priv
->ring
);
4199 args
->busy
= obj_priv
->active
;
4202 drm_gem_object_unreference(obj
);
4203 mutex_unlock(&dev
->struct_mutex
);
4208 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4209 struct drm_file
*file_priv
)
4211 return i915_gem_ring_throttle(dev
, file_priv
);
4215 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4216 struct drm_file
*file_priv
)
4218 struct drm_i915_gem_madvise
*args
= data
;
4219 struct drm_gem_object
*obj
;
4220 struct drm_i915_gem_object
*obj_priv
;
4222 switch (args
->madv
) {
4223 case I915_MADV_DONTNEED
:
4224 case I915_MADV_WILLNEED
:
4230 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4232 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4237 mutex_lock(&dev
->struct_mutex
);
4238 obj_priv
= to_intel_bo(obj
);
4240 if (obj_priv
->pin_count
) {
4241 drm_gem_object_unreference(obj
);
4242 mutex_unlock(&dev
->struct_mutex
);
4244 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4248 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4249 obj_priv
->madv
= args
->madv
;
4251 /* if the object is no longer bound, discard its backing storage */
4252 if (i915_gem_object_is_purgeable(obj_priv
) &&
4253 obj_priv
->gtt_space
== NULL
)
4254 i915_gem_object_truncate(obj
);
4256 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4258 drm_gem_object_unreference(obj
);
4259 mutex_unlock(&dev
->struct_mutex
);
4264 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4267 struct drm_i915_gem_object
*obj
;
4269 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4273 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4278 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4279 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4281 obj
->agp_type
= AGP_USER_MEMORY
;
4282 obj
->base
.driver_private
= NULL
;
4283 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4284 INIT_LIST_HEAD(&obj
->list
);
4285 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4286 obj
->madv
= I915_MADV_WILLNEED
;
4288 trace_i915_gem_object_create(&obj
->base
);
4293 int i915_gem_init_object(struct drm_gem_object
*obj
)
4300 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4302 struct drm_device
*dev
= obj
->dev
;
4303 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4304 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4307 ret
= i915_gem_object_unbind(obj
);
4308 if (ret
== -ERESTARTSYS
) {
4309 list_move(&obj_priv
->list
,
4310 &dev_priv
->mm
.deferred_free_list
);
4314 if (obj_priv
->mmap_offset
)
4315 i915_gem_free_mmap_offset(obj
);
4317 drm_gem_object_release(obj
);
4319 kfree(obj_priv
->page_cpu_valid
);
4320 kfree(obj_priv
->bit_17
);
4324 void i915_gem_free_object(struct drm_gem_object
*obj
)
4326 struct drm_device
*dev
= obj
->dev
;
4327 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4329 trace_i915_gem_object_destroy(obj
);
4331 while (obj_priv
->pin_count
> 0)
4332 i915_gem_object_unpin(obj
);
4334 if (obj_priv
->phys_obj
)
4335 i915_gem_detach_phys_object(dev
, obj
);
4337 i915_gem_free_object_tail(obj
);
4341 i915_gem_idle(struct drm_device
*dev
)
4343 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4346 mutex_lock(&dev
->struct_mutex
);
4348 if (dev_priv
->mm
.suspended
||
4349 (dev_priv
->render_ring
.gem_object
== NULL
) ||
4351 dev_priv
->bsd_ring
.gem_object
== NULL
)) {
4352 mutex_unlock(&dev
->struct_mutex
);
4356 ret
= i915_gpu_idle(dev
);
4358 mutex_unlock(&dev
->struct_mutex
);
4362 /* Under UMS, be paranoid and evict. */
4363 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4364 ret
= i915_gem_evict_inactive(dev
);
4366 mutex_unlock(&dev
->struct_mutex
);
4371 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4372 * We need to replace this with a semaphore, or something.
4373 * And not confound mm.suspended!
4375 dev_priv
->mm
.suspended
= 1;
4376 del_timer_sync(&dev_priv
->hangcheck_timer
);
4378 i915_kernel_lost_context(dev
);
4379 i915_gem_cleanup_ringbuffer(dev
);
4381 mutex_unlock(&dev
->struct_mutex
);
4383 /* Cancel the retire work handler, which should be idle now. */
4384 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4390 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4391 * over cache flushing.
4394 i915_gem_init_pipe_control(struct drm_device
*dev
)
4396 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4397 struct drm_gem_object
*obj
;
4398 struct drm_i915_gem_object
*obj_priv
;
4401 obj
= i915_gem_alloc_object(dev
, 4096);
4403 DRM_ERROR("Failed to allocate seqno page\n");
4407 obj_priv
= to_intel_bo(obj
);
4408 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4410 ret
= i915_gem_object_pin(obj
, 4096);
4414 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4415 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4416 if (dev_priv
->seqno_page
== NULL
)
4419 dev_priv
->seqno_obj
= obj
;
4420 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4425 i915_gem_object_unpin(obj
);
4427 drm_gem_object_unreference(obj
);
4434 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4436 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4437 struct drm_gem_object
*obj
;
4438 struct drm_i915_gem_object
*obj_priv
;
4440 obj
= dev_priv
->seqno_obj
;
4441 obj_priv
= to_intel_bo(obj
);
4442 kunmap(obj_priv
->pages
[0]);
4443 i915_gem_object_unpin(obj
);
4444 drm_gem_object_unreference(obj
);
4445 dev_priv
->seqno_obj
= NULL
;
4447 dev_priv
->seqno_page
= NULL
;
4451 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4453 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4456 dev_priv
->render_ring
= render_ring
;
4458 if (!I915_NEED_GFX_HWS(dev
)) {
4459 dev_priv
->render_ring
.status_page
.page_addr
4460 = dev_priv
->status_page_dmah
->vaddr
;
4461 memset(dev_priv
->render_ring
.status_page
.page_addr
,
4465 if (HAS_PIPE_CONTROL(dev
)) {
4466 ret
= i915_gem_init_pipe_control(dev
);
4471 ret
= intel_init_ring_buffer(dev
, &dev_priv
->render_ring
);
4473 goto cleanup_pipe_control
;
4476 dev_priv
->bsd_ring
= bsd_ring
;
4477 ret
= intel_init_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4479 goto cleanup_render_ring
;
4482 dev_priv
->next_seqno
= 1;
4486 cleanup_render_ring
:
4487 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4488 cleanup_pipe_control
:
4489 if (HAS_PIPE_CONTROL(dev
))
4490 i915_gem_cleanup_pipe_control(dev
);
4495 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4497 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4499 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4501 intel_cleanup_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4502 if (HAS_PIPE_CONTROL(dev
))
4503 i915_gem_cleanup_pipe_control(dev
);
4507 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4508 struct drm_file
*file_priv
)
4510 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4513 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4516 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4517 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4518 atomic_set(&dev_priv
->mm
.wedged
, 0);
4521 mutex_lock(&dev
->struct_mutex
);
4522 dev_priv
->mm
.suspended
= 0;
4524 ret
= i915_gem_init_ringbuffer(dev
);
4526 mutex_unlock(&dev
->struct_mutex
);
4530 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4531 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.active_list
));
4532 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4533 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4534 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4535 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.request_list
));
4536 mutex_unlock(&dev
->struct_mutex
);
4538 ret
= drm_irq_install(dev
);
4540 goto cleanup_ringbuffer
;
4545 mutex_lock(&dev
->struct_mutex
);
4546 i915_gem_cleanup_ringbuffer(dev
);
4547 dev_priv
->mm
.suspended
= 1;
4548 mutex_unlock(&dev
->struct_mutex
);
4554 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4555 struct drm_file
*file_priv
)
4557 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4560 drm_irq_uninstall(dev
);
4561 return i915_gem_idle(dev
);
4565 i915_gem_lastclose(struct drm_device
*dev
)
4569 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4572 ret
= i915_gem_idle(dev
);
4574 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4578 i915_gem_load(struct drm_device
*dev
)
4581 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4583 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4584 INIT_LIST_HEAD(&dev_priv
->mm
.gpu_write_list
);
4585 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4586 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4587 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4588 INIT_LIST_HEAD(&dev_priv
->render_ring
.active_list
);
4589 INIT_LIST_HEAD(&dev_priv
->render_ring
.request_list
);
4591 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.active_list
);
4592 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.request_list
);
4594 for (i
= 0; i
< 16; i
++)
4595 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4596 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4597 i915_gem_retire_work_handler
);
4598 spin_lock(&shrink_list_lock
);
4599 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4600 spin_unlock(&shrink_list_lock
);
4602 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4604 u32 tmp
= I915_READ(MI_ARB_STATE
);
4605 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4606 /* arb state is a masked write, so set bit + bit in mask */
4607 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4608 I915_WRITE(MI_ARB_STATE
, tmp
);
4612 /* Old X drivers will take 0-2 for front, back, depth buffers */
4613 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4614 dev_priv
->fence_reg_start
= 3;
4616 if (IS_I965G(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4617 dev_priv
->num_fence_regs
= 16;
4619 dev_priv
->num_fence_regs
= 8;
4621 /* Initialize fence registers to zero */
4622 if (IS_I965G(dev
)) {
4623 for (i
= 0; i
< 16; i
++)
4624 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4626 for (i
= 0; i
< 8; i
++)
4627 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4628 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4629 for (i
= 0; i
< 8; i
++)
4630 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4632 i915_gem_detect_bit_6_swizzle(dev
);
4633 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4637 * Create a physically contiguous memory object for this object
4638 * e.g. for cursor + overlay regs
4640 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4641 int id
, int size
, int align
)
4643 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4644 struct drm_i915_gem_phys_object
*phys_obj
;
4647 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4650 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4656 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4657 if (!phys_obj
->handle
) {
4662 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4665 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4673 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4675 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4676 struct drm_i915_gem_phys_object
*phys_obj
;
4678 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4681 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4682 if (phys_obj
->cur_obj
) {
4683 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4687 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4689 drm_pci_free(dev
, phys_obj
->handle
);
4691 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4694 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4698 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4699 i915_gem_free_phys_object(dev
, i
);
4702 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4703 struct drm_gem_object
*obj
)
4705 struct drm_i915_gem_object
*obj_priv
;
4710 obj_priv
= to_intel_bo(obj
);
4711 if (!obj_priv
->phys_obj
)
4714 ret
= i915_gem_object_get_pages(obj
, 0);
4718 page_count
= obj
->size
/ PAGE_SIZE
;
4720 for (i
= 0; i
< page_count
; i
++) {
4721 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4722 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4724 memcpy(dst
, src
, PAGE_SIZE
);
4725 kunmap_atomic(dst
, KM_USER0
);
4727 drm_clflush_pages(obj_priv
->pages
, page_count
);
4728 drm_agp_chipset_flush(dev
);
4730 i915_gem_object_put_pages(obj
);
4732 obj_priv
->phys_obj
->cur_obj
= NULL
;
4733 obj_priv
->phys_obj
= NULL
;
4737 i915_gem_attach_phys_object(struct drm_device
*dev
,
4738 struct drm_gem_object
*obj
,
4742 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4743 struct drm_i915_gem_object
*obj_priv
;
4748 if (id
> I915_MAX_PHYS_OBJECT
)
4751 obj_priv
= to_intel_bo(obj
);
4753 if (obj_priv
->phys_obj
) {
4754 if (obj_priv
->phys_obj
->id
== id
)
4756 i915_gem_detach_phys_object(dev
, obj
);
4759 /* create a new object */
4760 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4761 ret
= i915_gem_init_phys_object(dev
, id
,
4764 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4769 /* bind to the object */
4770 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4771 obj_priv
->phys_obj
->cur_obj
= obj
;
4773 ret
= i915_gem_object_get_pages(obj
, 0);
4775 DRM_ERROR("failed to get page list\n");
4779 page_count
= obj
->size
/ PAGE_SIZE
;
4781 for (i
= 0; i
< page_count
; i
++) {
4782 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4783 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4785 memcpy(dst
, src
, PAGE_SIZE
);
4786 kunmap_atomic(src
, KM_USER0
);
4789 i915_gem_object_put_pages(obj
);
4797 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4798 struct drm_i915_gem_pwrite
*args
,
4799 struct drm_file
*file_priv
)
4801 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4804 char __user
*user_data
;
4806 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4807 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4809 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4810 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4814 drm_agp_chipset_flush(dev
);
4818 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
)
4820 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
4822 /* Clean up our request list when the client is going away, so that
4823 * later retire_requests won't dereference our soon-to-be-gone
4826 mutex_lock(&dev
->struct_mutex
);
4827 while (!list_empty(&i915_file_priv
->mm
.request_list
))
4828 list_del_init(i915_file_priv
->mm
.request_list
.next
);
4829 mutex_unlock(&dev
->struct_mutex
);
4833 i915_gpu_is_active(struct drm_device
*dev
)
4835 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4838 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4839 list_empty(&dev_priv
->render_ring
.active_list
);
4841 lists_empty
&= list_empty(&dev_priv
->bsd_ring
.active_list
);
4843 return !lists_empty
;
4847 i915_gem_shrink(struct shrinker
*shrink
, int nr_to_scan
, gfp_t gfp_mask
)
4849 drm_i915_private_t
*dev_priv
, *next_dev
;
4850 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
4852 int would_deadlock
= 1;
4854 /* "fast-path" to count number of available objects */
4855 if (nr_to_scan
== 0) {
4856 spin_lock(&shrink_list_lock
);
4857 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4858 struct drm_device
*dev
= dev_priv
->dev
;
4860 if (mutex_trylock(&dev
->struct_mutex
)) {
4861 list_for_each_entry(obj_priv
,
4862 &dev_priv
->mm
.inactive_list
,
4865 mutex_unlock(&dev
->struct_mutex
);
4868 spin_unlock(&shrink_list_lock
);
4870 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4873 spin_lock(&shrink_list_lock
);
4876 /* first scan for clean buffers */
4877 list_for_each_entry_safe(dev_priv
, next_dev
,
4878 &shrink_list
, mm
.shrink_list
) {
4879 struct drm_device
*dev
= dev_priv
->dev
;
4881 if (! mutex_trylock(&dev
->struct_mutex
))
4884 spin_unlock(&shrink_list_lock
);
4885 i915_gem_retire_requests(dev
);
4887 list_for_each_entry_safe(obj_priv
, next_obj
,
4888 &dev_priv
->mm
.inactive_list
,
4890 if (i915_gem_object_is_purgeable(obj_priv
)) {
4891 i915_gem_object_unbind(&obj_priv
->base
);
4892 if (--nr_to_scan
<= 0)
4897 spin_lock(&shrink_list_lock
);
4898 mutex_unlock(&dev
->struct_mutex
);
4902 if (nr_to_scan
<= 0)
4906 /* second pass, evict/count anything still on the inactive list */
4907 list_for_each_entry_safe(dev_priv
, next_dev
,
4908 &shrink_list
, mm
.shrink_list
) {
4909 struct drm_device
*dev
= dev_priv
->dev
;
4911 if (! mutex_trylock(&dev
->struct_mutex
))
4914 spin_unlock(&shrink_list_lock
);
4916 list_for_each_entry_safe(obj_priv
, next_obj
,
4917 &dev_priv
->mm
.inactive_list
,
4919 if (nr_to_scan
> 0) {
4920 i915_gem_object_unbind(&obj_priv
->base
);
4926 spin_lock(&shrink_list_lock
);
4927 mutex_unlock(&dev
->struct_mutex
);
4936 * We are desperate for pages, so as a last resort, wait
4937 * for the GPU to finish and discard whatever we can.
4938 * This has a dramatic impact to reduce the number of
4939 * OOM-killer events whilst running the GPU aggressively.
4941 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4942 struct drm_device
*dev
= dev_priv
->dev
;
4944 if (!mutex_trylock(&dev
->struct_mutex
))
4947 spin_unlock(&shrink_list_lock
);
4949 if (i915_gpu_is_active(dev
)) {
4954 spin_lock(&shrink_list_lock
);
4955 mutex_unlock(&dev
->struct_mutex
);
4962 spin_unlock(&shrink_list_lock
);
4967 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4972 static struct shrinker shrinker
= {
4973 .shrink
= i915_gem_shrink
,
4974 .seeks
= DEFAULT_SEEKS
,
4978 i915_gem_shrinker_init(void)
4980 register_shrinker(&shrinker
);
4984 i915_gem_shrinker_exit(void)
4986 unregister_shrinker(&shrinker
);