1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <drm/intel-gtt.h>
39 /* General customization:
42 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
44 #define DRIVER_NAME "i915"
45 #define DRIVER_DESC "Intel Graphics"
46 #define DRIVER_DATE "20080730"
58 #define I915_NUM_PIPE 2
60 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
65 * 1.2: Add Power Management
66 * 1.3: Add vblank support
67 * 1.4: Fix cmdbuffer path, add heap destroy
68 * 1.5: Add vblank pipe configuration
69 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
70 * - Support vertical blank on secondary display pipe
72 #define DRIVER_MAJOR 1
73 #define DRIVER_MINOR 6
74 #define DRIVER_PATCHLEVEL 0
76 #define WATCH_COHERENCY 0
81 #define WATCH_INACTIVE 0
82 #define WATCH_PWRITE 0
84 #define I915_GEM_PHYS_CURSOR_0 1
85 #define I915_GEM_PHYS_CURSOR_1 2
86 #define I915_GEM_PHYS_OVERLAY_REGS 3
87 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
89 struct drm_i915_gem_phys_object
{
91 struct page
**page_list
;
92 drm_dma_handle_t
*handle
;
93 struct drm_gem_object
*cur_obj
;
97 struct mem_block
*next
;
98 struct mem_block
*prev
;
101 struct drm_file
*file_priv
; /* NULL: free, -1: heap, other: real files */
104 struct opregion_header
;
105 struct opregion_acpi
;
106 struct opregion_swsci
;
107 struct opregion_asle
;
109 struct intel_opregion
{
110 struct opregion_header
*header
;
111 struct opregion_acpi
*acpi
;
112 struct opregion_swsci
*swsci
;
113 struct opregion_asle
*asle
;
116 #define OPREGION_SIZE (8*1024)
118 struct intel_overlay
;
119 struct intel_overlay_error_state
;
121 struct drm_i915_master_private
{
122 drm_local_map_t
*sarea
;
123 struct _drm_i915_sarea
*sarea_priv
;
125 #define I915_FENCE_REG_NONE -1
127 struct drm_i915_fence_reg
{
128 struct drm_gem_object
*obj
;
129 struct list_head lru_list
;
132 struct sdvo_device_mapping
{
140 struct drm_i915_error_state
{
155 struct drm_i915_error_object
{
159 } *ringbuffer
, *batchbuffer
[2];
160 struct drm_i915_error_buffer
{
174 struct intel_overlay_error_state
*overlay
;
177 struct drm_i915_display_funcs
{
178 void (*dpms
)(struct drm_crtc
*crtc
, int mode
);
179 bool (*fbc_enabled
)(struct drm_device
*dev
);
180 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
181 void (*disable_fbc
)(struct drm_device
*dev
);
182 int (*get_display_clock_speed
)(struct drm_device
*dev
);
183 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
184 void (*update_wm
)(struct drm_device
*dev
, int planea_clock
,
185 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
187 /* clock updates for mode set */
189 /* render clock increase/decrease */
190 /* display clock increase/decrease */
191 /* pll clock increase/decrease */
192 /* clock gating init */
195 struct intel_device_info
{
209 u8 is_broadwater
: 1;
214 u8 has_pipe_cxsr
: 1;
216 u8 cursor_needs_physical
: 1;
218 u8 overlay_needs_physical
: 1;
222 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
223 FBC_STOLEN_TOO_SMALL
, /* not enough space to hold compressed buffers */
224 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
225 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
226 FBC_BAD_PLANE
, /* fbc not supported on plane */
227 FBC_NOT_TILED
, /* buffer not tiled */
228 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
232 PCH_IBX
, /* Ibexpeak PCH */
233 PCH_CPT
, /* Cougarpoint PCH */
236 #define QUIRK_PIPEA_FORCE (1<<0)
240 typedef struct drm_i915_private
{
241 struct drm_device
*dev
;
243 const struct intel_device_info
*info
;
249 struct pci_dev
*bridge_dev
;
250 struct intel_ring_buffer render_ring
;
251 struct intel_ring_buffer bsd_ring
;
254 drm_dma_handle_t
*status_page_dmah
;
256 dma_addr_t dma_status_page
;
258 unsigned int seqno_gfx_addr
;
259 drm_local_map_t hws_map
;
260 struct drm_gem_object
*seqno_obj
;
261 struct drm_gem_object
*pwrctx
;
262 struct drm_gem_object
*renderctx
;
264 struct resource mch_res
;
271 #define I915_DEBUG_READ (1<<0)
272 #define I915_DEBUG_WRITE (1<<1)
273 unsigned long debug_flags
;
275 wait_queue_head_t irq_queue
;
276 atomic_t irq_received
;
277 /** Protects user_irq_refcount and irq_mask_reg */
278 spinlock_t user_irq_lock
;
280 /** Cached value of IMR to avoid reads in updating the bitfield */
283 /** splitted irq regs for graphics and display engine on Ironlake,
284 irq_mask_reg is still used for display irq. */
286 u32 gt_irq_enable_reg
;
287 u32 de_irq_enable_reg
;
288 u32 pch_irq_mask_reg
;
289 u32 pch_irq_enable_reg
;
291 u32 hotplug_supported_mask
;
292 struct work_struct hotplug_work
;
294 int tex_lru_log_granularity
;
295 int allow_batchbuffer
;
296 struct mem_block
*agp_heap
;
297 unsigned int sr01
, adpa
, ppcr
, dvob
, dvoc
, lvds
;
301 /* For hangcheck timer */
302 #define DRM_I915_HANGCHECK_PERIOD 250 /* in ms */
303 struct timer_list hangcheck_timer
;
306 uint32_t last_instdone
;
307 uint32_t last_instdone1
;
309 unsigned long cfb_size
;
310 unsigned long cfb_pitch
;
311 unsigned long cfb_offset
;
318 struct intel_opregion opregion
;
321 struct intel_overlay
*overlay
;
324 int backlight_level
; /* restore backlight to this value */
325 bool panel_wants_dither
;
326 struct drm_display_mode
*panel_fixed_mode
;
327 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
328 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
330 /* Feature bits from the VBIOS */
331 unsigned int int_tv_support
:1;
332 unsigned int lvds_dither
:1;
333 unsigned int lvds_vbt
:1;
334 unsigned int int_crt_support
:1;
335 unsigned int lvds_use_ssc
:1;
336 unsigned int edp_support
:1;
340 struct notifier_block lid_notifier
;
342 int crt_ddc_bus
; /* 0 = unknown, else GPIO to use for CRT DDC */
343 struct drm_i915_fence_reg fence_regs
[16]; /* assume 965 */
344 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
345 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
347 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
349 spinlock_t error_lock
;
350 struct drm_i915_error_state
*first_error
;
351 struct work_struct error_work
;
352 struct workqueue_struct
*wq
;
354 /* Display functions */
355 struct drm_i915_display_funcs display
;
357 /* PCH chipset type */
358 enum intel_pch pch_type
;
360 unsigned long quirks
;
385 u32 saveTRANS_HTOTAL_A
;
386 u32 saveTRANS_HBLANK_A
;
387 u32 saveTRANS_HSYNC_A
;
388 u32 saveTRANS_VTOTAL_A
;
389 u32 saveTRANS_VBLANK_A
;
390 u32 saveTRANS_VSYNC_A
;
398 u32 savePFIT_PGM_RATIOS
;
399 u32 saveBLC_HIST_CTL
;
401 u32 saveBLC_PWM_CTL2
;
402 u32 saveBLC_CPU_PWM_CTL
;
403 u32 saveBLC_CPU_PWM_CTL2
;
416 u32 saveTRANS_HTOTAL_B
;
417 u32 saveTRANS_HBLANK_B
;
418 u32 saveTRANS_HSYNC_B
;
419 u32 saveTRANS_VTOTAL_B
;
420 u32 saveTRANS_VBLANK_B
;
421 u32 saveTRANS_VSYNC_B
;
435 u32 savePP_ON_DELAYS
;
436 u32 savePP_OFF_DELAYS
;
444 u32 savePFIT_CONTROL
;
445 u32 save_palette_a
[256];
446 u32 save_palette_b
[256];
447 u32 saveDPFC_CB_BASE
;
448 u32 saveFBC_CFB_BASE
;
451 u32 saveFBC_CONTROL2
;
461 u32 saveCACHE_MODE_0
;
462 u32 saveMI_ARB_STATE
;
473 uint64_t saveFENCE
[16];
484 u32 savePIPEA_GMCH_DATA_M
;
485 u32 savePIPEB_GMCH_DATA_M
;
486 u32 savePIPEA_GMCH_DATA_N
;
487 u32 savePIPEB_GMCH_DATA_N
;
488 u32 savePIPEA_DP_LINK_M
;
489 u32 savePIPEB_DP_LINK_M
;
490 u32 savePIPEA_DP_LINK_N
;
491 u32 savePIPEB_DP_LINK_N
;
502 u32 savePCH_DREF_CONTROL
;
503 u32 saveDISP_ARB_CTL
;
504 u32 savePIPEA_DATA_M1
;
505 u32 savePIPEA_DATA_N1
;
506 u32 savePIPEA_LINK_M1
;
507 u32 savePIPEA_LINK_N1
;
508 u32 savePIPEB_DATA_M1
;
509 u32 savePIPEB_DATA_N1
;
510 u32 savePIPEB_LINK_M1
;
511 u32 savePIPEB_LINK_N1
;
512 u32 saveMCHBAR_RENDER_STANDBY
;
515 /** Bridge to intel-gtt-ko */
516 struct intel_gtt
*gtt
;
517 /** Memory allocator for GTT stolen memory */
519 /** Memory allocator for GTT */
520 struct drm_mm gtt_space
;
522 struct io_mapping
*gtt_mapping
;
526 * Membership on list of all loaded devices, used to evict
527 * inactive buffers under memory pressure.
529 * Modifications should only be done whilst holding the
530 * shrink_list_lock spinlock.
532 struct list_head shrink_list
;
535 * List of objects which are not in the ringbuffer but which
536 * still have a write_domain which needs to be flushed before
539 * last_rendering_seqno is 0 while an object is in this list.
541 * A reference is held on the buffer while on this list.
543 struct list_head flushing_list
;
546 * List of objects currently pending a GPU write flush.
548 * All elements on this list will belong to either the
549 * active_list or flushing_list, last_rendering_seqno can
550 * be used to differentiate between the two elements.
552 struct list_head gpu_write_list
;
555 * LRU list of objects which are not in the ringbuffer and
556 * are ready to unbind, but are still in the GTT.
558 * last_rendering_seqno is 0 while an object is in this list.
560 * A reference is not held on the buffer while on this list,
561 * as merely being GTT-bound shouldn't prevent its being
562 * freed, and we'll pull it off the list in the free path.
564 struct list_head inactive_list
;
566 /** LRU list of objects with fence regs on them. */
567 struct list_head fence_list
;
570 * List of objects currently pending being freed.
572 * These objects are no longer in use, but due to a signal
573 * we were prevented from freeing them at the appointed time.
575 struct list_head deferred_free_list
;
578 * We leave the user IRQ off as much as possible,
579 * but this means that requests will finish and never
580 * be retired once the system goes idle. Set a timer to
581 * fire periodically while the ring is running. When it
582 * fires, go retire requests.
584 struct delayed_work retire_work
;
587 * Waiting sequence number, if any
589 uint32_t waiting_gem_seqno
;
592 * Last seq seen at irq time
594 uint32_t irq_gem_seqno
;
597 * Flag if the X Server, and thus DRM, is not currently in
598 * control of the device.
600 * This is set between LeaveVT and EnterVT. It needs to be
601 * replaced with a semaphore. It also needs to be
602 * transitioned away from for kernel modesetting.
607 * Flag if the hardware appears to be wedged.
609 * This is set when attempts to idle the device timeout.
610 * It prevents command submission from occuring and makes
611 * every pending request fail
615 /** Bit 6 swizzling required for X tiling */
616 uint32_t bit_6_swizzle_x
;
617 /** Bit 6 swizzling required for Y tiling */
618 uint32_t bit_6_swizzle_y
;
620 /* storage for physical objects */
621 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
623 struct sdvo_device_mapping sdvo_mappings
[2];
624 /* indicate whether the LVDS_BORDER should be enabled or not */
625 unsigned int lvds_border_bits
;
626 /* Panel fitter placement and size for Ironlake+ */
627 u32 pch_pf_pos
, pch_pf_size
;
629 struct drm_crtc
*plane_to_crtc_mapping
[2];
630 struct drm_crtc
*pipe_to_crtc_mapping
[2];
631 wait_queue_head_t pending_flip_queue
;
632 bool flip_pending_is_done
;
634 /* Reclocking support */
635 bool render_reclock_avail
;
636 bool lvds_downclock_avail
;
637 /* indicates the reduced downclock for LVDS*/
639 struct work_struct idle_work
;
640 struct timer_list idle_timer
;
644 struct child_device_config
*child_dev
;
645 struct drm_connector
*int_lvds_connector
;
647 bool mchbar_need_disable
;
656 unsigned long last_time1
;
658 struct timespec last_time2
;
659 unsigned long gfx_power
;
663 spinlock_t
*mchdev_lock
;
665 enum no_fbc_reason no_fbc_reason
;
667 struct drm_mm_node
*compressed_fb
;
668 struct drm_mm_node
*compressed_llb
;
670 /* list of fbdev register on this device */
671 struct intel_fbdev
*fbdev
;
672 } drm_i915_private_t
;
674 /** driver private structure attached to each drm_gem_object */
675 struct drm_i915_gem_object
{
676 struct drm_gem_object base
;
678 /** Current space allocated to this object in the GTT, if any. */
679 struct drm_mm_node
*gtt_space
;
681 /** This object's place on the active/flushing/inactive lists */
682 struct list_head list
;
683 /** This object's place on GPU write list */
684 struct list_head gpu_write_list
;
685 /** This object's place on eviction list */
686 struct list_head evict_list
;
689 * This is set if the object is on the active or flushing lists
690 * (has pending rendering), and is not set if it's on inactive (ready
693 unsigned int active
: 1;
696 * This is set if the object has been written to since last bound
699 unsigned int dirty
: 1;
702 * Fence register bits (if any) for this object. Will be set
703 * as needed when mapped into the GTT.
704 * Protected by dev->struct_mutex.
706 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
708 signed int fence_reg
: 5;
711 * Used for checking the object doesn't appear more than once
712 * in an execbuffer object list.
714 unsigned int in_execbuffer
: 1;
717 * Advice: are the backing pages purgeable?
719 unsigned int madv
: 2;
722 * Refcount for the pages array. With the current locking scheme, there
723 * are at most two concurrent users: Binding a bo to the gtt and
724 * pwrite/pread using physical addresses. So two bits for a maximum
725 * of two users are enough.
727 unsigned int pages_refcount
: 2;
728 #define DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT 0x3
731 * Current tiling mode for the object.
733 unsigned int tiling_mode
: 2;
735 /** How many users have pinned this object in GTT space. The following
736 * users can each hold at most one reference: pwrite/pread, pin_ioctl
737 * (via user_pin_count), execbuffer (objects are not allowed multiple
738 * times for the same batchbuffer), and the framebuffer code. When
739 * switching/pageflipping, the framebuffer code has at most two buffers
742 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
743 * bits with absolutely no headroom. So use 4 bits. */
744 unsigned int pin_count
: 4;
745 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
747 /** AGP memory structure for our GTT binding. */
748 DRM_AGP_MEM
*agp_mem
;
753 * Current offset of the object in GTT space.
755 * This is the same as gtt_space->start
759 /* Which ring is refering to is this object */
760 struct intel_ring_buffer
*ring
;
763 * Fake offset for use by mmap(2)
765 uint64_t mmap_offset
;
767 /** Breadcrumb of last rendering to the buffer. */
768 uint32_t last_rendering_seqno
;
770 /** Current tiling stride for the object, if it's tiled. */
773 /** Record of address bit 17 of each page at last unbind. */
774 unsigned long *bit_17
;
776 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
780 * If present, while GEM_DOMAIN_CPU is in the read domain this array
781 * flags which individual pages are valid.
783 uint8_t *page_cpu_valid
;
785 /** User space pin count and filp owning the pin */
786 uint32_t user_pin_count
;
787 struct drm_file
*pin_filp
;
789 /** for phy allocated objects */
790 struct drm_i915_gem_phys_object
*phys_obj
;
793 * Number of crtcs where this object is currently the fb, but
794 * will be page flipped away on the next vblank. When it
795 * reaches 0, dev_priv->pending_flip_queue will be woken up.
797 atomic_t pending_flip
;
800 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
803 * Request queue structure.
805 * The request queue allows us to note sequence numbers that have been emitted
806 * and may be associated with active buffers to be retired.
808 * By keeping this list, we can avoid having to do questionable
809 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
810 * an emission time with seqnos for tracking how far ahead of the GPU we are.
812 struct drm_i915_gem_request
{
813 /** On Which ring this request was generated */
814 struct intel_ring_buffer
*ring
;
816 /** GEM sequence number associated with this request. */
819 /** Time at which this request was emitted, in jiffies. */
820 unsigned long emitted_jiffies
;
822 /** global list entry for this request */
823 struct list_head list
;
825 /** file_priv list entry for this request */
826 struct list_head client_list
;
829 struct drm_i915_file_private
{
831 struct list_head request_list
;
835 enum intel_chip_family
{
842 extern struct drm_ioctl_desc i915_ioctls
[];
843 extern int i915_max_ioctl
;
844 extern unsigned int i915_fbpercrtc
;
845 extern unsigned int i915_powersave
;
846 extern unsigned int i915_lvds_downclock
;
848 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
849 extern int i915_resume(struct drm_device
*dev
);
850 extern void i915_save_display(struct drm_device
*dev
);
851 extern void i915_restore_display(struct drm_device
*dev
);
852 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
853 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
856 extern void i915_kernel_lost_context(struct drm_device
* dev
);
857 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
858 extern int i915_driver_unload(struct drm_device
*);
859 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
860 extern void i915_driver_lastclose(struct drm_device
* dev
);
861 extern void i915_driver_preclose(struct drm_device
*dev
,
862 struct drm_file
*file_priv
);
863 extern void i915_driver_postclose(struct drm_device
*dev
,
864 struct drm_file
*file_priv
);
865 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
866 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
868 extern int i915_emit_box(struct drm_device
*dev
,
869 struct drm_clip_rect
*boxes
,
870 int i
, int DR1
, int DR4
);
871 extern int i965_reset(struct drm_device
*dev
, u8 flags
);
872 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
873 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
874 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
875 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
879 void i915_hangcheck_elapsed(unsigned long data
);
880 extern int i915_irq_emit(struct drm_device
*dev
, void *data
,
881 struct drm_file
*file_priv
);
882 extern int i915_irq_wait(struct drm_device
*dev
, void *data
,
883 struct drm_file
*file_priv
);
884 void i915_trace_irq_get(struct drm_device
*dev
, u32 seqno
);
885 extern void i915_enable_interrupt (struct drm_device
*dev
);
887 extern irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
);
888 extern void i915_driver_irq_preinstall(struct drm_device
* dev
);
889 extern int i915_driver_irq_postinstall(struct drm_device
*dev
);
890 extern void i915_driver_irq_uninstall(struct drm_device
* dev
);
891 extern int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
892 struct drm_file
*file_priv
);
893 extern int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
894 struct drm_file
*file_priv
);
895 extern int i915_enable_vblank(struct drm_device
*dev
, int crtc
);
896 extern void i915_disable_vblank(struct drm_device
*dev
, int crtc
);
897 extern u32
i915_get_vblank_counter(struct drm_device
*dev
, int crtc
);
898 extern u32
gm45_get_vblank_counter(struct drm_device
*dev
, int crtc
);
899 extern int i915_vblank_swap(struct drm_device
*dev
, void *data
,
900 struct drm_file
*file_priv
);
901 extern void i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
);
902 extern void i915_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
);
903 extern void ironlake_enable_graphics_irq(drm_i915_private_t
*dev_priv
,
905 extern void ironlake_disable_graphics_irq(drm_i915_private_t
*dev_priv
,
909 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
912 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
914 void intel_enable_asle (struct drm_device
*dev
);
916 #ifdef CONFIG_DEBUG_FS
917 extern void i915_destroy_error_state(struct drm_device
*dev
);
919 #define i915_destroy_error_state(x)
924 extern int i915_mem_alloc(struct drm_device
*dev
, void *data
,
925 struct drm_file
*file_priv
);
926 extern int i915_mem_free(struct drm_device
*dev
, void *data
,
927 struct drm_file
*file_priv
);
928 extern int i915_mem_init_heap(struct drm_device
*dev
, void *data
,
929 struct drm_file
*file_priv
);
930 extern int i915_mem_destroy_heap(struct drm_device
*dev
, void *data
,
931 struct drm_file
*file_priv
);
932 extern void i915_mem_takedown(struct mem_block
**heap
);
933 extern void i915_mem_release(struct drm_device
* dev
,
934 struct drm_file
*file_priv
, struct mem_block
*heap
);
936 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
937 struct drm_file
*file_priv
);
938 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
939 struct drm_file
*file_priv
);
940 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
941 struct drm_file
*file_priv
);
942 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
943 struct drm_file
*file_priv
);
944 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
945 struct drm_file
*file_priv
);
946 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
947 struct drm_file
*file_priv
);
948 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
949 struct drm_file
*file_priv
);
950 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
951 struct drm_file
*file_priv
);
952 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
953 struct drm_file
*file_priv
);
954 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
955 struct drm_file
*file_priv
);
956 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
957 struct drm_file
*file_priv
);
958 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
959 struct drm_file
*file_priv
);
960 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
961 struct drm_file
*file_priv
);
962 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
963 struct drm_file
*file_priv
);
964 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
965 struct drm_file
*file_priv
);
966 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
967 struct drm_file
*file_priv
);
968 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
969 struct drm_file
*file_priv
);
970 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
971 struct drm_file
*file_priv
);
972 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
973 struct drm_file
*file_priv
);
974 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
975 struct drm_file
*file_priv
);
976 void i915_gem_load(struct drm_device
*dev
);
977 int i915_gem_init_object(struct drm_gem_object
*obj
);
978 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
980 void i915_gem_free_object(struct drm_gem_object
*obj
);
981 int i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
);
982 void i915_gem_object_unpin(struct drm_gem_object
*obj
);
983 int i915_gem_object_unbind(struct drm_gem_object
*obj
);
984 void i915_gem_release_mmap(struct drm_gem_object
*obj
);
985 void i915_gem_lastclose(struct drm_device
*dev
);
986 uint32_t i915_get_gem_seqno(struct drm_device
*dev
,
987 struct intel_ring_buffer
*ring
);
988 bool i915_seqno_passed(uint32_t seq1
, uint32_t seq2
);
989 int i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
);
990 int i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
);
991 void i915_gem_retire_requests(struct drm_device
*dev
);
992 void i915_gem_clflush_object(struct drm_gem_object
*obj
);
993 int i915_gem_object_set_domain(struct drm_gem_object
*obj
,
994 uint32_t read_domains
,
995 uint32_t write_domain
);
996 int i915_gem_init_ringbuffer(struct drm_device
*dev
);
997 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
998 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
1000 int i915_gpu_idle(struct drm_device
*dev
);
1001 int i915_gem_idle(struct drm_device
*dev
);
1002 uint32_t i915_add_request(struct drm_device
*dev
,
1003 struct drm_file
*file_priv
,
1004 struct drm_i915_gem_request
*request
,
1005 struct intel_ring_buffer
*ring
);
1006 int i915_do_wait_request(struct drm_device
*dev
,
1009 struct intel_ring_buffer
*ring
);
1010 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1011 void i915_gem_process_flushing_list(struct drm_device
*dev
,
1012 uint32_t flush_domains
,
1013 struct intel_ring_buffer
*ring
);
1014 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
,
1016 int i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
);
1017 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1018 struct drm_gem_object
*obj
,
1021 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1022 struct drm_gem_object
*obj
);
1023 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1024 int i915_gem_object_get_pages(struct drm_gem_object
*obj
, gfp_t gfpmask
);
1025 void i915_gem_object_put_pages(struct drm_gem_object
*obj
);
1026 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
);
1027 int i915_gem_object_flush_write_domain(struct drm_gem_object
*obj
);
1029 void i915_gem_shrinker_init(void);
1030 void i915_gem_shrinker_exit(void);
1032 /* i915_gem_evict.c */
1033 int i915_gem_evict_something(struct drm_device
*dev
, int min_size
, unsigned alignment
);
1034 int i915_gem_evict_everything(struct drm_device
*dev
);
1035 int i915_gem_evict_inactive(struct drm_device
*dev
);
1037 /* i915_gem_tiling.c */
1038 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
1039 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object
*obj
);
1040 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object
*obj
);
1041 bool i915_tiling_ok(struct drm_device
*dev
, int stride
, int size
,
1043 bool i915_gem_object_fence_offset_ok(struct drm_gem_object
*obj
,
1046 /* i915_gem_debug.c */
1047 void i915_gem_dump_object(struct drm_gem_object
*obj
, int len
,
1048 const char *where
, uint32_t mark
);
1050 void i915_verify_inactive(struct drm_device
*dev
, char *file
, int line
);
1052 #define i915_verify_inactive(dev, file, line)
1054 void i915_gem_object_check_coherency(struct drm_gem_object
*obj
, int handle
);
1055 void i915_gem_dump_object(struct drm_gem_object
*obj
, int len
,
1056 const char *where
, uint32_t mark
);
1057 void i915_dump_lru(struct drm_device
*dev
, const char *where
);
1059 /* i915_debugfs.c */
1060 int i915_debugfs_init(struct drm_minor
*minor
);
1061 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1063 /* i915_suspend.c */
1064 extern int i915_save_state(struct drm_device
*dev
);
1065 extern int i915_restore_state(struct drm_device
*dev
);
1067 /* i915_suspend.c */
1068 extern int i915_save_state(struct drm_device
*dev
);
1069 extern int i915_restore_state(struct drm_device
*dev
);
1071 /* intel_opregion.c */
1072 extern int intel_opregion_setup(struct drm_device
*dev
);
1074 extern void intel_opregion_init(struct drm_device
*dev
);
1075 extern void intel_opregion_fini(struct drm_device
*dev
);
1076 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
1077 extern void intel_opregion_gse_intr(struct drm_device
*dev
);
1078 extern void intel_opregion_enable_asle(struct drm_device
*dev
);
1080 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
1081 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
1082 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
1083 static inline void intel_opregion_gse_intr(struct drm_device
*dev
) { return; }
1084 static inline void intel_opregion_enable_asle(struct drm_device
*dev
) { return; }
1088 extern void intel_modeset_init(struct drm_device
*dev
);
1089 extern void intel_modeset_cleanup(struct drm_device
*dev
);
1090 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
1091 extern void i8xx_disable_fbc(struct drm_device
*dev
);
1092 extern void g4x_disable_fbc(struct drm_device
*dev
);
1093 extern void ironlake_disable_fbc(struct drm_device
*dev
);
1094 extern void intel_disable_fbc(struct drm_device
*dev
);
1095 extern void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
);
1096 extern bool intel_fbc_enabled(struct drm_device
*dev
);
1097 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
1098 extern void intel_detect_pch (struct drm_device
*dev
);
1099 extern int intel_trans_dp_port_sel (struct drm_crtc
*crtc
);
1102 #ifdef CONFIG_DEBUG_FS
1103 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
1104 extern void intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
);
1108 * Lock test for when it's just for synchronization of ring access.
1110 * In that case, we don't need to do it when GEM is initialized as nobody else
1111 * has access to the ring.
1113 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
1114 if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \
1116 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1119 static inline u32
i915_read(struct drm_i915_private
*dev_priv
, u32 reg
)
1123 val
= readl(dev_priv
->regs
+ reg
);
1124 if (dev_priv
->debug_flags
& I915_DEBUG_READ
)
1125 printk(KERN_ERR
"read 0x%08x from 0x%08x\n", val
, reg
);
1129 static inline void i915_write(struct drm_i915_private
*dev_priv
, u32 reg
,
1132 writel(val
, dev_priv
->regs
+ reg
);
1133 if (dev_priv
->debug_flags
& I915_DEBUG_WRITE
)
1134 printk(KERN_ERR
"wrote 0x%08x to 0x%08x\n", val
, reg
);
1137 #define I915_READ(reg) i915_read(dev_priv, (reg))
1138 #define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val))
1139 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
1140 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
1141 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
1142 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1143 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
1144 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
1145 #define POSTING_READ(reg) (void)I915_READ(reg)
1146 #define POSTING_READ16(reg) (void)I915_READ16(reg)
1148 #define I915_DEBUG_ENABLE_IO() (dev_priv->debug_flags |= I915_DEBUG_READ | \
1150 #define I915_DEBUG_DISABLE_IO() (dev_priv->debug_flags &= ~(I915_DEBUG_READ | \
1153 #define I915_VERBOSE 0
1155 #define BEGIN_LP_RING(n) do { \
1156 drm_i915_private_t *dev_priv__ = dev->dev_private; \
1158 DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \
1159 intel_ring_begin(dev, &dev_priv__->render_ring, (n)); \
1163 #define OUT_RING(x) do { \
1164 drm_i915_private_t *dev_priv__ = dev->dev_private; \
1166 DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \
1167 intel_ring_emit(dev, &dev_priv__->render_ring, x); \
1170 #define ADVANCE_LP_RING() do { \
1171 drm_i915_private_t *dev_priv__ = dev->dev_private; \
1173 DRM_DEBUG("ADVANCE_LP_RING %x\n", \
1174 dev_priv__->render_ring.tail); \
1175 intel_ring_advance(dev, &dev_priv__->render_ring); \
1179 * Reads a dword out of the status page, which is written to from the command
1180 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1181 * MI_STORE_DATA_IMM.
1183 * The following dwords have a reserved meaning:
1184 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1185 * 0x04: ring 0 head pointer
1186 * 0x05: ring 1 head pointer (915-class)
1187 * 0x06: ring 2 head pointer (915-class)
1188 * 0x10-0x1b: Context status DWords (GM45)
1189 * 0x1f: Last written status offset. (GM45)
1191 * The area from dword 0x20 to 0x3ff is available for driver usage.
1193 #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1194 (dev_priv->render_ring.status_page.page_addr))[reg])
1195 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1196 #define I915_GEM_HWS_INDEX 0x20
1197 #define I915_BREADCRUMB_INDEX 0x21
1199 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1201 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1202 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1203 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1204 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1205 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1206 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1207 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1208 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1209 #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
1210 #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
1211 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1212 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1213 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1214 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1215 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1216 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1217 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1218 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1219 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1220 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1221 #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
1222 #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
1223 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1225 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1226 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1227 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1228 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1229 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1231 #define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev))
1232 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1234 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1235 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1237 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1238 * rows, which changed the alignment requirements and fence programming.
1240 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1242 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev))
1243 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1244 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1245 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1246 #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
1247 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \
1249 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1250 /* dsparb controlled by hw only */
1251 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1253 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
1254 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1255 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1256 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1258 #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
1260 #define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))
1262 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1263 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1265 #define PRIMARY_RINGBUFFER_SIZE (128*1024)