arch/mips/mips-boards/malta/malta_smp.c

   1 /*
   2  * Malta Platform-specific hooks for SMP operation
   3  */
   4
   5 #include <linux/kernel.h>
   6 #include <linux/sched.h>
   7 #include <linux/cpumask.h>
   8 #include <linux/interrupt.h>
   9
  10 #include <asm/atomic.h>
  11 #include <asm/cpu.h>
  12 #include <asm/processor.h>
  13 #include <asm/system.h>
  14 #include <asm/hardirq.h>
  15 #include <asm/mmu_context.h>
  16 #include <asm/smp.h>
  17 #ifdef CONFIG_MIPS_MT_SMTC
  18 #include <asm/smtc_ipi.h>
  19 #endif /* CONFIG_MIPS_MT_SMTC */
  20
  21 /* VPE/SMP Prototype implements platform interfaces directly */
  22 #if !defined(CONFIG_MIPS_MT_SMP)
  23
  24 /*
  25  * Cause the specified action to be performed on a targeted "CPU"
  26  */
  27
  28 void core_send_ipi(int cpu, unsigned int action)
  29 {
  30 /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
  31 #ifdef CONFIG_MIPS_MT_SMTC
  32         smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
  33 #endif /* CONFIG_MIPS_MT_SMTC */
  34 }
  35
  36 /*
  37  * Platform "CPU" startup hook
  38  */
  39
  40 void prom_boot_secondary(int cpu, struct task_struct *idle)
  41 {
  42 #ifdef CONFIG_MIPS_MT_SMTC
  43         smtc_boot_secondary(cpu, idle);
  44 #endif /* CONFIG_MIPS_MT_SMTC */
  45 }
  46
  47 /*
  48  * Post-config but pre-boot cleanup entry point
  49  */
  50
  51 void prom_init_secondary(void)
  52 {
  53 #ifdef CONFIG_MIPS_MT_SMTC
  54         void smtc_init_secondary(void);
  55         int myvpe;
  56
  57         /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */
  58         myvpe = read_c0_tcbind() & TCBIND_CURVPE;
  59         if (myvpe != 0) {
  60                 /* Ideally, this should be done only once per VPE, but... */
  61                 clear_c0_status(STATUSF_IP2);
  62                 set_c0_status(STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP3
  63                                 | STATUSF_IP4 | STATUSF_IP5 | STATUSF_IP6
  64                                 | STATUSF_IP7);
  65         }
  66
  67         smtc_init_secondary();
  68 #endif /* CONFIG_MIPS_MT_SMTC */
  69 }
  70
  71 /*
  72  * Platform SMP pre-initialization
  73  *
  74  * As noted above, we can assume a single CPU for now
  75  * but it may be multithreaded.
  76  */
  77
  78 void plat_smp_setup(void)
  79 {
  80         if (read_c0_config3() & (1<<2))
  81                 mipsmt_build_cpu_map(0);
  82 }
  83
  84 void __init plat_prepare_cpus(unsigned int max_cpus)
  85 {
  86         if (read_c0_config3() & (1<<2))
  87                 mipsmt_prepare_cpus();
  88 }
  89
  90 /*
  91  * SMP initialization finalization entry point
  92  */
  93
  94 void prom_smp_finish(void)
  95 {
  96 #ifdef CONFIG_MIPS_MT_SMTC
  97         smtc_smp_finish();
  98 #endif /* CONFIG_MIPS_MT_SMTC */
  99 }
 100
 101 /*
 102  * Hook for after all CPUs are online
 103  */
 104
 105 void prom_cpus_done(void)
 106 {
 107 }
 108
 109 #endif /* CONFIG_MIPS32R2_MT_SMP */