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iwlagn: Sanity check for valid context
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
blob0acf92919048d6970b9eb7018978b8402799edbe
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/wireless.h>
44 #include <linux/firmware.h>
45 #include <linux/etherdevice.h>
46 #include <linux/if_arp.h>
47
48 #include <net/mac80211.h>
49
50 #include <asm/div64.h>
51
52 #define DRV_NAME "iwlagn"
53
54 #include "iwl-eeprom.h"
55 #include "iwl-dev.h"
56 #include "iwl-core.h"
57 #include "iwl-io.h"
58 #include "iwl-helpers.h"
59 #include "iwl-sta.h"
60 #include "iwl-agn-calib.h"
61 #include "iwl-agn.h"
62
63
64 /******************************************************************************
65 *
66 * module boiler plate
67 *
68 ******************************************************************************/
69
70 /*
71 * module name, copyright, version, etc.
72 */
73 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
74
75 #ifdef CONFIG_IWLWIFI_DEBUG
76 #define VD "d"
77 #else
78 #define VD
79 #endif
80
81 #define DRV_VERSION IWLWIFI_VERSION VD
82
83
84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
85 MODULE_VERSION(DRV_VERSION);
86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
87 MODULE_LICENSE("GPL");
88
89 static int iwlagn_ant_coupling;
90 static bool iwlagn_bt_ch_announce = 1;
91
92 void iwl_update_chain_flags(struct iwl_priv *priv)
93 {
94 struct iwl_rxon_context *ctx;
95
96 if (priv->cfg->ops->hcmd->set_rxon_chain) {
97 for_each_context(priv, ctx) {
98 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
99 if (ctx->active.rx_chain != ctx->staging.rx_chain)
100 iwlagn_commit_rxon(priv, ctx);
101 }
102 }
103 }
104
105 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
106 static void iwl_set_beacon_tim(struct iwl_priv *priv,
107 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
108 u8 *beacon, u32 frame_size)
109 {
110 u16 tim_idx;
111 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
112
113 /*
114 * The index is relative to frame start but we start looking at the
115 * variable-length part of the beacon.
116 */
117 tim_idx = mgmt->u.beacon.variable - beacon;
118
119 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
120 while ((tim_idx < (frame_size - 2)) &&
121 (beacon[tim_idx] != WLAN_EID_TIM))
122 tim_idx += beacon[tim_idx+1] + 2;
123
124 /* If TIM field was found, set variables */
125 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
126 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
127 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
128 } else
129 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
130 }
131
132 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
133 {
134 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
135 struct iwl_host_cmd cmd = {
136 .id = REPLY_TX_BEACON,
137 };
138 u32 frame_size;
139 u32 rate_flags;
140 u32 rate;
141
142 /*
143 * We have to set up the TX command, the TX Beacon command, and the
144 * beacon contents.
145 */
146
147 lockdep_assert_held(&priv->mutex);
148
149 if (!priv->beacon_ctx) {
150 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
151 return 0;
152 }
153
154 if (WARN_ON(!priv->beacon_skb))
155 return -EINVAL;
156
157 /* Allocate beacon command */
158 if (!priv->beacon_cmd)
159 priv->beacon_cmd = kzalloc(sizeof(*tx_beacon_cmd), GFP_KERNEL);
160 tx_beacon_cmd = priv->beacon_cmd;
161 if (!tx_beacon_cmd)
162 return -ENOMEM;
163
164 frame_size = priv->beacon_skb->len;
165
166 /* Set up TX command fields */
167 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
168 tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
169 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
170 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
171 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
172
173 /* Set up TX beacon command fields */
174 iwl_set_beacon_tim(priv, tx_beacon_cmd, priv->beacon_skb->data,
175 frame_size);
176
177 /* Set up packet rate and flags */
178 rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
179 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
180 priv->hw_params.valid_tx_ant);
181 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
182 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
183 rate_flags |= RATE_MCS_CCK_MSK;
184 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
185 rate_flags);
186
187 /* Submit command */
188 cmd.len[0] = sizeof(*tx_beacon_cmd);
189 cmd.data[0] = tx_beacon_cmd;
190 cmd.dataflags[0] = IWL_HCMD_DFL_NOCOPY;
191 cmd.len[1] = frame_size;
192 cmd.data[1] = priv->beacon_skb->data;
193 cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY;
194
195 return iwl_send_cmd_sync(priv, &cmd);
196 }
197
198 static void iwl_bg_beacon_update(struct work_struct *work)
199 {
200 struct iwl_priv *priv =
201 container_of(work, struct iwl_priv, beacon_update);
202 struct sk_buff *beacon;
203
204 mutex_lock(&priv->mutex);
205 if (!priv->beacon_ctx) {
206 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
207 goto out;
208 }
209
210 if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
211 /*
212 * The ucode will send beacon notifications even in
213 * IBSS mode, but we don't want to process them. But
214 * we need to defer the type check to here due to
215 * requiring locking around the beacon_ctx access.
216 */
217 goto out;
218 }
219
220 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
221 beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
222 if (!beacon) {
223 IWL_ERR(priv, "update beacon failed -- keeping old\n");
224 goto out;
225 }
226
227 /* new beacon skb is allocated every time; dispose previous.*/
228 dev_kfree_skb(priv->beacon_skb);
229
230 priv->beacon_skb = beacon;
231
232 iwlagn_send_beacon_cmd(priv);
233 out:
234 mutex_unlock(&priv->mutex);
235 }
236
237 static void iwl_bg_bt_runtime_config(struct work_struct *work)
238 {
239 struct iwl_priv *priv =
240 container_of(work, struct iwl_priv, bt_runtime_config);
241
242 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
243 return;
244
245 /* dont send host command if rf-kill is on */
246 if (!iwl_is_ready_rf(priv))
247 return;
248 priv->cfg->ops->hcmd->send_bt_config(priv);
249 }
250
251 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
252 {
253 struct iwl_priv *priv =
254 container_of(work, struct iwl_priv, bt_full_concurrency);
255 struct iwl_rxon_context *ctx;
256
257 mutex_lock(&priv->mutex);
258
259 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
260 goto out;
261
262 /* dont send host command if rf-kill is on */
263 if (!iwl_is_ready_rf(priv))
264 goto out;
265
266 IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
267 priv->bt_full_concurrent ?
268 "full concurrency" : "3-wire");
269
270 /*
271 * LQ & RXON updated cmds must be sent before BT Config cmd
272 * to avoid 3-wire collisions
273 */
274 for_each_context(priv, ctx) {
275 if (priv->cfg->ops->hcmd->set_rxon_chain)
276 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
277 iwlagn_commit_rxon(priv, ctx);
278 }
279
280 priv->cfg->ops->hcmd->send_bt_config(priv);
281 out:
282 mutex_unlock(&priv->mutex);
283 }
284
285 /**
286 * iwl_bg_statistics_periodic - Timer callback to queue statistics
287 *
288 * This callback is provided in order to send a statistics request.
289 *
290 * This timer function is continually reset to execute within
291 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
292 * was received. We need to ensure we receive the statistics in order
293 * to update the temperature used for calibrating the TXPOWER.
294 */
295 static void iwl_bg_statistics_periodic(unsigned long data)
296 {
297 struct iwl_priv *priv = (struct iwl_priv *)data;
298
299 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
300 return;
301
302 /* dont send host command if rf-kill is on */
303 if (!iwl_is_ready_rf(priv))
304 return;
305
306 iwl_send_statistics_request(priv, CMD_ASYNC, false);
307 }
308
309
310 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
311 u32 start_idx, u32 num_events,
312 u32 mode)
313 {
314 u32 i;
315 u32 ptr; /* SRAM byte address of log data */
316 u32 ev, time, data; /* event log data */
317 unsigned long reg_flags;
318
319 if (mode == 0)
320 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
321 else
322 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
323
324 /* Make sure device is powered up for SRAM reads */
325 spin_lock_irqsave(&priv->reg_lock, reg_flags);
326 if (iwl_grab_nic_access(priv)) {
327 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
328 return;
329 }
330
331 /* Set starting address; reads will auto-increment */
332 iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
333 rmb();
334
335 /*
336 * "time" is actually "data" for mode 0 (no timestamp).
337 * place event id # at far right for easier visual parsing.
338 */
339 for (i = 0; i < num_events; i++) {
340 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
341 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
342 if (mode == 0) {
343 trace_iwlwifi_dev_ucode_cont_event(priv,
344 0, time, ev);
345 } else {
346 data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
347 trace_iwlwifi_dev_ucode_cont_event(priv,
348 time, data, ev);
349 }
350 }
351 /* Allow device to power down */
352 iwl_release_nic_access(priv);
353 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
354 }
355
356 static void iwl_continuous_event_trace(struct iwl_priv *priv)
357 {
358 u32 capacity; /* event log capacity in # entries */
359 u32 base; /* SRAM byte address of event log header */
360 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
361 u32 num_wraps; /* # times uCode wrapped to top of log */
362 u32 next_entry; /* index of next entry to be written by uCode */
363
364 base = priv->device_pointers.error_event_table;
365 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
366 capacity = iwl_read_targ_mem(priv, base);
367 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
368 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
369 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
370 } else
371 return;
372
373 if (num_wraps == priv->event_log.num_wraps) {
374 iwl_print_cont_event_trace(priv,
375 base, priv->event_log.next_entry,
376 next_entry - priv->event_log.next_entry,
377 mode);
378 priv->event_log.non_wraps_count++;
379 } else {
380 if ((num_wraps - priv->event_log.num_wraps) > 1)
381 priv->event_log.wraps_more_count++;
382 else
383 priv->event_log.wraps_once_count++;
384 trace_iwlwifi_dev_ucode_wrap_event(priv,
385 num_wraps - priv->event_log.num_wraps,
386 next_entry, priv->event_log.next_entry);
387 if (next_entry < priv->event_log.next_entry) {
388 iwl_print_cont_event_trace(priv, base,
389 priv->event_log.next_entry,
390 capacity - priv->event_log.next_entry,
391 mode);
392
393 iwl_print_cont_event_trace(priv, base, 0,
394 next_entry, mode);
395 } else {
396 iwl_print_cont_event_trace(priv, base,
397 next_entry, capacity - next_entry,
398 mode);
399
400 iwl_print_cont_event_trace(priv, base, 0,
401 next_entry, mode);
402 }
403 }
404 priv->event_log.num_wraps = num_wraps;
405 priv->event_log.next_entry = next_entry;
406 }
407
408 /**
409 * iwl_bg_ucode_trace - Timer callback to log ucode event
410 *
411 * The timer is continually set to execute every
412 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
413 * this function is to perform continuous uCode event logging operation
414 * if enabled
415 */
416 static void iwl_bg_ucode_trace(unsigned long data)
417 {
418 struct iwl_priv *priv = (struct iwl_priv *)data;
419
420 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
421 return;
422
423 if (priv->event_log.ucode_trace) {
424 iwl_continuous_event_trace(priv);
425 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
426 mod_timer(&priv->ucode_trace,
427 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
428 }
429 }
430
431 static void iwl_bg_tx_flush(struct work_struct *work)
432 {
433 struct iwl_priv *priv =
434 container_of(work, struct iwl_priv, tx_flush);
435
436 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
437 return;
438
439 /* do nothing if rf-kill is on */
440 if (!iwl_is_ready_rf(priv))
441 return;
442
443 if (priv->cfg->ops->lib->txfifo_flush) {
444 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
445 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
446 }
447 }
448
449 /**
450 * iwl_rx_handle - Main entry function for receiving responses from uCode
451 *
452 * Uses the priv->rx_handlers callback function array to invoke
453 * the appropriate handlers, including command responses,
454 * frame-received notifications, and other notifications.
455 */
456 static void iwl_rx_handle(struct iwl_priv *priv)
457 {
458 struct iwl_rx_mem_buffer *rxb;
459 struct iwl_rx_packet *pkt;
460 struct iwl_rx_queue *rxq = &priv->rxq;
461 u32 r, i;
462 int reclaim;
463 unsigned long flags;
464 u8 fill_rx = 0;
465 u32 count = 8;
466 int total_empty;
467
468 /* uCode's read index (stored in shared DRAM) indicates the last Rx
469 * buffer that the driver may process (last buffer filled by ucode). */
470 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
471 i = rxq->read;
472
473 /* Rx interrupt, but nothing sent from uCode */
474 if (i == r)
475 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
476
477 /* calculate total frames need to be restock after handling RX */
478 total_empty = r - rxq->write_actual;
479 if (total_empty < 0)
480 total_empty += RX_QUEUE_SIZE;
481
482 if (total_empty > (RX_QUEUE_SIZE / 2))
483 fill_rx = 1;
484
485 while (i != r) {
486 int len;
487
488 rxb = rxq->queue[i];
489
490 /* If an RXB doesn't have a Rx queue slot associated with it,
491 * then a bug has been introduced in the queue refilling
492 * routines -- catch it here */
493 if (WARN_ON(rxb == NULL)) {
494 i = (i + 1) & RX_QUEUE_MASK;
495 continue;
496 }
497
498 rxq->queue[i] = NULL;
499
500 pci_unmap_page(priv->pci_dev, rxb->page_dma,
501 PAGE_SIZE << priv->hw_params.rx_page_order,
502 PCI_DMA_FROMDEVICE);
503 pkt = rxb_addr(rxb);
504
505 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
506 len += sizeof(u32); /* account for status word */
507 trace_iwlwifi_dev_rx(priv, pkt, len);
508
509 /* Reclaim a command buffer only if this packet is a response
510 * to a (driver-originated) command.
511 * If the packet (e.g. Rx frame) originated from uCode,
512 * there is no command buffer to reclaim.
513 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
514 * but apparently a few don't get set; catch them here. */
515 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
516 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
517 (pkt->hdr.cmd != REPLY_RX) &&
518 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
519 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
520 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
521 (pkt->hdr.cmd != REPLY_TX);
522
523 /*
524 * Do the notification wait before RX handlers so
525 * even if the RX handler consumes the RXB we have
526 * access to it in the notification wait entry.
527 */
528 if (!list_empty(&priv->_agn.notif_waits)) {
529 struct iwl_notification_wait *w;
530
531 spin_lock(&priv->_agn.notif_wait_lock);
532 list_for_each_entry(w, &priv->_agn.notif_waits, list) {
533 if (w->cmd == pkt->hdr.cmd) {
534 w->triggered = true;
535 if (w->fn)
536 w->fn(priv, pkt, w->fn_data);
537 }
538 }
539 spin_unlock(&priv->_agn.notif_wait_lock);
540
541 wake_up_all(&priv->_agn.notif_waitq);
542 }
543 if (priv->pre_rx_handler)
544 priv->pre_rx_handler(priv, rxb);
545
546 /* Based on type of command response or notification,
547 * handle those that need handling via function in
548 * rx_handlers table. See iwl_setup_rx_handlers() */
549 if (priv->rx_handlers[pkt->hdr.cmd]) {
550 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
551 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
552 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
553 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
554 } else {
555 /* No handling needed */
556 IWL_DEBUG_RX(priv,
557 "r %d i %d No handler needed for %s, 0x%02x\n",
558 r, i, get_cmd_string(pkt->hdr.cmd),
559 pkt->hdr.cmd);
560 }
561
562 /*
563 * XXX: After here, we should always check rxb->page
564 * against NULL before touching it or its virtual
565 * memory (pkt). Because some rx_handler might have
566 * already taken or freed the pages.
567 */
568
569 if (reclaim) {
570 /* Invoke any callbacks, transfer the buffer to caller,
571 * and fire off the (possibly) blocking iwl_send_cmd()
572 * as we reclaim the driver command queue */
573 if (rxb->page)
574 iwl_tx_cmd_complete(priv, rxb);
575 else
576 IWL_WARN(priv, "Claim null rxb?\n");
577 }
578
579 /* Reuse the page if possible. For notification packets and
580 * SKBs that fail to Rx correctly, add them back into the
581 * rx_free list for reuse later. */
582 spin_lock_irqsave(&rxq->lock, flags);
583 if (rxb->page != NULL) {
584 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
585 0, PAGE_SIZE << priv->hw_params.rx_page_order,
586 PCI_DMA_FROMDEVICE);
587 list_add_tail(&rxb->list, &rxq->rx_free);
588 rxq->free_count++;
589 } else
590 list_add_tail(&rxb->list, &rxq->rx_used);
591
592 spin_unlock_irqrestore(&rxq->lock, flags);
593
594 i = (i + 1) & RX_QUEUE_MASK;
595 /* If there are a lot of unused frames,
596 * restock the Rx queue so ucode wont assert. */
597 if (fill_rx) {
598 count++;
599 if (count >= 8) {
600 rxq->read = i;
601 iwlagn_rx_replenish_now(priv);
602 count = 0;
603 }
604 }
605 }
606
607 /* Backtrack one entry */
608 rxq->read = i;
609 if (fill_rx)
610 iwlagn_rx_replenish_now(priv);
611 else
612 iwlagn_rx_queue_restock(priv);
613 }
614
615 /* tasklet for iwlagn interrupt */
616 static void iwl_irq_tasklet(struct iwl_priv *priv)
617 {
618 u32 inta = 0;
619 u32 handled = 0;
620 unsigned long flags;
621 u32 i;
622 #ifdef CONFIG_IWLWIFI_DEBUG
623 u32 inta_mask;
624 #endif
625
626 spin_lock_irqsave(&priv->lock, flags);
627
628 /* Ack/clear/reset pending uCode interrupts.
629 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
630 */
631 /* There is a hardware bug in the interrupt mask function that some
632 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
633 * they are disabled in the CSR_INT_MASK register. Furthermore the
634 * ICT interrupt handling mechanism has another bug that might cause
635 * these unmasked interrupts fail to be detected. We workaround the
636 * hardware bugs here by ACKing all the possible interrupts so that
637 * interrupt coalescing can still be achieved.
638 */
639 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
640
641 inta = priv->_agn.inta;
642
643 #ifdef CONFIG_IWLWIFI_DEBUG
644 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
645 /* just for debug */
646 inta_mask = iwl_read32(priv, CSR_INT_MASK);
647 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
648 inta, inta_mask);
649 }
650 #endif
651
652 spin_unlock_irqrestore(&priv->lock, flags);
653
654 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
655 priv->_agn.inta = 0;
656
657 /* Now service all interrupt bits discovered above. */
658 if (inta & CSR_INT_BIT_HW_ERR) {
659 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
660
661 /* Tell the device to stop sending interrupts */
662 iwl_disable_interrupts(priv);
663
664 priv->isr_stats.hw++;
665 iwl_irq_handle_error(priv);
666
667 handled |= CSR_INT_BIT_HW_ERR;
668
669 return;
670 }
671
672 #ifdef CONFIG_IWLWIFI_DEBUG
673 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
674 /* NIC fires this, but we don't use it, redundant with WAKEUP */
675 if (inta & CSR_INT_BIT_SCD) {
676 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
677 "the frame/frames.\n");
678 priv->isr_stats.sch++;
679 }
680
681 /* Alive notification via Rx interrupt will do the real work */
682 if (inta & CSR_INT_BIT_ALIVE) {
683 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
684 priv->isr_stats.alive++;
685 }
686 }
687 #endif
688 /* Safely ignore these bits for debug checks below */
689 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
690
691 /* HW RF KILL switch toggled */
692 if (inta & CSR_INT_BIT_RF_KILL) {
693 int hw_rf_kill = 0;
694 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
695 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
696 hw_rf_kill = 1;
697
698 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
699 hw_rf_kill ? "disable radio" : "enable radio");
700
701 priv->isr_stats.rfkill++;
702
703 /* driver only loads ucode once setting the interface up.
704 * the driver allows loading the ucode even if the radio
705 * is killed. Hence update the killswitch state here. The
706 * rfkill handler will care about restarting if needed.
707 */
708 if (!test_bit(STATUS_ALIVE, &priv->status)) {
709 if (hw_rf_kill)
710 set_bit(STATUS_RF_KILL_HW, &priv->status);
711 else
712 clear_bit(STATUS_RF_KILL_HW, &priv->status);
713 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
714 }
715
716 handled |= CSR_INT_BIT_RF_KILL;
717 }
718
719 /* Chip got too hot and stopped itself */
720 if (inta & CSR_INT_BIT_CT_KILL) {
721 IWL_ERR(priv, "Microcode CT kill error detected.\n");
722 priv->isr_stats.ctkill++;
723 handled |= CSR_INT_BIT_CT_KILL;
724 }
725
726 /* Error detected by uCode */
727 if (inta & CSR_INT_BIT_SW_ERR) {
728 IWL_ERR(priv, "Microcode SW error detected. "
729 " Restarting 0x%X.\n", inta);
730 priv->isr_stats.sw++;
731 iwl_irq_handle_error(priv);
732 handled |= CSR_INT_BIT_SW_ERR;
733 }
734
735 /* uCode wakes up after power-down sleep */
736 if (inta & CSR_INT_BIT_WAKEUP) {
737 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
738 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
739 for (i = 0; i < priv->hw_params.max_txq_num; i++)
740 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
741
742 priv->isr_stats.wakeup++;
743
744 handled |= CSR_INT_BIT_WAKEUP;
745 }
746
747 /* All uCode command responses, including Tx command responses,
748 * Rx "responses" (frame-received notification), and other
749 * notifications from uCode come through here*/
750 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
751 CSR_INT_BIT_RX_PERIODIC)) {
752 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
753 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
754 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
755 iwl_write32(priv, CSR_FH_INT_STATUS,
756 CSR_FH_INT_RX_MASK);
757 }
758 if (inta & CSR_INT_BIT_RX_PERIODIC) {
759 handled |= CSR_INT_BIT_RX_PERIODIC;
760 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
761 }
762 /* Sending RX interrupt require many steps to be done in the
763 * the device:
764 * 1- write interrupt to current index in ICT table.
765 * 2- dma RX frame.
766 * 3- update RX shared data to indicate last write index.
767 * 4- send interrupt.
768 * This could lead to RX race, driver could receive RX interrupt
769 * but the shared data changes does not reflect this;
770 * periodic interrupt will detect any dangling Rx activity.
771 */
772
773 /* Disable periodic interrupt; we use it as just a one-shot. */
774 iwl_write8(priv, CSR_INT_PERIODIC_REG,
775 CSR_INT_PERIODIC_DIS);
776 iwl_rx_handle(priv);
777
778 /*
779 * Enable periodic interrupt in 8 msec only if we received
780 * real RX interrupt (instead of just periodic int), to catch
781 * any dangling Rx interrupt. If it was just the periodic
782 * interrupt, there was no dangling Rx activity, and no need
783 * to extend the periodic interrupt; one-shot is enough.
784 */
785 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
786 iwl_write8(priv, CSR_INT_PERIODIC_REG,
787 CSR_INT_PERIODIC_ENA);
788
789 priv->isr_stats.rx++;
790 }
791
792 /* This "Tx" DMA channel is used only for loading uCode */
793 if (inta & CSR_INT_BIT_FH_TX) {
794 iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
795 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
796 priv->isr_stats.tx++;
797 handled |= CSR_INT_BIT_FH_TX;
798 /* Wake up uCode load routine, now that load is complete */
799 priv->ucode_write_complete = 1;
800 wake_up_interruptible(&priv->wait_command_queue);
801 }
802
803 if (inta & ~handled) {
804 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
805 priv->isr_stats.unhandled++;
806 }
807
808 if (inta & ~(priv->inta_mask)) {
809 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
810 inta & ~priv->inta_mask);
811 }
812
813 /* Re-enable all interrupts */
814 /* only Re-enable if disabled by irq */
815 if (test_bit(STATUS_INT_ENABLED, &priv->status))
816 iwl_enable_interrupts(priv);
817 /* Re-enable RF_KILL if it occurred */
818 else if (handled & CSR_INT_BIT_RF_KILL)
819 iwl_enable_rfkill_int(priv);
820 }
821
822 /*****************************************************************************
823 *
824 * sysfs attributes
825 *
826 *****************************************************************************/
827
828 #ifdef CONFIG_IWLWIFI_DEBUG
829
830 /*
831 * The following adds a new attribute to the sysfs representation
832 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
833 * used for controlling the debug level.
834 *
835 * See the level definitions in iwl for details.
836 *
837 * The debug_level being managed using sysfs below is a per device debug
838 * level that is used instead of the global debug level if it (the per
839 * device debug level) is set.
840 */
841 static ssize_t show_debug_level(struct device *d,
842 struct device_attribute *attr, char *buf)
843 {
844 struct iwl_priv *priv = dev_get_drvdata(d);
845 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
846 }
847 static ssize_t store_debug_level(struct device *d,
848 struct device_attribute *attr,
849 const char *buf, size_t count)
850 {
851 struct iwl_priv *priv = dev_get_drvdata(d);
852 unsigned long val;
853 int ret;
854
855 ret = strict_strtoul(buf, 0, &val);
856 if (ret)
857 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
858 else {
859 priv->debug_level = val;
860 if (iwl_alloc_traffic_mem(priv))
861 IWL_ERR(priv,
862 "Not enough memory to generate traffic log\n");
863 }
864 return strnlen(buf, count);
865 }
866
867 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
868 show_debug_level, store_debug_level);
869
870
871 #endif /* CONFIG_IWLWIFI_DEBUG */
872
873
874 static ssize_t show_temperature(struct device *d,
875 struct device_attribute *attr, char *buf)
876 {
877 struct iwl_priv *priv = dev_get_drvdata(d);
878
879 if (!iwl_is_alive(priv))
880 return -EAGAIN;
881
882 return sprintf(buf, "%d\n", priv->temperature);
883 }
884
885 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
886
887 static ssize_t show_tx_power(struct device *d,
888 struct device_attribute *attr, char *buf)
889 {
890 struct iwl_priv *priv = dev_get_drvdata(d);
891
892 if (!iwl_is_ready_rf(priv))
893 return sprintf(buf, "off\n");
894 else
895 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
896 }
897
898 static ssize_t store_tx_power(struct device *d,
899 struct device_attribute *attr,
900 const char *buf, size_t count)
901 {
902 struct iwl_priv *priv = dev_get_drvdata(d);
903 unsigned long val;
904 int ret;
905
906 ret = strict_strtoul(buf, 10, &val);
907 if (ret)
908 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
909 else {
910 ret = iwl_set_tx_power(priv, val, false);
911 if (ret)
912 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
913 ret);
914 else
915 ret = count;
916 }
917 return ret;
918 }
919
920 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
921
922 static struct attribute *iwl_sysfs_entries[] = {
923 &dev_attr_temperature.attr,
924 &dev_attr_tx_power.attr,
925 #ifdef CONFIG_IWLWIFI_DEBUG
926 &dev_attr_debug_level.attr,
927 #endif
928 NULL
929 };
930
931 static struct attribute_group iwl_attribute_group = {
932 .name = NULL, /* put in device directory */
933 .attrs = iwl_sysfs_entries,
934 };
935
936 /******************************************************************************
937 *
938 * uCode download functions
939 *
940 ******************************************************************************/
941
942 static void iwl_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
943 {
944 if (desc->v_addr)
945 dma_free_coherent(&pci_dev->dev, desc->len,
946 desc->v_addr, desc->p_addr);
947 desc->v_addr = NULL;
948 desc->len = 0;
949 }
950
951 static void iwl_free_fw_img(struct pci_dev *pci_dev, struct fw_img *img)
952 {
953 iwl_free_fw_desc(pci_dev, &img->code);
954 iwl_free_fw_desc(pci_dev, &img->data);
955 }
956
957 static int iwl_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc,
958 const void *data, size_t len)
959 {
960 if (!len) {
961 desc->v_addr = NULL;
962 return -EINVAL;
963 }
964
965 desc->v_addr = dma_alloc_coherent(&pci_dev->dev, len,
966 &desc->p_addr, GFP_KERNEL);
967 if (!desc->v_addr)
968 return -ENOMEM;
969 desc->len = len;
970 memcpy(desc->v_addr, data, len);
971 return 0;
972 }
973
974 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
975 {
976 iwl_free_fw_img(priv->pci_dev, &priv->ucode_rt);
977 iwl_free_fw_img(priv->pci_dev, &priv->ucode_init);
978 }
979
980 struct iwlagn_ucode_capabilities {
981 u32 max_probe_length;
982 u32 standard_phy_calibration_size;
983 u32 flags;
984 };
985
986 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
987 static int iwl_mac_setup_register(struct iwl_priv *priv,
988 struct iwlagn_ucode_capabilities *capa);
989
990 #define UCODE_EXPERIMENTAL_INDEX 100
991 #define UCODE_EXPERIMENTAL_TAG "exp"
992
993 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
994 {
995 const char *name_pre = priv->cfg->fw_name_pre;
996 char tag[8];
997
998 if (first) {
999 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1000 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1001 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1002 } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1003 #endif
1004 priv->fw_index = priv->cfg->ucode_api_max;
1005 sprintf(tag, "%d", priv->fw_index);
1006 } else {
1007 priv->fw_index--;
1008 sprintf(tag, "%d", priv->fw_index);
1009 }
1010
1011 if (priv->fw_index < priv->cfg->ucode_api_min) {
1012 IWL_ERR(priv, "no suitable firmware found!\n");
1013 return -ENOENT;
1014 }
1015
1016 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1017
1018 IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1019 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1020 ? "EXPERIMENTAL " : "",
1021 priv->firmware_name);
1022
1023 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1024 &priv->pci_dev->dev, GFP_KERNEL, priv,
1025 iwl_ucode_callback);
1026 }
1027
1028 struct iwlagn_firmware_pieces {
1029 const void *inst, *data, *init, *init_data;
1030 size_t inst_size, data_size, init_size, init_data_size;
1031
1032 u32 build;
1033
1034 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1035 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1036 };
1037
1038 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1039 const struct firmware *ucode_raw,
1040 struct iwlagn_firmware_pieces *pieces)
1041 {
1042 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1043 u32 api_ver, hdr_size;
1044 const u8 *src;
1045
1046 priv->ucode_ver = le32_to_cpu(ucode->ver);
1047 api_ver = IWL_UCODE_API(priv->ucode_ver);
1048
1049 switch (api_ver) {
1050 default:
1051 hdr_size = 28;
1052 if (ucode_raw->size < hdr_size) {
1053 IWL_ERR(priv, "File size too small!\n");
1054 return -EINVAL;
1055 }
1056 pieces->build = le32_to_cpu(ucode->u.v2.build);
1057 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1058 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1059 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1060 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1061 src = ucode->u.v2.data;
1062 break;
1063 case 0:
1064 case 1:
1065 case 2:
1066 hdr_size = 24;
1067 if (ucode_raw->size < hdr_size) {
1068 IWL_ERR(priv, "File size too small!\n");
1069 return -EINVAL;
1070 }
1071 pieces->build = 0;
1072 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1073 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1074 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1075 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1076 src = ucode->u.v1.data;
1077 break;
1078 }
1079
1080 /* Verify size of file vs. image size info in file's header */
1081 if (ucode_raw->size != hdr_size + pieces->inst_size +
1082 pieces->data_size + pieces->init_size +
1083 pieces->init_data_size) {
1084
1085 IWL_ERR(priv,
1086 "uCode file size %d does not match expected size\n",
1087 (int)ucode_raw->size);
1088 return -EINVAL;
1089 }
1090
1091 pieces->inst = src;
1092 src += pieces->inst_size;
1093 pieces->data = src;
1094 src += pieces->data_size;
1095 pieces->init = src;
1096 src += pieces->init_size;
1097 pieces->init_data = src;
1098 src += pieces->init_data_size;
1099
1100 return 0;
1101 }
1102
1103 static int iwlagn_wanted_ucode_alternative = 1;
1104
1105 static int iwlagn_load_firmware(struct iwl_priv *priv,
1106 const struct firmware *ucode_raw,
1107 struct iwlagn_firmware_pieces *pieces,
1108 struct iwlagn_ucode_capabilities *capa)
1109 {
1110 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1111 struct iwl_ucode_tlv *tlv;
1112 size_t len = ucode_raw->size;
1113 const u8 *data;
1114 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1115 u64 alternatives;
1116 u32 tlv_len;
1117 enum iwl_ucode_tlv_type tlv_type;
1118 const u8 *tlv_data;
1119
1120 if (len < sizeof(*ucode)) {
1121 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1122 return -EINVAL;
1123 }
1124
1125 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1126 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1127 le32_to_cpu(ucode->magic));
1128 return -EINVAL;
1129 }
1130
1131 /*
1132 * Check which alternatives are present, and "downgrade"
1133 * when the chosen alternative is not present, warning
1134 * the user when that happens. Some files may not have
1135 * any alternatives, so don't warn in that case.
1136 */
1137 alternatives = le64_to_cpu(ucode->alternatives);
1138 tmp = wanted_alternative;
1139 if (wanted_alternative > 63)
1140 wanted_alternative = 63;
1141 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1142 wanted_alternative--;
1143 if (wanted_alternative && wanted_alternative != tmp)
1144 IWL_WARN(priv,
1145 "uCode alternative %d not available, choosing %d\n",
1146 tmp, wanted_alternative);
1147
1148 priv->ucode_ver = le32_to_cpu(ucode->ver);
1149 pieces->build = le32_to_cpu(ucode->build);
1150 data = ucode->data;
1151
1152 len -= sizeof(*ucode);
1153
1154 while (len >= sizeof(*tlv)) {
1155 u16 tlv_alt;
1156
1157 len -= sizeof(*tlv);
1158 tlv = (void *)data;
1159
1160 tlv_len = le32_to_cpu(tlv->length);
1161 tlv_type = le16_to_cpu(tlv->type);
1162 tlv_alt = le16_to_cpu(tlv->alternative);
1163 tlv_data = tlv->data;
1164
1165 if (len < tlv_len) {
1166 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1167 len, tlv_len);
1168 return -EINVAL;
1169 }
1170 len -= ALIGN(tlv_len, 4);
1171 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1172
1173 /*
1174 * Alternative 0 is always valid.
1175 *
1176 * Skip alternative TLVs that are not selected.
1177 */
1178 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1179 continue;
1180
1181 switch (tlv_type) {
1182 case IWL_UCODE_TLV_INST:
1183 pieces->inst = tlv_data;
1184 pieces->inst_size = tlv_len;
1185 break;
1186 case IWL_UCODE_TLV_DATA:
1187 pieces->data = tlv_data;
1188 pieces->data_size = tlv_len;
1189 break;
1190 case IWL_UCODE_TLV_INIT:
1191 pieces->init = tlv_data;
1192 pieces->init_size = tlv_len;
1193 break;
1194 case IWL_UCODE_TLV_INIT_DATA:
1195 pieces->init_data = tlv_data;
1196 pieces->init_data_size = tlv_len;
1197 break;
1198 case IWL_UCODE_TLV_BOOT:
1199 IWL_ERR(priv, "Found unexpected BOOT ucode\n");
1200 break;
1201 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1202 if (tlv_len != sizeof(u32))
1203 goto invalid_tlv_len;
1204 capa->max_probe_length =
1205 le32_to_cpup((__le32 *)tlv_data);
1206 break;
1207 case IWL_UCODE_TLV_PAN:
1208 if (tlv_len)
1209 goto invalid_tlv_len;
1210 capa->flags |= IWL_UCODE_TLV_FLAGS_PAN;
1211 break;
1212 case IWL_UCODE_TLV_FLAGS:
1213 /* must be at least one u32 */
1214 if (tlv_len < sizeof(u32))
1215 goto invalid_tlv_len;
1216 /* and a proper number of u32s */
1217 if (tlv_len % sizeof(u32))
1218 goto invalid_tlv_len;
1219 /*
1220 * This driver only reads the first u32 as
1221 * right now no more features are defined,
1222 * if that changes then either the driver
1223 * will not work with the new firmware, or
1224 * it'll not take advantage of new features.
1225 */
1226 capa->flags = le32_to_cpup((__le32 *)tlv_data);
1227 break;
1228 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1229 if (tlv_len != sizeof(u32))
1230 goto invalid_tlv_len;
1231 pieces->init_evtlog_ptr =
1232 le32_to_cpup((__le32 *)tlv_data);
1233 break;
1234 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1235 if (tlv_len != sizeof(u32))
1236 goto invalid_tlv_len;
1237 pieces->init_evtlog_size =
1238 le32_to_cpup((__le32 *)tlv_data);
1239 break;
1240 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1241 if (tlv_len != sizeof(u32))
1242 goto invalid_tlv_len;
1243 pieces->init_errlog_ptr =
1244 le32_to_cpup((__le32 *)tlv_data);
1245 break;
1246 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1247 if (tlv_len != sizeof(u32))
1248 goto invalid_tlv_len;
1249 pieces->inst_evtlog_ptr =
1250 le32_to_cpup((__le32 *)tlv_data);
1251 break;
1252 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1253 if (tlv_len != sizeof(u32))
1254 goto invalid_tlv_len;
1255 pieces->inst_evtlog_size =
1256 le32_to_cpup((__le32 *)tlv_data);
1257 break;
1258 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1259 if (tlv_len != sizeof(u32))
1260 goto invalid_tlv_len;
1261 pieces->inst_errlog_ptr =
1262 le32_to_cpup((__le32 *)tlv_data);
1263 break;
1264 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1265 if (tlv_len)
1266 goto invalid_tlv_len;
1267 priv->enhance_sensitivity_table = true;
1268 break;
1269 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1270 if (tlv_len != sizeof(u32))
1271 goto invalid_tlv_len;
1272 capa->standard_phy_calibration_size =
1273 le32_to_cpup((__le32 *)tlv_data);
1274 break;
1275 default:
1276 IWL_DEBUG_INFO(priv, "unknown TLV: %d\n", tlv_type);
1277 break;
1278 }
1279 }
1280
1281 if (len) {
1282 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1283 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1284 return -EINVAL;
1285 }
1286
1287 return 0;
1288
1289 invalid_tlv_len:
1290 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1291 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1292
1293 return -EINVAL;
1294 }
1295
1296 /**
1297 * iwl_ucode_callback - callback when firmware was loaded
1298 *
1299 * If loaded successfully, copies the firmware into buffers
1300 * for the card to fetch (via DMA).
1301 */
1302 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1303 {
1304 struct iwl_priv *priv = context;
1305 struct iwl_ucode_header *ucode;
1306 int err;
1307 struct iwlagn_firmware_pieces pieces;
1308 const unsigned int api_max = priv->cfg->ucode_api_max;
1309 const unsigned int api_min = priv->cfg->ucode_api_min;
1310 u32 api_ver;
1311 char buildstr[25];
1312 u32 build;
1313 struct iwlagn_ucode_capabilities ucode_capa = {
1314 .max_probe_length = 200,
1315 .standard_phy_calibration_size =
1316 IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1317 };
1318
1319 memset(&pieces, 0, sizeof(pieces));
1320
1321 if (!ucode_raw) {
1322 if (priv->fw_index <= priv->cfg->ucode_api_max)
1323 IWL_ERR(priv,
1324 "request for firmware file '%s' failed.\n",
1325 priv->firmware_name);
1326 goto try_again;
1327 }
1328
1329 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1330 priv->firmware_name, ucode_raw->size);
1331
1332 /* Make sure that we got at least the API version number */
1333 if (ucode_raw->size < 4) {
1334 IWL_ERR(priv, "File size way too small!\n");
1335 goto try_again;
1336 }
1337
1338 /* Data from ucode file: header followed by uCode images */
1339 ucode = (struct iwl_ucode_header *)ucode_raw->data;
1340
1341 if (ucode->ver)
1342 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1343 else
1344 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1345 &ucode_capa);
1346
1347 if (err)
1348 goto try_again;
1349
1350 api_ver = IWL_UCODE_API(priv->ucode_ver);
1351 build = pieces.build;
1352
1353 /*
1354 * api_ver should match the api version forming part of the
1355 * firmware filename ... but we don't check for that and only rely
1356 * on the API version read from firmware header from here on forward
1357 */
1358 /* no api version check required for experimental uCode */
1359 if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1360 if (api_ver < api_min || api_ver > api_max) {
1361 IWL_ERR(priv,
1362 "Driver unable to support your firmware API. "
1363 "Driver supports v%u, firmware is v%u.\n",
1364 api_max, api_ver);
1365 goto try_again;
1366 }
1367
1368 if (api_ver != api_max)
1369 IWL_ERR(priv,
1370 "Firmware has old API version. Expected v%u, "
1371 "got v%u. New firmware can be obtained "
1372 "from http://www.intellinuxwireless.org.\n",
1373 api_max, api_ver);
1374 }
1375
1376 if (build)
1377 sprintf(buildstr, " build %u%s", build,
1378 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1379 ? " (EXP)" : "");
1380 else
1381 buildstr[0] = '\0';
1382
1383 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1384 IWL_UCODE_MAJOR(priv->ucode_ver),
1385 IWL_UCODE_MINOR(priv->ucode_ver),
1386 IWL_UCODE_API(priv->ucode_ver),
1387 IWL_UCODE_SERIAL(priv->ucode_ver),
1388 buildstr);
1389
1390 snprintf(priv->hw->wiphy->fw_version,
1391 sizeof(priv->hw->wiphy->fw_version),
1392 "%u.%u.%u.%u%s",
1393 IWL_UCODE_MAJOR(priv->ucode_ver),
1394 IWL_UCODE_MINOR(priv->ucode_ver),
1395 IWL_UCODE_API(priv->ucode_ver),
1396 IWL_UCODE_SERIAL(priv->ucode_ver),
1397 buildstr);
1398
1399 /*
1400 * For any of the failures below (before allocating pci memory)
1401 * we will try to load a version with a smaller API -- maybe the
1402 * user just got a corrupted version of the latest API.
1403 */
1404
1405 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1406 priv->ucode_ver);
1407 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1408 pieces.inst_size);
1409 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1410 pieces.data_size);
1411 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1412 pieces.init_size);
1413 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1414 pieces.init_data_size);
1415
1416 /* Verify that uCode images will fit in card's SRAM */
1417 if (pieces.inst_size > priv->hw_params.max_inst_size) {
1418 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1419 pieces.inst_size);
1420 goto try_again;
1421 }
1422
1423 if (pieces.data_size > priv->hw_params.max_data_size) {
1424 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1425 pieces.data_size);
1426 goto try_again;
1427 }
1428
1429 if (pieces.init_size > priv->hw_params.max_inst_size) {
1430 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1431 pieces.init_size);
1432 goto try_again;
1433 }
1434
1435 if (pieces.init_data_size > priv->hw_params.max_data_size) {
1436 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1437 pieces.init_data_size);
1438 goto try_again;
1439 }
1440
1441 /* Allocate ucode buffers for card's bus-master loading ... */
1442
1443 /* Runtime instructions and 2 copies of data:
1444 * 1) unmodified from disk
1445 * 2) backup cache for save/restore during power-downs */
1446 if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_rt.code,
1447 pieces.inst, pieces.inst_size))
1448 goto err_pci_alloc;
1449 if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_rt.data,
1450 pieces.data, pieces.data_size))
1451 goto err_pci_alloc;
1452
1453 /* Initialization instructions and data */
1454 if (pieces.init_size && pieces.init_data_size) {
1455 if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init.code,
1456 pieces.init, pieces.init_size))
1457 goto err_pci_alloc;
1458 if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init.data,
1459 pieces.init_data, pieces.init_data_size))
1460 goto err_pci_alloc;
1461 }
1462
1463 /* Now that we can no longer fail, copy information */
1464
1465 /*
1466 * The (size - 16) / 12 formula is based on the information recorded
1467 * for each event, which is of mode 1 (including timestamp) for all
1468 * new microcodes that include this information.
1469 */
1470 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
1471 if (pieces.init_evtlog_size)
1472 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
1473 else
1474 priv->_agn.init_evtlog_size =
1475 priv->cfg->base_params->max_event_log_size;
1476 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
1477 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
1478 if (pieces.inst_evtlog_size)
1479 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
1480 else
1481 priv->_agn.inst_evtlog_size =
1482 priv->cfg->base_params->max_event_log_size;
1483 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
1484
1485 priv->new_scan_threshold_behaviour =
1486 !!(ucode_capa.flags & IWL_UCODE_TLV_FLAGS_NEWSCAN);
1487
1488 if ((priv->cfg->sku & EEPROM_SKU_CAP_IPAN_ENABLE) &&
1489 (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN)) {
1490 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
1491 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
1492 } else
1493 priv->sta_key_max_num = STA_KEY_MAX_NUM;
1494
1495 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1496 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
1497 else
1498 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
1499
1500 /*
1501 * figure out the offset of chain noise reset and gain commands
1502 * base on the size of standard phy calibration commands table size
1503 */
1504 if (ucode_capa.standard_phy_calibration_size >
1505 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
1506 ucode_capa.standard_phy_calibration_size =
1507 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1508
1509 priv->_agn.phy_calib_chain_noise_reset_cmd =
1510 ucode_capa.standard_phy_calibration_size;
1511 priv->_agn.phy_calib_chain_noise_gain_cmd =
1512 ucode_capa.standard_phy_calibration_size + 1;
1513
1514 /**************************************************
1515 * This is still part of probe() in a sense...
1516 *
1517 * 9. Setup and register with mac80211 and debugfs
1518 **************************************************/
1519 err = iwl_mac_setup_register(priv, &ucode_capa);
1520 if (err)
1521 goto out_unbind;
1522
1523 err = iwl_dbgfs_register(priv, DRV_NAME);
1524 if (err)
1525 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1526
1527 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
1528 &iwl_attribute_group);
1529 if (err) {
1530 IWL_ERR(priv, "failed to create sysfs device attributes\n");
1531 goto out_unbind;
1532 }
1533
1534 /* We have our copies now, allow OS release its copies */
1535 release_firmware(ucode_raw);
1536 complete(&priv->_agn.firmware_loading_complete);
1537 return;
1538
1539 try_again:
1540 /* try next, if any */
1541 if (iwl_request_firmware(priv, false))
1542 goto out_unbind;
1543 release_firmware(ucode_raw);
1544 return;
1545
1546 err_pci_alloc:
1547 IWL_ERR(priv, "failed to allocate pci memory\n");
1548 iwl_dealloc_ucode_pci(priv);
1549 out_unbind:
1550 complete(&priv->_agn.firmware_loading_complete);
1551 device_release_driver(&priv->pci_dev->dev);
1552 release_firmware(ucode_raw);
1553 }
1554
1555 static const char *desc_lookup_text[] = {
1556 "OK",
1557 "FAIL",
1558 "BAD_PARAM",
1559 "BAD_CHECKSUM",
1560 "NMI_INTERRUPT_WDG",
1561 "SYSASSERT",
1562 "FATAL_ERROR",
1563 "BAD_COMMAND",
1564 "HW_ERROR_TUNE_LOCK",
1565 "HW_ERROR_TEMPERATURE",
1566 "ILLEGAL_CHAN_FREQ",
1567 "VCC_NOT_STABLE",
1568 "FH_ERROR",
1569 "NMI_INTERRUPT_HOST",
1570 "NMI_INTERRUPT_ACTION_PT",
1571 "NMI_INTERRUPT_UNKNOWN",
1572 "UCODE_VERSION_MISMATCH",
1573 "HW_ERROR_ABS_LOCK",
1574 "HW_ERROR_CAL_LOCK_FAIL",
1575 "NMI_INTERRUPT_INST_ACTION_PT",
1576 "NMI_INTERRUPT_DATA_ACTION_PT",
1577 "NMI_TRM_HW_ER",
1578 "NMI_INTERRUPT_TRM",
1579 "NMI_INTERRUPT_BREAK_POINT"
1580 "DEBUG_0",
1581 "DEBUG_1",
1582 "DEBUG_2",
1583 "DEBUG_3",
1584 };
1585
1586 static struct { char *name; u8 num; } advanced_lookup[] = {
1587 { "NMI_INTERRUPT_WDG", 0x34 },
1588 { "SYSASSERT", 0x35 },
1589 { "UCODE_VERSION_MISMATCH", 0x37 },
1590 { "BAD_COMMAND", 0x38 },
1591 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
1592 { "FATAL_ERROR", 0x3D },
1593 { "NMI_TRM_HW_ERR", 0x46 },
1594 { "NMI_INTERRUPT_TRM", 0x4C },
1595 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
1596 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
1597 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
1598 { "NMI_INTERRUPT_HOST", 0x66 },
1599 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
1600 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
1601 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
1602 { "ADVANCED_SYSASSERT", 0 },
1603 };
1604
1605 static const char *desc_lookup(u32 num)
1606 {
1607 int i;
1608 int max = ARRAY_SIZE(desc_lookup_text);
1609
1610 if (num < max)
1611 return desc_lookup_text[num];
1612
1613 max = ARRAY_SIZE(advanced_lookup) - 1;
1614 for (i = 0; i < max; i++) {
1615 if (advanced_lookup[i].num == num)
1616 break;
1617 }
1618 return advanced_lookup[i].name;
1619 }
1620
1621 #define ERROR_START_OFFSET (1 * sizeof(u32))
1622 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1623
1624 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1625 {
1626 u32 base;
1627 struct iwl_error_event_table table;
1628
1629 base = priv->device_pointers.error_event_table;
1630 if (priv->ucode_type == IWL_UCODE_INIT) {
1631 if (!base)
1632 base = priv->_agn.init_errlog_ptr;
1633 } else {
1634 if (!base)
1635 base = priv->_agn.inst_errlog_ptr;
1636 }
1637
1638 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1639 IWL_ERR(priv,
1640 "Not valid error log pointer 0x%08X for %s uCode\n",
1641 base,
1642 (priv->ucode_type == IWL_UCODE_INIT)
1643 ? "Init" : "RT");
1644 return;
1645 }
1646
1647 iwl_read_targ_mem_words(priv, base, &table, sizeof(table));
1648
1649 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
1650 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1651 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1652 priv->status, table.valid);
1653 }
1654
1655 priv->isr_stats.err_code = table.error_id;
1656
1657 trace_iwlwifi_dev_ucode_error(priv, table.error_id, table.tsf_low,
1658 table.data1, table.data2, table.line,
1659 table.blink1, table.blink2, table.ilink1,
1660 table.ilink2, table.bcon_time, table.gp1,
1661 table.gp2, table.gp3, table.ucode_ver,
1662 table.hw_ver, table.brd_ver);
1663 IWL_ERR(priv, "0x%08X | %-28s\n", table.error_id,
1664 desc_lookup(table.error_id));
1665 IWL_ERR(priv, "0x%08X | uPc\n", table.pc);
1666 IWL_ERR(priv, "0x%08X | branchlink1\n", table.blink1);
1667 IWL_ERR(priv, "0x%08X | branchlink2\n", table.blink2);
1668 IWL_ERR(priv, "0x%08X | interruptlink1\n", table.ilink1);
1669 IWL_ERR(priv, "0x%08X | interruptlink2\n", table.ilink2);
1670 IWL_ERR(priv, "0x%08X | data1\n", table.data1);
1671 IWL_ERR(priv, "0x%08X | data2\n", table.data2);
1672 IWL_ERR(priv, "0x%08X | line\n", table.line);
1673 IWL_ERR(priv, "0x%08X | beacon time\n", table.bcon_time);
1674 IWL_ERR(priv, "0x%08X | tsf low\n", table.tsf_low);
1675 IWL_ERR(priv, "0x%08X | tsf hi\n", table.tsf_hi);
1676 IWL_ERR(priv, "0x%08X | time gp1\n", table.gp1);
1677 IWL_ERR(priv, "0x%08X | time gp2\n", table.gp2);
1678 IWL_ERR(priv, "0x%08X | time gp3\n", table.gp3);
1679 IWL_ERR(priv, "0x%08X | uCode version\n", table.ucode_ver);
1680 IWL_ERR(priv, "0x%08X | hw version\n", table.hw_ver);
1681 IWL_ERR(priv, "0x%08X | board version\n", table.brd_ver);
1682 IWL_ERR(priv, "0x%08X | hcmd\n", table.hcmd);
1683 }
1684
1685 #define EVENT_START_OFFSET (4 * sizeof(u32))
1686
1687 /**
1688 * iwl_print_event_log - Dump error event log to syslog
1689 *
1690 */
1691 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1692 u32 num_events, u32 mode,
1693 int pos, char **buf, size_t bufsz)
1694 {
1695 u32 i;
1696 u32 base; /* SRAM byte address of event log header */
1697 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1698 u32 ptr; /* SRAM byte address of log data */
1699 u32 ev, time, data; /* event log data */
1700 unsigned long reg_flags;
1701
1702 if (num_events == 0)
1703 return pos;
1704
1705 base = priv->device_pointers.log_event_table;
1706 if (priv->ucode_type == IWL_UCODE_INIT) {
1707 if (!base)
1708 base = priv->_agn.init_evtlog_ptr;
1709 } else {
1710 if (!base)
1711 base = priv->_agn.inst_evtlog_ptr;
1712 }
1713
1714 if (mode == 0)
1715 event_size = 2 * sizeof(u32);
1716 else
1717 event_size = 3 * sizeof(u32);
1718
1719 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1720
1721 /* Make sure device is powered up for SRAM reads */
1722 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1723 iwl_grab_nic_access(priv);
1724
1725 /* Set starting address; reads will auto-increment */
1726 iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
1727 rmb();
1728
1729 /* "time" is actually "data" for mode 0 (no timestamp).
1730 * place event id # at far right for easier visual parsing. */
1731 for (i = 0; i < num_events; i++) {
1732 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1733 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1734 if (mode == 0) {
1735 /* data, ev */
1736 if (bufsz) {
1737 pos += scnprintf(*buf + pos, bufsz - pos,
1738 "EVT_LOG:0x%08x:%04u\n",
1739 time, ev);
1740 } else {
1741 trace_iwlwifi_dev_ucode_event(priv, 0,
1742 time, ev);
1743 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1744 time, ev);
1745 }
1746 } else {
1747 data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1748 if (bufsz) {
1749 pos += scnprintf(*buf + pos, bufsz - pos,
1750 "EVT_LOGT:%010u:0x%08x:%04u\n",
1751 time, data, ev);
1752 } else {
1753 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1754 time, data, ev);
1755 trace_iwlwifi_dev_ucode_event(priv, time,
1756 data, ev);
1757 }
1758 }
1759 }
1760
1761 /* Allow device to power down */
1762 iwl_release_nic_access(priv);
1763 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
1764 return pos;
1765 }
1766
1767 /**
1768 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
1769 */
1770 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
1771 u32 num_wraps, u32 next_entry,
1772 u32 size, u32 mode,
1773 int pos, char **buf, size_t bufsz)
1774 {
1775 /*
1776 * display the newest DEFAULT_LOG_ENTRIES entries
1777 * i.e the entries just before the next ont that uCode would fill.
1778 */
1779 if (num_wraps) {
1780 if (next_entry < size) {
1781 pos = iwl_print_event_log(priv,
1782 capacity - (size - next_entry),
1783 size - next_entry, mode,
1784 pos, buf, bufsz);
1785 pos = iwl_print_event_log(priv, 0,
1786 next_entry, mode,
1787 pos, buf, bufsz);
1788 } else
1789 pos = iwl_print_event_log(priv, next_entry - size,
1790 size, mode, pos, buf, bufsz);
1791 } else {
1792 if (next_entry < size) {
1793 pos = iwl_print_event_log(priv, 0, next_entry,
1794 mode, pos, buf, bufsz);
1795 } else {
1796 pos = iwl_print_event_log(priv, next_entry - size,
1797 size, mode, pos, buf, bufsz);
1798 }
1799 }
1800 return pos;
1801 }
1802
1803 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
1804
1805 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
1806 char **buf, bool display)
1807 {
1808 u32 base; /* SRAM byte address of event log header */
1809 u32 capacity; /* event log capacity in # entries */
1810 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1811 u32 num_wraps; /* # times uCode wrapped to top of log */
1812 u32 next_entry; /* index of next entry to be written by uCode */
1813 u32 size; /* # entries that we'll print */
1814 u32 logsize;
1815 int pos = 0;
1816 size_t bufsz = 0;
1817
1818 base = priv->device_pointers.log_event_table;
1819 if (priv->ucode_type == IWL_UCODE_INIT) {
1820 logsize = priv->_agn.init_evtlog_size;
1821 if (!base)
1822 base = priv->_agn.init_evtlog_ptr;
1823 } else {
1824 logsize = priv->_agn.inst_evtlog_size;
1825 if (!base)
1826 base = priv->_agn.inst_evtlog_ptr;
1827 }
1828
1829 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1830 IWL_ERR(priv,
1831 "Invalid event log pointer 0x%08X for %s uCode\n",
1832 base,
1833 (priv->ucode_type == IWL_UCODE_INIT)
1834 ? "Init" : "RT");
1835 return -EINVAL;
1836 }
1837
1838 /* event log header */
1839 capacity = iwl_read_targ_mem(priv, base);
1840 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1841 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1842 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1843
1844 if (capacity > logsize) {
1845 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
1846 capacity, logsize);
1847 capacity = logsize;
1848 }
1849
1850 if (next_entry > logsize) {
1851 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
1852 next_entry, logsize);
1853 next_entry = logsize;
1854 }
1855
1856 size = num_wraps ? capacity : next_entry;
1857
1858 /* bail out if nothing in log */
1859 if (size == 0) {
1860 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
1861 return pos;
1862 }
1863
1864 /* enable/disable bt channel inhibition */
1865 priv->bt_ch_announce = iwlagn_bt_ch_announce;
1866
1867 #ifdef CONFIG_IWLWIFI_DEBUG
1868 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
1869 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
1870 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
1871 #else
1872 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
1873 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
1874 #endif
1875 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
1876 size);
1877
1878 #ifdef CONFIG_IWLWIFI_DEBUG
1879 if (display) {
1880 if (full_log)
1881 bufsz = capacity * 48;
1882 else
1883 bufsz = size * 48;
1884 *buf = kmalloc(bufsz, GFP_KERNEL);
1885 if (!*buf)
1886 return -ENOMEM;
1887 }
1888 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
1889 /*
1890 * if uCode has wrapped back to top of log,
1891 * start at the oldest entry,
1892 * i.e the next one that uCode would fill.
1893 */
1894 if (num_wraps)
1895 pos = iwl_print_event_log(priv, next_entry,
1896 capacity - next_entry, mode,
1897 pos, buf, bufsz);
1898 /* (then/else) start at top of log */
1899 pos = iwl_print_event_log(priv, 0,
1900 next_entry, mode, pos, buf, bufsz);
1901 } else
1902 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
1903 next_entry, size, mode,
1904 pos, buf, bufsz);
1905 #else
1906 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
1907 next_entry, size, mode,
1908 pos, buf, bufsz);
1909 #endif
1910 return pos;
1911 }
1912
1913 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1914 {
1915 struct iwl_ct_kill_config cmd;
1916 struct iwl_ct_kill_throttling_config adv_cmd;
1917 unsigned long flags;
1918 int ret = 0;
1919
1920 spin_lock_irqsave(&priv->lock, flags);
1921 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1922 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1923 spin_unlock_irqrestore(&priv->lock, flags);
1924 priv->thermal_throttle.ct_kill_toggle = false;
1925
1926 if (priv->cfg->base_params->support_ct_kill_exit) {
1927 adv_cmd.critical_temperature_enter =
1928 cpu_to_le32(priv->hw_params.ct_kill_threshold);
1929 adv_cmd.critical_temperature_exit =
1930 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
1931
1932 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1933 sizeof(adv_cmd), &adv_cmd);
1934 if (ret)
1935 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
1936 else
1937 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
1938 "succeeded, "
1939 "critical temperature enter is %d,"
1940 "exit is %d\n",
1941 priv->hw_params.ct_kill_threshold,
1942 priv->hw_params.ct_kill_exit_threshold);
1943 } else {
1944 cmd.critical_temperature_R =
1945 cpu_to_le32(priv->hw_params.ct_kill_threshold);
1946
1947 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1948 sizeof(cmd), &cmd);
1949 if (ret)
1950 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
1951 else
1952 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
1953 "succeeded, "
1954 "critical temperature is %d\n",
1955 priv->hw_params.ct_kill_threshold);
1956 }
1957 }
1958
1959 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
1960 {
1961 struct iwl_calib_cfg_cmd calib_cfg_cmd;
1962 struct iwl_host_cmd cmd = {
1963 .id = CALIBRATION_CFG_CMD,
1964 .len = { sizeof(struct iwl_calib_cfg_cmd), },
1965 .data = { &calib_cfg_cmd, },
1966 };
1967
1968 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
1969 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
1970 calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
1971
1972 return iwl_send_cmd(priv, &cmd);
1973 }
1974
1975
1976 /**
1977 * iwl_alive_start - called after REPLY_ALIVE notification received
1978 * from protocol/runtime uCode (initialization uCode's
1979 * Alive gets handled by iwl_init_alive_start()).
1980 */
1981 int iwl_alive_start(struct iwl_priv *priv)
1982 {
1983 int ret = 0;
1984 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1985
1986 iwl_reset_ict(priv);
1987
1988 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
1989
1990 /* After the ALIVE response, we can send host commands to the uCode */
1991 set_bit(STATUS_ALIVE, &priv->status);
1992
1993 /* Enable watchdog to monitor the driver tx queues */
1994 iwl_setup_watchdog(priv);
1995
1996 if (iwl_is_rfkill(priv))
1997 return -ERFKILL;
1998
1999 /* download priority table before any calibration request */
2000 if (priv->cfg->bt_params &&
2001 priv->cfg->bt_params->advanced_bt_coexist) {
2002 /* Configure Bluetooth device coexistence support */
2003 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2004 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2005 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2006 priv->cfg->ops->hcmd->send_bt_config(priv);
2007 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2008 iwlagn_send_prio_tbl(priv);
2009
2010 /* FIXME: w/a to force change uCode BT state machine */
2011 ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2012 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2013 if (ret)
2014 return ret;
2015 ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2016 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2017 if (ret)
2018 return ret;
2019 }
2020 if (priv->hw_params.calib_rt_cfg)
2021 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2022
2023 ieee80211_wake_queues(priv->hw);
2024
2025 priv->active_rate = IWL_RATES_MASK;
2026
2027 /* Configure Tx antenna selection based on H/W config */
2028 if (priv->cfg->ops->hcmd->set_tx_ant)
2029 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2030
2031 if (iwl_is_associated_ctx(ctx)) {
2032 struct iwl_rxon_cmd *active_rxon =
2033 (struct iwl_rxon_cmd *)&ctx->active;
2034 /* apply any changes in staging */
2035 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2036 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2037 } else {
2038 struct iwl_rxon_context *tmp;
2039 /* Initialize our rx_config data */
2040 for_each_context(priv, tmp)
2041 iwl_connection_init_rx_config(priv, tmp);
2042
2043 if (priv->cfg->ops->hcmd->set_rxon_chain)
2044 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2045 }
2046
2047 if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
2048 !priv->cfg->bt_params->advanced_bt_coexist)) {
2049 /*
2050 * default is 2-wire BT coexexistence support
2051 */
2052 priv->cfg->ops->hcmd->send_bt_config(priv);
2053 }
2054
2055 iwl_reset_run_time_calib(priv);
2056
2057 set_bit(STATUS_READY, &priv->status);
2058
2059 /* Configure the adapter for unassociated operation */
2060 ret = iwlagn_commit_rxon(priv, ctx);
2061 if (ret)
2062 return ret;
2063
2064 /* At this point, the NIC is initialized and operational */
2065 iwl_rf_kill_ct_config(priv);
2066
2067 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2068
2069 return iwl_power_update_mode(priv, true);
2070 }
2071
2072 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2073
2074 static void __iwl_down(struct iwl_priv *priv)
2075 {
2076 int exit_pending;
2077
2078 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2079
2080 iwl_scan_cancel_timeout(priv, 200);
2081
2082 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2083
2084 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2085 * to prevent rearm timer */
2086 del_timer_sync(&priv->watchdog);
2087
2088 iwl_clear_ucode_stations(priv, NULL);
2089 iwl_dealloc_bcast_stations(priv);
2090 iwl_clear_driver_stations(priv);
2091
2092 /* reset BT coex data */
2093 priv->bt_status = 0;
2094 if (priv->cfg->bt_params)
2095 priv->bt_traffic_load =
2096 priv->cfg->bt_params->bt_init_traffic_load;
2097 else
2098 priv->bt_traffic_load = 0;
2099 priv->bt_full_concurrent = false;
2100 priv->bt_ci_compliance = 0;
2101
2102 /* Wipe out the EXIT_PENDING status bit if we are not actually
2103 * exiting the module */
2104 if (!exit_pending)
2105 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2106
2107 if (priv->mac80211_registered)
2108 ieee80211_stop_queues(priv->hw);
2109
2110 /* Clear out all status bits but a few that are stable across reset */
2111 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2112 STATUS_RF_KILL_HW |
2113 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2114 STATUS_GEO_CONFIGURED |
2115 test_bit(STATUS_FW_ERROR, &priv->status) <<
2116 STATUS_FW_ERROR |
2117 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2118 STATUS_EXIT_PENDING;
2119
2120 iwlagn_stop_device(priv);
2121
2122 dev_kfree_skb(priv->beacon_skb);
2123 priv->beacon_skb = NULL;
2124 }
2125
2126 static void iwl_down(struct iwl_priv *priv)
2127 {
2128 mutex_lock(&priv->mutex);
2129 __iwl_down(priv);
2130 mutex_unlock(&priv->mutex);
2131
2132 iwl_cancel_deferred_work(priv);
2133 }
2134
2135 #define HW_READY_TIMEOUT (50)
2136
2137 /* Note: returns poll_bit return value, which is >= 0 if success */
2138 static int iwl_set_hw_ready(struct iwl_priv *priv)
2139 {
2140 int ret;
2141
2142 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2143 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2144
2145 /* See if we got it */
2146 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2147 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2148 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2149 HW_READY_TIMEOUT);
2150
2151 IWL_DEBUG_INFO(priv, "hardware%s ready\n", ret < 0 ? " not" : "");
2152 return ret;
2153 }
2154
2155 /* Note: returns standard 0/-ERROR code */
2156 int iwl_prepare_card_hw(struct iwl_priv *priv)
2157 {
2158 int ret;
2159
2160 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2161
2162 ret = iwl_set_hw_ready(priv);
2163 if (ret >= 0)
2164 return 0;
2165
2166 /* If HW is not ready, prepare the conditions to check again */
2167 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2168 CSR_HW_IF_CONFIG_REG_PREPARE);
2169
2170 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2171 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2172 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2173
2174 if (ret < 0)
2175 return ret;
2176
2177 /* HW should be ready by now, check again. */
2178 ret = iwl_set_hw_ready(priv);
2179 if (ret >= 0)
2180 return 0;
2181 return ret;
2182 }
2183
2184 #define MAX_HW_RESTARTS 5
2185
2186 static int __iwl_up(struct iwl_priv *priv)
2187 {
2188 struct iwl_rxon_context *ctx;
2189 int ret;
2190
2191 lockdep_assert_held(&priv->mutex);
2192
2193 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2194 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2195 return -EIO;
2196 }
2197
2198 for_each_context(priv, ctx) {
2199 ret = iwlagn_alloc_bcast_station(priv, ctx);
2200 if (ret) {
2201 iwl_dealloc_bcast_stations(priv);
2202 return ret;
2203 }
2204 }
2205
2206 ret = iwlagn_run_init_ucode(priv);
2207 if (ret) {
2208 IWL_ERR(priv, "Failed to run INIT ucode: %d\n", ret);
2209 goto error;
2210 }
2211
2212 ret = iwlagn_load_ucode_wait_alive(priv,
2213 &priv->ucode_rt,
2214 IWL_UCODE_REGULAR);
2215 if (ret) {
2216 IWL_ERR(priv, "Failed to start RT ucode: %d\n", ret);
2217 goto error;
2218 }
2219
2220 ret = iwl_alive_start(priv);
2221 if (ret)
2222 goto error;
2223 return 0;
2224
2225 error:
2226 set_bit(STATUS_EXIT_PENDING, &priv->status);
2227 __iwl_down(priv);
2228 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2229
2230 IWL_ERR(priv, "Unable to initialize device.\n");
2231 return ret;
2232 }
2233
2234
2235 /*****************************************************************************
2236 *
2237 * Workqueue callbacks
2238 *
2239 *****************************************************************************/
2240
2241 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2242 {
2243 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2244 run_time_calib_work);
2245
2246 mutex_lock(&priv->mutex);
2247
2248 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2249 test_bit(STATUS_SCANNING, &priv->status)) {
2250 mutex_unlock(&priv->mutex);
2251 return;
2252 }
2253
2254 if (priv->start_calib) {
2255 iwl_chain_noise_calibration(priv);
2256 iwl_sensitivity_calibration(priv);
2257 }
2258
2259 mutex_unlock(&priv->mutex);
2260 }
2261
2262 static void iwlagn_prepare_restart(struct iwl_priv *priv)
2263 {
2264 struct iwl_rxon_context *ctx;
2265 bool bt_full_concurrent;
2266 u8 bt_ci_compliance;
2267 u8 bt_load;
2268 u8 bt_status;
2269
2270 lockdep_assert_held(&priv->mutex);
2271
2272 for_each_context(priv, ctx)
2273 ctx->vif = NULL;
2274 priv->is_open = 0;
2275
2276 /*
2277 * __iwl_down() will clear the BT status variables,
2278 * which is correct, but when we restart we really
2279 * want to keep them so restore them afterwards.
2280 *
2281 * The restart process will later pick them up and
2282 * re-configure the hw when we reconfigure the BT
2283 * command.
2284 */
2285 bt_full_concurrent = priv->bt_full_concurrent;
2286 bt_ci_compliance = priv->bt_ci_compliance;
2287 bt_load = priv->bt_traffic_load;
2288 bt_status = priv->bt_status;
2289
2290 __iwl_down(priv);
2291
2292 priv->bt_full_concurrent = bt_full_concurrent;
2293 priv->bt_ci_compliance = bt_ci_compliance;
2294 priv->bt_traffic_load = bt_load;
2295 priv->bt_status = bt_status;
2296 }
2297
2298 static void iwl_bg_restart(struct work_struct *data)
2299 {
2300 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2301
2302 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2303 return;
2304
2305 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2306 mutex_lock(&priv->mutex);
2307 iwlagn_prepare_restart(priv);
2308 mutex_unlock(&priv->mutex);
2309 iwl_cancel_deferred_work(priv);
2310 ieee80211_restart_hw(priv->hw);
2311 } else {
2312 WARN_ON(1);
2313 }
2314 }
2315
2316 static void iwl_bg_rx_replenish(struct work_struct *data)
2317 {
2318 struct iwl_priv *priv =
2319 container_of(data, struct iwl_priv, rx_replenish);
2320
2321 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2322 return;
2323
2324 mutex_lock(&priv->mutex);
2325 iwlagn_rx_replenish(priv);
2326 mutex_unlock(&priv->mutex);
2327 }
2328
2329 static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2330 struct ieee80211_channel *chan,
2331 enum nl80211_channel_type channel_type,
2332 unsigned int wait)
2333 {
2334 struct iwl_priv *priv = hw->priv;
2335 int ret;
2336
2337 /* Not supported if we don't have PAN */
2338 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
2339 ret = -EOPNOTSUPP;
2340 goto free;
2341 }
2342
2343 /* Not supported on pre-P2P firmware */
2344 if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
2345 BIT(NL80211_IFTYPE_P2P_CLIENT))) {
2346 ret = -EOPNOTSUPP;
2347 goto free;
2348 }
2349
2350 mutex_lock(&priv->mutex);
2351
2352 if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
2353 /*
2354 * If the PAN context is free, use the normal
2355 * way of doing remain-on-channel offload + TX.
2356 */
2357 ret = 1;
2358 goto out;
2359 }
2360
2361 /* TODO: queue up if scanning? */
2362 if (test_bit(STATUS_SCANNING, &priv->status) ||
2363 priv->_agn.offchan_tx_skb) {
2364 ret = -EBUSY;
2365 goto out;
2366 }
2367
2368 /*
2369 * max_scan_ie_len doesn't include the blank SSID or the header,
2370 * so need to add that again here.
2371 */
2372 if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
2373 ret = -ENOBUFS;
2374 goto out;
2375 }
2376
2377 priv->_agn.offchan_tx_skb = skb;
2378 priv->_agn.offchan_tx_timeout = wait;
2379 priv->_agn.offchan_tx_chan = chan;
2380
2381 ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
2382 IWL_SCAN_OFFCH_TX, chan->band);
2383 if (ret)
2384 priv->_agn.offchan_tx_skb = NULL;
2385 out:
2386 mutex_unlock(&priv->mutex);
2387 free:
2388 if (ret < 0)
2389 kfree_skb(skb);
2390
2391 return ret;
2392 }
2393
2394 static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
2395 {
2396 struct iwl_priv *priv = hw->priv;
2397 int ret;
2398
2399 mutex_lock(&priv->mutex);
2400
2401 if (!priv->_agn.offchan_tx_skb) {
2402 ret = -EINVAL;
2403 goto unlock;
2404 }
2405
2406 priv->_agn.offchan_tx_skb = NULL;
2407
2408 ret = iwl_scan_cancel_timeout(priv, 200);
2409 if (ret)
2410 ret = -EIO;
2411 unlock:
2412 mutex_unlock(&priv->mutex);
2413
2414 return ret;
2415 }
2416
2417 /*****************************************************************************
2418 *
2419 * mac80211 entry point functions
2420 *
2421 *****************************************************************************/
2422
2423 static const struct ieee80211_iface_limit iwlagn_sta_ap_limits[] = {
2424 {
2425 .max = 1,
2426 .types = BIT(NL80211_IFTYPE_STATION),
2427 },
2428 {
2429 .max = 1,
2430 .types = BIT(NL80211_IFTYPE_AP),
2431 },
2432 };
2433
2434 static const struct ieee80211_iface_limit iwlagn_2sta_limits[] = {
2435 {
2436 .max = 2,
2437 .types = BIT(NL80211_IFTYPE_STATION),
2438 },
2439 };
2440
2441 static const struct ieee80211_iface_limit iwlagn_p2p_sta_go_limits[] = {
2442 {
2443 .max = 1,
2444 .types = BIT(NL80211_IFTYPE_STATION),
2445 },
2446 {
2447 .max = 1,
2448 .types = BIT(NL80211_IFTYPE_P2P_GO) |
2449 BIT(NL80211_IFTYPE_AP),
2450 },
2451 };
2452
2453 static const struct ieee80211_iface_limit iwlagn_p2p_2sta_limits[] = {
2454 {
2455 .max = 2,
2456 .types = BIT(NL80211_IFTYPE_STATION),
2457 },
2458 {
2459 .max = 1,
2460 .types = BIT(NL80211_IFTYPE_P2P_CLIENT),
2461 },
2462 };
2463
2464 static const struct ieee80211_iface_combination
2465 iwlagn_iface_combinations_dualmode[] = {
2466 { .num_different_channels = 1,
2467 .max_interfaces = 2,
2468 .beacon_int_infra_match = true,
2469 .limits = iwlagn_sta_ap_limits,
2470 .n_limits = ARRAY_SIZE(iwlagn_sta_ap_limits),
2471 },
2472 { .num_different_channels = 1,
2473 .max_interfaces = 2,
2474 .limits = iwlagn_2sta_limits,
2475 .n_limits = ARRAY_SIZE(iwlagn_2sta_limits),
2476 },
2477 };
2478
2479 static const struct ieee80211_iface_combination
2480 iwlagn_iface_combinations_p2p[] = {
2481 { .num_different_channels = 1,
2482 .max_interfaces = 2,
2483 .beacon_int_infra_match = true,
2484 .limits = iwlagn_p2p_sta_go_limits,
2485 .n_limits = ARRAY_SIZE(iwlagn_p2p_sta_go_limits),
2486 },
2487 { .num_different_channels = 1,
2488 .max_interfaces = 2,
2489 .limits = iwlagn_p2p_2sta_limits,
2490 .n_limits = ARRAY_SIZE(iwlagn_p2p_2sta_limits),
2491 },
2492 };
2493
2494 /*
2495 * Not a mac80211 entry point function, but it fits in with all the
2496 * other mac80211 functions grouped here.
2497 */
2498 static int iwl_mac_setup_register(struct iwl_priv *priv,
2499 struct iwlagn_ucode_capabilities *capa)
2500 {
2501 int ret;
2502 struct ieee80211_hw *hw = priv->hw;
2503 struct iwl_rxon_context *ctx;
2504
2505 hw->rate_control_algorithm = "iwl-agn-rs";
2506
2507 /* Tell mac80211 our characteristics */
2508 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2509 IEEE80211_HW_AMPDU_AGGREGATION |
2510 IEEE80211_HW_NEED_DTIM_PERIOD |
2511 IEEE80211_HW_SPECTRUM_MGMT |
2512 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2513
2514 hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2515
2516 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2517 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2518
2519 if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE)
2520 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2521 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2522
2523 if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP)
2524 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
2525
2526 hw->sta_data_size = sizeof(struct iwl_station_priv);
2527 hw->vif_data_size = sizeof(struct iwl_vif_priv);
2528
2529 for_each_context(priv, ctx) {
2530 hw->wiphy->interface_modes |= ctx->interface_modes;
2531 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
2532 }
2533
2534 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
2535
2536 if (hw->wiphy->interface_modes & BIT(NL80211_IFTYPE_P2P_CLIENT)) {
2537 hw->wiphy->iface_combinations = iwlagn_iface_combinations_p2p;
2538 hw->wiphy->n_iface_combinations =
2539 ARRAY_SIZE(iwlagn_iface_combinations_p2p);
2540 } else if (hw->wiphy->interface_modes & BIT(NL80211_IFTYPE_AP)) {
2541 hw->wiphy->iface_combinations = iwlagn_iface_combinations_dualmode;
2542 hw->wiphy->n_iface_combinations =
2543 ARRAY_SIZE(iwlagn_iface_combinations_dualmode);
2544 }
2545
2546 hw->wiphy->max_remain_on_channel_duration = 1000;
2547
2548 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2549 WIPHY_FLAG_DISABLE_BEACON_HINTS |
2550 WIPHY_FLAG_IBSS_RSN;
2551
2552 /*
2553 * For now, disable PS by default because it affects
2554 * RX performance significantly.
2555 */
2556 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2557
2558 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2559 /* we create the 802.11 header and a zero-length SSID element */
2560 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
2561
2562 /* Default value; 4 EDCA QOS priorities */
2563 hw->queues = 4;
2564
2565 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2566
2567 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2568 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2569 &priv->bands[IEEE80211_BAND_2GHZ];
2570 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2571 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2572 &priv->bands[IEEE80211_BAND_5GHZ];
2573
2574 iwl_leds_init(priv);
2575
2576 ret = ieee80211_register_hw(priv->hw);
2577 if (ret) {
2578 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2579 return ret;
2580 }
2581 priv->mac80211_registered = 1;
2582
2583 return 0;
2584 }
2585
2586
2587 static int iwlagn_mac_start(struct ieee80211_hw *hw)
2588 {
2589 struct iwl_priv *priv = hw->priv;
2590 int ret;
2591
2592 IWL_DEBUG_MAC80211(priv, "enter\n");
2593
2594 /* we should be verifying the device is ready to be opened */
2595 mutex_lock(&priv->mutex);
2596 ret = __iwl_up(priv);
2597 mutex_unlock(&priv->mutex);
2598 if (ret)
2599 return ret;
2600
2601 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2602
2603 /* Now we should be done, and the READY bit should be set. */
2604 if (WARN_ON(!test_bit(STATUS_READY, &priv->status)))
2605 ret = -EIO;
2606
2607 iwlagn_led_enable(priv);
2608
2609 priv->is_open = 1;
2610 IWL_DEBUG_MAC80211(priv, "leave\n");
2611 return 0;
2612 }
2613
2614 static void iwlagn_mac_stop(struct ieee80211_hw *hw)
2615 {
2616 struct iwl_priv *priv = hw->priv;
2617
2618 IWL_DEBUG_MAC80211(priv, "enter\n");
2619
2620 if (!priv->is_open)
2621 return;
2622
2623 priv->is_open = 0;
2624
2625 iwl_down(priv);
2626
2627 flush_workqueue(priv->workqueue);
2628
2629 /* User space software may expect getting rfkill changes
2630 * even if interface is down */
2631 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2632 iwl_enable_rfkill_int(priv);
2633
2634 IWL_DEBUG_MAC80211(priv, "leave\n");
2635 }
2636
2637 static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2638 {
2639 struct iwl_priv *priv = hw->priv;
2640
2641 IWL_DEBUG_MACDUMP(priv, "enter\n");
2642
2643 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2644 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2645
2646 if (iwlagn_tx_skb(priv, skb))
2647 dev_kfree_skb_any(skb);
2648
2649 IWL_DEBUG_MACDUMP(priv, "leave\n");
2650 }
2651
2652 static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
2653 struct ieee80211_vif *vif,
2654 struct ieee80211_key_conf *keyconf,
2655 struct ieee80211_sta *sta,
2656 u32 iv32, u16 *phase1key)
2657 {
2658 struct iwl_priv *priv = hw->priv;
2659 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2660
2661 IWL_DEBUG_MAC80211(priv, "enter\n");
2662
2663 iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
2664 iv32, phase1key);
2665
2666 IWL_DEBUG_MAC80211(priv, "leave\n");
2667 }
2668
2669 static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2670 struct ieee80211_vif *vif,
2671 struct ieee80211_sta *sta,
2672 struct ieee80211_key_conf *key)
2673 {
2674 struct iwl_priv *priv = hw->priv;
2675 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2676 struct iwl_rxon_context *ctx = vif_priv->ctx;
2677 int ret;
2678 u8 sta_id;
2679 bool is_default_wep_key = false;
2680
2681 IWL_DEBUG_MAC80211(priv, "enter\n");
2682
2683 if (iwlagn_mod_params.sw_crypto) {
2684 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
2685 return -EOPNOTSUPP;
2686 }
2687
2688 /*
2689 * To support IBSS RSN, don't program group keys in IBSS, the
2690 * hardware will then not attempt to decrypt the frames.
2691 */
2692 if (vif->type == NL80211_IFTYPE_ADHOC &&
2693 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
2694 return -EOPNOTSUPP;
2695
2696 sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
2697 if (sta_id == IWL_INVALID_STATION)
2698 return -EINVAL;
2699
2700 mutex_lock(&priv->mutex);
2701 iwl_scan_cancel_timeout(priv, 100);
2702
2703 /*
2704 * If we are getting WEP group key and we didn't receive any key mapping
2705 * so far, we are in legacy wep mode (group key only), otherwise we are
2706 * in 1X mode.
2707 * In legacy wep mode, we use another host command to the uCode.
2708 */
2709 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
2710 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
2711 !sta) {
2712 if (cmd == SET_KEY)
2713 is_default_wep_key = !ctx->key_mapping_keys;
2714 else
2715 is_default_wep_key =
2716 (key->hw_key_idx == HW_KEY_DEFAULT);
2717 }
2718
2719 switch (cmd) {
2720 case SET_KEY:
2721 if (is_default_wep_key)
2722 ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
2723 else
2724 ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
2725 key, sta_id);
2726
2727 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
2728 break;
2729 case DISABLE_KEY:
2730 if (is_default_wep_key)
2731 ret = iwl_remove_default_wep_key(priv, ctx, key);
2732 else
2733 ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
2734
2735 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
2736 break;
2737 default:
2738 ret = -EINVAL;
2739 }
2740
2741 mutex_unlock(&priv->mutex);
2742 IWL_DEBUG_MAC80211(priv, "leave\n");
2743
2744 return ret;
2745 }
2746
2747 static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
2748 struct ieee80211_vif *vif,
2749 enum ieee80211_ampdu_mlme_action action,
2750 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
2751 u8 buf_size)
2752 {
2753 struct iwl_priv *priv = hw->priv;
2754 int ret = -EINVAL;
2755 struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
2756
2757 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
2758 sta->addr, tid);
2759
2760 if (!(priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE))
2761 return -EACCES;
2762
2763 mutex_lock(&priv->mutex);
2764
2765 switch (action) {
2766 case IEEE80211_AMPDU_RX_START:
2767 IWL_DEBUG_HT(priv, "start Rx\n");
2768 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
2769 break;
2770 case IEEE80211_AMPDU_RX_STOP:
2771 IWL_DEBUG_HT(priv, "stop Rx\n");
2772 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
2773 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2774 ret = 0;
2775 break;
2776 case IEEE80211_AMPDU_TX_START:
2777 IWL_DEBUG_HT(priv, "start Tx\n");
2778 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
2779 if (ret == 0) {
2780 priv->_agn.agg_tids_count++;
2781 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
2782 priv->_agn.agg_tids_count);
2783 }
2784 break;
2785 case IEEE80211_AMPDU_TX_STOP:
2786 IWL_DEBUG_HT(priv, "stop Tx\n");
2787 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
2788 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
2789 priv->_agn.agg_tids_count--;
2790 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
2791 priv->_agn.agg_tids_count);
2792 }
2793 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2794 ret = 0;
2795 if (priv->cfg->ht_params &&
2796 priv->cfg->ht_params->use_rts_for_aggregation) {
2797 /*
2798 * switch off RTS/CTS if it was previously enabled
2799 */
2800 sta_priv->lq_sta.lq.general_params.flags &=
2801 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
2802 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
2803 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
2804 }
2805 break;
2806 case IEEE80211_AMPDU_TX_OPERATIONAL:
2807 buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
2808
2809 iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size);
2810
2811 /*
2812 * If the limit is 0, then it wasn't initialised yet,
2813 * use the default. We can do that since we take the
2814 * minimum below, and we don't want to go above our
2815 * default due to hardware restrictions.
2816 */
2817 if (sta_priv->max_agg_bufsize == 0)
2818 sta_priv->max_agg_bufsize =
2819 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2820
2821 /*
2822 * Even though in theory the peer could have different
2823 * aggregation reorder buffer sizes for different sessions,
2824 * our ucode doesn't allow for that and has a global limit
2825 * for each station. Therefore, use the minimum of all the
2826 * aggregation sessions and our default value.
2827 */
2828 sta_priv->max_agg_bufsize =
2829 min(sta_priv->max_agg_bufsize, buf_size);
2830
2831 if (priv->cfg->ht_params &&
2832 priv->cfg->ht_params->use_rts_for_aggregation) {
2833 /*
2834 * switch to RTS/CTS if it is the prefer protection
2835 * method for HT traffic
2836 */
2837
2838 sta_priv->lq_sta.lq.general_params.flags |=
2839 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
2840 }
2841
2842 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
2843 sta_priv->max_agg_bufsize;
2844
2845 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
2846 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
2847
2848 IWL_INFO(priv, "Tx aggregation enabled on ra = %pM tid = %d\n",
2849 sta->addr, tid);
2850 ret = 0;
2851 break;
2852 }
2853 mutex_unlock(&priv->mutex);
2854
2855 return ret;
2856 }
2857
2858 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
2859 struct ieee80211_vif *vif,
2860 struct ieee80211_sta *sta)
2861 {
2862 struct iwl_priv *priv = hw->priv;
2863 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
2864 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2865 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
2866 int ret;
2867 u8 sta_id;
2868
2869 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
2870 sta->addr);
2871 mutex_lock(&priv->mutex);
2872 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
2873 sta->addr);
2874 sta_priv->common.sta_id = IWL_INVALID_STATION;
2875
2876 atomic_set(&sta_priv->pending_frames, 0);
2877 if (vif->type == NL80211_IFTYPE_AP)
2878 sta_priv->client = true;
2879
2880 ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
2881 is_ap, sta, &sta_id);
2882 if (ret) {
2883 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
2884 sta->addr, ret);
2885 /* Should we return success if return code is EEXIST ? */
2886 mutex_unlock(&priv->mutex);
2887 return ret;
2888 }
2889
2890 sta_priv->common.sta_id = sta_id;
2891
2892 /* Initialize rate scaling */
2893 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
2894 sta->addr);
2895 iwl_rs_rate_init(priv, sta, sta_id);
2896 mutex_unlock(&priv->mutex);
2897
2898 return 0;
2899 }
2900
2901 static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
2902 struct ieee80211_channel_switch *ch_switch)
2903 {
2904 struct iwl_priv *priv = hw->priv;
2905 const struct iwl_channel_info *ch_info;
2906 struct ieee80211_conf *conf = &hw->conf;
2907 struct ieee80211_channel *channel = ch_switch->channel;
2908 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
2909 /*
2910 * MULTI-FIXME
2911 * When we add support for multiple interfaces, we need to
2912 * revisit this. The channel switch command in the device
2913 * only affects the BSS context, but what does that really
2914 * mean? And what if we get a CSA on the second interface?
2915 * This needs a lot of work.
2916 */
2917 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2918 u16 ch;
2919
2920 IWL_DEBUG_MAC80211(priv, "enter\n");
2921
2922 mutex_lock(&priv->mutex);
2923
2924 if (iwl_is_rfkill(priv))
2925 goto out;
2926
2927 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2928 test_bit(STATUS_SCANNING, &priv->status) ||
2929 test_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status))
2930 goto out;
2931
2932 if (!iwl_is_associated_ctx(ctx))
2933 goto out;
2934
2935 if (!priv->cfg->ops->lib->set_channel_switch)
2936 goto out;
2937
2938 ch = channel->hw_value;
2939 if (le16_to_cpu(ctx->active.channel) == ch)
2940 goto out;
2941
2942 ch_info = iwl_get_channel_info(priv, channel->band, ch);
2943 if (!is_channel_valid(ch_info)) {
2944 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
2945 goto out;
2946 }
2947
2948 spin_lock_irq(&priv->lock);
2949
2950 priv->current_ht_config.smps = conf->smps_mode;
2951
2952 /* Configure HT40 channels */
2953 ctx->ht.enabled = conf_is_ht(conf);
2954 if (ctx->ht.enabled) {
2955 if (conf_is_ht40_minus(conf)) {
2956 ctx->ht.extension_chan_offset =
2957 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
2958 ctx->ht.is_40mhz = true;
2959 } else if (conf_is_ht40_plus(conf)) {
2960 ctx->ht.extension_chan_offset =
2961 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
2962 ctx->ht.is_40mhz = true;
2963 } else {
2964 ctx->ht.extension_chan_offset =
2965 IEEE80211_HT_PARAM_CHA_SEC_NONE;
2966 ctx->ht.is_40mhz = false;
2967 }
2968 } else
2969 ctx->ht.is_40mhz = false;
2970
2971 if ((le16_to_cpu(ctx->staging.channel) != ch))
2972 ctx->staging.flags = 0;
2973
2974 iwl_set_rxon_channel(priv, channel, ctx);
2975 iwl_set_rxon_ht(priv, ht_conf);
2976 iwl_set_flags_for_band(priv, ctx, channel->band, ctx->vif);
2977
2978 spin_unlock_irq(&priv->lock);
2979
2980 iwl_set_rate(priv);
2981 /*
2982 * at this point, staging_rxon has the
2983 * configuration for channel switch
2984 */
2985 set_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status);
2986 priv->switch_channel = cpu_to_le16(ch);
2987 if (priv->cfg->ops->lib->set_channel_switch(priv, ch_switch)) {
2988 clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status);
2989 priv->switch_channel = 0;
2990 ieee80211_chswitch_done(ctx->vif, false);
2991 }
2992
2993 out:
2994 mutex_unlock(&priv->mutex);
2995 IWL_DEBUG_MAC80211(priv, "leave\n");
2996 }
2997
2998 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
2999 unsigned int changed_flags,
3000 unsigned int *total_flags,
3001 u64 multicast)
3002 {
3003 struct iwl_priv *priv = hw->priv;
3004 __le32 filter_or = 0, filter_nand = 0;
3005 struct iwl_rxon_context *ctx;
3006
3007 #define CHK(test, flag) do { \
3008 if (*total_flags & (test)) \
3009 filter_or |= (flag); \
3010 else \
3011 filter_nand |= (flag); \
3012 } while (0)
3013
3014 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3015 changed_flags, *total_flags);
3016
3017 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3018 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3019 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3020 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3021
3022 #undef CHK
3023
3024 mutex_lock(&priv->mutex);
3025
3026 for_each_context(priv, ctx) {
3027 ctx->staging.filter_flags &= ~filter_nand;
3028 ctx->staging.filter_flags |= filter_or;
3029
3030 /*
3031 * Not committing directly because hardware can perform a scan,
3032 * but we'll eventually commit the filter flags change anyway.
3033 */
3034 }
3035
3036 mutex_unlock(&priv->mutex);
3037
3038 /*
3039 * Receiving all multicast frames is always enabled by the
3040 * default flags setup in iwl_connection_init_rx_config()
3041 * since we currently do not support programming multicast
3042 * filters into the device.
3043 */
3044 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3045 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3046 }
3047
3048 static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3049 {
3050 struct iwl_priv *priv = hw->priv;
3051
3052 mutex_lock(&priv->mutex);
3053 IWL_DEBUG_MAC80211(priv, "enter\n");
3054
3055 /* do not support "flush" */
3056 if (!priv->cfg->ops->lib->txfifo_flush)
3057 goto done;
3058
3059 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3060 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3061 goto done;
3062 }
3063 if (iwl_is_rfkill(priv)) {
3064 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3065 goto done;
3066 }
3067
3068 /*
3069 * mac80211 will not push any more frames for transmit
3070 * until the flush is completed
3071 */
3072 if (drop) {
3073 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3074 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3075 IWL_ERR(priv, "flush request fail\n");
3076 goto done;
3077 }
3078 }
3079 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3080 iwlagn_wait_tx_queue_empty(priv);
3081 done:
3082 mutex_unlock(&priv->mutex);
3083 IWL_DEBUG_MAC80211(priv, "leave\n");
3084 }
3085
3086 static void iwlagn_disable_roc(struct iwl_priv *priv)
3087 {
3088 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3089 struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3090
3091 lockdep_assert_held(&priv->mutex);
3092
3093 if (!ctx->is_active)
3094 return;
3095
3096 ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3097 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3098 iwl_set_rxon_channel(priv, chan, ctx);
3099 iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3100
3101 priv->_agn.hw_roc_channel = NULL;
3102
3103 iwlagn_commit_rxon(priv, ctx);
3104
3105 ctx->is_active = false;
3106 }
3107
3108 static void iwlagn_bg_roc_done(struct work_struct *work)
3109 {
3110 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3111 _agn.hw_roc_work.work);
3112
3113 mutex_lock(&priv->mutex);
3114 ieee80211_remain_on_channel_expired(priv->hw);
3115 iwlagn_disable_roc(priv);
3116 mutex_unlock(&priv->mutex);
3117 }
3118
3119 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3120 struct ieee80211_channel *channel,
3121 enum nl80211_channel_type channel_type,
3122 int duration)
3123 {
3124 struct iwl_priv *priv = hw->priv;
3125 int err = 0;
3126
3127 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3128 return -EOPNOTSUPP;
3129
3130 if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3131 BIT(NL80211_IFTYPE_P2P_CLIENT)))
3132 return -EOPNOTSUPP;
3133
3134 mutex_lock(&priv->mutex);
3135
3136 if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3137 test_bit(STATUS_SCAN_HW, &priv->status)) {
3138 err = -EBUSY;
3139 goto out;
3140 }
3141
3142 priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3143 priv->_agn.hw_roc_channel = channel;
3144 priv->_agn.hw_roc_chantype = channel_type;
3145 priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3146 iwlagn_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3147 queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3148 msecs_to_jiffies(duration + 20));
3149
3150 msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3151 ieee80211_ready_on_channel(priv->hw);
3152
3153 out:
3154 mutex_unlock(&priv->mutex);
3155
3156 return err;
3157 }
3158
3159 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3160 {
3161 struct iwl_priv *priv = hw->priv;
3162
3163 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3164 return -EOPNOTSUPP;
3165
3166 cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3167
3168 mutex_lock(&priv->mutex);
3169 iwlagn_disable_roc(priv);
3170 mutex_unlock(&priv->mutex);
3171
3172 return 0;
3173 }
3174
3175 /*****************************************************************************
3176 *
3177 * driver setup and teardown
3178 *
3179 *****************************************************************************/
3180
3181 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3182 {
3183 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3184
3185 init_waitqueue_head(&priv->wait_command_queue);
3186
3187 INIT_WORK(&priv->restart, iwl_bg_restart);
3188 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3189 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3190 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3191 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3192 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3193 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3194 INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3195
3196 iwl_setup_scan_deferred_work(priv);
3197
3198 if (priv->cfg->ops->lib->setup_deferred_work)
3199 priv->cfg->ops->lib->setup_deferred_work(priv);
3200
3201 init_timer(&priv->statistics_periodic);
3202 priv->statistics_periodic.data = (unsigned long)priv;
3203 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3204
3205 init_timer(&priv->ucode_trace);
3206 priv->ucode_trace.data = (unsigned long)priv;
3207 priv->ucode_trace.function = iwl_bg_ucode_trace;
3208
3209 init_timer(&priv->watchdog);
3210 priv->watchdog.data = (unsigned long)priv;
3211 priv->watchdog.function = iwl_bg_watchdog;
3212
3213 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3214 iwl_irq_tasklet, (unsigned long)priv);
3215 }
3216
3217 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3218 {
3219 if (priv->cfg->ops->lib->cancel_deferred_work)
3220 priv->cfg->ops->lib->cancel_deferred_work(priv);
3221
3222 cancel_work_sync(&priv->run_time_calib_work);
3223 cancel_work_sync(&priv->beacon_update);
3224
3225 iwl_cancel_scan_deferred_work(priv);
3226
3227 cancel_work_sync(&priv->bt_full_concurrency);
3228 cancel_work_sync(&priv->bt_runtime_config);
3229
3230 del_timer_sync(&priv->statistics_periodic);
3231 del_timer_sync(&priv->ucode_trace);
3232 }
3233
3234 static void iwl_init_hw_rates(struct iwl_priv *priv,
3235 struct ieee80211_rate *rates)
3236 {
3237 int i;
3238
3239 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3240 rates[i].bitrate = iwl_rates[i].ieee * 5;
3241 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3242 rates[i].hw_value_short = i;
3243 rates[i].flags = 0;
3244 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3245 /*
3246 * If CCK != 1M then set short preamble rate flag.
3247 */
3248 rates[i].flags |=
3249 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3250 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3251 }
3252 }
3253 }
3254
3255 static int iwl_init_drv(struct iwl_priv *priv)
3256 {
3257 int ret;
3258
3259 spin_lock_init(&priv->sta_lock);
3260 spin_lock_init(&priv->hcmd_lock);
3261
3262 mutex_init(&priv->mutex);
3263
3264 priv->ieee_channels = NULL;
3265 priv->ieee_rates = NULL;
3266 priv->band = IEEE80211_BAND_2GHZ;
3267
3268 priv->iw_mode = NL80211_IFTYPE_STATION;
3269 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3270 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3271 priv->_agn.agg_tids_count = 0;
3272
3273 /* initialize force reset */
3274 priv->force_reset[IWL_RF_RESET].reset_duration =
3275 IWL_DELAY_NEXT_FORCE_RF_RESET;
3276 priv->force_reset[IWL_FW_RESET].reset_duration =
3277 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3278
3279 priv->rx_statistics_jiffies = jiffies;
3280
3281 /* Choose which receivers/antennas to use */
3282 if (priv->cfg->ops->hcmd->set_rxon_chain)
3283 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3284 &priv->contexts[IWL_RXON_CTX_BSS]);
3285
3286 iwl_init_scan_params(priv);
3287
3288 /* init bt coex */
3289 if (priv->cfg->bt_params &&
3290 priv->cfg->bt_params->advanced_bt_coexist) {
3291 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3292 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3293 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3294 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3295 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3296 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3297 }
3298
3299 ret = iwl_init_channel_map(priv);
3300 if (ret) {
3301 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3302 goto err;
3303 }
3304
3305 ret = iwlcore_init_geos(priv);
3306 if (ret) {
3307 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3308 goto err_free_channel_map;
3309 }
3310 iwl_init_hw_rates(priv, priv->ieee_rates);
3311
3312 return 0;
3313
3314 err_free_channel_map:
3315 iwl_free_channel_map(priv);
3316 err:
3317 return ret;
3318 }
3319
3320 static void iwl_uninit_drv(struct iwl_priv *priv)
3321 {
3322 iwl_calib_free_results(priv);
3323 iwlcore_free_geos(priv);
3324 iwl_free_channel_map(priv);
3325 kfree(priv->scan_cmd);
3326 kfree(priv->beacon_cmd);
3327 }
3328
3329 struct ieee80211_ops iwlagn_hw_ops = {
3330 .tx = iwlagn_mac_tx,
3331 .start = iwlagn_mac_start,
3332 .stop = iwlagn_mac_stop,
3333 .add_interface = iwl_mac_add_interface,
3334 .remove_interface = iwl_mac_remove_interface,
3335 .change_interface = iwl_mac_change_interface,
3336 .config = iwlagn_mac_config,
3337 .configure_filter = iwlagn_configure_filter,
3338 .set_key = iwlagn_mac_set_key,
3339 .update_tkip_key = iwlagn_mac_update_tkip_key,
3340 .conf_tx = iwl_mac_conf_tx,
3341 .bss_info_changed = iwlagn_bss_info_changed,
3342 .ampdu_action = iwlagn_mac_ampdu_action,
3343 .hw_scan = iwl_mac_hw_scan,
3344 .sta_notify = iwlagn_mac_sta_notify,
3345 .sta_add = iwlagn_mac_sta_add,
3346 .sta_remove = iwl_mac_sta_remove,
3347 .channel_switch = iwlagn_mac_channel_switch,
3348 .flush = iwlagn_mac_flush,
3349 .tx_last_beacon = iwl_mac_tx_last_beacon,
3350 .remain_on_channel = iwl_mac_remain_on_channel,
3351 .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
3352 .offchannel_tx = iwl_mac_offchannel_tx,
3353 .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
3354 CFG80211_TESTMODE_CMD(iwl_testmode_cmd)
3355 CFG80211_TESTMODE_DUMP(iwl_testmode_dump)
3356 };
3357
3358 static u32 iwl_hw_detect(struct iwl_priv *priv)
3359 {
3360 u8 rev_id;
3361
3362 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
3363 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
3364 return iwl_read32(priv, CSR_HW_REV);
3365 }
3366
3367 static int iwl_set_hw_params(struct iwl_priv *priv)
3368 {
3369 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3370 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
3371 if (iwlagn_mod_params.amsdu_size_8K)
3372 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3373 else
3374 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3375
3376 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3377
3378 if (iwlagn_mod_params.disable_11n)
3379 priv->cfg->sku &= ~EEPROM_SKU_CAP_11N_ENABLE;
3380
3381 /* Device-specific setup */
3382 return priv->cfg->ops->lib->set_hw_params(priv);
3383 }
3384
3385 static const u8 iwlagn_bss_ac_to_fifo[] = {
3386 IWL_TX_FIFO_VO,
3387 IWL_TX_FIFO_VI,
3388 IWL_TX_FIFO_BE,
3389 IWL_TX_FIFO_BK,
3390 };
3391
3392 static const u8 iwlagn_bss_ac_to_queue[] = {
3393 0, 1, 2, 3,
3394 };
3395
3396 static const u8 iwlagn_pan_ac_to_fifo[] = {
3397 IWL_TX_FIFO_VO_IPAN,
3398 IWL_TX_FIFO_VI_IPAN,
3399 IWL_TX_FIFO_BE_IPAN,
3400 IWL_TX_FIFO_BK_IPAN,
3401 };
3402
3403 static const u8 iwlagn_pan_ac_to_queue[] = {
3404 7, 6, 5, 4,
3405 };
3406
3407 /* This function both allocates and initializes hw and priv. */
3408 static struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg)
3409 {
3410 struct iwl_priv *priv;
3411 /* mac80211 allocates memory for this device instance, including
3412 * space for this driver's private structure */
3413 struct ieee80211_hw *hw;
3414
3415 hw = ieee80211_alloc_hw(sizeof(struct iwl_priv), &iwlagn_hw_ops);
3416 if (hw == NULL) {
3417 pr_err("%s: Can not allocate network device\n",
3418 cfg->name);
3419 goto out;
3420 }
3421
3422 priv = hw->priv;
3423 priv->hw = hw;
3424
3425 out:
3426 return hw;
3427 }
3428
3429 static void iwl_init_context(struct iwl_priv *priv)
3430 {
3431 int i;
3432
3433 /*
3434 * The default context is always valid,
3435 * more may be discovered when firmware
3436 * is loaded.
3437 */
3438 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3439
3440 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3441 priv->contexts[i].ctxid = i;
3442
3443 priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3444 priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
3445 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3446 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
3447 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
3448 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
3449 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
3450 priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
3451 priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
3452 priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
3453 priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
3454 BIT(NL80211_IFTYPE_ADHOC);
3455 priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
3456 BIT(NL80211_IFTYPE_STATION);
3457 priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
3458 priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
3459 priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
3460 priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
3461
3462 priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
3463 priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd =
3464 REPLY_WIPAN_RXON_TIMING;
3465 priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd =
3466 REPLY_WIPAN_RXON_ASSOC;
3467 priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
3468 priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
3469 priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
3470 priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
3471 priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
3472 priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
3473 priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
3474 priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
3475 priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
3476 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
3477 #ifdef CONFIG_IWL_P2P
3478 priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
3479 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
3480 #endif
3481 priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
3482 priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
3483 priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
3484
3485 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
3486 }
3487
3488 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3489 {
3490 int err = 0;
3491 struct iwl_priv *priv;
3492 struct ieee80211_hw *hw;
3493 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3494 unsigned long flags;
3495 u16 pci_cmd, num_mac;
3496 u32 hw_rev;
3497
3498 /************************
3499 * 1. Allocating HW data
3500 ************************/
3501
3502 hw = iwl_alloc_all(cfg);
3503 if (!hw) {
3504 err = -ENOMEM;
3505 goto out; }
3506 priv = hw->priv;
3507 /* At this point both hw and priv are allocated. */
3508
3509 SET_IEEE80211_DEV(hw, &pdev->dev);
3510
3511 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3512 priv->cfg = cfg;
3513 priv->pci_dev = pdev;
3514 priv->inta_mask = CSR_INI_SET_MASK;
3515
3516 /* is antenna coupling more than 35dB ? */
3517 priv->bt_ant_couple_ok =
3518 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
3519 true : false;
3520
3521 /* enable/disable bt channel inhibition */
3522 priv->bt_ch_announce = iwlagn_bt_ch_announce;
3523 IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
3524 (priv->bt_ch_announce) ? "On" : "Off");
3525
3526 if (iwl_alloc_traffic_mem(priv))
3527 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3528
3529 /**************************
3530 * 2. Initializing PCI bus
3531 **************************/
3532 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3533 PCIE_LINK_STATE_CLKPM);
3534
3535 if (pci_enable_device(pdev)) {
3536 err = -ENODEV;
3537 goto out_ieee80211_free_hw;
3538 }
3539
3540 pci_set_master(pdev);
3541
3542 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3543 if (!err)
3544 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3545 if (err) {
3546 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3547 if (!err)
3548 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3549 /* both attempts failed: */
3550 if (err) {
3551 IWL_WARN(priv, "No suitable DMA available.\n");
3552 goto out_pci_disable_device;
3553 }
3554 }
3555
3556 err = pci_request_regions(pdev, DRV_NAME);
3557 if (err)
3558 goto out_pci_disable_device;
3559
3560 pci_set_drvdata(pdev, priv);
3561
3562
3563 /***********************
3564 * 3. Read REV register
3565 ***********************/
3566 priv->hw_base = pci_iomap(pdev, 0, 0);
3567 if (!priv->hw_base) {
3568 err = -ENODEV;
3569 goto out_pci_release_regions;
3570 }
3571
3572 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3573 (unsigned long long) pci_resource_len(pdev, 0));
3574 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3575
3576 /* these spin locks will be used in apm_ops.init and EEPROM access
3577 * we should init now
3578 */
3579 spin_lock_init(&priv->reg_lock);
3580 spin_lock_init(&priv->lock);
3581
3582 /*
3583 * stop and reset the on-board processor just in case it is in a
3584 * strange state ... like being left stranded by a primary kernel
3585 * and this is now the kdump kernel trying to start up
3586 */
3587 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3588
3589 hw_rev = iwl_hw_detect(priv);
3590 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
3591 priv->cfg->name, hw_rev);
3592
3593 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3594 * PCI Tx retries from interfering with C3 CPU state */
3595 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3596
3597 if (iwl_prepare_card_hw(priv)) {
3598 IWL_WARN(priv, "Failed, HW not ready\n");
3599 goto out_iounmap;
3600 }
3601
3602 /*****************
3603 * 4. Read EEPROM
3604 *****************/
3605 /* Read the EEPROM */
3606 err = iwl_eeprom_init(priv, hw_rev);
3607 if (err) {
3608 IWL_ERR(priv, "Unable to init EEPROM\n");
3609 goto out_iounmap;
3610 }
3611 err = iwl_eeprom_check_version(priv);
3612 if (err)
3613 goto out_free_eeprom;
3614
3615 err = iwl_eeprom_check_sku(priv);
3616 if (err)
3617 goto out_free_eeprom;
3618
3619 /* extract MAC Address */
3620 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
3621 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
3622 priv->hw->wiphy->addresses = priv->addresses;
3623 priv->hw->wiphy->n_addresses = 1;
3624 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
3625 if (num_mac > 1) {
3626 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
3627 ETH_ALEN);
3628 priv->addresses[1].addr[5]++;
3629 priv->hw->wiphy->n_addresses++;
3630 }
3631
3632 /* initialize all valid contexts */
3633 iwl_init_context(priv);
3634
3635 /************************
3636 * 5. Setup HW constants
3637 ************************/
3638 if (iwl_set_hw_params(priv)) {
3639 IWL_ERR(priv, "failed to set hw parameters\n");
3640 goto out_free_eeprom;
3641 }
3642
3643 /*******************
3644 * 6. Setup priv
3645 *******************/
3646
3647 err = iwl_init_drv(priv);
3648 if (err)
3649 goto out_free_eeprom;
3650 /* At this point both hw and priv are initialized. */
3651
3652 /********************
3653 * 7. Setup services
3654 ********************/
3655 spin_lock_irqsave(&priv->lock, flags);
3656 iwl_disable_interrupts(priv);
3657 spin_unlock_irqrestore(&priv->lock, flags);
3658
3659 pci_enable_msi(priv->pci_dev);
3660
3661 iwl_alloc_isr_ict(priv);
3662
3663 err = request_irq(priv->pci_dev->irq, iwl_isr_ict,
3664 IRQF_SHARED, DRV_NAME, priv);
3665 if (err) {
3666 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3667 goto out_disable_msi;
3668 }
3669
3670 iwl_setup_deferred_work(priv);
3671 iwl_setup_rx_handlers(priv);
3672 iwl_testmode_init(priv);
3673
3674 /*********************************************
3675 * 8. Enable interrupts and read RFKILL state
3676 *********************************************/
3677
3678 /* enable rfkill interrupt: hw bug w/a */
3679 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3680 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3681 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3682 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3683 }
3684
3685 iwl_enable_rfkill_int(priv);
3686
3687 /* If platform's RF_KILL switch is NOT set to KILL */
3688 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3689 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3690 else
3691 set_bit(STATUS_RF_KILL_HW, &priv->status);
3692
3693 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3694 test_bit(STATUS_RF_KILL_HW, &priv->status));
3695
3696 iwl_power_initialize(priv);
3697 iwl_tt_initialize(priv);
3698
3699 init_completion(&priv->_agn.firmware_loading_complete);
3700
3701 err = iwl_request_firmware(priv, true);
3702 if (err)
3703 goto out_destroy_workqueue;
3704
3705 return 0;
3706
3707 out_destroy_workqueue:
3708 destroy_workqueue(priv->workqueue);
3709 priv->workqueue = NULL;
3710 free_irq(priv->pci_dev->irq, priv);
3711 out_disable_msi:
3712 iwl_free_isr_ict(priv);
3713 pci_disable_msi(priv->pci_dev);
3714 iwl_uninit_drv(priv);
3715 out_free_eeprom:
3716 iwl_eeprom_free(priv);
3717 out_iounmap:
3718 pci_iounmap(pdev, priv->hw_base);
3719 out_pci_release_regions:
3720 pci_set_drvdata(pdev, NULL);
3721 pci_release_regions(pdev);
3722 out_pci_disable_device:
3723 pci_disable_device(pdev);
3724 out_ieee80211_free_hw:
3725 iwl_free_traffic_mem(priv);
3726 ieee80211_free_hw(priv->hw);
3727 out:
3728 return err;
3729 }
3730
3731 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
3732 {
3733 struct iwl_priv *priv = pci_get_drvdata(pdev);
3734 unsigned long flags;
3735
3736 if (!priv)
3737 return;
3738
3739 wait_for_completion(&priv->_agn.firmware_loading_complete);
3740
3741 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
3742
3743 iwl_dbgfs_unregister(priv);
3744 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3745
3746 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3747 * to be called and iwl_down since we are removing the device
3748 * we need to set STATUS_EXIT_PENDING bit.
3749 */
3750 set_bit(STATUS_EXIT_PENDING, &priv->status);
3751
3752 iwl_testmode_cleanup(priv);
3753 iwl_leds_exit(priv);
3754
3755 if (priv->mac80211_registered) {
3756 ieee80211_unregister_hw(priv->hw);
3757 priv->mac80211_registered = 0;
3758 }
3759
3760 /* Reset to low power before unloading driver. */
3761 iwl_apm_stop(priv);
3762
3763 iwl_tt_exit(priv);
3764
3765 /* make sure we flush any pending irq or
3766 * tasklet for the driver
3767 */
3768 spin_lock_irqsave(&priv->lock, flags);
3769 iwl_disable_interrupts(priv);
3770 spin_unlock_irqrestore(&priv->lock, flags);
3771
3772 iwl_synchronize_irq(priv);
3773
3774 iwl_dealloc_ucode_pci(priv);
3775
3776 if (priv->rxq.bd)
3777 iwlagn_rx_queue_free(priv, &priv->rxq);
3778 iwlagn_hw_txq_ctx_free(priv);
3779
3780 iwl_eeprom_free(priv);
3781
3782
3783 /*netif_stop_queue(dev); */
3784 flush_workqueue(priv->workqueue);
3785
3786 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
3787 * priv->workqueue... so we can't take down the workqueue
3788 * until now... */
3789 destroy_workqueue(priv->workqueue);
3790 priv->workqueue = NULL;
3791 iwl_free_traffic_mem(priv);
3792
3793 free_irq(priv->pci_dev->irq, priv);
3794 pci_disable_msi(priv->pci_dev);
3795 pci_iounmap(pdev, priv->hw_base);
3796 pci_release_regions(pdev);
3797 pci_disable_device(pdev);
3798 pci_set_drvdata(pdev, NULL);
3799
3800 iwl_uninit_drv(priv);
3801
3802 iwl_free_isr_ict(priv);
3803
3804 dev_kfree_skb(priv->beacon_skb);
3805
3806 ieee80211_free_hw(priv->hw);
3807 }
3808
3809
3810 /*****************************************************************************
3811 *
3812 * driver and module entry point
3813 *
3814 *****************************************************************************/
3815
3816 /* Hardware specific file defines the PCI IDs table for that hardware module */
3817 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
3818 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
3819 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
3820 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
3821 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
3822 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
3823 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
3824 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
3825 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
3826 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
3827 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
3828 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
3829 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
3830 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
3831 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
3832 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
3833 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
3834 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
3835 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
3836 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
3837 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
3838 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
3839 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
3840 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
3841 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
3842
3843 /* 5300 Series WiFi */
3844 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
3845 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
3846 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
3847 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
3848 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
3849 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
3850 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
3851 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
3852 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
3853 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
3854 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
3855 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
3856
3857 /* 5350 Series WiFi/WiMax */
3858 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
3859 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
3860 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
3861
3862 /* 5150 Series Wifi/WiMax */
3863 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
3864 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
3865 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
3866 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
3867 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
3868 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
3869
3870 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
3871 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
3872 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
3873 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
3874
3875 /* 6x00 Series */
3876 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3877 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3878 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3879 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3880 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3881 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3882 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3883 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3884 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3885 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
3886
3887 /* 6x05 Series */
3888 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
3889 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
3890 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
3891 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
3892 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
3893 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
3894 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
3895
3896 /* 6x30 Series */
3897 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
3898 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
3899 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
3900 {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
3901 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
3902 {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
3903 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
3904 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
3905 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
3906 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
3907 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
3908 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
3909 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
3910 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
3911 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
3912 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
3913
3914 /* 6x50 WiFi/WiMax Series */
3915 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3916 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3917 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3918 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
3919 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3920 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3921
3922 /* 6150 WiFi/WiMax Series */
3923 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
3924 {IWL_PCI_DEVICE(0x0885, 0x1307, iwl6150_bg_cfg)},
3925 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
3926 {IWL_PCI_DEVICE(0x0885, 0x1327, iwl6150_bg_cfg)},
3927 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
3928 {IWL_PCI_DEVICE(0x0886, 0x1317, iwl6150_bg_cfg)},
3929
3930 /* 1000 Series WiFi */
3931 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3932 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3933 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3934 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3935 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3936 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
3937 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
3938 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
3939 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
3940 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
3941 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
3942 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
3943
3944 /* 100 Series WiFi */
3945 {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
3946 {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
3947 {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
3948 {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
3949 {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
3950 {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
3951
3952 /* 130 Series WiFi */
3953 {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
3954 {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
3955 {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
3956 {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
3957 {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
3958 {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
3959
3960 /* 2x00 Series */
3961 {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
3962 {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
3963 {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
3964 {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
3965 {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
3966 {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
3967
3968 /* 2x30 Series */
3969 {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
3970 {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
3971 {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
3972 {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
3973 {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
3974 {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
3975
3976 /* 6x35 Series */
3977 {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
3978 {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
3979 {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
3980 {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
3981 {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
3982 {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
3983 {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
3984 {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
3985 {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
3986
3987 /* 105 Series */
3988 {IWL_PCI_DEVICE(0x0894, 0x0022, iwl105_bgn_cfg)},
3989 {IWL_PCI_DEVICE(0x0895, 0x0222, iwl105_bgn_cfg)},
3990 {IWL_PCI_DEVICE(0x0894, 0x0422, iwl105_bgn_cfg)},
3991 {IWL_PCI_DEVICE(0x0894, 0x0026, iwl105_bg_cfg)},
3992 {IWL_PCI_DEVICE(0x0895, 0x0226, iwl105_bg_cfg)},
3993 {IWL_PCI_DEVICE(0x0894, 0x0426, iwl105_bg_cfg)},
3994
3995 /* 135 Series */
3996 {IWL_PCI_DEVICE(0x0892, 0x0062, iwl135_bgn_cfg)},
3997 {IWL_PCI_DEVICE(0x0893, 0x0262, iwl135_bgn_cfg)},
3998 {IWL_PCI_DEVICE(0x0892, 0x0462, iwl135_bgn_cfg)},
3999 {IWL_PCI_DEVICE(0x0892, 0x0066, iwl135_bg_cfg)},
4000 {IWL_PCI_DEVICE(0x0893, 0x0266, iwl135_bg_cfg)},
4001 {IWL_PCI_DEVICE(0x0892, 0x0466, iwl135_bg_cfg)},
4002
4003 {0}
4004 };
4005 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4006
4007 static struct pci_driver iwl_driver = {
4008 .name = DRV_NAME,
4009 .id_table = iwl_hw_card_ids,
4010 .probe = iwl_pci_probe,
4011 .remove = __devexit_p(iwl_pci_remove),
4012 .driver.pm = IWL_PM_OPS,
4013 };
4014
4015 static int __init iwl_init(void)
4016 {
4017
4018 int ret;
4019 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4020 pr_info(DRV_COPYRIGHT "\n");
4021
4022 ret = iwlagn_rate_control_register();
4023 if (ret) {
4024 pr_err("Unable to register rate control algorithm: %d\n", ret);
4025 return ret;
4026 }
4027
4028 ret = pci_register_driver(&iwl_driver);
4029 if (ret) {
4030 pr_err("Unable to initialize PCI module\n");
4031 goto error_register;
4032 }
4033
4034 return ret;
4035
4036 error_register:
4037 iwlagn_rate_control_unregister();
4038 return ret;
4039 }
4040
4041 static void __exit iwl_exit(void)
4042 {
4043 pci_unregister_driver(&iwl_driver);
4044 iwlagn_rate_control_unregister();
4045 }
4046
4047 module_exit(iwl_exit);
4048 module_init(iwl_init);
4049
4050 #ifdef CONFIG_IWLWIFI_DEBUG
4051 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4052 MODULE_PARM_DESC(debug, "debug output mask");
4053 #endif
4054
4055 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4056 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4057 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4058 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4059 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4060 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4061 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4062 int, S_IRUGO);
4063 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4064 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4065 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4066
4067 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4068 S_IRUGO);
4069 MODULE_PARM_DESC(ucode_alternative,
4070 "specify ucode alternative to use from ucode file");
4071
4072 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4073 MODULE_PARM_DESC(antenna_coupling,
4074 "specify antenna coupling in dB (defualt: 0 dB)");
4075
4076 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4077 MODULE_PARM_DESC(bt_ch_inhibition,
4078 "Disable BT channel inhibition (default: enable)");
4079
4080 module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
4081 MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
4082
4083 module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
4084 MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");
4085
4086 /*
4087 * set bt_coex_active to true, uCode will do kill/defer
4088 * every time the priority line is asserted (BT is sending signals on the
4089 * priority line in the PCIx).
4090 * set bt_coex_active to false, uCode will ignore the BT activity and
4091 * perform the normal operation
4092 *
4093 * User might experience transmit issue on some platform due to WiFi/BT
4094 * co-exist problem. The possible behaviors are:
4095 * Able to scan and finding all the available AP
4096 * Not able to associate with any AP
4097 * On those platforms, WiFi communication can be restored by set
4098 * "bt_coex_active" module parameter to "false"
4099 *
4100 * default: bt_coex_active = true (BT_COEX_ENABLE)
4101 */
4102 module_param_named(bt_coex_active, iwlagn_mod_params.bt_coex_active,
4103 bool, S_IRUGO);
4104 MODULE_PARM_DESC(bt_coex_active, "enable wifi/bt co-exist (default: enable)");
4105
4106 module_param_named(led_mode, iwlagn_mod_params.led_mode, int, S_IRUGO);
4107 MODULE_PARM_DESC(led_mode, "0=system default, "
4108 "1=On(RF On)/Off(RF Off), 2=blinking (default: 0)");
4109
4110 /*
4111 * For now, keep using power level 1 instead of automatically
4112 * adjusting ...
4113 */
4114 module_param_named(no_sleep_autoadjust, iwlagn_mod_params.no_sleep_autoadjust,
4115 bool, S_IRUGO);
4116 MODULE_PARM_DESC(no_sleep_autoadjust,
4117 "don't automatically adjust sleep level "
4118 "according to maximum network latency (default: true)");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree