drivers/kvm/paging_tmpl.h

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * MMU support
   8  *
   9  * Copyright (C) 2006 Qumranet, Inc.
  10  *
  11  * Authors:
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *   Avi Kivity   <avi@qumranet.com>
  14  *
  15  * This work is licensed under the terms of the GNU GPL, version 2.  See
  16  * the COPYING file in the top-level directory.
  17  *
  18  */
  19
  20 /*
  21  * We need the mmu code to access both 32-bit and 64-bit guest ptes,
  22  * so the code in this file is compiled twice, once per pte size.
  23  */
  24
  25 #if PTTYPE == 64
  26         #define pt_element_t u64
  27         #define guest_walker guest_walker64
  28         #define FNAME(name) paging##64_##name
  29         #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
  30         #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
  31         #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
  32         #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
  33         #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
  34         #define PT_LEVEL_BITS PT64_LEVEL_BITS
  35         #ifdef CONFIG_X86_64
  36         #define PT_MAX_FULL_LEVELS 4
  37         #else
  38         #define PT_MAX_FULL_LEVELS 2
  39         #endif
  40 #elif PTTYPE == 32
  41         #define pt_element_t u32
  42         #define guest_walker guest_walker32
  43         #define FNAME(name) paging##32_##name
  44         #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
  45         #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
  46         #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
  47         #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
  48         #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
  49         #define PT_LEVEL_BITS PT32_LEVEL_BITS
  50         #define PT_MAX_FULL_LEVELS 2
  51 #else
  52         #error Invalid PTTYPE value
  53 #endif
  54
  55 /*
  56  * The guest_walker structure emulates the behavior of the hardware page
  57  * table walker.
  58  */
  59 struct guest_walker {
  60         int level;
  61         gfn_t table_gfn[PT_MAX_FULL_LEVELS];
  62         pt_element_t pte;
  63         pt_element_t inherited_ar;
  64         gfn_t gfn;
  65         u32 error_code;
  66 };
  67
  68 /*
  69  * Fetch a guest pte for a guest virtual address
  70  */
  71 static int FNAME(walk_addr)(struct guest_walker *walker,
  72                             struct kvm_vcpu *vcpu, gva_t addr,
  73                             int write_fault, int user_fault, int fetch_fault)
  74 {
  75         pt_element_t pte;
  76         gfn_t table_gfn;
  77         unsigned index;
  78         gpa_t pte_gpa;
  79
  80         pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
  81         walker->level = vcpu->mmu.root_level;
  82         pte = vcpu->cr3;
  83 #if PTTYPE == 64
  84         if (!is_long_mode(vcpu)) {
  85                 pte = vcpu->pdptrs[(addr >> 30) & 3];
  86                 if (!is_present_pte(pte))
  87                         goto not_present;
  88                 --walker->level;
  89         }
  90 #endif
  91         ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
  92                (vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
  93
  94         walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK;
  95
  96         for (;;) {
  97                 index = PT_INDEX(addr, walker->level);
  98
  99                 table_gfn = (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
 100                 pte_gpa = table_gfn << PAGE_SHIFT;
 101                 pte_gpa += index * sizeof(pt_element_t);
 102                 walker->table_gfn[walker->level - 1] = table_gfn;
 103                 pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
 104                          walker->level - 1, table_gfn);
 105
 106                 kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
 107
 108                 if (!is_present_pte(pte))
 109                         goto not_present;
 110
 111                 if (write_fault && !is_writeble_pte(pte))
 112                         if (user_fault || is_write_protection(vcpu))
 113                                 goto access_error;
 114
 115                 if (user_fault && !(pte & PT_USER_MASK))
 116                         goto access_error;
 117
 118 #if PTTYPE == 64
 119                 if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
 120                         goto access_error;
 121 #endif
 122
 123                 if (!(pte & PT_ACCESSED_MASK)) {
 124                         mark_page_dirty(vcpu->kvm, table_gfn);
 125                         pte |= PT_ACCESSED_MASK;
 126                         kvm_write_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
 127                 }
 128
 129                 if (walker->level == PT_PAGE_TABLE_LEVEL) {
 130                         walker->gfn = (pte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
 131                         break;
 132                 }
 133
 134                 if (walker->level == PT_DIRECTORY_LEVEL
 135                     && (pte & PT_PAGE_SIZE_MASK)
 136                     && (PTTYPE == 64 || is_pse(vcpu))) {
 137                         walker->gfn = (pte & PT_DIR_BASE_ADDR_MASK)
 138                                 >> PAGE_SHIFT;
 139                         walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
 140                         break;
 141                 }
 142
 143                 walker->inherited_ar &= pte;
 144                 --walker->level;
 145         }
 146
 147         if (write_fault && !is_dirty_pte(pte)) {
 148                 mark_page_dirty(vcpu->kvm, table_gfn);
 149                 pte |= PT_DIRTY_MASK;
 150                 kvm_write_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
 151                 kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
 152         }
 153
 154         walker->pte = pte;
 155         pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)pte);
 156         return 1;
 157
 158 not_present:
 159         walker->error_code = 0;
 160         goto err;
 161
 162 access_error:
 163         walker->error_code = PFERR_PRESENT_MASK;
 164
 165 err:
 166         if (write_fault)
 167                 walker->error_code |= PFERR_WRITE_MASK;
 168         if (user_fault)
 169                 walker->error_code |= PFERR_USER_MASK;
 170         if (fetch_fault)
 171                 walker->error_code |= PFERR_FETCH_MASK;
 172         return 0;
 173 }
 174
 175 static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu,
 176                                   u64 *shadow_pte,
 177                                   gpa_t gaddr,
 178                                   pt_element_t gpte,
 179                                   u64 access_bits,
 180                                   int user_fault,
 181                                   int write_fault,
 182                                   int *ptwrite,
 183                                   struct guest_walker *walker,
 184                                   gfn_t gfn)
 185 {
 186         hpa_t paddr;
 187         int dirty = gpte & PT_DIRTY_MASK;
 188         u64 spte;
 189         int was_rmapped = is_rmap_pte(*shadow_pte);
 190         struct page *page;
 191
 192         pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d"
 193                  " user_fault %d gfn %lx\n",
 194                  __FUNCTION__, *shadow_pte, (u64)gpte, access_bits,
 195                  write_fault, user_fault, gfn);
 196
 197         /*
 198          * We don't set the accessed bit, since we sometimes want to see
 199          * whether the guest actually used the pte (in order to detect
 200          * demand paging).
 201          */
 202         spte = PT_PRESENT_MASK | PT_DIRTY_MASK;
 203         spte |= gpte & PT64_NX_MASK;
 204         if (!dirty)
 205                 access_bits &= ~PT_WRITABLE_MASK;
 206
 207         paddr = gpa_to_hpa(vcpu->kvm, gaddr & PT64_BASE_ADDR_MASK);
 208
 209         /*
 210          * the reason paddr get mask even that it isnt pte is beacuse the
 211          * HPA_ERR_MASK bit might be used to signal error
 212          */
 213         page = pfn_to_page((paddr & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT);
 214
 215         spte |= PT_PRESENT_MASK;
 216         if (access_bits & PT_USER_MASK)
 217                 spte |= PT_USER_MASK;
 218
 219         if (is_error_hpa(paddr)) {
 220                 set_shadow_pte(shadow_pte,
 221                                shadow_trap_nonpresent_pte | PT_SHADOW_IO_MARK);
 222                 kvm_release_page_clean(page);
 223                 return;
 224         }
 225
 226         spte |= paddr;
 227
 228         if ((access_bits & PT_WRITABLE_MASK)
 229             || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
 230                 struct kvm_mmu_page *shadow;
 231
 232                 spte |= PT_WRITABLE_MASK;
 233                 if (user_fault) {
 234                         mmu_unshadow(vcpu->kvm, gfn);
 235                         goto unshadowed;
 236                 }
 237
 238                 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
 239                 if (shadow) {
 240                         pgprintk("%s: found shadow page for %lx, marking ro\n",
 241                                  __FUNCTION__, gfn);
 242                         access_bits &= ~PT_WRITABLE_MASK;
 243                         if (is_writeble_pte(spte)) {
 244                                 spte &= ~PT_WRITABLE_MASK;
 245                                 kvm_x86_ops->tlb_flush(vcpu);
 246                         }
 247                         if (write_fault)
 248                                 *ptwrite = 1;
 249                 }
 250         }
 251
 252 unshadowed:
 253
 254         if (access_bits & PT_WRITABLE_MASK)
 255                 mark_page_dirty(vcpu->kvm, gaddr >> PAGE_SHIFT);
 256
 257         pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte);
 258         set_shadow_pte(shadow_pte, spte);
 259         page_header_update_slot(vcpu->kvm, shadow_pte, gaddr);
 260         if (!was_rmapped) {
 261                 rmap_add(vcpu, shadow_pte, (gaddr & PT64_BASE_ADDR_MASK)
 262                          >> PAGE_SHIFT);
 263                 if (!is_rmap_pte(*shadow_pte))
 264                         kvm_release_page_clean(page);
 265         }
 266         else
 267                 kvm_release_page_clean(page);
 268         if (!ptwrite || !*ptwrite)
 269                 vcpu->last_pte_updated = shadow_pte;
 270 }
 271
 272 static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte,
 273                            u64 *shadow_pte, u64 access_bits,
 274                            int user_fault, int write_fault, int *ptwrite,
 275                            struct guest_walker *walker, gfn_t gfn)
 276 {
 277         access_bits &= gpte;
 278         FNAME(set_pte_common)(vcpu, shadow_pte, gpte & PT_BASE_ADDR_MASK,
 279                               gpte, access_bits, user_fault, write_fault,
 280                               ptwrite, walker, gfn);
 281 }
 282
 283 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
 284                               u64 *spte, const void *pte, int bytes,
 285                               int offset_in_pte)
 286 {
 287         pt_element_t gpte;
 288
 289         gpte = *(const pt_element_t *)pte;
 290         if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
 291                 if (!offset_in_pte && !is_present_pte(gpte))
 292                         set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
 293                 return;
 294         }
 295         if (bytes < sizeof(pt_element_t))
 296                 return;
 297         pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
 298         FNAME(set_pte)(vcpu, gpte, spte, PT_USER_MASK | PT_WRITABLE_MASK, 0,
 299                        0, NULL, NULL,
 300                        (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT);
 301 }
 302
 303 static void FNAME(set_pde)(struct kvm_vcpu *vcpu, pt_element_t gpde,
 304                            u64 *shadow_pte, u64 access_bits,
 305                            int user_fault, int write_fault, int *ptwrite,
 306                            struct guest_walker *walker, gfn_t gfn)
 307 {
 308         gpa_t gaddr;
 309
 310         access_bits &= gpde;
 311         gaddr = (gpa_t)gfn << PAGE_SHIFT;
 312         if (PTTYPE == 32 && is_cpuid_PSE36())
 313                 gaddr |= (gpde & PT32_DIR_PSE36_MASK) <<
 314                         (32 - PT32_DIR_PSE36_SHIFT);
 315         FNAME(set_pte_common)(vcpu, shadow_pte, gaddr,
 316                               gpde, access_bits, user_fault, write_fault,
 317                               ptwrite, walker, gfn);
 318 }
 319
 320 /*
 321  * Fetch a shadow pte for a specific level in the paging hierarchy.
 322  */
 323 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
 324                          struct guest_walker *walker,
 325                          int user_fault, int write_fault, int *ptwrite)
 326 {
 327         hpa_t shadow_addr;
 328         int level;
 329         u64 *shadow_ent;
 330         u64 *prev_shadow_ent = NULL;
 331
 332         if (!is_present_pte(walker->pte))
 333                 return NULL;
 334
 335         shadow_addr = vcpu->mmu.root_hpa;
 336         level = vcpu->mmu.shadow_root_level;
 337         if (level == PT32E_ROOT_LEVEL) {
 338                 shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
 339                 shadow_addr &= PT64_BASE_ADDR_MASK;
 340                 --level;
 341         }
 342
 343         for (; ; level--) {
 344                 u32 index = SHADOW_PT_INDEX(addr, level);
 345                 struct kvm_mmu_page *shadow_page;
 346                 u64 shadow_pte;
 347                 int metaphysical;
 348                 gfn_t table_gfn;
 349                 unsigned hugepage_access = 0;
 350
 351                 shadow_ent = ((u64 *)__va(shadow_addr)) + index;
 352                 if (is_shadow_present_pte(*shadow_ent)) {
 353                         if (level == PT_PAGE_TABLE_LEVEL)
 354                                 break;
 355                         shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
 356                         prev_shadow_ent = shadow_ent;
 357                         continue;
 358                 }
 359
 360                 if (level == PT_PAGE_TABLE_LEVEL)
 361                         break;
 362
 363                 if (level - 1 == PT_PAGE_TABLE_LEVEL
 364                     && walker->level == PT_DIRECTORY_LEVEL) {
 365                         metaphysical = 1;
 366                         hugepage_access = walker->pte;
 367                         hugepage_access &= PT_USER_MASK | PT_WRITABLE_MASK;
 368                         if (!is_dirty_pte(walker->pte))
 369                                 hugepage_access &= ~PT_WRITABLE_MASK;
 370                         hugepage_access >>= PT_WRITABLE_SHIFT;
 371                         if (walker->pte & PT64_NX_MASK)
 372                                 hugepage_access |= (1 << 2);
 373                         table_gfn = (walker->pte & PT_BASE_ADDR_MASK)
 374                                 >> PAGE_SHIFT;
 375                 } else {
 376                         metaphysical = 0;
 377                         table_gfn = walker->table_gfn[level - 2];
 378                 }
 379                 shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
 380                                                metaphysical, hugepage_access,
 381                                                shadow_ent);
 382                 shadow_addr = __pa(shadow_page->spt);
 383                 shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
 384                         | PT_WRITABLE_MASK | PT_USER_MASK;
 385                 *shadow_ent = shadow_pte;
 386                 prev_shadow_ent = shadow_ent;
 387         }
 388
 389         if (walker->level == PT_DIRECTORY_LEVEL) {
 390                 FNAME(set_pde)(vcpu, walker->pte, shadow_ent,
 391                                walker->inherited_ar, user_fault, write_fault,
 392                                ptwrite, walker, walker->gfn);
 393         } else {
 394                 ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
 395                 FNAME(set_pte)(vcpu, walker->pte, shadow_ent,
 396                                walker->inherited_ar, user_fault, write_fault,
 397                                ptwrite, walker, walker->gfn);
 398         }
 399         return shadow_ent;
 400 }
 401
 402 /*
 403  * Page fault handler.  There are several causes for a page fault:
 404  *   - there is no shadow pte for the guest pte
 405  *   - write access through a shadow pte marked read only so that we can set
 406  *     the dirty bit
 407  *   - write access to a shadow pte marked read only so we can update the page
 408  *     dirty bitmap, when userspace requests it
 409  *   - mmio access; in this case we will never install a present shadow pte
 410  *   - normal guest page fault due to the guest pte marked not present, not
 411  *     writable, or not executable
 412  *
 413  *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 414  *           a negative value on error.
 415  */
 416 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
 417                                u32 error_code)
 418 {
 419         int write_fault = error_code & PFERR_WRITE_MASK;
 420         int user_fault = error_code & PFERR_USER_MASK;
 421         int fetch_fault = error_code & PFERR_FETCH_MASK;
 422         struct guest_walker walker;
 423         u64 *shadow_pte;
 424         int write_pt = 0;
 425         int r;
 426
 427         pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
 428         kvm_mmu_audit(vcpu, "pre page fault");
 429
 430         r = mmu_topup_memory_caches(vcpu);
 431         if (r)
 432                 return r;
 433
 434         /*
 435          * Look up the shadow pte for the faulting address.
 436          */
 437         r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
 438                              fetch_fault);
 439
 440         /*
 441          * The page is not mapped by the guest.  Let the guest handle it.
 442          */
 443         if (!r) {
 444                 pgprintk("%s: guest page fault\n", __FUNCTION__);
 445                 inject_page_fault(vcpu, addr, walker.error_code);
 446                 vcpu->last_pt_write_count = 0; /* reset fork detector */
 447                 return 0;
 448         }
 449
 450         shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
 451                                   &write_pt);
 452         pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
 453                  shadow_pte, *shadow_pte, write_pt);
 454
 455         if (!write_pt)
 456                 vcpu->last_pt_write_count = 0; /* reset fork detector */
 457
 458         /*
 459          * mmio: emulate if accessible, otherwise its a guest fault.
 460          */
 461         if (is_io_pte(*shadow_pte))
 462                 return 1;
 463
 464         ++vcpu->stat.pf_fixed;
 465         kvm_mmu_audit(vcpu, "post page fault (fixed)");
 466
 467         return write_pt;
 468 }
 469
 470 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
 471 {
 472         struct guest_walker walker;
 473         gpa_t gpa = UNMAPPED_GVA;
 474         int r;
 475
 476         r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
 477
 478         if (r) {
 479                 gpa = (gpa_t)walker.gfn << PAGE_SHIFT;
 480                 gpa |= vaddr & ~PAGE_MASK;
 481         }
 482
 483         return gpa;
 484 }
 485
 486 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
 487                                  struct kvm_mmu_page *sp)
 488 {
 489         int i, offset = 0;
 490         pt_element_t *gpt;
 491         struct page *page;
 492
 493         if (sp->role.metaphysical
 494             || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
 495                 nonpaging_prefetch_page(vcpu, sp);
 496                 return;
 497         }
 498
 499         if (PTTYPE == 32)
 500                 offset = sp->role.quadrant << PT64_LEVEL_BITS;
 501         page = gfn_to_page(vcpu->kvm, sp->gfn);
 502         gpt = kmap_atomic(page, KM_USER0);
 503         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
 504                 if (is_present_pte(gpt[offset + i]))
 505                         sp->spt[i] = shadow_trap_nonpresent_pte;
 506                 else
 507                         sp->spt[i] = shadow_notrap_nonpresent_pte;
 508         kunmap_atomic(gpt, KM_USER0);
 509         kvm_release_page_clean(page);
 510 }
 511
 512 #undef pt_element_t
 513 #undef guest_walker
 514 #undef FNAME
 515 #undef PT_BASE_ADDR_MASK
 516 #undef PT_INDEX
 517 #undef SHADOW_PT_INDEX
 518 #undef PT_LEVEL_MASK
 519 #undef PT_DIR_BASE_ADDR_MASK
 520 #undef PT_LEVEL_BITS
 521 #undef PT_MAX_FULL_LEVELS